coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 70f3f74 rk3288: configure l2ctlr in romstage
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9347 -gerrit commit 70f3f7437af09c1644eacbcf2a945d42959dc78c Author: huang lin <hl(a)rock-chips.com> Date: Thu Oct 16 09:27:31 2014 -0700 rk3288: configure l2ctlr in romstage Data RAM write latency: 2 cycles Data RAM read latency: 2 cycles Data RAM setup latency: 1 cycle Tag RAM write latency: 1 cycle Tag RAM read latency: 1 cycle Tag RAM setup latency: 1 cycle BUG=None TEST=Boot Veyron Pinky Change-Id: I1d710f65114be6a976aa3fe23b076e89c14ac8b8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 421c2e5ba44f1693f8b3c869289fc93ab9ef5965 Original-Change-Id: Ic9c909b7913d434bd40016c6a820ddff7e991634 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223713 Original-Reviewed-by: Doug Anderson <dianders(a)chromium.org> Original-Commit-Queue: Doug Anderson <dianders(a)chromium.org> --- src/mainboard/google/veyron_pinky/romstage.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 6f9b9d1..76a57e2 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -55,6 +55,25 @@ static void regulate_vdd_log(unsigned int mv) pwm_init(1, period_ns, duty_ns); } +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + void main(void) { #if CONFIG_COLLECT_TIMESTAMPS @@ -66,6 +85,7 @@ void main(void) #endif console_init(); + configure_l2ctlr(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200);

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New patch to review for coreboot: 0ee3082 tegra132: Remove clamp_tristate_inputs() call
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9346 -gerrit commit 0ee308248f48c8798a3fa28137fbdc8353e9ef51 Author: Tom Warren <twarren(a)nvidia.com> Date: Fri Oct 17 10:27:09 2014 -0700 tegra132: Remove clamp_tristate_inputs() call As per NV SysEng, setting PINMUX_CLAMP_INPUTS=1 is now considered a bad thing. It clamps _all_ tristated inputs to zero, and isn't really the panacea for duplicated pinmux mappings as was stated previously. BUG=None BRANCH=None TEST=Built both Rush and Ryu OK. Tested on Rush, booted kernel OK. Change-Id: I7d6982a18a772efda7f1d3bf0dcb0d4d0a5bed8f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c5f77fa31961d39dd7b4bd2902288ead9ad80100 Original-Change-Id: I566c4516b34686b744a47a2b0c18c4b801456727 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224032 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/nvidia/tegra132/bootblock.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 6f25050..0394c78 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -59,9 +59,6 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void) void main(void) { - // enable pinmux clamp inputs - clamp_tristate_inputs(); - // enable JTAG at the earliest stage enable_jtag();

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New patch to review for coreboot: 2aea7b8 arm: Dump additional fault registers in abort handlers
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9345 -gerrit commit 2aea7b84836819c3658b3245773c21a984f66a2d Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Oct 16 10:23:36 2014 -0700 arm: Dump additional fault registers in abort handlers Paging code is tricky and figuring out what is wrong with it can be a pain. This patch tries to ease the burden by giving a little more information for prefetch and data aborts, dumping the Instruction Fault Address Register (IFAR), Instruction Fault Status Register (IFSR) and Auxiliary Instruction Fault Status Register (AIFSR) or the respective Data registers. These contain additional information about the cause of the abort (internal/external, write or read, fault subtype, etc.) and the faulting address. BUG=None TEST=I have read through enough imprecise asynchronous external abort reports with this patch that I learned the bit pattern by heart. Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223784 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/arm/exception.c | 12 +++++++ payloads/libpayload/include/arm/arch/cache.h | 48 ++++++++++++++++++++++++++++ src/arch/arm/armv7/exception.c | 6 ++++ src/arch/arm/include/armv7/arch/cache.h | 48 ++++++++++++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/payloads/libpayload/arch/arm/exception.c b/payloads/libpayload/arch/arm/exception.c index d100937..6f17960 100644 --- a/payloads/libpayload/arch/arm/exception.c +++ b/payloads/libpayload/arch/arm/exception.c @@ -90,6 +90,18 @@ void exception_dispatch(u32 idx) printf("%s Exception\n", names[idx]); print_regs(); + switch (idx) { + case EXC_PABORT: + printf("IFAR = %#.8x\n", read_ifar()); + printf("IFSR = %#.8x\n", read_ifsr()); + printf("AIFSR = %#.8x\n", read_aifsr()); + break; + case EXC_DABORT: + printf("DFAR = %#.8x\n", read_dfar()); + printf("DFSR = %#.8x\n", read_dfsr()); + printf("ADFSR = %#.8x\n", read_adfsr()); + break; + }; dump_stack(exception_state.regs[13], 512); halt(); } diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h index 67f6fd4..b258185 100644 --- a/payloads/libpayload/include/arm/arch/cache.h +++ b/payloads/libpayload/include/arm/arch/cache.h @@ -268,6 +268,54 @@ static inline void write_sctlr(uint32_t val) isb(); } +/* read data fault address register (DFAR) */ +static inline uint32_t read_dfar(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (val)); + return val; +} + +/* read data fault status register (DFSR) */ +static inline uint32_t read_dfsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (val)); + return val; +} + +/* read instruction fault address register (IFAR) */ +static inline uint32_t read_ifar(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r" (val)); + return val; +} + +/* read instruction fault status register (IFSR) */ +static inline uint32_t read_ifsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (val)); + return val; +} + +/* read auxiliary data fault status register (ADFSR) */ +static inline uint32_t read_adfsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r" (val)); + return val; +} + +/* read auxiliary instruction fault status register (AIFSR) */ +static inline uint32_t read_aifsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r" (val)); + return val; +} + /* * Cache maintenance API */ diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index eedd47d..4fac0bc 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -100,6 +100,9 @@ void exception_prefetch_abort(uint32_t *regs) printk(BIOS_ERR, "exception _prefetch_abort\n"); regs[15] -= 4; print_regs(regs); + printk(BIOS_ERR, "IFAR = %#.8x\n", read_ifar()); + printk(BIOS_ERR, "IFSR = %#.8x\n", read_ifsr()); + printk(BIOS_ERR, "AIFSR = %#.8x\n", read_aifsr()); dump_stack(regs[13], 512); die("exception"); } @@ -109,6 +112,9 @@ void exception_data_abort(uint32_t *regs) printk(BIOS_ERR, "exception _data_abort\n"); regs[15] -= 8; print_regs(regs); + printk(BIOS_ERR, "DFAR = %#.8x\n", read_dfar()); + printk(BIOS_ERR, "DFSR = %#.8x\n", read_dfsr()); + printk(BIOS_ERR, "ADFSR = %#.8x\n", read_adfsr()); dump_stack(regs[13], 512); die("exception"); } diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index f23dec1..12df5c3 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -295,6 +295,54 @@ static inline void write_sctlr(uint32_t val) isb(); } +/* read data fault address register (DFAR) */ +static inline uint32_t read_dfar(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (val)); + return val; +} + +/* read data fault status register (DFSR) */ +static inline uint32_t read_dfsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (val)); + return val; +} + +/* read instruction fault address register (IFAR) */ +static inline uint32_t read_ifar(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r" (val)); + return val; +} + +/* read instruction fault status register (IFSR) */ +static inline uint32_t read_ifsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (val)); + return val; +} + +/* read auxiliary data fault status register (ADFSR) */ +static inline uint32_t read_adfsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r" (val)); + return val; +} + +/* read auxiliary instruction fault status register (AIFSR) */ +static inline uint32_t read_aifsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r" (val)); + return val; +} + /* * Cache maintenance API */

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New patch to review for coreboot: 03d7fd9 arm: Add timestamp.c to bootblock and verstage
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9344 -gerrit commit 03d7fd9ff336e29069ef8ac8d1e4db2aca02dd42 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Oct 14 15:24:50 2014 -0700 arm: Add timestamp.c to bootblock and verstage BUG=chrome-os-partner:32973 BRANCH=None TEST=cbmem -t and verified timestamps on ryu Change-Id: Ia2d4d88c5230702319c5651641d8a1a3cc5128b5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a227beb4dd4de8c9e6188a62a3b92ba4eeded80c Original-Change-Id: I4687c2ffe77dcc93d0853de32c8492c7b4d1dbb0 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223346 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 4b8b473..4277ca7 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -62,6 +62,7 @@ bootblock-y += memcpy.S bootblock-y += memmove.S bootblock-y += div0.c bootblock-y += clock.c +bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) $$(VERSTAGE_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -83,6 +84,7 @@ verstage-y += memset.S verstage-y += memcpy.S verstage-y += memmove.S verstage-y += stages.c +verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ############################################################################### # romstage

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New patch to review for coreboot: 182141e armv7: Change all memory domains to Client so XN bits work
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9343 -gerrit commit 182141ee45812c2606bbcb74e20a878c78515244 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Oct 16 09:56:27 2014 -0700 armv7: Change all memory domains to Client so XN bits work Remember the XN bit? The one we had so much fun with on Nyan (LPAE) because not setting it allows random instruction prefetches to device memory that hang the system every few thousand boots? Thankfully, we had always been setting it in the non-LPAE MMU code already... "When the XN bit is 1, a Permission fault is generated if the processor attempts to execute an instruction fetched from the corresponding memory region. However, when using the Short-descriptor translation table format, the fault is generated only if the access is to memory in the Client domain, see Domains[...]" - ARM A.R.M. section B3.7.2 Oops. This patch changes our Domain Access Control Register (DACR) to set domain 0 (the only one we are using) to Client. This means that access permissions (AP[2:0] bits) become enforced, but they are already set to full access (0b011). It also means that non-LPAE systems will not be allowed to execute from DCACHE_OFF memory with enabled MMU anymore. As far as I can see, Veyron_Pinky has been the only board that does that. BUG=chrome-os-partner:32118 TEST=Booted Veyron_Pinky with MMU in the bootblock, saw hangs that look like spurious prefetches and confirmed that this patch fixes them. Change-Id: I81c00743f938924a5dc8825389fe512a069b77db Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cbc96db296a41ae700371a8515a1179c142f58e7 Original-Change-Id: I30676a5bfe12d516e5f910f51ee6854f6e5be557 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/armv7/mmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index de7fa40..581c572 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -302,6 +302,6 @@ void mmu_init(void) 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ ); - /* disable domain-level checking of permissions */ - write_dacr(~0); + /* Set domain 0 to Client so XN bit works (to prevent prefetches) */ + write_dacr(0x5); }

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New patch to review for coreboot: acfcba9 rk3288: Add early SRAM mapping
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9342 -gerrit commit acfcba96f000243306a1382ccf9d796a0ac45ff7 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Oct 15 18:50:45 2014 -0700 rk3288: Add early SRAM mapping Solving the DACR bug will mean that XN bits suddenly become enforced on non-LPAE systems, and we will no longer be able to execute out of a region mapped DCACHE_OFF. When we enable the MMU in romstage we are still executing out of SRAM, so we would instantly kill ourselves. Solve this issue by enabling the MMU earlier (in the bootblock) and mapping the SRAM regions as DCACHE_WRITETHROUGH. They should really be DCACHE_WRITEBACK, but it looks like there might be hardware limitations in the Cortex-A12 cache architecture that prevent us from doing so. Write-through mappings are equivalent to normal non-cacheable on the A12 anyway, and by using this attribute we don't need to introduce a new DCACHE_OFF_BUT_WITHOUT_XN_BIT type in our API. (Also, using normal non-cacheable might still have a slight speed advantage over strongly ordered since it should fetch whole cache lines at once if the processor finds enough accesses it can combine.) CQ-DEPEND=CL:223783 BUG=chrome-os-partner:32118 TEST=None (depends on follow-up CL) Change-Id: I1e5127421f82177ca11af892b1539538b379625e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e7b079f4b6a69449f3c7cc18ef0e1704f2006847 Original-Change-Id: I53e827d95acc2db909f1251de78d65e295eceaa7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223782 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/veyron_pinky/romstage.c | 18 ++++-------------- src/soc/rockchip/rk3288/bootblock.c | 11 +++++++++++ src/soc/rockchip/rk3288/memlayout.ld | 3 ++- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 1d7812b..6f9b9d1 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -64,10 +64,6 @@ void main(void) uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); #endif - /* used for MMU and CBMEM setup, in MB */ - u32 dram_start_mb = (uintptr_t)_dram/MiB; - u32 dram_size_mb = CONFIG_DRAM_SIZE_MB; - u32 dram_end_mb = dram_start_mb + dram_size_mb; console_init(); @@ -80,18 +76,12 @@ void main(void) #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif - mmu_init(); - /* Device memory below DRAM is uncached. */ - mmu_config_range(0, dram_start_mb, DCACHE_OFF); - /* DRAM is cached. */ - mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); - /* A window for DMA is uncached. */ + + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ + mmu_config_range((uintptr_t)_dram/MiB, + CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); - /* The space above DRAM is uncached. */ - if (dram_end_mb < 4096) - mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); - dcache_mmu_enable(); cbmem_initialize_empty(); diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index eec3456..b2f5bd9 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -17,10 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cache.h> #include <arch/io.h> #include <bootblock_common.h> #include <console/console.h> #include <soc/rockchip/rk3288/grf.h> +#include <symbols.h> #include "addressmap.h" #include "timer.h" #include "clock.h" @@ -41,4 +43,13 @@ static void bootblock_cpu_init(void) } rkclk_init(); + + mmu_init(); + /* Start with a clean slate. */ + mmu_config_range(0, 4096, DCACHE_OFF); + /* SRAM is tightly wedged between registers, need to use subtables. Map + * write-through as equivalent for non-cacheable without XN on A17. */ + mmu_config_range_kb((uintptr_t)_sram/KiB, + _sram_size/KiB, DCACHE_WRITETHROUGH); + dcache_mmu_enable(); } diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 6faec63..2ddb6a6 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -34,7 +34,8 @@ SECTIONS SRAM_START(0xFF700000) TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 16K - 4) + BOOTBLOCK(0xFF704004, 15K - 4) + TTB_SUBTABLES(0xFF707c00, 1K) VBOOT2_WORK(0xFF708000, 16K) OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K) PRERAM_CBFS_CACHE(0xFF716000, 4K)

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New patch to review for coreboot: 7ff09d1 armv7: Add fine-grained page table support
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9341 -gerrit commit 7ff09d14f66986341b8a3355d52bfd790b8a7fac Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Oct 9 17:31:45 2014 -0700 armv7: Add fine-grained page table support This patch adds an mmu_config_range_kb() function, which can set memory types at the 4KB level by chaining a fine-grained page table to an existing superpage entry. It is only intended for special cases where this level of precision is really necessary and therefore comes with a few practical limitations (the area for each invocation must be confined within a single superpage, and you are not allowed to remap the same region with mmu_config_range() again later). Since the fine-grained page tables need some space, boards intending to use this feature must define a TTB_SUBTABLES() region in their memlayout.ld. BUG=chrome-os-partner:32848 TEST=Booted both Veyron_Pinky (normal) and Nyan_Blaze (LPAE), ensured that they still work. Checksummed the page tables with and without this patch, confirmed that they end up equal. Hacked in some subtable test entries, hexdumped all tables and manually confirmed that they look as expected. Change-Id: I8c3eb7c2eb9c82e2abc5f2c0dda91f5b2eee7023 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2f13e60cf5509b9a63fb7b8d84846daf889dc1b7 Original-Change-Id: Iedf7ca435ae337ead85115200d6987fb0d4828d7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223781 --- src/arch/arm/armv7/mmu.c | 188 +++++++++++++++++++++----------- src/arch/arm/include/arch/memlayout.h | 5 + src/arch/arm/include/armv4/arch/cache.h | 19 ---- src/arch/arm/include/armv7/arch/cache.h | 11 +- src/include/symbols.h | 4 + 5 files changed, 140 insertions(+), 87 deletions(-) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index e9c6815..de7fa40 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -42,7 +42,7 @@ #if CONFIG_ARM_LPAE /* See B3.6.2 of ARMv7 Architecture Reference Manual */ /* TODO: Utilize the contiguous hint flag */ -#define ATTR_BASE (\ +#define ATTR_BLOCK (\ 0ULL << 54 | /* XN. 0:Not restricted */ \ 0ULL << 53 | /* PXN. 0:Not restricted */ \ 1 << 10 | /* AF. 1:Accessed. This is to prevent access \ @@ -52,16 +52,18 @@ 0 << 1 | /* block/table. 0:block entry */ \ 1 << 0 /* validity. 1:valid */ \ ) -#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2) | \ - (1ULL << 53) | (1ULL << 54)) -#define ATTR_WT (ATTR_BASE | (MAIR_INDX_WT << 2)) -#define ATTR_WB (ATTR_BASE | (MAIR_INDX_WB << 2)) +#define ATTR_PAGE (ATTR_BLOCK | 1 << 1) +#define ATTR_NEXTLEVEL (0x3) +#define ATTR_NC ((MAIR_INDX_NC << 2) | (1ULL << 53) | (1ULL << 54)) +#define ATTR_WT (MAIR_INDX_WT << 2) +#define ATTR_WB (MAIR_INDX_WB << 2) +#define PAGE_MASK 0x000ffffffffff000ULL +#define BLOCK_MASK 0x000fffffffe00000ULL +#define NEXTLEVEL_MASK PAGE_MASK #define BLOCK_SHIFT 21 -typedef uint64_t pgd_t; -typedef uint64_t pmd_t; -static const unsigned int denom = 2; +typedef uint64_t pte_t; #else /* CONFIG_ARM_LPAE */ /* * Section entry bits: @@ -79,27 +81,28 @@ static const unsigned int denom = 2; * 2 - B, 1 for bufferable * 1: 0 - 0b10 to indicate section entry */ -#define ATTR_BASE ((3 << 10) | 0x2) -#define ATTR_NC (ATTR_BASE | (1 << 4)) -#define ATTR_WT (ATTR_BASE | (1 << 3)) -#define ATTR_WB (ATTR_BASE | (1 << 3) | (1 << 2)) +#define ATTR_BLOCK ((3 << 10) | 0x2) +#define ATTR_PAGE ((3 << 4) | 0x2) +#define ATTR_NEXTLEVEL (0x1) +#define ATTR_NC (1 << 4) +#define ATTR_WT (1 << 3) +#define ATTR_WB ((1 << 3) | (1 << 2)) +#define PAGE_MASK 0xfffff000UL +#define BLOCK_MASK 0xfff00000UL +#define NEXTLEVEL_MASK 0xfffffc00UL #define BLOCK_SHIFT 20 -typedef uint32_t pgd_t; -typedef uint32_t pmd_t; -static const unsigned int denom = 1; +typedef uint32_t pte_t; #endif /* CONFIG_ARM_LPAE */ -static pmd_t *const ttb_buff = (pmd_t *)_ttb; - /* * mask/shift/size for pages and blocks */ #define PAGE_SHIFT 12 #define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK ~((1UL << PAGE_SHIFT) - 1) #define BLOCK_SIZE (1UL << BLOCK_SHIFT) +#define SUBTABLE_SIZE ((1 << (BLOCK_SHIFT - PAGE_SHIFT)) * sizeof(pte_t)) /* * MAIR Index @@ -108,69 +111,124 @@ static pmd_t *const ttb_buff = (pmd_t *)_ttb; #define MAIR_INDX_WT 1 #define MAIR_INDX_WB 2 -static void mmu_flush_page_table_entry_range( - unsigned long start_mb, unsigned long size_mb) +static pte_t *const ttb_buff = (void *)_ttb; +static int used_tables = 0; + +/* Not all boards want to use subtables and declare them in memlayout.ld. This + * outputs two 0x00000000 symbols if they don't, making _ttb_subtables_size 0. + * (I would like to explicitly assign them to 0 here, but that triggers + * https://sourceware.org/bugzilla/show_bug.cgi?id=1038 in GNU as.) */ +asm (".weak _ttb_subtables, _ettb_subtables"); + +static struct { + pte_t value; + const char *name; +} attrs[] = { + [DCACHE_OFF] = {.value = ATTR_NC, .name = "uncached"}, + [DCACHE_WRITEBACK] = {.value = ATTR_WB, .name = "writeback"}, + [DCACHE_WRITETHROUGH] = {.value = ATTR_WT, .name = "writethrough"}, +}; + +/* Fills page table entries in |table| from |start_idx| to |end_idx| with |attr| + * and performs necessary invalidations. |offset| is the start address of the + * area described by |table|, and |shift| is the size-shift of each frame. */ +static void mmu_fill_table(pte_t *table, u32 start_idx, u32 end_idx, + uintptr_t offset, u32 shift, pte_t attr) { int i; + /* Write out page table entries. */ + for (i = start_idx; i < end_idx; i++) + table[i] = (offset + (i << shift)) | attr; + /* Flush the page table entries from the dcache. */ - for (i = start_mb/denom; i*denom < start_mb + size_mb; i++) - dccmvac((uintptr_t)&ttb_buff[i]); + for (i = start_idx; i < end_idx; i++) + dccmvac((uintptr_t)&table[i]); dsb(); + /* Invalidate the TLB entries. */ - for (i = start_mb/denom; i*denom < start_mb + size_mb; i++) - tlbimvaa(i*denom*MiB); + for (i = start_idx; i < end_idx; i++) + tlbimvaa(offset + (i << shift)); dsb(); isb(); } -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) +static pte_t *mmu_create_subtable(pte_t *pgd_entry) { - int i; + if (used_tables >= _ttb_subtables_size / SUBTABLE_SIZE) + die("Not enough room for another sub-pagetable!"); - printk(BIOS_DEBUG, "Disabling: [0x%08lx:0x%08lx)\n", - start_mb*MiB, start_mb*MiB + size_mb*MiB); + /* We assume that *pgd_entry must already be a valid block mapping. */ + uintptr_t start_addr = (uintptr_t)(*pgd_entry & BLOCK_MASK); + pte_t *table = (void *)(_ttb_subtables + used_tables++ * SUBTABLE_SIZE); + printk(BIOS_DEBUG, "Creating new subtable @%p for [%#.8x:%#.8lx)\n", + table, start_addr, start_addr + BLOCK_SIZE); - for (i = start_mb/denom; i*denom < start_mb + size_mb; i++) - ttb_buff[i] = 0; + /* Initialize the new subtable with entries of the same attributes + * (XN bit moves from 4 to 0, set PAGE unless block was unmapped). */ + pte_t attr = *pgd_entry & ~(BLOCK_MASK); + if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4))) + attr = ((attr & ~(1 << 4)) | (1 << 0)); + if (attr & ATTR_BLOCK) + attr = (attr & ~ATTR_BLOCK) | ATTR_PAGE; + mmu_fill_table(table, 0, SUBTABLE_SIZE / sizeof(pte_t), + start_addr, PAGE_SHIFT, attr); - mmu_flush_page_table_entry_range(start_mb, size_mb); + /* Replace old entry in upper level table to point at subtable. */ + *pgd_entry = (pte_t)(uintptr_t)table | ATTR_NEXTLEVEL; + dccmvac((uintptr_t)pgd_entry); + dsb(); + tlbimvaa(start_addr); + dsb(); + isb(); + + return table; } -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy) +void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy) { - const char *str = NULL; - pmd_t attr; - int i; + pte_t *pgd_entry = &ttb_buff[start_kb / (BLOCK_SIZE/KiB)]; + pte_t *table = (void *)(uintptr_t)(*pgd_entry & NEXTLEVEL_MASK); - switch(policy) { - case DCACHE_OFF: - /* XN set to avoid prefetches to uncached/unbuffered regions */ - attr = ATTR_NC; - str = "off"; - break; - case DCACHE_WRITEBACK: - attr = ATTR_WB; - str = "writeback"; - break; - case DCACHE_WRITETHROUGH: - attr = ATTR_WT; - str = "writethrough"; - break; - default: - printk(BIOS_ERR, "unknown dcache policy: %02x\n", policy); - return; - } - - printk(BIOS_DEBUG, "Setting dcache policy: [0x%08lx:0x%08lx) [%s]\n", - start_mb << 20, ((start_mb + size_mb) << 20), str); + /* Make sure the range is contained within a single superpage. */ + assert(((start_kb + size_kb - 1) & (BLOCK_MASK/KiB)) + == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB)); - /* Write out page table entries. */ - for (i = start_mb/denom; i*denom < start_mb + size_mb; i++) - ttb_buff[i] = ((pmd_t)i << BLOCK_SHIFT) | attr; + if ((*pgd_entry & ~NEXTLEVEL_MASK) != ATTR_NEXTLEVEL) + table = mmu_create_subtable(pgd_entry); + + /* Always _one_ _damn_ bit that won't fit... (XN moves from 4 to 0) */ + pte_t attr = attrs[policy].value; + if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4))) + attr = ((attr & ~(1 << 4)) | (1 << 0)); + + /* Mask away high address bits that are handled by upper level table. */ + u32 mask = BLOCK_SIZE/KiB - 1; + printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n", + start_kb * KiB, (start_kb + size_kb) * KiB, attrs[policy].name); + mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB), + div_round_up((start_kb + size_kb) & mask, PAGE_SIZE/KiB), + (start_kb & ~mask) * KiB, PAGE_SHIFT, ATTR_PAGE | attr); +} - mmu_flush_page_table_entry_range(start_mb, size_mb); +void mmu_disable_range(u32 start_mb, u32 size_mb) +{ + printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n", + start_mb * MiB, (start_mb + size_mb) * MiB); + assert(start_mb + size_mb <= 4 * (GiB/MiB)); + mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB), + div_round_up(start_mb + size_mb, BLOCK_SIZE/MiB), + 0, BLOCK_SHIFT, 0); +} + +void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy) +{ + printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n", + start_mb * MiB, (start_mb + size_mb) * MiB, attrs[policy].name); + assert(start_mb + size_mb <= 4 * (GiB/MiB)); + mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB), + div_round_up(start_mb + size_mb, BLOCK_SIZE/MiB), + 0, BLOCK_SHIFT, ATTR_BLOCK | attrs[policy].value); } /* @@ -187,8 +245,8 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, void mmu_init(void) { if (CONFIG_ARM_LPAE) { - pgd_t *const pgd_buff = (pgd_t*)(_ttb + 16*KiB); - pmd_t *pmd = ttb_buff; + pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB); + pte_t *pmd = ttb_buff; int i; printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", @@ -214,8 +272,8 @@ void mmu_init(void) * See B3.6.1 of ARMv7 Architecture Reference Manual */ for (i = 0; i < 4; i++) { - pgd_buff[i] = ((uint32_t)pmd & PAGE_MASK) | - 3; /* 0b11: valid table entry */ + pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | + ATTR_NEXTLEVEL; pmd += BLOCK_SIZE / PAGE_SIZE; } diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h index 9f5b383..2c73394 100644 --- a/src/arch/arm/include/arch/memlayout.h +++ b/src/arch/arm/include/arch/memlayout.h @@ -27,6 +27,11 @@ _ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \ "TTB must be 16K (+ 32 for LPAE)!"); +#define TTB_SUBTABLES(addr, size) \ + REGION(ttb_subtables, addr, size, IS_ENABLED(CONFIG_ARM_LPAE)*3K + 1K) \ + _ = ASSERT(size % (1K + 3K * IS_ENABLED(CONFIG_ARM_LPAE)) == 0, \ + "TTB subtable region must be evenly divisible by table size!"); + /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */ #define STACK(addr, size) REGION(stack, addr, size, 8) diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h index e41ff9a..65f5966 100644 --- a/src/arch/arm/include/armv4/arch/cache.h +++ b/src/arch/arm/include/armv4/arch/cache.h @@ -72,23 +72,4 @@ void cache_sync_instructions(void); /* tlb invalidate all */ void tlb_invalidate_all(void); -/* - * Generalized setup/init functions - */ - -/* mmu initialization (set page table address, set permissions, etc) */ -void mmu_init(void); - -enum dcache_policy { - DCACHE_OFF, - DCACHE_WRITEBACK, - DCACHE_WRITETHROUGH, -}; - -/* disable the mmu for a range. Primarily useful to lock out address 0. */ -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); -/* mmu range configuration (set dcache policy) */ -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy); - #endif /* ARM_CACHE_H */ diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index dde2c08..f23dec1 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -345,9 +345,14 @@ enum dcache_policy { }; /* disable the mmu for a range. Primarily useful to lock out address 0. */ -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); +void mmu_disable_range(u32 start_mb, u32 size_mb); /* mmu range configuration (set dcache policy) */ -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy); +void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy); + +/* Reconfigure memory mappings at the fine-grained (4K) page level. Must be + * called on a range contained within a single, already mapped block/superpage. + * Careful: Do NOT map over this address range with mmu_config_range() again + * later, or you will leak resources and may desync your TLB! */ +void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy); #endif /* ARM_CACHE_H */ diff --git a/src/include/symbols.h b/src/include/symbols.h index c343fd9..2259dcb 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -69,6 +69,10 @@ extern u8 _ttb[]; extern u8 _ettb[]; #define _ttb_size (_ettb - _ttb) +extern u8 _ttb_subtables[]; +extern u8 _ettb_subtables[]; +#define _ttb_subtables_size (_ettb_subtables - _ttb_subtables) + extern u8 _dma_coherent[]; extern u8 _edma_coherent[]; #define _dma_coherent_size (_edma_coherent - _dma_coherent)

1 0

New patch to review for coreboot: de3318e timestamp: Add bootblock start and end to timestamp constants
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9340 -gerrit commit de3318ece20a5b3d64f578dc3a6fc195a7e95b59 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Oct 14 15:18:38 2014 -0700 timestamp: Add bootblock start and end to timestamp constants BUG=chrome-os-partner:32973 BRANCH=None TEST=cbmem -t to check proper timestamps on ryu Change-Id: Ic31c5d9f3e397d90b08fe1c5e152148f4a278b95 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 92469e04c1c52bd60a8a37f017d865d0a838bff5 Original-Change-Id: I95419a6d240c168c8b6a489cac969390ecf6dea0 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223345 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/include/timestamp.h | 2 ++ util/cbmem/cbmem.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/include/timestamp.h b/src/include/timestamp.h index ba73135..c2bc6f1 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -44,6 +44,8 @@ enum timestamp_id { TS_START_COPYRAM = 8, TS_END_COPYRAM = 9, TS_START_RAMSTAGE = 10, + TS_START_BOOTBLOCK = 11, + TS_END_BOOTBLOCK = 12, TS_DEVICE_ENUMERATE = 30, TS_FSP_BEFORE_ENUMERATE, TS_FSP_AFTER_ENUMERATE, diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 4314d30..7c96c6e 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -384,6 +384,8 @@ static const struct timestamp_id_to_name { { TS_START_COPYRAM, "start of copying ram stage" }, { TS_END_COPYRAM, "end of copying ram stage" }, { TS_START_RAMSTAGE, "start of ramstage" }, + { TS_START_BOOTBLOCK, "start of bootblock" }, + { TS_END_BOOTBLOCK, "end of bootblock" }, { TS_DEVICE_ENUMERATE, "device enumeration" }, { TS_DEVICE_CONFIGURE, "device configuration" }, { TS_DEVICE_ENABLE, "device enable" },

1 0

New patch to review for coreboot: 63cf62f rk3288: Fix some PLL divisors and improve clock code
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9339 -gerrit commit 63cf62f53c6033367eeaf0173f6800f5fcce169b Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 6 15:02:12 2014 -0700 rk3288: Fix some PLL divisors and improve clock code This patch does some general cleanup in the Rockchip clock code, and adds some more assertions regarding the PLL VCO and output frequency ranges. It changes all PLL divisors to use the lowest values that can still hit the target frequency, since higher NR values lead to higher jitter and higher NO values increase power draw. Also change DDR3 frequency code to hardcode the optimal divisors for certail frequencies. As a little hack we will interpret 666000000 to actually mean 666666666.6P (and analogous for 533MHz), since that's what you usually want for memory. BUG=chrome-os-partner:32139 TEST=Boot on veyron_pinky rev2, check that dpll_is shown as 666666666 in /sys/kernel/debug/clk/clk_summary. Change-Id: I57d7ef34500984184e010c0cc7d73789338834d4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7466ffc035b3f06ac280f412bc496059abf3239c Original-Change-Id: I4f3c39641955a95c6dfbe9334035eb670b138bf0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221801 --- src/soc/rockchip/rk3288/clock.c | 67 ++++++++++++++++++++++++----------------- src/soc/rockchip/rk3288/timer.h | 4 +-- 2 files changed, 42 insertions(+), 29 deletions(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 37d366f..bdfe079 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <arch/io.h> #include <stdint.h> +#include <string.h> #include <console/console.h> #include <delay.h> #include "clock.h" @@ -65,15 +66,15 @@ check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c); static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PLL_DIVISORS(hz, _nr, _no) {\ - .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / (24*MHz)), .no = _no};\ - _Static_assert(((u64)hz * _nr * _no / (24*MHz)) * (24*MHz) /\ - (_nr * _no) == hz,\ - #hz "Hz cannot be hit with PLL divisors in " __FILE__); + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ + "divisors on line " STRINGIFY(__LINE__)); -/* apll = 816MHz, gpll = 594MHz, cpll = 384MHz */ -static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 2); -static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 4); -static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4); +/* Keep divisors as low as possible to reduce jitter and power usage. */ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); /*******************PLL CON0 BITS***************************/ #define PLL_OD_MSK (0x0F) @@ -190,19 +191,28 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4); #define SOCSTS_CPLL_LOCK (1 << 7) #define SOCSTS_GPLL_LOCK (1 << 8) -static int rkclk_set_pll(u32 *pll_con, const struct pll_div *pll_div_cfg) +static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div) { + /* All PLLs have same VCO and output frequency range restrictions. */ + u32 vco_khz = OSC_HZ/KHz * div->nf / div->nr; + u32 output_khz = vco_khz / div->no; + + printk(BIOS_DEBUG, "Configuring PLL at %p with NF = %d, NR = %d and " + "NO = %d (VCO = %uKHz, output = %uKHz)\n", + pll_con, div->nf, div->nr, div->no, vco_khz, output_khz); + assert(vco_khz >= 440*(MHz/KHz) && vco_khz <= 2200*(MHz/KHz) && + output_khz >= 27500 && output_khz <= 2200*(MHz/KHz) && + (div->no == 1 || !(div->no % 2))); + /* enter rest */ writel(RK_SETBITS(PLL_RESET_MSK), &pll_con[3]); - writel(RK_CLRSETBITS(PLL_NR_MSK, (pll_div_cfg->nr - 1) << PLL_NR_SHIFT) - | RK_CLRSETBITS(PLL_OD_MSK, (pll_div_cfg->no - 1)), &pll_con[0]); + writel(RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) + | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1)), &pll_con[0]); - writel(RK_CLRSETBITS(PLL_NF_MSK, (pll_div_cfg->nf - 1)), - &pll_con[1]); + writel(RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1)), &pll_con[1]); - writel(RK_CLRSETBITS(PLL_BWADJ_MSK, ((pll_div_cfg->nf >> 1) - 1)), - &pll_con[2]); + writel(RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1)), &pll_con[2]); udelay(10); @@ -352,20 +362,23 @@ void rkclk_configure_ddr(unsigned int hz) { struct pll_div dpll_cfg; - if (hz <= 150*MHz) { - dpll_cfg.nr = 3; - dpll_cfg.no = 8; - } else if (hz <= 540*MHz) { - dpll_cfg.nr = 6; - dpll_cfg.no = 4; - } else { - dpll_cfg.nr = 1; - dpll_cfg.no = 1; + switch (hz) { + case 300*MHz: + dpll_cfg = (struct pll_div){.nf = 25, .nr = 2, .no = 1}; + break; + case 533*MHz: /* actually 533.3P MHz */ + dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2}; + break; + case 666*MHz: /* actually 666.6P MHz */ + dpll_cfg = (struct pll_div){.nf = 500, .nr = 9, .no = 2}; + break; + case 800*MHz: + dpll_cfg = (struct pll_div){.nf = 100, .nr = 3, .no = 1}; + break; + default: + die("Unsupported SDRAM frequency, add to clock.c!"); } - dpll_cfg.nf = (hz/KHz * dpll_cfg.nr * dpll_cfg.no) / (24*KHz); - assert(dpll_cfg.nf < 4096 && hz == dpll_cfg.nf * (24*KHz) / - (dpll_cfg.nr * dpll_cfg.no) * 1000); /* pll enter slow-mode */ writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), &cru_ptr->cru_mode_con); diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h index 9f1fbaf..8507939 100644 --- a/src/soc/rockchip/rk3288/timer.h +++ b/src/soc/rockchip/rk3288/timer.h @@ -23,9 +23,9 @@ #include <inttypes.h> #include <timer.h> #include "addressmap.h" +#include "clock.h" -#define SYS_CLK_FREQ (24*MHz) -static const u32 clocks_per_usec = SYS_CLK_FREQ/USECS_PER_SEC; +static const u32 clocks_per_usec = OSC_HZ/USECS_PER_SEC; struct rk3288_timer { u32 timer_load_count0;

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New patch to review for coreboot: 26443ed rk3288: Re-write spi_xfer() to support full duplex
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9338 -gerrit commit 26443ed84825c3302d1b14f3eaf2c2f423bf88b6 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Sep 12 18:58:47 2014 -0700 rk3288: Re-write spi_xfer() to support full duplex This change re-writes the spi_xfer() function to support full-duplex transfers. Even though the code looks much different, the same basic algorithm for setting up the transfer is used. The main difference is that reads from rxdr and writes to txdr occur simultaneously and accounting is more complicated, so I separated the higher-level accounting portion from the low-level FIFO handling portion to simplify things. BUG=chrome-os-partner:31850 BRANCH=none TEST=Loaded content from SPI ROM fine, needs testing w/ EC Change-Id: Ic109a02daf52ba694b63a73fec1a72b3c5c0fd71 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6a14f5ff8ed04d62e8de6ad2f468b763ffb8213c Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I33d2f5179360baf94627c86b57d12f032897caf5 Original-Reviewed-on: https://chromium-review.googlesource.com/218881 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/spi.c | 182 ++++++++++++++++++++++++++++-------------- 1 file changed, 122 insertions(+), 60 deletions(-) diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index a74d423..796107e 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -171,77 +171,121 @@ static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) return -1; } -int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int sout, - void *din, unsigned int sin) +static void set_tmod(struct rockchip_spi *regs, unsigned int tmod) +{ + clrsetbits_le32(&regs->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, + tmod << SPI_TMOD_OFFSET); +} + +static void set_transfer_mode(struct rockchip_spi *regs, + unsigned int sout, unsigned int sin) +{ + if (!sin && !sout) + return; + else if (sin && sout) + set_tmod(regs, SPI_TMOD_TR); /* tx and rx */ + else if (!sin) + set_tmod(regs, SPI_TMOD_TO); /* tx only */ + else if (!sout) + set_tmod(regs, SPI_TMOD_RO); /* rx only */ +} + +/* returns 0 to indicate success, <0 otherwise */ +static int do_xfer(struct spi_slave *slave, const void *dout, + unsigned int *bytes_out, void *din, unsigned int *bytes_in) { - unsigned int len; - unsigned int bytes_remaining; - uint8_t *p; struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + uint8_t *in_buf = din; + uint8_t *out_buf = (uint8_t *)dout; + unsigned int min_xfer; + + if (*bytes_out == 0) + min_xfer = *bytes_in; + else if (*bytes_in == 0) + min_xfer = *bytes_out; + else + min_xfer = MIN(*bytes_in, *bytes_out); - if (dout) { - len = sout; - p = (uint8_t *) dout; - bytes_remaining = len; - writel(0, &regs->spienr); /*disable spi */ - writel(len - 1, &regs->ctrlr1); /*wrtie len */ - - /*tx only */ - clrsetbits_le32(&regs->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, - SPI_TMOD_TO << SPI_TMOD_OFFSET); - writel(1, &regs->spienr);/*enable spi */ - while (bytes_remaining) { - if ((readl(&regs->txflr) & 0x3f) < SPI_FIFO_DEPTH) { - writel(*p++, &regs->txdr); - bytes_remaining--; - } + while (min_xfer) { + uint32_t sr = readl(&regs->sr); + int xferred = 0; /* in either (or both) directions */ + + if (*bytes_out && !(sr & SR_TF_FULL)) { + writel(*out_buf, &regs->txdr); + out_buf++; + *bytes_out -= 1; + xferred = 1; } - if (rockchip_spi_wait_till_not_busy(regs)) - return -1; - } - if (din) { - len = sin; - p = (uint8_t *) din; - writel(0, &regs->spienr); /*disable spi */ - writel(len - 1, &regs->ctrlr1); /*write len */ - - /*rx only */ - clrsetbits_le32(&regs->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, - SPI_TMOD_RO << SPI_TMOD_OFFSET); - while (len) { - writel(0, &regs->spienr);/*disable spi */ - bytes_remaining = MIN(len, 0xffff); - writel(bytes_remaining - 1, &regs->ctrlr1); - len -= bytes_remaining; - writel(1, &regs->spienr);/*enable spi */ - while (bytes_remaining) { - if (readl(&regs->rxflr) & 0x3f) { - *p = readl(&regs->rxdr) & 0xff; - p += 1; - bytes_remaining--; - } - } + + if (*bytes_in && !(sr & SR_RF_EMPT)) { + *in_buf = readl(&regs->rxdr) & 0xff; + in_buf++; + *bytes_in -= 1; + xferred = 1; } - if (rockchip_spi_wait_till_not_busy(regs)) - return -1; + + min_xfer -= xferred; + } + + if (rockchip_spi_wait_till_not_busy(regs)) { + printk(BIOS_ERR, "Timed out waiting on SPI transfer\n"); + return -1; } + return 0; } -static int rockchip_spi_read(struct spi_slave *slave, void *dest, uint32_t len, - uint32_t off) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bytes_out, void *din, unsigned int bytes_in) { - unsigned int cmd; + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + int ret = 0; + + /* + * RK3288 SPI controller can transfer up to 65536 data frames (bytes + * in our case) continuously. Break apart large requests as necessary. + * + * FIXME: And by 65536, we really mean 65535. If 0xffff is written to + * ctrlr1, all bytes that we see in rxdr end up being 0x00. 0xffff - 1 + * seems to work fine. + */ + while (bytes_out || bytes_in) { + unsigned int in_now = MIN(bytes_in, 0xffff); + unsigned int out_now = MIN(bytes_out, 0xffff); + unsigned int in_rem, out_rem; + + rockchip_spi_enable_chip(regs, 0); + + /* Enable/disable transmitter and receiver as needed to + * avoid sending or reading spurious bits. */ + set_transfer_mode(regs, bytes_out, bytes_in); + + /* MAX() in case either counter is 0 */ + writel(MAX(in_now, out_now) - 1, &regs->ctrlr1); + + rockchip_spi_enable_chip(regs, 1); + + in_rem = in_now; + out_rem = out_now; + ret = do_xfer(slave, dout, &out_rem, din, &in_rem); + if (ret < 0) + break; + + if (bytes_out) { + unsigned int sent = out_now - out_rem; + bytes_out -= sent; + dout += sent; + } - spi_claim_bus(slave); - cmd = swab32(off) | SF_READ_DATA_CMD; - if (spi_xfer(slave, &cmd, sizeof(cmd), dest, len)) { - printk(BIOS_DEBUG, "rockchip_spi_read err\n"); - spi_release_bus(slave); - return -1; + if (bytes_in) { + unsigned int received = in_now - in_rem; + bytes_in -= received; + din += received; + } } - spi_release_bus(slave); - return len; + + rockchip_spi_enable_chip(regs, 0); + return ret < 0 ? ret : 0; } struct rockchip_spi_media { @@ -262,10 +306,28 @@ static int rockchip_spi_cbfs_close(struct cbfs_media *media) static size_t rockchip_spi_cbfs_read(struct cbfs_media *media, void *dest, size_t offset, size_t count) { + unsigned int cmd; struct rockchip_spi_media *spi = (struct rockchip_spi_media *)media->context; + int ret; + + spi_claim_bus(spi->slave); + cmd = swab32(offset) | SF_READ_DATA_CMD; + if (spi_xfer(spi->slave, &cmd, sizeof(cmd), NULL, 0)) { + printk(BIOS_DEBUG, "%s: could not send command\n", __func__); + ret = 0; + goto rockchip_spi_cbfs_read_done; + } + + if (spi_xfer(spi->slave, NULL, 0, dest, count)) { + printk(BIOS_DEBUG, "%s: could not receive data\n", __func__); + ret = 0; + goto rockchip_spi_cbfs_read_done; + } - return rockchip_spi_read(spi->slave, dest, count, offset); +rockchip_spi_cbfs_read_done: + spi_release_bus(spi->slave); + return ret < 0 ? 0 : count; } static void *rockchip_spi_cbfs_map(struct cbfs_media *media, size_t offset,

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coreboot-gerrit April 2015