coreboot-gerrit April 2015

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Patch set updated for coreboot: a981f22 bg4cd: add SPI controller driver skeleton
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9355 -gerrit commit a981f226bfc7aa16313325ad695d4f62148f2719 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 16 11:07:41 2014 -0700 bg4cd: add SPI controller driver skeleton This file provides the SOC specific SPI driver API, it needs to be filled up with code. Function descriptions can be found in src/include/spi-generic.h. BRANCH=none BUG=chrome-os-partner:32631 TEST=compiles with the upcoming patches applied. Change-Id: I3546d5f9fb2971f4ccb7a57ce8164fd77686af72 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0583f17fe3f6a258321765b91eae608e33577afe Original-Change-Id: I0ee04ca17874a13403007bba80d5e8a7708bc625 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223719 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/marvell/bg4cd/spi.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/soc/marvell/bg4cd/spi.c b/src/soc/marvell/bg4cd/spi.c new file mode 100644 index 0000000..8ae22d1 --- /dev/null +++ b/src/soc/marvell/bg4cd/spi.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <spi-generic.h> + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + return NULL; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned out_bytes, void *din, unsigned in_bytes) +{ + return 0; +}

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Patch set updated for coreboot: 92a835d cosmos: add template for soc and board files
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9351 -gerrit commit 92a835d15045d428a5955719e6e416aab00f125c Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Oct 8 11:38:52 2014 -0700 cosmos: add template for soc and board files This adds board and soc files as a template for cosmos. BUG=chrome-os-partner:32772 BRANCH=none TEST=Built coreboot for cosmos and veyron_pinky. Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I6e17058afaa629c6aa70c2d195230dba782af526 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fd9dbcf1023a79921c8501bbe09969d65ca9e742 Original-Change-Id: I676bdf460f5dd996dcce1fc422a69882798bc112 Original-Reviewed-on: https://chromium-review.googlesource.com/222050 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/mainboard/google/Kconfig | 3 ++ src/mainboard/google/cosmos/Kconfig | 57 ++++++++++++++++++++++++ src/mainboard/google/cosmos/Makefile.inc | 40 +++++++++++++++++ src/mainboard/google/cosmos/boardid.c | 25 +++++++++++ src/mainboard/google/cosmos/bootblock.c | 24 +++++++++++ src/mainboard/google/cosmos/chromeos.c | 41 ++++++++++++++++++ src/mainboard/google/cosmos/devicetree.cb | 23 ++++++++++ src/mainboard/google/cosmos/mainboard.c | 38 ++++++++++++++++ src/mainboard/google/cosmos/memlayout.ld | 1 + src/mainboard/google/cosmos/reset.c | 26 +++++++++++ src/mainboard/google/cosmos/romstage.c | 72 +++++++++++++++++++++++++++++++ src/soc/Kconfig | 1 + src/soc/Makefile.inc | 1 + src/soc/marvell/Kconfig | 20 +++++++++ src/soc/marvell/Makefile.inc | 20 +++++++++ src/soc/marvell/bg4cd/Kconfig | 52 ++++++++++++++++++++++ src/soc/marvell/bg4cd/Makefile.inc | 46 ++++++++++++++++++++ src/soc/marvell/bg4cd/cbmem.c | 26 +++++++++++ src/soc/marvell/bg4cd/i2c.c | 30 +++++++++++++ src/soc/marvell/bg4cd/i2c.h | 26 +++++++++++ src/soc/marvell/bg4cd/media.c | 25 +++++++++++ src/soc/marvell/bg4cd/memlayout.ld | 39 +++++++++++++++++ src/soc/marvell/bg4cd/monotonic_timer.c | 29 +++++++++++++ src/soc/marvell/bg4cd/sdram.c | 26 +++++++++++ src/soc/marvell/bg4cd/sdram.h | 24 +++++++++++ 25 files changed, 715 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index c193d81..22e8618 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -25,6 +25,8 @@ config BOARD_GOOGLE_BOLT bool "Bolt" config BOARD_GOOGLE_BUTTERFLY bool "Butterfly" +config BOARD_GOOGLE_COSMOS + bool "Cosmos" config BOARD_GOOGLE_DAISY bool "Daisy" config BOARD_GOOGLE_FALCO @@ -68,6 +70,7 @@ endchoice source "src/mainboard/google/bolt/Kconfig" source "src/mainboard/google/butterfly/Kconfig" +source "src/mainboard/google/cosmos/Kconfig" source "src/mainboard/google/daisy/Kconfig" source "src/mainboard/google/falco/Kconfig" source "src/mainboard/google/link/Kconfig" diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig new file mode 100644 index 0000000..4af9986 --- /dev/null +++ b/src/mainboard/google/cosmos/Kconfig @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_COSMOS + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_1024 + select BOARD_ID_SUPPORT + select CHROMEOS + select CHROMEOS_VBNV_FLASH + select SOC_MARVELL_BG4CD + select MAINBOARD_HAS_BOOTBLOCK_INIT + select HAVE_HARD_RESET + select RETURN_FROM_VERSTAGE + +config MAINBOARD_DIR + string + default google/cosmos + +config MAINBOARD_PART_NUMBER + string + default "Cosmos" + +config MAINBOARD_VENDOR + string + default "Google" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +config BOOT_MEDIA_SPI_BUS + int + default 2 + +config DRAM_SIZE_MB + int + default 1024 + +endif # BOARD_GOOGLE_COSMOS diff --git a/src/mainboard/google/cosmos/Makefile.inc b/src/mainboard/google/cosmos/Makefile.inc new file mode 100644 index 0000000..3e970fb --- /dev/null +++ b/src/mainboard/google/cosmos/Makefile.inc @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +bootblock-y += bootblock.c +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += romstage.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c + +bootblock-y += memlayout.ld +verstage-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/cosmos/boardid.c b/src/mainboard/google/cosmos/boardid.c new file mode 100644 index 0000000..8b61891 --- /dev/null +++ b/src/mainboard/google/cosmos/boardid.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boardid.h> + +uint8_t board_id(void) +{ + return -1; +} diff --git a/src/mainboard/google/cosmos/bootblock.c b/src/mainboard/google/cosmos/bootblock.c new file mode 100644 index 0000000..d5bffea --- /dev/null +++ b/src/mainboard/google/cosmos/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/cosmos/chromeos.c b/src/mainboard/google/cosmos/chromeos.c new file mode 100644 index 0000000..0ad05c8 --- /dev/null +++ b/src/mainboard/google/cosmos/chromeos.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} + diff --git a/src/mainboard/google/cosmos/devicetree.cb b/src/mainboard/google/cosmos/devicetree.cb new file mode 100644 index 0000000..b82d57c --- /dev/null +++ b/src/mainboard/google/cosmos/devicetree.cb @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/marvell/bg4cd + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/cosmos/mainboard.c b/src/mainboard/google/cosmos/mainboard.c new file mode 100644 index 0000000..5866fea --- /dev/null +++ b/src/mainboard/google/cosmos/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <boot/coreboot_tables.h> + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ +} diff --git a/src/mainboard/google/cosmos/memlayout.ld b/src/mainboard/google/cosmos/memlayout.ld new file mode 100644 index 0000000..d788b78 --- /dev/null +++ b/src/mainboard/google/cosmos/memlayout.ld @@ -0,0 +1 @@ +#include <soc/marvell/bg4cd/memlayout.ld> diff --git a/src/mainboard/google/cosmos/reset.c b/src/mainboard/google/cosmos/reset.c new file mode 100644 index 0000000..8020fbf --- /dev/null +++ b/src/mainboard/google/cosmos/reset.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <reset.h> + +void hard_reset(void) +{ + while (1) + ; +} diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c new file mode 100644 index 0000000..f3e98e0 --- /dev/null +++ b/src/mainboard/google/cosmos/romstage.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <armv7.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <delay.h> +#include <timestamp.h> +#include <arch/cache.h> +#include <arch/exception.h> +#include <stdlib.h> +#include <program_loading.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/marvell/bg4cd/sdram.h> +#include <symbols.h> +#include "timer.h" + +void main(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + uint64_t start_romstage_time; + uint64_t before_dram_time; + uint64_t after_dram_time; + uint64_t base_time = timestamp_get(); + start_romstage_time = timestamp_get(); +#endif + + console_init(); + +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); +#endif + sdram_init(); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); +#endif + mmu_init(); + mmu_config_range(0, 4096, DCACHE_OFF); + dcache_mmu_enable(); + + cbmem_initialize_empty(); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); +#endif + +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); +#endif + run_ramstage(); +} diff --git a/src/soc/Kconfig b/src/soc/Kconfig index 43c2010..cff6f27 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -1,5 +1,6 @@ source src/soc/imgtec/Kconfig source src/soc/intel/Kconfig +source src/soc/marvell/Kconfig source src/soc/nvidia/Kconfig source src/soc/qualcomm/Kconfig source src/soc/rockchip/Kconfig diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index 543e155..b722323 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -3,6 +3,7 @@ ################################################################################ subdirs-y += imgtec subdirs-y += intel +subdirs-y += marvell subdirs-y += nvidia subdirs-y += qualcomm subdirs-y += rockchip diff --git a/src/soc/marvell/Kconfig b/src/soc/marvell/Kconfig new file mode 100644 index 0000000..95b8c50 --- /dev/null +++ b/src/soc/marvell/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +source src/soc/marvell/bg4cd/Kconfig diff --git a/src/soc/marvell/Makefile.inc b/src/soc/marvell/Makefile.inc new file mode 100644 index 0000000..ef7bcd9 --- /dev/null +++ b/src/soc/marvell/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-$(CONFIG_SOC_MARVELL_BG4CD) += bg4cd diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig new file mode 100644 index 0000000..0a9778d --- /dev/null +++ b/src/soc/marvell/bg4cd/Kconfig @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOC_MARVELL_BG4CD + bool + default n + select CPU_HAS_BOOTBLOCK_INIT + select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY + select EARLY_CONSOLE + select DYNAMIC_CBMEM + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + select BOOTBLOCK_CONSOLE + +if SOC_MARVELL_BG4CD + +config BOOTBLOCK_CPU_INIT + string + default "soc/marvell/bg4cd/bootblock.c" + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x0008000 + +config CBFS_ROM_OFFSET + hex + default 0x0018000 + +endif diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc new file mode 100644 index 0000000..7d114dd --- /dev/null +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bootblock-y += cbmem.c +bootblock-y += monotonic_timer.c +bootblock-y += media.c +bootblock-y += i2c.c + +verstage-y += monotonic_timer.c +verstage-y += i2c.c +verstage-y += media.c + +romstage-y += cbmem.c +romstage-y += monotonic_timer.c +romstage-y += i2c.c +romstage-y += media.c +romstage-y += sdram.c + +ramstage-y += cbmem.c +ramstage-y += monotonic_timer.c +ramstage-y += i2c.c +ramstage-y += media.c + +$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf + cp $< $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + @mkdir -p $(dir $@) + @mv $< $@ diff --git a/src/soc/marvell/bg4cd/cbmem.c b/src/soc/marvell/bg4cd/cbmem.c new file mode 100644 index 0000000..168673d --- /dev/null +++ b/src/soc/marvell/bg4cd/cbmem.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <stddef.h> + +void *cbmem_top(void) +{ + return NULL; +} diff --git a/src/soc/marvell/bg4cd/i2c.c b/src/soc/marvell/bg4cd/i2c.c new file mode 100644 index 0000000..1aa02d0 --- /dev/null +++ b/src/soc/marvell/bg4cd/i2c.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/i2c.h> +#include "i2c.h" + +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) +{ + return 0; +} + +void i2c_init(unsigned int bus, unsigned int hz) +{ +} diff --git a/src/soc/marvell/bg4cd/i2c.h b/src/soc/marvell/bg4cd/i2c.h new file mode 100644 index 0000000..40db31a --- /dev/null +++ b/src/soc/marvell/bg4cd/i2c.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MARVELL_BG4CD_I2C_H__ +#define __SOC_MARVELL_BG4CD_I2C_H__ + +void i2c_init(unsigned int bus, unsigned int hz); + +#endif + diff --git a/src/soc/marvell/bg4cd/media.c b/src/soc/marvell/bg4cd/media.c new file mode 100644 index 0000000..5a4dc5f --- /dev/null +++ b/src/soc/marvell/bg4cd/media.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/marvell/bg4cd/memlayout.ld b/src/soc/marvell/bg4cd/memlayout.ld new file mode 100644 index 0000000..45cf395 --- /dev/null +++ b/src/soc/marvell/bg4cd/memlayout.ld @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + + SRAM_START(0x80000000) + TTB(0x80000000, 16K) + BOOTBLOCK(0x80004004, 16K - 4) + VBOOT2_WORK(0x80008000, 16K) + OVERLAP_VERSTAGE_ROMSTAGE(0x8000C000, 40K) + PRERAM_CBFS_CACHE(0x80016000, 4K) + STACK(0x80017000, 4K) + SRAM_END(0x80018000) +} diff --git a/src/soc/marvell/bg4cd/monotonic_timer.c b/src/soc/marvell/bg4cd/monotonic_timer.c new file mode 100644 index 0000000..a84b036 --- /dev/null +++ b/src/soc/marvell/bg4cd/monotonic_timer.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ +} + +void init_timer(void) +{ +} diff --git a/src/soc/marvell/bg4cd/sdram.c b/src/soc/marvell/bg4cd/sdram.c new file mode 100644 index 0000000..1b5575b --- /dev/null +++ b/src/soc/marvell/bg4cd/sdram.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include "sdram.h" + +void sdram_init(void) +{ + printk(BIOS_INFO, "Starting SDRAM initialization...\n"); + printk(BIOS_INFO, "Finish SDRAM initialization...\n"); +} diff --git a/src/soc/marvell/bg4cd/sdram.h b/src/soc/marvell/bg4cd/sdram.h new file mode 100644 index 0000000..6850d27 --- /dev/null +++ b/src/soc/marvell/bg4cd/sdram.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MARVELL_BG4CD_SDRAM_H__ +#define __SOC_MARVELL_BG4CD_SDRAM_H__ + +void sdram_init(void); +#endif

1 0

Patch set updated for coreboot: 51205a6 libpayload: Add drivers for bg4cd
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9360 -gerrit commit 51205a6b6350bfc8cf2ea9fc8c5ca9da93911650 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Oct 9 09:56:43 2014 -0700 libpayload: Add drivers for bg4cd BUG=chrome-os-partner:32772 BRANCH=none TEST=Built chromeos-bootimage Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1 Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7 Original-Reviewed-on: https://chromium-review.googlesource.com/222662 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- payloads/libpayload/Config.in | 5 +++ payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/serial/bg4cd.c | 49 ++++++++++++++++++++++++++++++ payloads/libpayload/drivers/timer/bg4cd.c | 30 ++++++++++++++++++ 4 files changed, 85 insertions(+) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 8ac96b5..cb1d529 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -214,6 +214,11 @@ config IPQ806X_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config BG4CD_SERIAL_CONSOLE + bool "Serial port driver for Marvell's BG4CD" + depends on SERIAL_CONSOLE + default n + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 4a569c4..6dc1403 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -38,6 +38,7 @@ libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c libc-$(CONFIG_LP_TEGRA_SERIAL_CONSOLE) += serial/tegra.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c libc-$(CONFIG_LP_RK_SERIAL_CONSOLE) += serial/rk_serial.c +libc-$(CONFIG_LP_BG4CD_SERIAL_CONSOLE) += serial/bg4cd.c libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c diff --git a/payloads/libpayload/drivers/serial/bg4cd.c b/payloads/libpayload/drivers/serial/bg4cd.c new file mode 100644 index 0000000..9dfa996 --- /dev/null +++ b/payloads/libpayload/drivers/serial/bg4cd.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <libpayload-config.h> +#include <libpayload.h> + +void serial_putchar(unsigned int c) +{ +} + +int serial_havechar(void) +{ + return 0; +} + +int serial_getchar(void) +{ + return 0; +} + +static struct console_input_driver consin = { + .havekey = &serial_havechar, + .getchar = &serial_getchar +}; + +static struct console_output_driver consout = { + .putchar = &serial_putchar +}; + +void serial_console_init(void) +{ + console_add_input_driver(&consin); + console_add_output_driver(&consout); +} diff --git a/payloads/libpayload/drivers/timer/bg4cd.c b/payloads/libpayload/drivers/timer/bg4cd.c new file mode 100644 index 0000000..34872a3 --- /dev/null +++ b/payloads/libpayload/drivers/timer/bg4cd.c @@ -0,0 +1,30 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <libpayload.h> + +uint64_t timer_hz(void) +{ + return 0; +} + +uint64_t timer_raw_value(void) +{ + return 0; +}

1 0

New patch to review for coreboot: 23e685a cosmos: add template files for libpayload
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9360 -gerrit commit 23e685a5d2d621b40adad3bc461619bf86ec7164 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Oct 9 09:56:43 2014 -0700 cosmos: add template files for libpayload this adds template files to build chromeos-bootimage. it also adjusts coreboot.rom size and flash map offset with respect to the board's fmap.dts. BUG=chrome-os-partner:32772 BRANCH=none TEST=Built chromeos-bootimage Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1 Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7 Original-Reviewed-on: https://chromium-review.googlesource.com/222662 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- payloads/libpayload/Config.in | 5 ++ payloads/libpayload/configs/config.cosmos | 76 ++++++++++++++++++++++++++++++ payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/serial/bg4cd.c | 49 +++++++++++++++++++ payloads/libpayload/drivers/timer/bg4cd.c | 30 ++++++++++++ 5 files changed, 161 insertions(+) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 8ac96b5..cb1d529 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -214,6 +214,11 @@ config IPQ806X_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config BG4CD_SERIAL_CONSOLE + bool "Serial port driver for Marvell's BG4CD" + depends on SERIAL_CONSOLE + default n + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.cosmos b/payloads/libpayload/configs/config.cosmos new file mode 100644 index 0000000..06441a6 --- /dev/null +++ b/payloads/libpayload/configs/config.cosmos @@ -0,0 +1,76 @@ +# +# Automatically generated make config: don't edit +# libpayload version: 0.2.0 +# Tue Oct 14 18:32:48 2014 +# + +# +# Generic Options +# +CONFIG_LP_GPL=y +# CONFIG_LP_EXPERIMENTAL is not set +# CONFIG_LP_OBSOLETE is not set +# CONFIG_LP_DEVELOPER is not set +# CONFIG_LP_REMOTEGDB is not set +CONFIG_LP_CHROMEOS=y + +# +# Architecture Options +# +CONFIG_LP_ARCH_ARM=y +# CONFIG_LP_ARCH_X86 is not set +# CONFIG_LP_ARCH_ARM64 is not set +# CONFIG_LP_MEMMAP_RAM_ONLY is not set + +# +# Standard Libraries +# +CONFIG_LP_LIBC=y +# CONFIG_LP_CURSES is not set +# CONFIG_LP_TINYCURSES is not set +# CONFIG_LP_PDCURSES is not set +CONFIG_LP_CBFS=y +CONFIG_LP_LZMA=y + +# +# Console Options +# +CONFIG_LP_SKIP_CONSOLE_INIT=y +CONFIG_LP_CBMEM_CONSOLE=y +CONFIG_LP_SERIAL_CONSOLE=y +# CONFIG_LP_8250_SERIAL_CONSOLE is not set +# CONFIG_LP_S5P_SERIAL_CONSOLE is not set +# CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set +# CONFIG_LP_RK_SERIAL_CONSOLE is not set +# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set +CONFIG_LP_BG4CD_SERIAL_CONSOLE=y +# CONFIG_LP_SERIAL_SET_SPEED is not set +# CONFIG_LP_SERIAL_ACS_FALLBACK is not set +# CONFIG_LP_VIDEO_CONSOLE is not set +# CONFIG_LP_PC_KEYBOARD is not set + +# +# Drivers +# +# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set +# CONFIG_LP_STORAGE is not set +# CONFIG_LP_TIMER_NONE is not set +# CONFIG_LP_TIMER_MCT is not set +# CONFIG_LP_TIMER_TEGRA_1US is not set +# CONFIG_LP_TIMER_IPQ806X is not set +# CONFIG_LP_TIMER_RK is not set +CONFIG_LP_TIMER_BG4CD=y +CONFIG_LP_USB=y +# CONFIG_LP_USB_OHCI is not set +# CONFIG_LP_USB_EHCI is not set +# CONFIG_LP_USB_XHCI is not set +# CONFIG_LP_USB_DWC2 is not set +# CONFIG_LP_USB_HID is not set +# CONFIG_LP_USB_HUB is not set +# CONFIG_LP_USB_MSC is not set +# CONFIG_LP_USB_PCI is not set +# CONFIG_LP_USB_GEN_HUB is not set +# CONFIG_LP_BIG_ENDIAN is not set +CONFIG_LP_LITTLE_ENDIAN=y +# CONFIG_LP_IO_ADDRESS_SPACE is not set +CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 4a569c4..6dc1403 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -38,6 +38,7 @@ libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c libc-$(CONFIG_LP_TEGRA_SERIAL_CONSOLE) += serial/tegra.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c libc-$(CONFIG_LP_RK_SERIAL_CONSOLE) += serial/rk_serial.c +libc-$(CONFIG_LP_BG4CD_SERIAL_CONSOLE) += serial/bg4cd.c libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c diff --git a/payloads/libpayload/drivers/serial/bg4cd.c b/payloads/libpayload/drivers/serial/bg4cd.c new file mode 100644 index 0000000..9dfa996 --- /dev/null +++ b/payloads/libpayload/drivers/serial/bg4cd.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <libpayload-config.h> +#include <libpayload.h> + +void serial_putchar(unsigned int c) +{ +} + +int serial_havechar(void) +{ + return 0; +} + +int serial_getchar(void) +{ + return 0; +} + +static struct console_input_driver consin = { + .havekey = &serial_havechar, + .getchar = &serial_getchar +}; + +static struct console_output_driver consout = { + .putchar = &serial_putchar +}; + +void serial_console_init(void) +{ + console_add_input_driver(&consin); + console_add_output_driver(&consout); +} diff --git a/payloads/libpayload/drivers/timer/bg4cd.c b/payloads/libpayload/drivers/timer/bg4cd.c new file mode 100644 index 0000000..34872a3 --- /dev/null +++ b/payloads/libpayload/drivers/timer/bg4cd.c @@ -0,0 +1,30 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <libpayload.h> + +uint64_t timer_hz(void) +{ + return 0; +} + +uint64_t timer_raw_value(void) +{ + return 0; +}

1 0

New patch to review for coreboot: 77844d9 arm64: Add timestamp.c to bootblock and verstage
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9359 -gerrit commit 77844d98184c43304ecab4ac1cda7278ac9ef820 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Oct 14 15:25:39 2014 -0700 arm64: Add timestamp.c to bootblock and verstage BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully Change-Id: Ia4715fd7a852b82c66d436eb12988f8e3290b9b0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0d88dd324a8ee0ace51e9ad2343d81cc828a4f34 Original-Change-Id: I662163848a772018f1e8eb003aa3d3bc06e80e98 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223347 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 59330a5..e401017 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -63,6 +63,7 @@ bootblock-y += stage_entry.S bootblock-y += stages.c bootblock-y += eabi_compat.c bootblock-y += transition.c transition_asm.S +bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c bootblock-y += ../../lib/memset.c bootblock-y += ../../lib/memcpy.c @@ -93,6 +94,7 @@ verstage-y += ../../lib/memset.c verstage-y += ../../lib/memcpy.c verstage-y += ../../lib/memmove.c verstage-y += stages.c +verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c endif # CONFIG_ARCH_VERSTAGE_ARM64

1 0

New patch to review for coreboot: 5bdf2eb bg4cd: Change all SoC headers to <soc/headername.h> system
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9358 -gerrit commit 5bdf2eb2b03feae99176d2372cb01e6e559093f7 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 20 14:21:22 2014 -0700 bg4cd: Change all SoC headers to <soc/headername.h> system This patch aligns bg4cd to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Cosmos. Change-Id: I32a4407f7deb2b1752b6220a140352724f320637 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0b6bb6990417863010258632374c3f5ac19350c9 Original-Change-Id: Ia5299659ad186f2e7d698adfa7562396e747473f Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224506 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/cosmos/memlayout.ld | 2 +- src/mainboard/google/cosmos/romstage.c | 17 +++++------ src/soc/marvell/bg4cd/Makefile.inc | 2 ++ src/soc/marvell/bg4cd/i2c.c | 2 +- src/soc/marvell/bg4cd/i2c.h | 26 ----------------- src/soc/marvell/bg4cd/include/soc/i2c.h | 26 +++++++++++++++++ src/soc/marvell/bg4cd/include/soc/memlayout.ld | 39 ++++++++++++++++++++++++++ src/soc/marvell/bg4cd/include/soc/sdram.h | 24 ++++++++++++++++ src/soc/marvell/bg4cd/memlayout.ld | 39 -------------------------- src/soc/marvell/bg4cd/sdram.c | 2 +- src/soc/marvell/bg4cd/sdram.h | 24 ---------------- 11 files changed, 103 insertions(+), 100 deletions(-) diff --git a/src/mainboard/google/cosmos/memlayout.ld b/src/mainboard/google/cosmos/memlayout.ld index d788b78..ead7f47 100644 --- a/src/mainboard/google/cosmos/memlayout.ld +++ b/src/mainboard/google/cosmos/memlayout.ld @@ -1 +1 @@ -#include <soc/marvell/bg4cd/memlayout.ld> +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c index a78debe..e80d331 100644 --- a/src/mainboard/google/cosmos/romstage.c +++ b/src/mainboard/google/cosmos/romstage.c @@ -17,20 +17,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> +#include <arch/cache.h> +#include <arch/exception.h> +#include <arch/stages.h> #include <armv7.h> #include <cbfs.h> -#include <console/console.h> -#include <arch/stages.h> #include <cbmem.h> +#include <console/console.h> #include <delay.h> -#include <timestamp.h> -#include <arch/cache.h> -#include <arch/exception.h> +#include <soc/sdram.h> #include <stdlib.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/marvell/bg4cd/sdram.h> #include <symbols.h> +#include <timestamp.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + #include "timer.h" void main(void) diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index 0271fc7..01bbee4 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -42,6 +42,8 @@ ramstage-y += monotonic_timer.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_CONSOLE_SERIAL) += uart.c +CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/ + $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@ diff --git a/src/soc/marvell/bg4cd/i2c.c b/src/soc/marvell/bg4cd/i2c.c index 1aa02d0..16ad9ab 100644 --- a/src/soc/marvell/bg4cd/i2c.c +++ b/src/soc/marvell/bg4cd/i2c.c @@ -18,7 +18,7 @@ */ #include <device/i2c.h> -#include "i2c.h" +#include <soc/i2c.h> int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) { diff --git a/src/soc/marvell/bg4cd/i2c.h b/src/soc/marvell/bg4cd/i2c.h deleted file mode 100644 index 40db31a..0000000 --- a/src/soc/marvell/bg4cd/i2c.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_MARVELL_BG4CD_I2C_H__ -#define __SOC_MARVELL_BG4CD_I2C_H__ - -void i2c_init(unsigned int bus, unsigned int hz); - -#endif - diff --git a/src/soc/marvell/bg4cd/include/soc/i2c.h b/src/soc/marvell/bg4cd/include/soc/i2c.h new file mode 100644 index 0000000..40db31a --- /dev/null +++ b/src/soc/marvell/bg4cd/include/soc/i2c.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MARVELL_BG4CD_I2C_H__ +#define __SOC_MARVELL_BG4CD_I2C_H__ + +void i2c_init(unsigned int bus, unsigned int hz); + +#endif + diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld new file mode 100644 index 0000000..45cf395 --- /dev/null +++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + + SRAM_START(0x80000000) + TTB(0x80000000, 16K) + BOOTBLOCK(0x80004004, 16K - 4) + VBOOT2_WORK(0x80008000, 16K) + OVERLAP_VERSTAGE_ROMSTAGE(0x8000C000, 40K) + PRERAM_CBFS_CACHE(0x80016000, 4K) + STACK(0x80017000, 4K) + SRAM_END(0x80018000) +} diff --git a/src/soc/marvell/bg4cd/include/soc/sdram.h b/src/soc/marvell/bg4cd/include/soc/sdram.h new file mode 100644 index 0000000..6850d27 --- /dev/null +++ b/src/soc/marvell/bg4cd/include/soc/sdram.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MARVELL_BG4CD_SDRAM_H__ +#define __SOC_MARVELL_BG4CD_SDRAM_H__ + +void sdram_init(void); +#endif diff --git a/src/soc/marvell/bg4cd/memlayout.ld b/src/soc/marvell/bg4cd/memlayout.ld deleted file mode 100644 index 45cf395..0000000 --- a/src/soc/marvell/bg4cd/memlayout.ld +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> - -#include <arch/header.ld> - -SECTIONS -{ - DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) - POSTRAM_CBFS_CACHE(0x01000000, 1M) - - SRAM_START(0x80000000) - TTB(0x80000000, 16K) - BOOTBLOCK(0x80004004, 16K - 4) - VBOOT2_WORK(0x80008000, 16K) - OVERLAP_VERSTAGE_ROMSTAGE(0x8000C000, 40K) - PRERAM_CBFS_CACHE(0x80016000, 4K) - STACK(0x80017000, 4K) - SRAM_END(0x80018000) -} diff --git a/src/soc/marvell/bg4cd/sdram.c b/src/soc/marvell/bg4cd/sdram.c index 1b5575b..0ebee15 100644 --- a/src/soc/marvell/bg4cd/sdram.c +++ b/src/soc/marvell/bg4cd/sdram.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> -#include "sdram.h" +#include <soc/sdram.h> void sdram_init(void) { diff --git a/src/soc/marvell/bg4cd/sdram.h b/src/soc/marvell/bg4cd/sdram.h deleted file mode 100644 index 6850d27..0000000 --- a/src/soc/marvell/bg4cd/sdram.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_MARVELL_BG4CD_SDRAM_H__ -#define __SOC_MARVELL_BG4CD_SDRAM_H__ - -void sdram_init(void); -#endif

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New patch to review for coreboot: 3fdac00 cosmos: add SPI configuration options
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9357 -gerrit commit 3fdac00944b992de18a2266bc03be39228e04c23 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 16 11:35:25 2014 -0700 cosmos: add SPI configuration options Enable SPI support for cosmos, the earlier patches provided plumbing for the CBFS SPI wrapper support. BRANCH=none BUG=chrome-os-partner:32631 TEST=cosmos image builds with the SPI driver skeleton compiled in Change-Id: Ieb869d3c0a16a6f7460739d8959e972c23866677 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7b1d095e5df6a864d3564bbf7a20cc211f75629a Original-Change-Id: If9dd80cb96120d34a0865f7882cd62e45fed749d Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223752 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/cosmos/Kconfig | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig index ccce6a8..648d31b 100644 --- a/src/mainboard/google/cosmos/Kconfig +++ b/src/mainboard/google/cosmos/Kconfig @@ -24,10 +24,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ID_SUPPORT select CHROMEOS select CHROMEOS_VBNV_FLASH - select SOC_MARVELL_BG4CD - select MAINBOARD_HAS_BOOTBLOCK_INIT + select COMMON_CBFS_SPI_WRAPPER select HAVE_HARD_RESET + select MAINBOARD_HAS_BOOTBLOCK_INIT select RETURN_FROM_VERSTAGE + select SOC_MARVELL_BG4CD + select SPI_FLASH + select SPI_FLASH_SPANSION config MAINBOARD_DIR string

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New patch to review for coreboot: f080155 bg4cd: provide support for the SPI_WRAPPER configuration mode
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9356 -gerrit commit f0801552c2fc21c527cf994a84b6ad9d0870044a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 16 11:20:15 2014 -0700 bg4cd: provide support for the SPI_WRAPPER configuration mode The SOC code should include the SPI controller driver when configured. With the upcoming configuration change media.c is not needed anymore. BRANCH=none BUG=chrome-os-partner:32631 TEST=the driver compiles when the upcoming patches are applied Change-Id: I8212f191b7d80f0bee86f746813edaf8e5ee6db1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fd4853be5157247bb73fc22b9d4f8300228fe6ce Original-Change-Id: If7e12e2fb04e63c36d9696d13e08397b91a77a8c Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223750 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/marvell/bg4cd/Makefile.inc | 8 ++++---- src/soc/marvell/bg4cd/media.c | 25 ------------------------- 2 files changed, 4 insertions(+), 29 deletions(-) diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index 7367c3d..0271fc7 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -20,26 +20,26 @@ bootblock-y += bootblock.c bootblock-y += cbmem.c bootblock-y += i2c.c -bootblock-y += media.c bootblock-y += monotonic_timer.c +bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c verstage-y += i2c.c -verstage-y += media.c verstage-y += monotonic_timer.c +verstage-$(CONFIG_SPI_FLASH) += spi.c verstage-$(CONFIG_CONSOLE_SERIAL) += uart.c romstage-y += cbmem.c romstage-y += i2c.c -romstage-y += media.c romstage-y += monotonic_timer.c romstage-y += sdram.c +romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-$(CONFIG_CONSOLE_SERIAL) += uart.c ramstage-y += cbmem.c ramstage-y += i2c.c -ramstage-y += media.c ramstage-y += monotonic_timer.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_CONSOLE_SERIAL) += uart.c $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf diff --git a/src/soc/marvell/bg4cd/media.c b/src/soc/marvell/bg4cd/media.c deleted file mode 100644 index 5a4dc5f..0000000 --- a/src/soc/marvell/bg4cd/media.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cbfs.h> - -int init_default_cbfs_media(struct cbfs_media *media) -{ - return 0; -}

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New patch to review for coreboot: 84859de bg4cd: add SPI controller driver skeleton
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9355 -gerrit commit 84859deb533f19e19c99ea3c3b7955f1f3a72079 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 16 11:07:41 2014 -0700 bg4cd: add SPI controller driver skeleton This file provides the SOC specific SPI driver API, it needs to be filled up with code. Function descriptions can be found in src/include/spi-generic.h. BRANCH=none BUG=chrome-os-partner:32631 TEST=compiles with the upcoming patches applied. Change-Id: I3546d5f9fb2971f4ccb7a57ce8164fd77686af72 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0583f17fe3f6a258321765b91eae608e33577afe Original-Change-Id: I0ee04ca17874a13403007bba80d5e8a7708bc625 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223719 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/marvell/bg4cd/spi.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/soc/marvell/bg4cd/spi.c b/src/soc/marvell/bg4cd/spi.c new file mode 100644 index 0000000..8ae22d1 --- /dev/null +++ b/src/soc/marvell/bg4cd/spi.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <spi-generic.h> + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + return NULL; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned out_bytes, void *din, unsigned in_bytes) +{ + return 0; +}

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New patch to review for coreboot: 561b237 cosmos: enable SOC uart driver
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9354 -gerrit commit 561b2377ada1328e01729f7fa4ea017378ad97a8 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Oct 15 16:32:05 2014 -0700 cosmos: enable SOC uart driver Add necessary configuration to enable the inclusion of the UART driver into the image when serial console is enabled. BRANCH=none BUG=chrome-os-partner:32631 TEST=building with serial console enabled includes the skeleton uart driver into the build Change-Id: I9ef14c93fd4534ba3d6c6bafdf908cb7f1a3b14b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3b49c258910af63d51feca3c461d589d0a41221e Original-Change-Id: I6cbd110f600169021901b3f864d596404587fbcc Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223598 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/marvell/bg4cd/Kconfig | 2 ++ src/soc/marvell/bg4cd/Makefile.inc | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig index 759ba46..8906402 100644 --- a/src/soc/marvell/bg4cd/Kconfig +++ b/src/soc/marvell/bg4cd/Kconfig @@ -30,6 +30,8 @@ config SOC_MARVELL_BG4CD select EARLY_CONSOLE select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER + select HAVE_UART_MEMORY_MAPPED + select HAVE_UART_SPECIAL if SOC_MARVELL_BG4CD diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index 3be5f63..7367c3d 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -22,21 +22,25 @@ bootblock-y += cbmem.c bootblock-y += i2c.c bootblock-y += media.c bootblock-y += monotonic_timer.c +bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c verstage-y += i2c.c verstage-y += media.c verstage-y += monotonic_timer.c +verstage-$(CONFIG_CONSOLE_SERIAL) += uart.c romstage-y += cbmem.c romstage-y += i2c.c romstage-y += media.c romstage-y += monotonic_timer.c romstage-y += sdram.c +romstage-$(CONFIG_CONSOLE_SERIAL) += uart.c ramstage-y += cbmem.c ramstage-y += i2c.c ramstage-y += media.c ramstage-y += monotonic_timer.c +ramstage-$(CONFIG_CONSOLE_SERIAL) += uart.c $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@

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coreboot-gerrit April 2015