coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 32a7a81 pistachio: modify memory layout
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9337 -gerrit commit 32a7a81c7e7a5ae51cdebf5fc02c51bc23b3f375 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Nov 11 20:14:47 2014 -0800 pistachio: modify memory layout With the code now running on the FPGA board it makes sense to correct the memory layout definitions to match the actual hardware. Note that the latest FPGA board firmware introduced support of the additional 128KB of SRAM (called GRAM) at base address of 0x9a000000. These are still interim values, which will be tweaked when the actual bring up board is available. BRANCH=none BUG=chrome-os-partner:31438 TEST=the code put into SPI NOR flash boots all the way to ramstage. Change-Id: I00aa5bc3aabba50df2187bb208cf2fcd11b26b3d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a6378be5cd304744b40c57a34d7a276233d45779 Original-Change-Id: I50183c2d5f9017801d5c8a7a7addf08efa492b35 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229203 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 21c3d73..554ebfc 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -21,18 +21,19 @@ #include <arch/header.ld> -/* TODO: This should be revised by someone who understands the SoC better. */ - SECTIONS { - CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */ - DRAM_START(0x80000000) RAMSTAGE(0x80000000, 128K) - /* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */ - BOOTBLOCK(0x9B000000, 16K) - ROMSTAGE(0x9B004000, 40K) - STACK(0x9B00E000, 6K) - PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K) + /* GRAM becomes the SRAM. */ + SRAM_START(0x9a000000) + BOOTBLOCK(0x9a000000, 16K) + ROMSTAGE(0x9a004000, 32K) + STACK(0x9a01c000, 8K) + PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K) + SRAM_END(0x9a020000) + + /* Let's use SRAM for CBFS cache. */ + CBFS_CACHE(0x9b000000, 64K) }

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New patch to review for coreboot: c6ce82b mips: add c0 register access plumbing
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9336 -gerrit commit c6ce82b3b9eb08bc4776377472999b7f725e86c5 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Nov 5 17:51:19 2014 -0800 mips: add c0 register access plumbing C0 is a coprocessor register set defined in certain MIPS architectures. This patch adds macros necessary to access the registers and a couple of helper macros to access two particular registers needed in the next patch. The definitions come straight from arch/mips/include/asm/mipsregs.h in the 3.14 kernel tree. BRANCH=none BUG=chrome-os-partner:31438 TEST=the following patch demonstrates timer counter C0 register configuration and use. Change-Id: Ia5d52ffa75f2dd66d4cee3a4ed0af5122ccb2113 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: eb3d69eaf1561ca0b995720c24dafe2e6e22707d Original-Change-Id: Ia4b1da40ecc1a03cf1cba0c648d42cd189fbcf93 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227887 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/mips/include/arch/cpu.h | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 0ac9f31..4f4c376 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -40,4 +40,52 @@ struct cpu_info { #endif /* !__PRE_RAM__ */ +/*************************************************************************** + * The following section was copied from arch/mips/include/asm/mipsregs.h in + * the 3.14 kernel tree. + */ + +/* + * Macros to access the system control coprocessor + */ + +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +/* Shortcuts to access various internal registers, keep adding as needed. */ +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, (val)) + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val)) + +#define C0_CAUSE_DC (1 << 27) +/**************************************************************************/ + #endif /* __MIPS_ARCH_CPU_H */

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New patch to review for coreboot: 9ea6535 pistachio: Change all SoC headers to <soc/headername.h> system
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9335 -gerrit commit 9ea6535d63e3805bbcb4d53a9c5e9994ab6e30ec Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 20 13:22:00 2014 -0700 pistachio: Change all SoC headers to <soc/headername.h> system This patch aligns pistachio to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Urara. Change-Id: I0609b307695ba6a922384ac34dd604bffcb20692 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0a577918babf26adf10baa0f56a7065f5659d285 Original-Change-Id: I3ed405a3efdeec28965538d19a22f2b5b8204f01 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224503 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/urara/memlayout.ld | 2 +- src/soc/imgtec/pistachio/Makefile.inc | 2 + src/soc/imgtec/pistachio/cpu.h | 24 -- src/soc/imgtec/pistachio/include/soc/cpu.h | 24 ++ src/soc/imgtec/pistachio/include/soc/memlayout.ld | 38 +++ src/soc/imgtec/pistachio/include/soc/spi.h | 358 ++++++++++++++++++++++ src/soc/imgtec/pistachio/memlayout.ld | 38 --- src/soc/imgtec/pistachio/spi.c | 4 +- src/soc/imgtec/pistachio/spi.h | 358 ---------------------- 9 files changed, 425 insertions(+), 423 deletions(-) diff --git a/src/mainboard/google/urara/memlayout.ld b/src/mainboard/google/urara/memlayout.ld index ab0b4dd..ead7f47 100644 --- a/src/mainboard/google/urara/memlayout.ld +++ b/src/mainboard/google/urara/memlayout.ld @@ -1 +1 @@ -#include <soc/imgtec/pistachio/memlayout.ld> +#include <soc/memlayout.ld> diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index d052c8f..e955968 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -42,6 +42,8 @@ romstage-y += romstage.c romstage-y += monotonic_timer.c romstage-y += timestamp.c +CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/ + # Generate the actual coreboot bootblock code $(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" diff --git a/src/soc/imgtec/pistachio/cpu.h b/src/soc/imgtec/pistachio/cpu.h deleted file mode 100644 index c61c58d..0000000 --- a/src/soc/imgtec/pistachio/cpu.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_DANUBE_CPU_H__ -#define __SOC_IMGTEC_DANUBE_CPU_H__ - -#define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 -#define IMG_SPIM1_BASE_ADDRESS 0xB8101000 - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h new file mode 100644 index 0000000..c61c58d --- /dev/null +++ b/src/soc/imgtec/pistachio/include/soc/cpu.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __SOC_IMGTEC_DANUBE_CPU_H__ +#define __SOC_IMGTEC_DANUBE_CPU_H__ + +#define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 +#define IMG_SPIM1_BASE_ADDRESS 0xB8101000 + +#endif diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld new file mode 100644 index 0000000..21c3d73 --- /dev/null +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* TODO: This should be revised by someone who understands the SoC better. */ + +SECTIONS +{ + CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */ + + DRAM_START(0x80000000) + RAMSTAGE(0x80000000, 128K) + + /* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */ + BOOTBLOCK(0x9B000000, 16K) + ROMSTAGE(0x9B004000, 40K) + STACK(0x9B00E000, 6K) + PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K) +} diff --git a/src/soc/imgtec/pistachio/include/soc/spi.h b/src/soc/imgtec/pistachio/include/soc/spi.h new file mode 100644 index 0000000..91d6d55 --- /dev/null +++ b/src/soc/imgtec/pistachio/include/soc/spi.h @@ -0,0 +1,358 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef __SOC_IMGTEC_DANUBE_SPI_H__ +#define __SOC_IMGTEC_DANUBE_SPI_H__ + +#include <arch/types.h> +#include <arch/io.h> + +#define spi_read_reg_field(regval, field) \ +( \ + ((field##_MASK) == 0xFFFFFFFF) ? \ + (regval) : \ + (((regval) & (field##_MASK)) >> (field##_SHIFT))\ +) + +#define spi_write_reg_field(regval, field, val) \ +( \ + ((field##_MASK) == 0xFFFFFFFF) ? \ + (val) : \ + (((regval) & ~(field##_MASK)) | \ + (((val) << (field##_SHIFT)) & (field##_MASK))) \ +) + +/* + * Parameter register + * Each of these corresponds to a single port (ie CS line) in the interface + * Fields Name Description + * ====== ==== =========== + * b31:24 CLK_RATE Bit Clock rate = (24.576 * value / 512) MHz + * b23:16 CS_SETUP Chip Select setup = (40 * value) ns + * b15:8 CS_HOLD Chip Select hold = (40 * value) ns + * b7:0 CS_DELAY Chip Select delay = (40 * value) ns + */ + +#define SPIM_CLK_DIVIDE_MASK (0xFF000000) +#define SPIM_CS_SETUP_MASK (0x00FF0000) +#define SPIM_CS_HOLD_MASK (0x0000FF00) +#define SPIM_CS_DELAY_MASK (0x000000FF) +#define SPIM_CS_PARAM_MASK (SPIM_CS_SETUP_MASK \ + | SPIM_CS_HOLD_MASK \ + | SPIM_CS_DELAY_MASK) + +#define SPIM_CLK_DIVIDE_SHIFT (24) +#define SPIM_CS_SETUP_SHIFT (16) +#define SPIM_CS_HOLD_SHIFT (8) +#define SPIM_CS_DELAY_SHIFT (0) +#define SPIM_CS_PARAM_SHIFT (0) + +/* Control register */ + +#define SPFI_DRIBBLE_COUNT_MASK (0x000e0000) +#define SPFI_MEMORY_IF_MASK (0x00008000) +#define SPIM_BYTE_DELAY_MASK (0x00004000) +#define SPIM_CS_DEASSERT_MASK (0x00002000) +#define SPIM_CONTINUE_MASK (0x00001000) +#define SPIM_SOFT_RESET_MASK (0x00000800) +#define SPIM_SEND_DMA_MASK (0x00000400) +#define SPIM_GET_DMA_MASK (0x00000200) +#define SPIM_EDGE_TX_RX_MASK (0x00000100) +#define SPFI_TRNSFR_MODE_MASK (0x000000e0) +#define SPFI_TRNSFR_MODE_DQ_MASK (0x0000001c) +#define SPFI_TX_RX_MASK (0x00000002) +#define SPFI_EN_MASK (0x00000001) + +#define SPFI_DRIBBLE_COUNT_SHIFT (17) +#define SPFI_MEMORY_IF_SHIFT (15) +#define SPIM_BYTE_DELAY_SHIFT (14) +#define SPIM_CS_DEASSERT_SHIFT (13) +#define SPIM_CONTINUE_SHIFT (12) +#define SPIM_SOFT_RESET_SHIFT (11) +#define SPIM_SEND_DMA_SHIFT (10) +#define SPIM_GET_DMA_SHIFT (9) +#define SPIM_EDGE_TX_RX_SHIFT (8) +#define SPFI_TRNSFR_MODE_SHIFT (5) +#define SPFI_TRNSFR_MODE_DQ_SHIFT (2) +#define SPFI_TX_RX_SHIFT (1) +#define SPFI_EN_SHIFT (0) + +/* Transaction register */ + +#define SPFI_TSIZE_MASK (0xffff0000) +#define SPFI_CMD_LENGTH_MASK (0x0000e000) +#define SPFI_ADDR_LENGTH_MASK (0x00001c00) +#define SPFI_DUMMY_LENGTH_MASK (0x000003e0) +#define SPFI_PI_LENGTH_MASK (0x0000001c) + +#define SPFI_TSIZE_SHIFT (16) +#define SPFI_CMD_LENGTH_SHIFT (13) +#define SPFI_ADDR_LENGTH_SHIFT (10) +#define SPFI_DUMMY_LENGTH_SHIFT (5) +#define SPFI_PI_LENGTH_SHIFT (2) + +/* Port state register */ + +#define SPFI_PORT_SELECT_MASK (0x00700000) +/* WARNING the following bits are reversed */ +#define SPFI_CLOCK0_IDLE_MASK (0x000f8000) +#define SPFI_CLOCK0_PHASE_MASK (0x00007c00) +#define SPFI_CS0_IDLE_MASK (0x000003e0) +#define SPFI_DATA0_IDLE_MASK (0x0000001f) + +#define SPIM_CLOCK0_IDLE_MASK (0x000f8000) +#define SPIM_CLOCK0_PHASE_MASK (0x00007c00) +#define SPIM_CS0_IDLE_MASK (0x000003e0) +#define SPIM_DATA0_IDLE_MASK (0x0000001f) + +#define SPIM_PORT0_MASK (0x00084210) + +#define SPFI_PORT_SELECT_SHIFT (20) +/* WARNING the following bits are reversed, bit 0 is highest */ +#define SPFI_CLOCK0_IDLE_SHIFT (19) +#define SPFI_CLOCK0_PHASE_SHIFT (14) +#define SPFI_CS0_IDLE_SHIFT (9) +#define SPFI_DATA0_IDLE_SHIFT (4) + +#define SPIM_CLOCK0_IDLE_SHIFT (19) +#define SPIM_CLOCK0_PHASE_SHIFT (14) +#define SPIM_CS0_IDLE_SHIFT (9) +#define SPIM_DATA0_IDLE_SHIFT (4) + + +/* + * Interrupt registers + * SPFI_GDOF_MASK means Rx buffer full, not an overflow, because clock stalls + * SPFI_SDUF_MASK means Tx buffer empty, not an underflow, because clock stalls + */ +#define SPFI_IACCESS_MASK (0x00001000) +#define SPFI_GDEX8BIT_MASK (0x00000800) +#define SPFI_ALLDONE_MASK (0x00000200) +#define SPFI_GDFUL_MASK (0x00000100) +#define SPFI_GDHF_MASK (0x00000080) +#define SPFI_GDEX32BIT_MASK (0x00000040) +#define SPFI_GDTRIG_MASK (0x00000020) +#define SPFI_SDFUL_MASK (0x00000008) +#define SPFI_SDHF_MASK (0x00000004) +#define SPFI_SDE_MASK (0x00000002) +#define SPFI_SDTRIG_MASK (0x00000001) + +#define SPFI_IACCESS_SHIFT (12) +#define SPFI_GDEX8BIT_SHIFT (11) +#define SPFI_ALLDONE_SHIFT (9) +#define SPFI_GDFUL_SHIFT (8) +#define SPFI_GDHF_SHIFT (7) +#define SPFI_GDEX32BIT_SHIFT (6) +#define SPFI_GDTRIG_SHIFT (5) +#define SPFI_SDFUL_SHIFT (3) +#define SPFI_SDHF_SHIFT (2) +#define SPFI_SDE_SHIFT (1) +#define SPFI_SDTRIG_SHIFT (0) + + +/* SPFI register block */ + +#define SPFI_PORT_0_PARAM_REG_OFFSET (0x00) +#define SPFI_PORT_1_PARAM_REG_OFFSET (0x04) +#define SPFI_PORT_2_PARAM_REG_OFFSET (0x08) +#define SPFI_PORT_3_PARAM_REG_OFFSET (0x0C) +#define SPFI_PORT_4_PARAM_REG_OFFSET (0x10) +#define SPFI_CONTROL_REG_OFFSET (0x14) +#define SPFI_TRANSACTION_REG_OFFSET (0x18) +#define SPFI_PORT_STATE_REG_OFFSET (0x1C) + +#define SPFI_SEND_LONG_REG_OFFSET (0x20) +#define SPFI_SEND_BYTE_REG_OFFSET (0x24) +#define SPFI_GET_LONG_REG_OFFSET (0x28) +#define SPFI_GET_BYTE_REG_OFFSET (0x2C) + +#define SPFI_INT_STATUS_REG_OFFSET (0x30) +#define SPFI_INT_ENABLE_REG_OFFSET (0x34) +#define SPFI_INT_CLEAR_REG_OFFSET (0x38) + +#define SPFI_IMMEDIATE_STATUS_REG_OFFSET (0x3c) + +#define SPFI_FLASH_BASE_ADDRESS_REG_OFFSET (0x48) +#define SPFI_FLASH_STATUS_REG_OFFSET (0x4C) + +#define IMG_FALSE 0 +#define IMG_TRUE 1 + +/* Number of SPIM interfaces*/ +#define SPIM_NUM_BLOCKS 2 +/* Number of chip select lines supported by the SPI master port. */ +#define SPIM_NUM_PORTS_PER_BLOCK (SPIM_DUMMY_CS) +/* Maximum transfer size (in bytes) for the SPI master port. */ +#define SPIM_MAX_TRANSFER_BYTES (0xFFFF) +/* Maximum size of a flash command: command bytes+address_bytes. */ +#define SPIM_MAX_FLASH_COMMAND_BYTES (0x8) +/* Write operation to fifo done in blocks of 16 words (64 bytes) */ +#define SPIM_MAX_BLOCK_BYTES (0x40) +/* Number of tries until timeout error is returned*/ +#define SPI_TIMEOUT_VALUE_US 500000 + +/* SPIM initialisation function return value.*/ +enum spim_return { + /* Initialisation parameters are valid. */ + SPIM_OK = 0, + /* Mode parameter is invalid. */ + SPIM_INVALID_SPI_MODE, + /* Chip select idle level is invalid. */ + SPIM_INVALID_CS_IDLE_LEVEL, + /* Data idle level is invalid. */ + SPIM_INVALID_DATA_IDLE_LEVEL, + /* Chip select line parameter is invalid. */ + SPIM_INVALID_CS_LINE, + /* Transfer size parameter is invalid. */ + SPIM_INVALID_SIZE, + /* Read/write parameter is invalid. */ + SPIM_INVALID_READ_WRITE, + /* Continue parameter is invalid. */ + SPIM_INVALID_CONTINUE, + /* Invalid block index */ + SPIM_INVALID_BLOCK_INDEX, + /* Extended error values */ + /* Invalid bit rate */ + SPIM_INVALID_BIT_RATE, + /* Invalid CS hold value */ + SPIM_INVALID_CS_HOLD_VALUE, + /* API function called before API is initialised */ + SPIM_API_NOT_INITIALISED, + /* SPI driver initialisation failed */ + SPIM_DRIVER_INIT_ERROR, + /* Invalid transfer description */ + SPIM_INVALID_TRANSFER_DESC, + /* Timeout */ + SPIM_TIMEOUT + +}; + +/* This type defines the SPI Mode.*/ +enum spim_mode { + /* Mode 0 (clock idle low, data valid on first clock transition). */ + SPIM_MODE_0 = 0, + /* Mode 1 (clock idle low, data valid on second clock transition). */ + SPIM_MODE_1, + /* Mode 2 (clock idle high, data valid on first clock transition). */ + SPIM_MODE_2, + /* Mode 3 (clock idle high, data valid on second clock transition). */ + SPIM_MODE_3 + +}; + +/* This type defines the SPIM device numbers (chip select lines). */ +enum spim_device { + /* Device 0 (CS0). */ + SPIM_DEVICE0 = 0, + /* Device 1 (CS1). */ + SPIM_DEVICE1, + /* Device 2 (CS2). */ + SPIM_DEVICE2, + /* Device 3 (CS3). */ + SPIM_DEVICE3, + /* Device 4 (CS4). */ + SPIM_DEVICE4, + /* Dummy chip select. */ + SPIM_DUMMY_CS + +}; + +/* This structure defines communication parameters for a slave device */ +struct spim_device_parameters { + /* Bit rate value.*/ + unsigned char bitrate; + /* + * Chip select set up time. + * Time taken between chip select going active and activity occurring + * on the clock, calculated by dividing the desired set up time in ns + * by the Input clock period. (setup time / Input clock freq) + */ + unsigned char cs_setup; + /* + * Chip select hold time. + * Time after the last clock pulse before chip select goes inactive, + * calculated by dividing the desired hold time in ns by the + * Input clock period (hold time / Input clock freq). + */ + unsigned char cs_hold; + /* + * Chip select delay time (CS minimum inactive time). + * Minimum time after chip select goes inactive before chip select + * can go active again, calculated by dividing the desired delay time + * in ns by the Input clock period (delay time / Input clock freq). + */ + unsigned char cs_delay; + /* SPI Mode. */ + enum spim_mode spi_mode; + /* Chip select idle level (0=low, 1=high, Others=invalid). */ + unsigned int cs_idle_level; + /* Data idle level (0=low, 1=high, Others=invalid). */ + unsigned int data_idle_level; + +}; + +/* Command transfer mode */ +enum command_mode { + /* Command, address, dummy and PI cycles are transferred on sio0 */ + SPIM_CMD_MODE_0 = 0, + /* + * Command and Address are transferred on sio0 port only but dummy + * cycles and PI is transferred on all the interface ports. + */ + SPIM_CMD_MODE_1, + /* + * Command is transferred on sio0 port only but address, dummy + * and PI is transferred on all the interface portS + */ + SPIM_CMD_MODE_2, + /* + * Command, address, dummy and PI bytes are transferred on all + * the interfaces + */ + SPIM_CMD_MODE_3 +}; + +/* Data transfer mode */ +enum transfer_mode { + /* Transfer data in single mode */ + SPIM_DMODE_SINGLE = 0, + /* Transfer data in dual mode */ + SPIM_DMODE_DUAL, + /* Transfer data in quad mode */ + SPIM_DMODE_QUAD +}; + +/* This structure contains parameters that describe an SPIM operation. */ +struct spim_buffer { + /* The buffer to read from or write to. */ + unsigned char *buffer; + + /* Number of bytes to read/write. Valid range is 0 to 65536 bytes. */ + unsigned int size; + + /* Read/write select. TRUE for read, FALSE for write, Others-invalid.*/ + int isread; + + /* + * ByteDelay select. + * Selects whether or not a delay is inserted between bytes. + * 0 - Minimum inter-byte delay + * 1 - Inter-byte delay of (cs_hold/master_clk half period)*master_clk. + */ + int inter_byte_delay; +}; + +#endif /* __SOC_IMGTEC_DANUBE_SPI_H__ */ diff --git a/src/soc/imgtec/pistachio/memlayout.ld b/src/soc/imgtec/pistachio/memlayout.ld deleted file mode 100644 index 21c3d73..0000000 --- a/src/soc/imgtec/pistachio/memlayout.ld +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <memlayout.h> - -#include <arch/header.ld> - -/* TODO: This should be revised by someone who understands the SoC better. */ - -SECTIONS -{ - CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */ - - DRAM_START(0x80000000) - RAMSTAGE(0x80000000, 128K) - - /* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */ - BOOTBLOCK(0x9B000000, 16K) - ROMSTAGE(0x9B004000, 40K) - STACK(0x9B00E000, 6K) - PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K) -} diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index 2b21475..69682d0 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -16,10 +16,10 @@ #include <string.h> #include <stdlib.h> #include <timer.h> +#include <soc/cpu.h> +#include <soc/spi.h> #include <spi-generic.h> #include <spi_flash.h> -#include "cpu.h" -#include "spi.h" #if !CONFIG_SPI_ATOMIC_SEQUENCING #error "Unsupported SPI driver API" diff --git a/src/soc/imgtec/pistachio/spi.h b/src/soc/imgtec/pistachio/spi.h deleted file mode 100644 index 91d6d55..0000000 --- a/src/soc/imgtec/pistachio/spi.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef __SOC_IMGTEC_DANUBE_SPI_H__ -#define __SOC_IMGTEC_DANUBE_SPI_H__ - -#include <arch/types.h> -#include <arch/io.h> - -#define spi_read_reg_field(regval, field) \ -( \ - ((field##_MASK) == 0xFFFFFFFF) ? \ - (regval) : \ - (((regval) & (field##_MASK)) >> (field##_SHIFT))\ -) - -#define spi_write_reg_field(regval, field, val) \ -( \ - ((field##_MASK) == 0xFFFFFFFF) ? \ - (val) : \ - (((regval) & ~(field##_MASK)) | \ - (((val) << (field##_SHIFT)) & (field##_MASK))) \ -) - -/* - * Parameter register - * Each of these corresponds to a single port (ie CS line) in the interface - * Fields Name Description - * ====== ==== =========== - * b31:24 CLK_RATE Bit Clock rate = (24.576 * value / 512) MHz - * b23:16 CS_SETUP Chip Select setup = (40 * value) ns - * b15:8 CS_HOLD Chip Select hold = (40 * value) ns - * b7:0 CS_DELAY Chip Select delay = (40 * value) ns - */ - -#define SPIM_CLK_DIVIDE_MASK (0xFF000000) -#define SPIM_CS_SETUP_MASK (0x00FF0000) -#define SPIM_CS_HOLD_MASK (0x0000FF00) -#define SPIM_CS_DELAY_MASK (0x000000FF) -#define SPIM_CS_PARAM_MASK (SPIM_CS_SETUP_MASK \ - | SPIM_CS_HOLD_MASK \ - | SPIM_CS_DELAY_MASK) - -#define SPIM_CLK_DIVIDE_SHIFT (24) -#define SPIM_CS_SETUP_SHIFT (16) -#define SPIM_CS_HOLD_SHIFT (8) -#define SPIM_CS_DELAY_SHIFT (0) -#define SPIM_CS_PARAM_SHIFT (0) - -/* Control register */ - -#define SPFI_DRIBBLE_COUNT_MASK (0x000e0000) -#define SPFI_MEMORY_IF_MASK (0x00008000) -#define SPIM_BYTE_DELAY_MASK (0x00004000) -#define SPIM_CS_DEASSERT_MASK (0x00002000) -#define SPIM_CONTINUE_MASK (0x00001000) -#define SPIM_SOFT_RESET_MASK (0x00000800) -#define SPIM_SEND_DMA_MASK (0x00000400) -#define SPIM_GET_DMA_MASK (0x00000200) -#define SPIM_EDGE_TX_RX_MASK (0x00000100) -#define SPFI_TRNSFR_MODE_MASK (0x000000e0) -#define SPFI_TRNSFR_MODE_DQ_MASK (0x0000001c) -#define SPFI_TX_RX_MASK (0x00000002) -#define SPFI_EN_MASK (0x00000001) - -#define SPFI_DRIBBLE_COUNT_SHIFT (17) -#define SPFI_MEMORY_IF_SHIFT (15) -#define SPIM_BYTE_DELAY_SHIFT (14) -#define SPIM_CS_DEASSERT_SHIFT (13) -#define SPIM_CONTINUE_SHIFT (12) -#define SPIM_SOFT_RESET_SHIFT (11) -#define SPIM_SEND_DMA_SHIFT (10) -#define SPIM_GET_DMA_SHIFT (9) -#define SPIM_EDGE_TX_RX_SHIFT (8) -#define SPFI_TRNSFR_MODE_SHIFT (5) -#define SPFI_TRNSFR_MODE_DQ_SHIFT (2) -#define SPFI_TX_RX_SHIFT (1) -#define SPFI_EN_SHIFT (0) - -/* Transaction register */ - -#define SPFI_TSIZE_MASK (0xffff0000) -#define SPFI_CMD_LENGTH_MASK (0x0000e000) -#define SPFI_ADDR_LENGTH_MASK (0x00001c00) -#define SPFI_DUMMY_LENGTH_MASK (0x000003e0) -#define SPFI_PI_LENGTH_MASK (0x0000001c) - -#define SPFI_TSIZE_SHIFT (16) -#define SPFI_CMD_LENGTH_SHIFT (13) -#define SPFI_ADDR_LENGTH_SHIFT (10) -#define SPFI_DUMMY_LENGTH_SHIFT (5) -#define SPFI_PI_LENGTH_SHIFT (2) - -/* Port state register */ - -#define SPFI_PORT_SELECT_MASK (0x00700000) -/* WARNING the following bits are reversed */ -#define SPFI_CLOCK0_IDLE_MASK (0x000f8000) -#define SPFI_CLOCK0_PHASE_MASK (0x00007c00) -#define SPFI_CS0_IDLE_MASK (0x000003e0) -#define SPFI_DATA0_IDLE_MASK (0x0000001f) - -#define SPIM_CLOCK0_IDLE_MASK (0x000f8000) -#define SPIM_CLOCK0_PHASE_MASK (0x00007c00) -#define SPIM_CS0_IDLE_MASK (0x000003e0) -#define SPIM_DATA0_IDLE_MASK (0x0000001f) - -#define SPIM_PORT0_MASK (0x00084210) - -#define SPFI_PORT_SELECT_SHIFT (20) -/* WARNING the following bits are reversed, bit 0 is highest */ -#define SPFI_CLOCK0_IDLE_SHIFT (19) -#define SPFI_CLOCK0_PHASE_SHIFT (14) -#define SPFI_CS0_IDLE_SHIFT (9) -#define SPFI_DATA0_IDLE_SHIFT (4) - -#define SPIM_CLOCK0_IDLE_SHIFT (19) -#define SPIM_CLOCK0_PHASE_SHIFT (14) -#define SPIM_CS0_IDLE_SHIFT (9) -#define SPIM_DATA0_IDLE_SHIFT (4) - - -/* - * Interrupt registers - * SPFI_GDOF_MASK means Rx buffer full, not an overflow, because clock stalls - * SPFI_SDUF_MASK means Tx buffer empty, not an underflow, because clock stalls - */ -#define SPFI_IACCESS_MASK (0x00001000) -#define SPFI_GDEX8BIT_MASK (0x00000800) -#define SPFI_ALLDONE_MASK (0x00000200) -#define SPFI_GDFUL_MASK (0x00000100) -#define SPFI_GDHF_MASK (0x00000080) -#define SPFI_GDEX32BIT_MASK (0x00000040) -#define SPFI_GDTRIG_MASK (0x00000020) -#define SPFI_SDFUL_MASK (0x00000008) -#define SPFI_SDHF_MASK (0x00000004) -#define SPFI_SDE_MASK (0x00000002) -#define SPFI_SDTRIG_MASK (0x00000001) - -#define SPFI_IACCESS_SHIFT (12) -#define SPFI_GDEX8BIT_SHIFT (11) -#define SPFI_ALLDONE_SHIFT (9) -#define SPFI_GDFUL_SHIFT (8) -#define SPFI_GDHF_SHIFT (7) -#define SPFI_GDEX32BIT_SHIFT (6) -#define SPFI_GDTRIG_SHIFT (5) -#define SPFI_SDFUL_SHIFT (3) -#define SPFI_SDHF_SHIFT (2) -#define SPFI_SDE_SHIFT (1) -#define SPFI_SDTRIG_SHIFT (0) - - -/* SPFI register block */ - -#define SPFI_PORT_0_PARAM_REG_OFFSET (0x00) -#define SPFI_PORT_1_PARAM_REG_OFFSET (0x04) -#define SPFI_PORT_2_PARAM_REG_OFFSET (0x08) -#define SPFI_PORT_3_PARAM_REG_OFFSET (0x0C) -#define SPFI_PORT_4_PARAM_REG_OFFSET (0x10) -#define SPFI_CONTROL_REG_OFFSET (0x14) -#define SPFI_TRANSACTION_REG_OFFSET (0x18) -#define SPFI_PORT_STATE_REG_OFFSET (0x1C) - -#define SPFI_SEND_LONG_REG_OFFSET (0x20) -#define SPFI_SEND_BYTE_REG_OFFSET (0x24) -#define SPFI_GET_LONG_REG_OFFSET (0x28) -#define SPFI_GET_BYTE_REG_OFFSET (0x2C) - -#define SPFI_INT_STATUS_REG_OFFSET (0x30) -#define SPFI_INT_ENABLE_REG_OFFSET (0x34) -#define SPFI_INT_CLEAR_REG_OFFSET (0x38) - -#define SPFI_IMMEDIATE_STATUS_REG_OFFSET (0x3c) - -#define SPFI_FLASH_BASE_ADDRESS_REG_OFFSET (0x48) -#define SPFI_FLASH_STATUS_REG_OFFSET (0x4C) - -#define IMG_FALSE 0 -#define IMG_TRUE 1 - -/* Number of SPIM interfaces*/ -#define SPIM_NUM_BLOCKS 2 -/* Number of chip select lines supported by the SPI master port. */ -#define SPIM_NUM_PORTS_PER_BLOCK (SPIM_DUMMY_CS) -/* Maximum transfer size (in bytes) for the SPI master port. */ -#define SPIM_MAX_TRANSFER_BYTES (0xFFFF) -/* Maximum size of a flash command: command bytes+address_bytes. */ -#define SPIM_MAX_FLASH_COMMAND_BYTES (0x8) -/* Write operation to fifo done in blocks of 16 words (64 bytes) */ -#define SPIM_MAX_BLOCK_BYTES (0x40) -/* Number of tries until timeout error is returned*/ -#define SPI_TIMEOUT_VALUE_US 500000 - -/* SPIM initialisation function return value.*/ -enum spim_return { - /* Initialisation parameters are valid. */ - SPIM_OK = 0, - /* Mode parameter is invalid. */ - SPIM_INVALID_SPI_MODE, - /* Chip select idle level is invalid. */ - SPIM_INVALID_CS_IDLE_LEVEL, - /* Data idle level is invalid. */ - SPIM_INVALID_DATA_IDLE_LEVEL, - /* Chip select line parameter is invalid. */ - SPIM_INVALID_CS_LINE, - /* Transfer size parameter is invalid. */ - SPIM_INVALID_SIZE, - /* Read/write parameter is invalid. */ - SPIM_INVALID_READ_WRITE, - /* Continue parameter is invalid. */ - SPIM_INVALID_CONTINUE, - /* Invalid block index */ - SPIM_INVALID_BLOCK_INDEX, - /* Extended error values */ - /* Invalid bit rate */ - SPIM_INVALID_BIT_RATE, - /* Invalid CS hold value */ - SPIM_INVALID_CS_HOLD_VALUE, - /* API function called before API is initialised */ - SPIM_API_NOT_INITIALISED, - /* SPI driver initialisation failed */ - SPIM_DRIVER_INIT_ERROR, - /* Invalid transfer description */ - SPIM_INVALID_TRANSFER_DESC, - /* Timeout */ - SPIM_TIMEOUT - -}; - -/* This type defines the SPI Mode.*/ -enum spim_mode { - /* Mode 0 (clock idle low, data valid on first clock transition). */ - SPIM_MODE_0 = 0, - /* Mode 1 (clock idle low, data valid on second clock transition). */ - SPIM_MODE_1, - /* Mode 2 (clock idle high, data valid on first clock transition). */ - SPIM_MODE_2, - /* Mode 3 (clock idle high, data valid on second clock transition). */ - SPIM_MODE_3 - -}; - -/* This type defines the SPIM device numbers (chip select lines). */ -enum spim_device { - /* Device 0 (CS0). */ - SPIM_DEVICE0 = 0, - /* Device 1 (CS1). */ - SPIM_DEVICE1, - /* Device 2 (CS2). */ - SPIM_DEVICE2, - /* Device 3 (CS3). */ - SPIM_DEVICE3, - /* Device 4 (CS4). */ - SPIM_DEVICE4, - /* Dummy chip select. */ - SPIM_DUMMY_CS - -}; - -/* This structure defines communication parameters for a slave device */ -struct spim_device_parameters { - /* Bit rate value.*/ - unsigned char bitrate; - /* - * Chip select set up time. - * Time taken between chip select going active and activity occurring - * on the clock, calculated by dividing the desired set up time in ns - * by the Input clock period. (setup time / Input clock freq) - */ - unsigned char cs_setup; - /* - * Chip select hold time. - * Time after the last clock pulse before chip select goes inactive, - * calculated by dividing the desired hold time in ns by the - * Input clock period (hold time / Input clock freq). - */ - unsigned char cs_hold; - /* - * Chip select delay time (CS minimum inactive time). - * Minimum time after chip select goes inactive before chip select - * can go active again, calculated by dividing the desired delay time - * in ns by the Input clock period (delay time / Input clock freq). - */ - unsigned char cs_delay; - /* SPI Mode. */ - enum spim_mode spi_mode; - /* Chip select idle level (0=low, 1=high, Others=invalid). */ - unsigned int cs_idle_level; - /* Data idle level (0=low, 1=high, Others=invalid). */ - unsigned int data_idle_level; - -}; - -/* Command transfer mode */ -enum command_mode { - /* Command, address, dummy and PI cycles are transferred on sio0 */ - SPIM_CMD_MODE_0 = 0, - /* - * Command and Address are transferred on sio0 port only but dummy - * cycles and PI is transferred on all the interface ports. - */ - SPIM_CMD_MODE_1, - /* - * Command is transferred on sio0 port only but address, dummy - * and PI is transferred on all the interface portS - */ - SPIM_CMD_MODE_2, - /* - * Command, address, dummy and PI bytes are transferred on all - * the interfaces - */ - SPIM_CMD_MODE_3 -}; - -/* Data transfer mode */ -enum transfer_mode { - /* Transfer data in single mode */ - SPIM_DMODE_SINGLE = 0, - /* Transfer data in dual mode */ - SPIM_DMODE_DUAL, - /* Transfer data in quad mode */ - SPIM_DMODE_QUAD -}; - -/* This structure contains parameters that describe an SPIM operation. */ -struct spim_buffer { - /* The buffer to read from or write to. */ - unsigned char *buffer; - - /* Number of bytes to read/write. Valid range is 0 to 65536 bytes. */ - unsigned int size; - - /* Read/write select. TRUE for read, FALSE for write, Others-invalid.*/ - int isread; - - /* - * ByteDelay select. - * Selects whether or not a delay is inserted between bytes. - * 0 - Minimum inter-byte delay - * 1 - Inter-byte delay of (cs_hold/master_clk half period)*master_clk. - */ - int inter_byte_delay; -}; - -#endif /* __SOC_IMGTEC_DANUBE_SPI_H__ */

1 0

Patch set updated for coreboot: 3deefe5 pistachio: implement timer support
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9188 -gerrit commit 3deefe570d067d669e1c8cdfab4dcb582abff50a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Nov 5 17:50:09 2014 -0800 pistachio: implement timer support C0_COUNT register is a free running counter clocked by the CPU frequency divided by two. On the FPGA board it results in 25 MHz, on real SOCs it will have to be figured out later. Some magic addresses and numbers are used to find out if the code is running on the FPGA board. timestamp_get() and timer_monotonic_get() are kept in the same file. The CPU initialization makes sure that CO COUNT is in fact enabled and starts from zero. BRANCH=none BUG=chrome-os-partner:33595,chrome-os-partner:31438 TEST=with timer enabled, the startup code properly initializes UART and prints the coreboot bootblock banner message on the serial console. Change-Id: I98fe330b961f677448b222917ab7d586494ed4b7 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a7324221c1d856ac72fa2b0ab586b5ea8cab3a05 Original-Change-Id: I2d518213de939e91a35f8aea174aed76d297dd72 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227888 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/Makefile.inc | 3 --- src/soc/imgtec/pistachio/bootblock.c | 15 +++++++++++++++ src/soc/imgtec/pistachio/include/soc/cpu.h | 7 +++++++ src/soc/imgtec/pistachio/monotonic_timer.c | 26 +++++++++++++++++++++++++- src/soc/imgtec/pistachio/timestamp.c | 19 ------------------- 5 files changed, 47 insertions(+), 23 deletions(-) diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index e955968..f7a0848 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -31,16 +31,13 @@ ramstage-y += uart.c endif bootblock-y += monotonic_timer.c -bootblock-y += timestamp.c ramstage-y += cbmem.c ramstage-y += monotonic_timer.c -ramstage-y += timestamp.c romstage-y += cbmem.c romstage-y += romstage.c romstage-y += monotonic_timer.c -romstage-y += timestamp.c CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/ diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index f6cc76b..9011264 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -19,6 +19,21 @@ * MA 02110-1301 USA */ +#include <stdint.h> +#include <arch/cpu.h> + static void bootblock_cpu_init(void) { + uint32_t cause; + + /* + * Make sure the count register is counting by clearing the "Disable + * Counter" bit, in case it is set. + */ + cause = read_c0_cause(); + if (cause & C0_CAUSE_DC) + write_c0_cause(cause & ~(C0_CAUSE_DC)); + + /* And make sure that it starts from zero. */ + write_c0_count(0); } diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h index c61c58d..72775b5 100644 --- a/src/soc/imgtec/pistachio/include/soc/cpu.h +++ b/src/soc/imgtec/pistachio/include/soc/cpu.h @@ -21,4 +21,11 @@ #define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 #define IMG_SPIM1_BASE_ADDRESS 0xB8101000 +/* + * Reading at this address allows to identify the platform the code is running + * on. + */ +#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) +#define IMG_PLATFORM_ID_SILICON 0xF00D0006 + #endif diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index a8fe27c..99c147b 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -17,9 +17,33 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> #include <timer.h> +#include <timestamp.h> +#include <arch/cpu.h> +#include <soc/cpu.h> + +static int get_count_mhz_freq(void) +{ + static unsigned count_mhz_freq; + + if (!count_mhz_freq) { + if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) + count_mhz_freq = 25; /* FPGA board */ + /* + * Will need some means of finding out the counter + * frequency on a real SOC + */ + } + return count_mhz_freq; +} void timer_monotonic_get(struct mono_time *mt) { - /* to be defined */ + mt->microseconds = (long)timestamp_get(); +} + +uint64_t timestamp_get(void) +{ + return read_c0_count()/get_count_mhz_freq(); } diff --git a/src/soc/imgtec/pistachio/timestamp.c b/src/soc/imgtec/pistachio/timestamp.c deleted file mode 100644 index f0dc5ad..0000000 --- a/src/soc/imgtec/pistachio/timestamp.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <timestamp.h> - -uint64_t timestamp_get(void) -{ - return 0; -}

1 0

Patch set updated for coreboot: 9ed7f83 pistachio: enable early console
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9189 -gerrit commit 9ed7f83cbd8623ba8b0963d2d5e6ebe0436720c1 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Nov 11 19:55:07 2014 -0800 pistachio: enable early console Adding this configuration option enables romstage console output. Ideally this setting should be enabled automatically in case the bootblock console is enabled. BRANCH=none BUG=chrome-os-partner:31438 TEST=romstage messages show up on the console Change-Id: I5823fc737f4c65a4222592a8857ac89e7fe0ba3e Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 30f5f64ffcb8ab938781d87b7928dc3b19c58504 Original-Change-Id: I710e05ce24e1aeccc90aead50336f00dec52fff0 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229202 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 70e5741..123b5cf 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -24,6 +24,7 @@ config CPU_IMGTEC_PISTACHIO select DYNAMIC_CBMEM select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER + select EARLY_CONSOLE select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING

1 0

Patch set updated for coreboot: 10b59b9 pistachio: allow more room for bootblock
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9190 -gerrit commit 10b59b97d0615403723008164cc238d762c21452 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 29 15:28:23 2014 -0800 pistachio: allow more room for bootblock 32K is a more appropriate room for Pistachio bootblock. BRANCH=none BUG=chrome-os-partner:31438 TEST=there is no bootblock overflow even when compiled with -O0. Change-Id: I454746ce0b9daabc93ccbf3316655fac836af8ff Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 56adf22ba12f5a7c69d11c0c720996de32ca9149 Original-Change-Id: I74b6674aea95b1138e2168527239e2cfb4a7ad42 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232291 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 123b5cf..3558614 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -38,11 +38,11 @@ config BOOTBLOCK_CPU_INIT config CBFS_ROM_OFFSET hex - default 0x4100 + default 0x8100 config CBFS_HEADER_ROM_OFFSET # Effectively the maximum size of the bootblock hex - default 0x4000 + default 0x8000 endif

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Patch set updated for coreboot: 6ed1f51 pistachio: set correct CBMEM top address
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9191 -gerrit commit 6ed1f5182d639de845a2a5851f3f70f800436e97 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 29 15:31:40 2014 -0800 pistachio: set correct CBMEM top address This is required for proper dynamic CBMEM operation. BRANCH=none BUG=chrome-os-partner:31438 TEST=urara ramstage does not crash anymore in CBMEM initialization Change-Id: Id8e001be20fc245c91b2639f89775e594b0de966 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b7c6e4090d76a172c269bff002428015cc8aac8a Original-Change-Id: I5d44907443724891c8cff805208a7a3bb8e36752 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232292 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/cbmem.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 373d4f8..1aed030 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -25,6 +25,5 @@ void *cbmem_top(void) { - uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20; - return _dram + top; + return _dram + (CONFIG_DRAM_SIZE_MB << 20); }

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Patch set updated for coreboot: 8f7703c pistachio: add SOC descriptor
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9192 -gerrit commit 8f7703c0b5edc405c70f0d72a219ce767a505bdb Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Dec 1 18:34:37 2014 -0800 pistachio: add SOC descriptor With this descriptor added ramstage properly allocates memory resources and creates entries in coreboot table. This also allows to proceed to booting depthcharge, as it now can be loaded into the existing memory. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the set of patches applied the firmware properly finds depthcharge in CBFS, uncompresses it and attempts to start: ... Booting payload fallback/payload from cbfs Loading segment from rom address 0x9b000058 code (compression=1) New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe Loading segment from rom address 0x9b000074 Entry Point 0x80124038 Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe lb: [0x0000000080000000, 0x0000000080013858) Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe using LZMA [ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090 Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054 dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129 Jumping to boot code at 80124038 ERROR: dropped a timestamp entry CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes entry = 80124038 Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a1577c5532a064426a3ea88b6f7f30ccdae24eaf Original-Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232571 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/urara/devicetree.cb | 1 + src/soc/imgtec/pistachio/Makefile.inc | 1 + src/soc/imgtec/pistachio/soc.c | 48 ++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/src/mainboard/google/urara/devicetree.cb b/src/mainboard/google/urara/devicetree.cb index a328b9d..e3eb091 100644 --- a/src/mainboard/google/urara/devicetree.cb +++ b/src/mainboard/google/urara/devicetree.cb @@ -20,6 +20,7 @@ # chip soc/imgtec/pistachio + device cpu_cluster 0 on end chip drivers/generic/generic # I2C0 controller device i2c 6 on end # Fake component for testing end diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index f7a0848..fdeba0c 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -34,6 +34,7 @@ bootblock-y += monotonic_timer.c ramstage-y += cbmem.c ramstage-y += monotonic_timer.c +ramstage-y += soc.c romstage-y += cbmem.c romstage-y += romstage.c diff --git a/src/soc/imgtec/pistachio/soc.c b/src/soc/imgtec/pistachio/soc.c new file mode 100644 index 0000000..7c2884f --- /dev/null +++ b/src/soc/imgtec/pistachio/soc.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <symbols.h> + +static void soc_read_resources(device_t dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, + (CONFIG_DRAM_SIZE_MB * MiB) / KiB); +} + +static void soc_init(device_t dev) +{ + printk(BIOS_INFO, "CPU: Imgtec Pistachio\n"); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_imgtec_pistachio_ops = { + CHIP_NAME("SOC: Imgtec Pistachio") + .enable_dev = enable_soc_dev, +};

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Patch set updated for coreboot: 18ca0bd pistachio: add timer frequency for SOC; correct platform ID
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9193 -gerrit commit 18ca0bdb5ea40c509c03ec78f97a08ea5942a95b Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Mon Jan 19 02:39:18 2015 +0000 pistachio: add timer frequency for SOC; correct platform ID Corrected platform ID and added timer frequency for SOC. The timer frequency is half the CPU frequency. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: If7e03232106b52f2522fc7da586bdaf95f5eefec Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d94789950d5300bbe5defbf529480d8d545e743e Original-Change-Id: I1187e4b5280eaf796777d882a2e154e2808e9e37 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241426 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/imgtec/pistachio/include/soc/cpu.h | 12 ++++++++---- src/soc/imgtec/pistachio/monotonic_timer.c | 19 ++++++++++++++++--- 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h index 72775b5..8995219 100644 --- a/src/soc/imgtec/pistachio/include/soc/cpu.h +++ b/src/soc/imgtec/pistachio/include/soc/cpu.h @@ -18,14 +18,18 @@ #ifndef __SOC_IMGTEC_DANUBE_CPU_H__ #define __SOC_IMGTEC_DANUBE_CPU_H__ +#include <arch/io.h> + #define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 #define IMG_SPIM1_BASE_ADDRESS 0xB8101000 /* - * Reading at this address allows to identify the platform the code is running - * on. + * This register holds the FPGA image version + * If we're not working on the FPGA this will be 0 */ -#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) -#define IMG_PLATFORM_ID_SILICON 0xF00D0006 +#define PRIMARY_FPGA_VERSION 0xB8149060 +#define IMG_PLATFORM_ID() read32(PRIMARY_FPGA_VERSION) +#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ +#define IMG_PLATFORM_ID_SILICON 0 #endif diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index 99c147b..c2408b0 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -23,6 +23,9 @@ #include <arch/cpu.h> #include <soc/cpu.h> +#define PISTACHIO_CLOCK_SWITCH 0xB8144200 +#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 + static int get_count_mhz_freq(void) { static unsigned count_mhz_freq; @@ -30,10 +33,20 @@ static int get_count_mhz_freq(void) if (!count_mhz_freq) { if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) count_mhz_freq = 25; /* FPGA board */ - /* - * Will need some means of finding out the counter - * frequency on a real SOC + else { + /* If MIPS PLL external bypass bit is set, it means + * that the MIPS PLL is already set up to work at a + * frequency of 550 MHz; otherwise, the crystal is + * used with a frequency of 52 MHz */ + if (read32(PISTACHIO_CLOCK_SWITCH) & + MIPS_EXTERN_PLL_BYPASS_MASK) + /* Half MIPS PLL freq. */ + count_mhz_freq = 275; + else + /* Half Xtal freq. */ + count_mhz_freq = 26; + } } return count_mhz_freq; }

1 0

New patch to review for coreboot: 82caae6 timer: generic udelay()
by Patrick Georgi 07 Apr '15

07 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9334 -gerrit commit 82caae681f5b3603d191d2f895883bf11c93a8f5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 25 10:05:15 2014 -0500 timer: generic udelay() Add GENERIC_UDELAY Kconfig option so that a generic udelay() implementation is provided utilizing the monotonic timer. That way each board/chipset doesn't need to duplicate the same udelay(). Additionally, assume that GENERIC_UDELAY implies init_timer() is not required. BUG=None BRANCH=None TEST=Built nyan, ryu, and rambi. May need help testing. Change-Id: I7f511a2324b5aa5d1b2959f4519be85a6a7360e8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1a85fbcad778933d13eaef545135abe7e4de46ed Original-Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219719 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/Kconfig | 7 +++++ src/arch/mips/Makefile.inc | 3 -- src/arch/mips/timer.c | 31 ------------------ src/include/delay.h | 4 +++ src/lib/Makefile.inc | 5 +++ src/lib/timer.c | 42 +++++++++++++++++++++++++ src/soc/nvidia/tegra124/Kconfig | 2 ++ src/soc/nvidia/tegra124/Makefile.inc | 4 --- src/soc/nvidia/tegra124/timer.c | 53 ------------------------------- src/soc/nvidia/tegra132/Kconfig | 1 + src/soc/nvidia/tegra132/Makefile.inc | 3 -- src/soc/nvidia/tegra132/timer.c | 45 -------------------------- src/soc/rockchip/rk3288/Kconfig | 1 + src/soc/rockchip/rk3288/timer.c | 27 ---------------- src/soc/samsung/exynos5250/Kconfig | 1 + src/soc/samsung/exynos5250/Makefile.inc | 3 -- src/soc/samsung/exynos5250/timer.c | 53 ------------------------------- src/soc/samsung/exynos5420/Kconfig | 1 + src/soc/samsung/exynos5420/Makefile.inc | 3 -- src/soc/samsung/exynos5420/timer.c | 56 --------------------------------- 20 files changed, 64 insertions(+), 281 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index aa4d6ee..d6229be 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -387,6 +387,13 @@ config HAVE_MONOTONIC_TIMER help The board/chipset provides a monotonic timer. +config GENERIC_UDELAY + def_bool n + depends on HAVE_MONOTONIC_TIMER + help + The board/chipset uses a generic udelay function utilizing the + monotonic timer. + config TIMER_QUEUE def_bool n depends on HAVE_MONOTONIC_TIMER diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index 9e88ba8..1929140 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -38,7 +38,6 @@ bootblock-y += boot.c bootblock-y += bootblock.S bootblock-y += bootblock_simple.c bootblock-y += stages.c -bootblock-y += timer.c bootblock-y += ../../lib/memcpy.c bootblock-y += ../../lib/memmove.c bootblock-y += ../../lib/memset.c @@ -64,7 +63,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) romstage-y += boot.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c romstage-y += stages.c -romstage-y += timer.c romstage-y += ../../lib/memcpy.c romstage-y += ../../lib/memmove.c romstage-y += ../../lib/memset.c @@ -85,7 +83,6 @@ ramstage-y += ashldi3.c ramstage-y += boot.c ramstage-y += stages.c ramstage-y += tables.c -ramstage-y += timer.c ramstage-y += ../../lib/memcpy.c ramstage-y += ../../lib/memmove.c ramstage-y += ../../lib/memset.c diff --git a/src/arch/mips/timer.c b/src/arch/mips/timer.c deleted file mode 100644 index c38601d..0000000 --- a/src/arch/mips/timer.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <timer.h> - -void init_timer(void) -{ - /* TODO */ -} - -void udelay(unsigned usec) -{ - /* TODO */ -} diff --git a/src/include/delay.h b/src/include/delay.h index b3d8ed9..ab1f4f9 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,7 +1,11 @@ #ifndef DELAY_H #define DELAY_H +#if IS_ENABLED(CONFIG_GENERIC_UDELAY) +static inline void init_timer(void) {} +#else void init_timer(void); +#endif void udelay(unsigned usecs); void mdelay(unsigned msecs); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f5b2afa..fc29763 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -22,6 +22,8 @@ bootblock-y += prog_ops.c bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +bootblock-$(CONFIG_GENERIC_UDELAY) += timer.c + bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c bootblock-y += memcmp.c @@ -61,6 +63,8 @@ romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c endif +romstage-$(CONFIG_GENERIC_UDELAY) += timer.c + ramstage-y += prog_ops.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c @@ -89,6 +93,7 @@ ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c ramstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c +ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c diff --git a/src/lib/timer.c b/src/lib/timer.c new file mode 100644 index 0000000..a2edc5c --- /dev/null +++ b/src/lib/timer.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +void udelay(unsigned usec) +{ + struct stopwatch sw; + + /* + * As the timer granularity is in microseconds pad the + * requested delay by one to get at least >= requested usec delay. + */ + usec += 1; + + if (!thread_yield_microseconds(usec)) + return; + + stopwatch_init_usecs_expire(&sw, usec); + + while (!stopwatch_expired(&sw)) + ; +} diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 1680f45..3ce368b 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -7,6 +7,8 @@ config SOC_NVIDIA_TEGRA124 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select HAVE_HARD_RESET + select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select BOOTBLOCK_CONSOLE select ARM_BOOTBLOCK_CUSTOM select ARM_LPAE diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 6de142d..49669eb 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -15,7 +15,6 @@ bootblock-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c bootblock-y += ../tegra/pingroup.c bootblock-y += ../tegra/pinmux.c bootblock-y += ../tegra/apbmisc.c -bootblock-y += timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif @@ -25,7 +24,6 @@ verstage-y += cbfs.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c -verstage-y += timer.c verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += ../tegra/gpio.c verstage-y += ../tegra/i2c.c @@ -48,7 +46,6 @@ romstage-y += ../tegra/gpio.c romstage-y += ../tegra/i2c.c romstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c romstage-y += ../tegra/pinmux.c -romstage-y += timer.c romstage-y += cache.c romstage-$(CONFIG_DRIVERS_UART) += uart.c @@ -70,7 +67,6 @@ ramstage-y += ../tegra/i2c.c ramstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c ramstage-y += ../tegra/pinmux.c ramstage-y += ../tegra/usb.c -ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c rmodules_$(ARCH-romstage-y)-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra124/timer.c b/src/soc/nvidia/tegra124/timer.c deleted file mode 100644 index 83f499c..0000000 --- a/src/soc/nvidia/tegra124/timer.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <timer.h> -#include <delay.h> -#include <thread.h> - -void init_timer(void) -{ -} - -/* delay x useconds */ -void udelay(unsigned usec) -{ - struct mono_time current, end; - - if (!thread_yield_microseconds(usec)) - return; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, usec); - - if (mono_time_after(&current, &end)) { - printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", - usec); - /* There's not much we can do if usec is too big. Use a long, - * paranoid delay value and hope for the best... */ - end = current; - mono_time_add_usecs(&end, USECS_PER_SEC); - } - - while (mono_time_before(&current, &end)) - timer_monotonic_get(&current); -} - diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index c87698a..0a1b28b 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -8,6 +8,7 @@ config SOC_NVIDIA_TEGRA132 select BOOTBLOCK_CONSOLE select GIC select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select HAVE_HARD_RESET select HAVE_UART_SPECIAL select HAVE_UART_MEMORY_MAPPED diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 81d08f5..8ad9b83 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -1,7 +1,6 @@ bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c -bootblock-y += timer.c bootblock-y += clock.c bootblock-y += spi.c bootblock-y += i2c.c @@ -26,7 +25,6 @@ romstage-y += romstage_asm.S romstage-y += addressmap.c romstage-y += cbfs.c romstage-y += cbmem.c -romstage-y += timer.c romstage-y += ccplex.c romstage-y += clock.c romstage-y += cpu.c @@ -53,7 +51,6 @@ ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += cpu.c ramstage-y += cpu_lib.S -ramstage-y += timer.c ramstage-y += clock.c ramstage-y += soc.c ramstage-y += spi.c diff --git a/src/soc/nvidia/tegra132/timer.c b/src/soc/nvidia/tegra132/timer.c deleted file mode 100644 index ed10340..0000000 --- a/src/soc/nvidia/tegra132/timer.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <timer.h> -#include <delay.h> -#include <thread.h> - -void init_timer(void) -{ -} - -void udelay(unsigned usec) -{ - struct stopwatch sw; - - /* - * As the hardware clock granularity is in microseconds pad the - * requested delay by one to get at least >= requested usec delay. - */ - usec += 1; - - if (!thread_yield_microseconds(usec)) - return; - - stopwatch_init_usecs_expire(&sw, usec); - while (!stopwatch_expired(&sw)) - ; -} diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 0865fe8..70951a5 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -26,6 +26,7 @@ config SOC_ROCKCHIP_RK3288 select ARCH_RAMSTAGE_ARMV7 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index 91186cc..95f5be5 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -22,36 +22,9 @@ #include <arch/io.h> #include "timer.h" -void init_timer(void) -{ -} - void rk3288_init_timer(void) { write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0); write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1); write32(1, &timer7_ptr->timer_ctrl_reg); } - -/* delay x useconds */ -void udelay(unsigned usec) -{ - struct mono_time current, end; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, usec); - - if (mono_time_after(&current, &end)) { - printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", - usec); - /* There's not much we can do if usec is too big. Use a long, - * paranoid delay value and hope for the best... */ - end = current; - mono_time_add_usecs(&end, USECS_PER_SEC); - } - - while (mono_time_before(&current, &end)) - timer_monotonic_get(&current); -} - diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 4126ec1..7034e96 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -5,6 +5,7 @@ config CPU_SAMSUNG_EXYNOS5250 select ARCH_RAMSTAGE_ARMV7 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select HAVE_UART_SPECIAL bool default n diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 735ce2e..1d0b55c 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -10,7 +10,6 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c bootblock-y += gpio.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c romstage-y += spi.c alternate_cbfs.c romstage-y += clock.c @@ -24,7 +23,6 @@ romstage-y += monotonic_timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += wakeup.c romstage-y += gpio.c -romstage-y += timer.c romstage-y += trustzone.c romstage-y += i2c.c #romstage-y += wdt.c @@ -40,7 +38,6 @@ ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c ramstage-y += monotonic_timer.c -ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp-reg.c diff --git a/src/soc/samsung/exynos5250/timer.c b/src/soc/samsung/exynos5250/timer.c deleted file mode 100644 index 5d402bc..0000000 --- a/src/soc/samsung/exynos5250/timer.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Samsung Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <timer.h> -#include <delay.h> - -#include "clk.h" - -void init_timer(void) -{ - /* Nothing to do because we manually - * call mct_start() in the bootblock - */ -} - -/* delay x useconds */ -void udelay(unsigned usec) -{ - struct mono_time current, end; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, usec); - - if (mono_time_after(&current, &end)) { - printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", - usec); - /* There's not much we can do if usec is too big. Use a long, - * paranoid delay value and hope for the best... */ - end = current; - mono_time_add_usecs(&end, USECS_PER_SEC); - } - - while (mono_time_before(&current, &end)) - timer_monotonic_get(&current); -} diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index ed9d2f8..072976a 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -5,6 +5,7 @@ config CPU_SAMSUNG_EXYNOS5420 select ARCH_RAMSTAGE_ARMV7 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select HAVE_UART_SPECIAL select RELOCATABLE_MODULES bool diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index eadf8ed..350d589 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -10,7 +10,6 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c bootblock-y += gpio.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c romstage-y += spi.c alternate_cbfs.c romstage-y += smp.c @@ -25,7 +24,6 @@ romstage-y += monotonic_timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += wakeup.c romstage-y += gpio.c -romstage-y += timer.c romstage-y += i2c.c #romstage-y += wdt.c romstage-y += cbmem.c @@ -41,7 +39,6 @@ ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c ramstage-y += monotonic_timer.c -ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp.c dp_lowlevel.c fimd.c diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c deleted file mode 100644 index ae13342..0000000 --- a/src/soc/samsung/exynos5420/timer.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Samsung Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <timer.h> -#include <delay.h> -#include <thread.h> -#include "clk.h" - -void init_timer(void) -{ - /* Nothing to do because we manually - * call mct_start() in the bootblock - */ -} - -/* delay x useconds */ -void udelay(unsigned usec) -{ - struct mono_time current, end; - - if (!thread_yield_microseconds(usec)) - return; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, usec); - - if (mono_time_after(&current, &end)) { - printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", - usec); - /* There's not much we can do if usec is too big. Use a long, - * paranoid delay value and hope for the best... */ - end = current; - mono_time_add_usecs(&end, USECS_PER_SEC); - } - - while (mono_time_before(&current, &end)) - timer_monotonic_get(&current); -}

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coreboot-gerrit April 2015