the following patch was just integrated into master:
commit b63d34102ad074d0db2347ffadd30bc6ab834160
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 6 13:32:42 2015 -0800
broadwell: Update SATA Gen3 TX adjustment registers
The registers that were used here are for CPT/PPT and not
for HSW/BDW chips.
Update this to update just the Gen3 TX Output Voltage Downscale
Amplitude Adjustment field in the SATA ECR T88.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I94b702dc4a3c98678ba048ff9cfa4a85cc5b1eed
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4c5816cc647b84266751e8a591eb85d7735fee12
Original-Change-Id: I98ec9678938a6675828721d5b57683077f555d21
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238800
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9484
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9484 for details.
-gerrit
the following patch was just integrated into master:
commit 88bbf166bc1856156b5b2f3f4767f9365dfd60c6
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Jan 9 13:23:05 2015 -0800
broadwell: Add a few bits to finalize step
Added a few bits to set in finalize step from scrubbing BWG
and reference code.
BUG=chrome-os-partner:28234
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: I7b0c4dd3f14c06175c973561760ad1bdafd46fbb
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3802aef908849fe6ea2bb0034d884064154ae9da
Original-Change-Id: Ia62055b32be039eef84a0f60f0ba307eb5dce6a1
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/239958
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9485
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9485 for details.
-gerrit
the following patch was just integrated into master:
commit 5c8d43e207b4349e95ffb359e0ed08ffa3f789a0
Author: Kevin L Lee <kevin.l.lee(a)intel.com>
Date: Fri Dec 12 14:02:43 2014 +0800
baytrail: fix the coding error on PCIe L1 exit latency
The original code uses L1EXIT_MASK to shift the bit for
PCIe L1 exit latency, the code should use L1EXIT_SHIFT
for bit shifting.
BUG=chrome-os-partner:34037
BRANCH=None
TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15]
set to 010b. Correspond WIFI device performance got improvement.
Signed-off-by: Kevin L Lee <kevin.l.lee(a)intel.com>
Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be
Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92
Original-Reviewed-on: https://chromium-review.googlesource.com/234673
Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com>
Reviewed-on: http://review.coreboot.org/9480
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9480 for details.
-gerrit
the following patch was just integrated into master:
commit e6cf3c6f78149b4c11c7a53f27e684bd560c0ac2
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Dec 19 14:38:51 2014 -0800
TPM: Reduce buffer size to fix stack overflow
The TPM driver by default allocates a 4K transfer buffer on the stack,
which leads to lots of fun on boards with 2K or 3K stack sizes. On
RK3288 this ends up writing over random memory sections which dependent
on the memlayout of the day might contain timestamp data (no big deal)
or page tables (-> bad time).
This patch fixes the problem by reducing the buffer size to slightly
above 1K, which still seems to work as far as I can tell. There was
already some really odd code that #undef'ed this value and redefined it
with the lower number in one .c file (unfortunately not the one with the
buffer declaration), with no explanation whatsoever... I'm removing that
and just assume the smaller value will be fine for everything.
BRANCH=veyron
BUG=None
TEST=Booted Pinky and Falco.
Change-Id: I440a5662b41cbd8b7becab3113262e1140b7f763
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3d3288041b6629b7623b9d58816e782e72836b81
Original-Change-Id: Idf80f44cbfb9617c56b64a5c88ebedf7fcb4ec71
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236976
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9481
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9481 for details.
-gerrit
the following patch was just integrated into master:
commit d946f5e61d0c8966bec57f7d3961e41555b5299a
Author: Kevin Hsieh <kevin.hsieh(a)intel.com>
Date: Wed Nov 26 03:08:18 2014 +0800
Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms
Using REG_PCI_POLL32 to check if the LINK is active with 50ms timeout.
BRANCH=none
BUG=chromium:431169
TEST=Test on Enguarde, compile ok and boot OS
Change-Id: If98ab4e31d17ec4e62d68b93edcec6d9aee87367
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: cf692ae9aebb43ab46cb07d36b62b300b16be1dc
Original-Change-Id: I490e6ffa40979628edf52a7444808b6d25a6e83d
Original-Signed-off-by: Kevin Hsieh <kevin.hsieh(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/231777
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9478
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9478 for details.
-gerrit
the following patch was just integrated into master:
commit 47f112cf80b108066ea7693501665371b8fd41fd
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Nov 23 17:07:50 2014 -0800
tpm: Remove error message for unknown resource type
This is being triggered because the base address is added, but
there is nothing that needs done with it in set_resources step
and the ERROR message is tripping suspend resume test scripts.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=boot on samus and check for ERROR strings,
successfully run suspend_stress_test without failures
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231603
(cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480)
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Change-Id: I565c8af954f1c5a406d2c65f01c274e9259e43ec
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 9062734d884f814dc880589ee615b4d7e1fdc61a
Original-Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3
Original-Reviewed-on: https://chromium-review.googlesource.com/231604
Original-Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org>
Original-Tested-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9476
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9476 for details.
-gerrit
the following patch was just integrated into master:
commit 89f6388e8ca170be7aab143b39bda68798954e08
Author: Kenji Chen <kenji.chen(a)intel.com>
Date: Thu Nov 13 14:44:46 2014 -0800
Broadwell: Set boot_mode of pei_data before running reference code
Some actions are needed and some are not on the way resume from S3.
BRANCH=master
BUG=chrome-os-partner:33025,chrome-os-partner:33796
TEST=Built the image and confimed the boot_mode is correctly
configured.
Signed-off-by: Kenji Chen <kenji.chen(a)intel.com>
Change-Id: If400df94f970a55f3921a5a2df24038d28beb489
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 40e719618ec101235cdb1755933e719abd873239
Original-Change-Id: Ia042ea8c63c2306e9d6a80d8efa66c4fc0722d85
Original-Reviewed-on: https://chromium-review.googlesource.com/229615
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com>
Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com>
Reviewed-on: http://review.coreboot.org/9475
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9475 for details.
-gerrit
the following patch was just integrated into master:
commit 432762410e74b94a17be6e1027592c9d6ced8610
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Nov 11 08:31:26 2014 -0800
samus: Move board version to a separate file
This combines the board version reading and parsing to
a separate file that is compiled in both romstage (for
early serial output) and ramstage (for smbios tables).
It also adds a new board version that is wrapped back
to number zero as we are running out of available IDs.
BUG=chrome-os-partner:32895
BRANCH=samus
TEST=build and boot on samus EVT1 and EVT2 and check
for proper board versions reported in console and smbios.
Change-Id: I8c8f17708ced7167277a98529ff4597589f53095
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3ab8bba1021a8dd41dd2210ba73efd2231eb596c
Original-Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229041
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9473
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9473 for details.
-gerrit
the following patch was just integrated into master:
commit dd281edcfab464c4bf9df3fa9d86db5639c845e0
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Oct 30 15:20:19 2014 -0700
tpm: Add ramstage driver and interrupt configuration
This adds a ramstage driver for the TPM and allows the interrupt
to be configured in devicetree.cb.
The interrupt vector is set like other PNP devices, and the
interrupt polarity is set with a register configuration variable.
These values are written into locality 0 TPM_INT_VECTOR and
TPM_INT_ENABLE and then all interrupts are disabled so they are
not used in firmware but can be enabled by the OS.
It also adds an ACPI device for the TPM which will configure the
reported interrupt based on what has been written into the TPM
during ramstage. The _STA method returns enabled if CONFIG_LPC_TPM
is enabled, and the _CRS method will only report an interrupt if one
has been set in the TPM itself.
The TPM memory address is added by the driver and declared in the
ACPI code. In order to access it in ACPI a Kconfig entry is added for
the default TPM TIS 1.2 base address. Note that IO address 0x2e is
required to be declared in ACPI for the kernel driver to probe correctly.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=manual testing on samus:
1) Add TPM device in devicetree.cb with configured interrupt and
ensure that it is functional in the OS.
2) Test with active high and active low, edge triggered and level
triggered setups.
3) Ensure that with no device added to devicetree.cb that the TPM
is still functional in polling mode.
Change-Id: Iee2a1832394dfe32f3ea3700753b8ecc443c7fbf
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: fc2c106caae939467fb07f3a0207adee71dda48e
Original-Change-Id: Id8a5a251f193c71ab2209f85fb470120a3b6a80d
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226661
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9469 for details.
-gerrit
the following patch was just integrated into master:
commit 1ab1eac63ec4c13655e917eb34c86bbf290802a2
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Oct 30 15:11:48 2014 -0700
tpm: Move the LPC TPM driver to a subdirectory
This moves the LPC TPM driver to drivers/pc80/tpm so it can
be turned into a ramstage driver with a chip.h
It includes no other changes yet.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=emerge-samus coreboot
Change-Id: Iac83e52db96201f37a0086eae9df244f8b8d48d9
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: be2db391f9da80b8b75137af0fe81dc4724bc9d1
Original-Change-Id: I60ddd1d2a3e72bcf169a0b44e0c7ebcb87f4617d
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226660
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9468
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9468 for details.
-gerrit