the following patch was just integrated into master:
commit f9a6a82ea64074ba401213256011f4875b2763de
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Jan 15 13:24:38 2015 -0800
samus: Add clear_recovery_mode_switch function
In order for recovery request to be cleared with software sync disabled
we need to implement this function in the mainboard.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=boot in recovery with software sync disabled, ensure that the next
boot will not boot in recovery again.
Change-Id: Ie9c845396dfc6ab65296b2f18a86e23590c833d6
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 430f85608cc3b59a68a86dba64ffe428bfc216a9
Original-Change-Id: Iac15b6a1b23cc971231339439bceb013f4a031bd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241052
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9492
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9492 for details.
-gerrit
the following patch was just integrated into master:
commit a5c417ecd8174b0c8bfaa3f89acbad97efc9de34
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:36:08 2015 -0800
samus: Set current backlight PWM value
With recent changes in the 3.14 kernel and the switch to not
using X the panel backlight is not geting turned on until
chrome is started which means the splash screen is not visible.
If we set the backlight PWM in coreboot then it will at least
turn on for the early boot process.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=boot on samus in normal mode and see the boot splash logo
Change-Id: I81e6b90617acb181b4de3365f8f56ec3b846b78b
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f850fe3faff268a64f18e6bd176ec1126b921e3b
Original-Change-Id: I622bef8af9bb6b753fe228b33ecdc4aae76af131
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240853
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9491
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9491 for details.
-gerrit
the following patch was just integrated into master:
commit f3e0a13f70f2467dc99fec89baa8298636a9251c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:33:00 2015 -0800
broadwell: Turn off panel backlight in S5 SMI handler
In order for some panels to meet spec when the system is put
into S5 by way of power button during firmware (i.e. not by
the OS) then it needs to turn off the backlight and give it
time to turn off before going into S5.
If the OS properly sequences the panel down then the backlight
enable bit will not be set in this step and nothing will happen.
BUG=chrome-os-partner:33994
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: Ic86f388218f889b1fe690cc1bfc5c3e233e95115
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: e3c9c131a87bae380e1fd3f96c9ad780441add56
Original-Change-Id: I43c5aee8e32768fc9e82790c9f7ceda0ed17ed13
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240852
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9490
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9490 for details.
-gerrit
the following patch was just integrated into master:
commit cad2b7b6e896ffd11d09f0017da1fd1f80d61c09
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:30:20 2015 -0800
broadwell: Skip steps when disabling PCIe port
When disabling PCIe ports skip steps if no card is detected.
This prevents the loop from timing out on each empty slot.
BUG=chrome-os-partner:31424
BRANCH=broadwell
TEST=build and boot on samus, check that this code is
no longer timing out when disabling PCIe ports
Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef
Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240851
Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9489
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9489 for details.
-gerrit
the following patch was just integrated into master:
commit cf544ac1f9a62cc58e3911c23a0b905950a0ff2f
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 12:18:46 2015 -0800
broadwell: Remove XHCI workarounds on WPT
The workarounds in ACPI methods for D0/D3 transition that are
used on haswell/LPT do not all apply to broadwell/WPT.
BUG=chrome-os-partner:28234
BRANCH=broadwell
TEST=build and boot on samus, test USB functionality and wake
and ensure the device still does into D3 state
Change-Id: Ic3a75f5bf50e826ade7d942b48cfebb75cf976e6
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 1b54d105957ee80ca34048c42fb8f241731281cf
Original-Change-Id: I877afd51fc6c9b7906e923b893fc31bdf2cd1090
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240850
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9488
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9488 for details.
-gerrit
the following patch was just integrated into master:
commit b8a7b71e611fed87a41cc940baa1e42624f97657
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Nov 10 13:00:27 2014 -0800
broadwell: Only do pre-graphics delay when running option rom
This changes the broadwell graphics init path to only do the delay
before initializing graphics when running chromeos if we are also
going to execute the option rom.
BUG=chrome-os-partner:33671
BRANCH=samus
TEST=build and boot on samus
Change-Id: Idb7d39b22f7f6dc3be6dfbd2fa3cc2e33d78a397
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f7ed93504a74760f16acb8fb3c6c57ac514b7260
Original-Change-Id: I350f85738efe3d17152de4f025adbfd52ae15b95
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228882
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9474 for details.
-gerrit
the following patch was just integrated into master:
commit e0dae99b47faf6e750938bc52550128a4351f93e
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Thu Jan 15 15:02:55 2015 -0800
PCI - Add interrupt disable bit definition
BRANCH=none
BUG=None
TEST=Build Braswell/Strago
Change-Id: I11a4c02af3b40edf2252b9e20298941b99f31d21
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 1629d7454a3d4adb8930d14849c41c9a711f4c9a
Original-Change-Id: Ie907637f7c823de681ef2e315e803dffc6ad33d3
Original-Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241081
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9487
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9487 for details.
-gerrit
the following patch was just integrated into master:
commit c05710f196e2ff20881a67adace949efc29d9f1f
Author: Ben Zhang <benzh(a)chromium.org>
Date: Mon Dec 15 17:38:11 2014 -0800
samus: Add ACPI binding for rt5677 codec SPI
We'll need to find a real ACPI device ID for
the rt5677 SPI driver. "RT5677AA" is temporary.
BUG=chrome-os-partner:33495
BRANCH=samus
TEST=load firmware via SPI; hotword detection works
Change-Id: I6dc55c4641c27a38570debe841a6afeb048eb868
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f0d7013b62c78deb82db1a431f079c79eded5270
Original-Change-Id: Ifb4a1b12776669e21c0b7c4679246717d72981ad
Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/235902
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9486 for details.
-gerrit
the following patch was just integrated into master:
commit 83067610f754f89025bf781cdf8857135e946b03
Author: Wenkai Du <wenkai.du(a)intel.com>
Date: Fri Dec 5 14:00:26 2014 -0800
broadwell: Fix PCIe ports programming sequences to enable HSIOPC
HSIOPC/GPIO71 is used to control power to VCCHSIO, VCCUSB3PLL and
VCCSATA3PLL in S0. PCH will drive HSIOPC low when all the high
speed I/O controllers (xHCI, SATA, GbE and PCIe) are idle.
This patch added a few additional PCIe programming steps as required
in 535127 BIOS Writer Guide Rev 2.3.0 to enable this power saving mode.
BUG=none
BRANCH=none
TEST=tested on Paine watching GPIO71 toggling as expected
Change-Id: Ica6954c125ec3129e2659168f1f23dc861ce5708
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: e38f9ef57c480ca5ee420020eb80a1adb3c381d3
Original-Change-Id: I88ef125c681c8631e8b887f7ccf017b90b8c0f10
Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/238580
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9482
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9482 for details.
-gerrit
the following patch was just integrated into master:
commit b75fb0acda99e804b5049ff75f3a51454fb7ba2c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 6 15:22:41 2015 -0800
samus: Add RT5677 ACPI/DT bindings with _DSD
To support the ACPI device specific properties that conform to the
existing devicetree bindings for this codec (in upstream kernels)
add a _DSD object to the existing codec device.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=build and boot on samus
Change-Id: Ice808ba7bf2f0378ac5a38afd27dbf6c8cac0da5
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: b3fc2d7e5a5878b1fff7627f803b883b38fea28d
Original-Change-Id: I344636171a3086a72087314503bfc99de5945b1f
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238857
Original-Reviewed-by: Ben Zhang <benzh(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9483
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9483 for details.
-gerrit