coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 6e76fff program loading: provide one cache maintenance callback
by gerrit＠coreboot.org 31 Mar '15

31 Mar '15

the following patch was just integrated into master: commit 6e76fff96961264e8c7213142966de6589092291 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 20 09:42:05 2015 -0500 program loading: provide one cache maintenance callback Instead of having 2 different functions to call when a program is loaded provide a single callback with flags parameter. The previous callbacks for cache management routines did this: for_each_program_segment: arch_program_segment_loaded(start, size); arch_program_loaded(); Now, use one callback instead: for_each_program_segment: arch_segment_loaded(start, size, SEG_FINAL?); Change-Id: I3811cba92e3355d172f605e4444f053321b07a2a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/8838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8838 for details. -gerrit

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Patch merged into coreboot/master: ebf2ed4 payload loading: remove passing of struct payload
by gerrit＠coreboot.org 31 Mar '15

31 Mar '15

the following patch was just integrated into master: commit ebf2ed46211e0ccd82d11c34226eb578f9532a2a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 20 10:20:15 2015 -0500 payload loading: remove passing of struct payload There's no need to keep track of struct payload within the boot state machine. It is completely contained within the payload loader module. Change-Id: I16fcecf43d7fb41fc311955fdb82eabbd5c96b11 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/8836 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8836 for details. -gerrit

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Patch merged into coreboot/master: fcfdff8 loading: move ramstage cache function declarations
by gerrit＠coreboot.org 31 Mar '15

31 Mar '15

the following patch was just integrated into master: commit fcfdff84f4ddd6fe7bf68c3bc84c0173911d13de Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 20 10:58:41 2015 -0500 loading: move ramstage cache function declarations The functions related to caching ramstage were in cbfs.h. Now that the loading code is separate move those declarations to the common program_loading.h. Change-Id: Ib22ef8a9c66e1d2b53388bceb8386baa6302d28b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/8835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8835 for details. -gerrit

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Patch set updated for coreboot: 3549fff northbridge/amd/amdmct: Pack MCT and DCT info structs
by Timothy Pearson 31 Mar '15

31 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9158 -gerrit commit 3549ffffc23083a5e1f4d1a5b4e5b6d76c697f50 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Mar 29 16:21:23 2015 -0500 northbridge/amd/amdmct: Pack MCT and DCT info structs This allows safe access of romstage MCT values from ramstage Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct/mct_d.h | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 0a1f925..0c6df6c 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -260,7 +260,7 @@ struct MCTStatStruc { of sub 4GB dram hole for HW remapping.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ -}; +} __attribute__((packed)); /*============================================================================= Global MCT Configuration Status Word (GStatus) @@ -512,7 +512,7 @@ struct DCTStatStruc { /* A per Node structure*/ u32 dev_map; u32 dev_dct; u32 dev_nbmisc; -}; +} __attribute__((packed)); /*=============================================================================== Local Error Status Codes (DCTStatStruc.ErrCode) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 42cca26..8e73afe 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -287,7 +287,7 @@ struct MCTStatStruc { of sub 4GB dram hole for HW remapping.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ -}; +} __attribute__((packed)); /*============================================================================= Global MCT Configuration Status Word (GStatus) @@ -575,7 +575,7 @@ struct DCTStatStruc { /* A per Node structure*/ struct _sMCTStruct s_C_MCTPtr; struct _sDCTStruct s_C_DCTPtr[2]; /* struct _sDCTStruct s_C_DCT1Ptr[8]; */ -}; +} __attribute__((packed)); /*=============================================================================== Local Error Status Codes (DCTStatStruc.ErrCode)

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Patch set updated for coreboot: 7802ead northbridge/amd/amdfam10: Collect DIMM information for ramstage use
by Timothy Pearson 31 Mar '15

31 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9137 -gerrit commit 7802eadc48813ec02030a42bb8975f89173256c9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:50:09 2015 -0500 northbridge/amd/amdfam10: Collect DIMM information for ramstage use 1.) Allow MCT information structures to be copied to cbmem. 2.) Retrieve DIMM vendor, model, and serial information. 3.) Allow maximum installable memory to be set via devicetree. Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/include/cbmem.h | 2 ++ src/northbridge/amd/amdfam10/amdfam10.h | 1 + src/northbridge/amd/amdfam10/amdfam10_util.c | 1 + src/northbridge/amd/amdfam10/chip.h | 29 ++++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct/mct_d.c | 28 +++++++++++++++++++++++++-- src/northbridge/amd/amdmct/mct/mct_d.h | 29 ++++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 29 ++++++++++++++++++++++++++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 28 +++++++++++++++++++++++++++ 8 files changed, 143 insertions(+), 4 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index f605191..8ba0881 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -73,6 +73,7 @@ #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_RAM_OOPS 0x05430095 #define CBMEM_ID_MEMINFO 0x494D454D +#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E #define CBMEM_ID_SPINTABLE 0x59175917 #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 @@ -119,6 +120,7 @@ struct cbmem_id_to_name { { CBMEM_ID_POWER_STATE, "POWER STATE" }, \ { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \ { CBMEM_ID_MEMINFO, "MEM INFO " }, \ + { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, struct cbmem_entry; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index a77d036..238c45f 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -977,6 +977,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "raminit.h" +#include "../amdmct/wrappers/mcti.h" #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ #include "../amdmct/mct_ddr3/mct_d.h" #else diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 2726b28..621c28f 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <arch/cpu.h> +#include <northbridge/amd/amdmct/wrappers/mcti.h> #include <northbridge/amd/amdmct/mct/mct_d.h> #include <northbridge/amd/amdmct/amddefs.h> diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h new file mode 100644 index 0000000..ab853d6 --- /dev/null +++ b/src/northbridge/amd/amdfam10/chip.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_FAM10_CHIP_H_ +#define _AMD_FAM10_CHIP_H_ + +#include <stdint.h> + +struct northbridge_amd_amdfam10_config { + uint64_t maximum_memory_capacity; +}; + +#endif /* _AMD_FAM10_CHIP_H_ */ \ No newline at end of file diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index bf832da..64cb1bc 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -2122,7 +2122,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, * DATABload=number of ranks on the "B" bus slots. */ - u16 i, j; + u16 i, j, k; u8 smbaddr, Index; u16 Checksum; u8 SPDCtrl; @@ -2183,10 +2183,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid |= 1 << i; } } + /* Get module information for SMBIOS */ + if (pDCTstat->DIMMValid & (1 << i)) { + pDCTstat->DimmManufacturerID[i] = 0; + for (k = 0; k < 8; k++) + pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); + for (k = 0; k < SPD_PARTN_LENGTH; k++) + pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); + pDCTstat->DimmRevisionNumber[i] = 0; + for (k = 0; k < 2; k++) + pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); + pDCTstat->DimmSerialNumber[i] = 0; + for (k = 0; k < 4; k++) + pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); + pDCTstat->DimmRows[i] = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0xf; + pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_COLSZ) & 0xf; + pDCTstat->DimmRanks[i] = (mctRead_SPD(smbaddr, SPD_DMBANKS) & 0x7) + 1; + pDCTstat->DimmBanks[i] = mctRead_SPD(smbaddr, SPD_LBANKS); + pDCTstat->DimmWidth[i] = mctRead_SPD(smbaddr, SPD_DEVWIDTH); + } /* Check module type */ byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE); - if (byte & JED_REGADCMSK) + if (byte & JED_REGADCMSK) { RegDIMMPresent |= 1 << i; + pDCTstat->DimmRegistered[i] = 1; + } + else { + pDCTstat->DimmRegistered[i] = 0; + } /* Check ECC capable */ byte = mctRead_SPD(smbaddr, SPD_EDCTYPE); if (byte & JED_ECC) { diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 0c6df6c..a178696 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -231,10 +232,17 @@ #define SPD_TRC 41 #define SPD_TRFC 42 +#define SPD_MANID_START 64 +#define SPD_PARTN_START 73 +#define SPD_PARTN_LENGTH 18 +#define SPD_REVNO_START 91 + #define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ +#define SPD_SERIAL_START 95 + /*----------------------------- Jedec DDR II related equates -----------------------------*/ @@ -512,6 +520,18 @@ struct DCTStatStruc { /* A per Node structure*/ u32 dev_map; u32 dev_dct; u32 dev_nbmisc; + + uint8_t DimmRows[MAX_DIMMS_SUPPORTED]; + uint8_t DimmCols[MAX_DIMMS_SUPPORTED]; + uint8_t DimmRanks[MAX_DIMMS_SUPPORTED]; + uint8_t DimmBanks[MAX_DIMMS_SUPPORTED]; + uint8_t DimmWidth[MAX_DIMMS_SUPPORTED]; + uint8_t DimmRegistered[MAX_DIMMS_SUPPORTED]; + + uint64_t DimmManufacturerID[MAX_DIMMS_SUPPORTED]; + char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH]; + uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; + uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; } __attribute__((packed)); /*=============================================================================== @@ -666,6 +686,15 @@ struct DCTStatStruc { /* A per Node structure*/ xx0b = disable yy1b = enable with DctSelIntLvAddr set to yyb */ +/*=============================================================================== + CBMEM storage +===============================================================================*/ +struct amdmct_memory_info { + struct MCTStatStruc mct_stat; + struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; + uint16_t ecc_enabled; + uint16_t ecc_scrub_rate; +} __attribute__((packed)); u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 770b663..0f4dd43 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -2030,7 +2031,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, * DATAAload=number of ranks on the "A" bus slots. * DATABload=number of ranks on the "B" bus slots. */ - u16 i, j; + u16 i, j, k; u8 smbaddr; u8 SPDCtrl; u16 RegDIMMPresent, MaxDimms; @@ -2077,10 +2078,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid |= 1 << i; } } + /* Get module information for SMBIOS */ + if (pDCTstat->DIMMValid & (1 << i)) { + pDCTstat->DimmManufacturerID[i] = 0; + for (k = 0; k < 8; k++) + pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); + for (k = 0; k < SPD_PARTN_LENGTH; k++) + pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); + pDCTstat->DimmRevisionNumber[i] = 0; + for (k = 0; k < 2; k++) + pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); + pDCTstat->DimmSerialNumber[i] = 0; + for (k = 0; k < 4; k++) + pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); + pDCTstat->DimmRows[i] = (mctRead_SPD(smbaddr, SPD_Addressing) & 0x38) >> 3; + pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_Addressing) & 0x7; + pDCTstat->DimmRanks[i] = ((mctRead_SPD(smbaddr, SPD_Organization) & 0x38) >> 3) + 1; + pDCTstat->DimmBanks[i] = 1ULL << (((mctRead_SPD(smbaddr, SPD_Density) & 0x70) >> 4) + 3); + pDCTstat->DimmWidth[i] = 1ULL << ((mctRead_SPD(smbaddr, SPD_BusWidth) & 0x7) + 3); + } /* Check module type */ byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE) & 0x7; - if (byte == JED_RDIMM || byte == JED_MiniRDIMM) + if (byte == JED_RDIMM || byte == JED_MiniRDIMM) { RegDIMMPresent |= 1 << i; + pDCTstat->DimmRegistered[i] = 1; + } + else { + pDCTstat->DimmRegistered[i] = 0; + } /* Check ECC capable */ byte = mctRead_SPD(smbaddr, SPD_BusWidth); if (byte & JED_ECC) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 8e73afe..0b1d48f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -262,6 +263,12 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ +#define SPD_MANID_START 117 +#define SPD_SERIAL_START 122 +#define SPD_PARTN_START 128 +#define SPD_PARTN_LENGTH 18 +#define SPD_REVNO_START 146 + /*----------------------------- Jedec DDR II related equates -----------------------------*/ @@ -575,6 +582,18 @@ struct DCTStatStruc { /* A per Node structure*/ struct _sMCTStruct s_C_MCTPtr; struct _sDCTStruct s_C_DCTPtr[2]; /* struct _sDCTStruct s_C_DCT1Ptr[8]; */ + + uint8_t DimmRows[MAX_DIMMS_SUPPORTED]; + uint8_t DimmCols[MAX_DIMMS_SUPPORTED]; + uint8_t DimmRanks[MAX_DIMMS_SUPPORTED]; + uint8_t DimmBanks[MAX_DIMMS_SUPPORTED]; + uint8_t DimmWidth[MAX_DIMMS_SUPPORTED]; + uint8_t DimmRegistered[MAX_DIMMS_SUPPORTED]; + + uint64_t DimmManufacturerID[MAX_DIMMS_SUPPORTED]; + char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH]; + uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; + uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; } __attribute__((packed)); /*=============================================================================== @@ -727,6 +746,15 @@ struct DCTStatStruc { /* A per Node structure*/ xx0b = disable yy1b = enable with DctSelIntLvAddr set to yyb */ +/*=============================================================================== + CBMEM storage +===============================================================================*/ +struct amdmct_memory_info { + struct MCTStatStruc mct_stat; + struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; + uint16_t ecc_enabled; + uint16_t ecc_scrub_rate; +} __attribute__((packed)); u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val);

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Patch set updated for coreboot: 963f9de mainboard/asus/kfsn4-dre: Set maximum installable memory to 64GB
by Timothy Pearson 31 Mar '15

31 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9139 -gerrit commit 963f9deeec46303af52da38b3963b408fcc1a630 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:48:51 2015 -0500 mainboard/asus/kfsn4-dre: Set maximum installable memory to 64GB Change-Id: I480d6bfe29c77119892fcb1fbb9779fd7e3529c3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb index 928790b..50e2862 100644 --- a/src/mainboard/asus/kfsn4-dre/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -7,6 +7,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device domain 0 on # PCI domain subsystemid 0x1043 0x8162 inherit chip northbridge/amd/amdfam10 # Northbridge / RAM controller + register "maximum_memory_capacity" = "0x1000000000" # 64GB device pci 18.0 on end # Link 0 == LDT 0 device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] chip southbridge/nvidia/ck804 # Southbridge

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Patch set updated for coreboot: eb9fc91 mainboards/amdfam10: Copy DIMM information to cbmem after romstage
by Timothy Pearson 31 Mar '15

31 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9138 -gerrit commit eb9fc91265cf3a528c861f4a5939ee6f3fd2ff25 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:49:18 2015 -0500 mainboards/amdfam10: Copy DIMM information to cbmem after romstage src/northbridge/amd/amdfam10: Add amdmct_cbmem_store_info() function. Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/advansus/a785e-i/romstage.c | 2 ++ src/mainboard/amd/bimini_fam10/romstage.c | 2 ++ src/mainboard/amd/mahogany_fam10/romstage.c | 2 ++ .../amd/serengeti_cheetah_fam10/romstage.c | 2 ++ src/mainboard/amd/tilapia_fam10/romstage.c | 2 ++ src/mainboard/asus/kfsn4-dre/romstage.c | 2 ++ src/mainboard/asus/m4a78-em/romstage.c | 2 ++ src/mainboard/asus/m4a785-m/romstage.c | 2 ++ src/mainboard/asus/m5a88-v/romstage.c | 2 ++ src/mainboard/avalue/eax-785e/romstage.c | 2 ++ src/mainboard/gigabyte/ma785gm/romstage.c | 2 ++ src/mainboard/gigabyte/ma785gmt/romstage.c | 2 ++ src/mainboard/gigabyte/ma78gm/romstage.c | 2 ++ src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 ++ src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 ++ src/mainboard/jetway/pa78vm5/romstage.c | 2 ++ src/mainboard/msi/ms9652_fam10/romstage.c | 2 ++ src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 ++ src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 ++ src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 ++ src/mainboard/tyan/s2912_fam10/romstage.c | 2 ++ src/northbridge/amd/amdfam10/raminit_amdmct.c | 40 ++++++++++++++++++++++ 22 files changed, 82 insertions(+) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index a70c269..e94d1e1 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index f4df3a3..299bc5e 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -208,6 +208,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 501c8c3..669e152 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 2932c83..a330ccd 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -322,6 +322,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 97bf51a..8c6a8ce 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index af6858f..9680174 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -353,6 +353,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + printk(BIOS_DEBUG, "disable_spd()\n"); ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index da63c66..e2e60ab 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -212,6 +212,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index e0c132f..e43dc05 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -212,6 +212,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index cc4d04d..23bdb97 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -207,6 +207,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 5cc9fb1..ee83fb5 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -211,6 +211,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 991531d..f1fdfc0 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -207,6 +207,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index a022a20..cee66fa 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -207,6 +207,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 7675e25..5ba5f15 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index bf054d5..9610dda 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -214,6 +214,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + bcm5785_early_setup(); timestamp_add_now(TS_END_ROMSTAGE); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 5f99df6..0d1fd89 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -210,6 +210,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 1686988..1467a9e 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -215,6 +215,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index b2bfc8b..4231675 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -241,6 +241,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + timestamp_add_now(TS_END_ROMSTAGE); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 980437b..e1707ac 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -238,6 +238,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + timestamp_add_now(TS_END_ROMSTAGE); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 20522e1..7a75159 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -301,6 +301,8 @@ post_code(0x40); cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + timestamp_add_now(TS_END_ROMSTAGE); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 355cf82..4b6eeb6 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -222,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 933d709..fef8ecc 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -237,6 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + amdmct_cbmem_store_info(sysinfo); + timestamp_add_now(TS_END_ROMSTAGE); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 02dc956..6a71cd5 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -204,3 +204,43 @@ static void raminit_amdmct(struct sys_info *sysinfo) printk(BIOS_DEBUG, "raminit_amdmct end:\n"); } + +static void amdmct_cbmem_store_info(struct sys_info *sysinfo) +{ + /* Save memory info structures for use in ramstage */ + size_t i; + struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); + struct DCTStatStruc *pDCTstatA = NULL; + + if (pMCTstat && sysinfo->DCTstatA) { + /* Allocate memory */ + struct amdmct_memory_info* mem_info; + mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); + if (!mem_info) + return; + + printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__); + + /* Initialize memory */ + memset(mem_info, 0, sizeof(struct amdmct_memory_info)); + + /* Copy data */ + memcpy(&mem_info->mct_stat, &(sysinfo->MCTstat), sizeof(struct MCTStatStruc)); + for (i = 0; i < MAX_NODES_SUPPORTED; i++) { + pDCTstatA = sysinfo->DCTstatA + i; + memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc)); + } + mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP); + mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); + + /* Zero out invalid/unused pointers */ +#if IS_ENABLED(CONFIG_DIMM_DDR3) + + for (i = 0; i < MAX_NODES_SUPPORTED; i++) { + mem_info->dct_stat[i].C_MCTPtr = NULL; + mem_info->dct_stat[i].C_DCTPtr[0] = NULL; + mem_info->dct_stat[i].C_DCTPtr[1] = NULL; + } +#endif + } +}

1 0

Patch set updated for coreboot: 29a9493 northbridge/amd/amdfam10: Generate SMBIOS tables for RAM
by Timothy Pearson 31 Mar '15

31 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9140 -gerrit commit 29a9493ceff7cd7c2b56195c61b38434da06edaf Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:58:45 2015 -0500 northbridge/amd/amdfam10: Generate SMBIOS tables for RAM TEST: Booted ASUS KFSN4-DRE and verified SMBIOS contents via dmidecode utility. Change-Id: Id656f2f6cf5a4ecafa03e150ad91f69107a4fe88 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 177 +++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 9206de7..f857b72 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -28,6 +28,7 @@ #include <stdlib.h> #include <string.h> #include <lib.h> +#include <smbios.h> #include <cpu/cpu.h> #include <cpu/x86/lapic.h> @@ -43,6 +44,7 @@ #include "northbridge.h" #include "amdfam10.h" #include "ht_config.h" +#include "chip.h" #if CONFIG_HW_MEM_HOLE_SIZEK != 0 #include <cpu/amd/model_10xxx_rev.h> @@ -945,6 +947,178 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) return max; } +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *current) +{ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info == NULL) + return 0; /* can't find amdmct information in cbmem */ + + struct device *dev = get_node_pci(0, 0); + struct northbridge_amd_amdfam10_config *config = dev->chip_info; + + int node; + int slot; + + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16); + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = handle; + t->length = len - 2; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->use = MEMORY_ARRAY_USE_SYSTEM; + t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; + if ((mem_info->ecc_enabled) + && (mem_info->mct_stat.GStatus & (1 << GSB_ECCDIMMs)) + && !(mem_info->mct_stat.GStatus & (1 << GSB_DramECCDis))) + /* Single-bit ECC enabled */ + t->memory_error_correction = MEMORY_ARRAY_ECC_SINGLE_BIT; + t->maximum_capacity = config->maximum_memory_capacity / 1024; /* Convert to kilobytes */ + t->memory_error_information_handle = 0xFFFE; /* no error information handle available */ + + t->number_of_memory_devices = 0; + /* Check all nodes for installed DIMMs */ + for (node = 0; node < MAX_NODES_SUPPORTED; node++) + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) + /* Found an installed DIMM; increment count */ + t->number_of_memory_devices++; + + *current += len; + *count += 1; + return len; +} + +static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) +{ + switch (speed) { + case 1: + return 200; + case 2: + return 266; + case 3: + return 333; + case 4: + return 400; + case 5: + return 533; + default: + return 0; + } +} + +static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, unsigned long *current) +{ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info == NULL) + return 0; /* can't find amdmct information in cbmem */ + + int single_len; + int len = 0; + int node; + int slot; + + /* Check all nodes for installed DIMMs */ + for (node = 0; node < MAX_NODES_SUPPORTED; node++) { + /* Get configured RAM bus speed */ + uint16_t speed; + speed = amdmct_mct_speed_enum_to_mhz(mem_info->dct_stat[node].Speed); + + /* Get maximum RAM bus speed */ + uint16_t max_speed; + max_speed = amdmct_mct_speed_enum_to_mhz(mem_info->dct_stat[node].DIMMAutoSpeed); + + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { + /* Found an installed DIMM; populate tables */ + struct smbios_type17 *t = (struct smbios_type17 *)*current; + char string_buffer[256]; + + /* Initialize structure */ + memset(t, 0, sizeof(struct smbios_type17)); + + /* Calculate the total module size in bytes: + * Primary data width * 2^(#rows) * 2^(#cols) * #banks * #ranks + */ + uint8_t width, rows, cols, banks, ranks; + width = 8; + rows = mem_info->dct_stat[node].DimmRows[slot]; + cols = mem_info->dct_stat[node].DimmCols[slot]; + ranks = mem_info->dct_stat[node].DimmRanks[slot]; + banks = mem_info->dct_stat[node].DimmBanks[slot]; + uint64_t dimm_size_bytes = width * (1ULL << rows) * (1ULL << cols) * banks * ranks; + + memset(t, 0, sizeof(struct smbios_type17)); + t->type = SMBIOS_MEMORY_DEVICE; + t->handle = handle; + t->phys_memory_array_handle = parent_handle; + t->length = sizeof(struct smbios_type17) - 2; + if (dimm_size_bytes > 0x800000000) { + t->size = 0x7FFF; + t->extended_size = dimm_size_bytes; + } + else { + t->size = dimm_size_bytes / (1024*1024); + t->size &= (~0x8000); /* size specified in megabytes */ + } + t->total_width = t->data_width = 64; + if (mem_info->dct_stat[node].DimmECCPresent & (1 << slot)) + t->total_width += 8; + t->attributes = 0; + t->attributes |= ranks & 0xf; /* rank number is stored in the lowest 4 bits of the attributes field */ + t->form_factor = MEMORY_FORMFACTOR_DIMM; + snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); + t->device_locator = smbios_add_string(t->eos, string_buffer); + if (IS_ENABLED(CONFIG_DIMM_DDR2)) + t->memory_type = MEMORY_TYPE_DDR2; + else if (IS_ENABLED(CONFIG_DIMM_DDR3)) + t->memory_type = MEMORY_TYPE_DDR3; + t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; + if (mem_info->dct_stat[node].DimmRegistered[slot]) + t->type_detail |= MEMORY_TYPE_DETAIL_REGISTERED; + else + t->type_detail |= MEMORY_TYPE_DETAIL_UNBUFFERED; + t->speed = max_speed; + t->clock_speed = speed; + smbios_fill_dimm_manufacturer_from_id(mem_info->dct_stat[node].DimmManufacturerID[slot], t); + t->part_number = smbios_add_string(t->eos, mem_info->dct_stat[node].DimmPartNumber[slot]); + if (mem_info->dct_stat[node].DimmSerialNumber[slot] == 0) { + t->serial_number = smbios_add_string(t->eos, "None"); + } + else { + snprintf(string_buffer, sizeof (string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]); + t->serial_number = smbios_add_string(t->eos, string_buffer); + } + t->memory_error_information_handle = 0xFFFE; /* no error information handle available */ + single_len = t->length + smbios_string_table_len(t->eos); + len += single_len; + *current += single_len; + handle++; + *count += 1; + } + } + } + + return len; +} + +static int amdfam10_get_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + int count = 0; + len = amdfam10_get_smbios_data16(&count, *handle, current); + len += amdfam10_get_smbios_data17(&count, *handle + 1, *handle, current); + *handle += count; + return len; +} +#endif + static struct device_operations pci_domain_ops = { .read_resources = amdfam10_domain_read_resources, .set_resources = amdfam10_domain_set_resources, @@ -952,6 +1126,9 @@ static struct device_operations pci_domain_ops = { .init = NULL, .scan_bus = amdfam10_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, +#if CONFIG_GENERATE_SMBIOS_TABLES + .get_smbios_data = amdfam10_get_smbios_data, +#endif }; static void sysconf_init(device_t dev) // first node

1 0

Patch set updated for coreboot: 044ceea mainboard/supermicro/h8qme_fam10: Fix indentations and spelling
by Timothy Pearson 31 Mar '15

31 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9177 -gerrit commit 044ceeac014fd0d1a6b60cc608ffea837f639d48 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 31 11:54:03 2015 -0500 mainboard/supermicro/h8qme_fam10: Fix indentations and spelling Change-Id: I49c5d39a674351f7375fb762fc9ef4a3700d7c87 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/supermicro/h8qme_fam10/romstage.c | 181 ++++++++++++------------ 1 file changed, 91 insertions(+), 90 deletions(-) diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 7a75159..8583f2a 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -50,10 +50,11 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); } @@ -77,36 +78,36 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void sio_setup(void) { - uint32_t dword; - uint8_t byte; - enable_smbus(); + uint32_t dword; + uint8_t byte; + enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } static const u8 spd_addr[] = { - //first node + /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - //third node + /* third node */ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - //forth node + /* fourth node */ RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, #endif }; @@ -183,12 +184,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sio_setup(); } - post_code(0x30); + post_code(0x30); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - post_code(0x32); + post_code(0x32); w83627hf_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -200,113 +201,113 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); - update_microcode(val); + update_microcode(val); - post_code(0x33); + post_code(0x33); - cpuSetAMDMSR(); - post_code(0x34); + cpuSetAMDMSR(); + post_code(0x34); - amd_ht_init(sysinfo); - post_code(0x35); + amd_ht_init(sysinfo); + post_code(0x35); - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fixup prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); #endif - post_code(0x38); + post_code(0x38); #if CONFIG_SET_FIDVID - msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ + /* FIXME: The sb fid change may survive the warm reset and only + * need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - post_code(0x39); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } - post_code(0x3A); + post_code(0x3A); - /* show final fid and vid */ - msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); // Need to use TMICT to synchronize FID/VID - wants_reset = mcp55_early_setup_x(); + wants_reset = mcp55_early_setup_x(); - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset_x - shouldn't see this message!!!\n"); - } + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } - if (wants_reset) - printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); + if (wants_reset) + printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); - post_code(0x3B); + post_code(0x3B); -/* It's the time to set ctrl in sysinfo now; */ -printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); -fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); -post_code(0x3D); + post_code(0x3D); -//printk(BIOS_DEBUG, "enable_smbus()\n"); -// enable_smbus(); /* enable in sio_setup */ +// printk(BIOS_DEBUG, "enable_smbus()\n"); +// enable_smbus(); /* enable in sio_setup */ -post_code(0x40); + post_code(0x40); timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); - raminit_amdmct(sysinfo); + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); timestamp_add_now(TS_AFTER_INITRAM); - cbmem_initialize_empty(); - post_code(0x41); + cbmem_initialize_empty(); + post_code(0x41); - amdmct_cbmem_store_info(sysinfo); + amdmct_cbmem_store_info(sysinfo); timestamp_add_now(TS_END_ROMSTAGE); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x42); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute CB. */ + post_code(0x42); /* Should never see this post code. */ } /**

1 0

New patch to review for coreboot: c81e2ed mainboard/supermicro/h8qme_fam10: Fix indentations and spelling
by Timothy Pearson 31 Mar '15

31 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9177 -gerrit commit c81e2ede094219e8b91a348c0b306551988f4922 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 31 11:54:03 2015 -0500 mainboard/supermicro/h8qme_fam10: Fix indentations and spelling Change-Id: I49c5d39a674351f7375fb762fc9ef4a3700d7c87 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/supermicro/h8qme_fam10/romstage.c | 181 ++++++++++++------------ 1 file changed, 91 insertions(+), 90 deletions(-) diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 7a75159..8583f2a 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -50,10 +50,11 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); } @@ -77,36 +78,36 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void sio_setup(void) { - uint32_t dword; - uint8_t byte; - enable_smbus(); + uint32_t dword; + uint8_t byte; + enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } static const u8 spd_addr[] = { - //first node + /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - //third node + /* third node */ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - //forth node + /* fourth node */ RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, #endif }; @@ -183,12 +184,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sio_setup(); } - post_code(0x30); + post_code(0x30); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - post_code(0x32); + post_code(0x32); w83627hf_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -200,113 +201,113 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); - update_microcode(val); + update_microcode(val); - post_code(0x33); + post_code(0x33); - cpuSetAMDMSR(); - post_code(0x34); + cpuSetAMDMSR(); + post_code(0x34); - amd_ht_init(sysinfo); - post_code(0x35); + amd_ht_init(sysinfo); + post_code(0x35); - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fixup prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); #endif - post_code(0x38); + post_code(0x38); #if CONFIG_SET_FIDVID - msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ + /* FIXME: The sb fid change may survive the warm reset and only + * need to be done once.*/ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - post_code(0x39); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } - post_code(0x3A); + post_code(0x3A); - /* show final fid and vid */ - msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); // Need to use TMICT to synchronize FID/VID - wants_reset = mcp55_early_setup_x(); + wants_reset = mcp55_early_setup_x(); - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset_x - shouldn't see this message!!!\n"); - } + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } - if (wants_reset) - printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); + if (wants_reset) + printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); - post_code(0x3B); + post_code(0x3B); -/* It's the time to set ctrl in sysinfo now; */ -printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); -fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); -post_code(0x3D); + post_code(0x3D); -//printk(BIOS_DEBUG, "enable_smbus()\n"); -// enable_smbus(); /* enable in sio_setup */ +// printk(BIOS_DEBUG, "enable_smbus()\n"); +// enable_smbus(); /* enable in sio_setup */ -post_code(0x40); + post_code(0x40); timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); - raminit_amdmct(sysinfo); + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); timestamp_add_now(TS_AFTER_INITRAM); - cbmem_initialize_empty(); - post_code(0x41); + cbmem_initialize_empty(); + post_code(0x41); - amdmct_cbmem_store_info(sysinfo); + amdmct_cbmem_store_info(sysinfo); timestamp_add_now(TS_END_ROMSTAGE); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x42); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute CB. */ + post_code(0x42); /* Should never see this post code. */ } /**

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coreboot-gerrit March 2015