Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9179
-gerrit
commit 252ce9b3af6e36e8be7d47ec11fa6b8b71384322
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Fri Aug 15 17:07:39 2014 -0700
Nyans: replace cpu_reset with hard_reset
The existing cpu_reset does board-wide reset, thus, should be renamed.
BUG=none
BRANCH=none
TEST=Built firmware for Nyans. Ran faft on Blaze.
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9
Original-Reviewed-on: https://chromium-review.googlesource.com/212982
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org>
(cherry picked from commit 29753b9c1dfe7ecd156042d69b74e9fe4244f455)
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Change-Id: I98eca40c50637bda01a9029a904bca6880cd081f
---
src/mainboard/google/nyan/Makefile.inc | 1 +
src/mainboard/google/nyan/pmic.c | 4 ++--
src/mainboard/google/nyan/reset.c | 5 ++---
src/mainboard/google/nyan/reset.h | 25 -------------------------
src/mainboard/google/nyan/romstage.c | 4 ++--
src/mainboard/google/nyan_big/Makefile.inc | 1 +
src/mainboard/google/nyan_big/pmic.c | 4 ++--
src/mainboard/google/nyan_big/reset.c | 5 ++---
src/mainboard/google/nyan_big/reset.h | 25 -------------------------
src/mainboard/google/nyan_big/romstage.c | 4 ++--
src/mainboard/google/nyan_blaze/Makefile.inc | 1 +
src/mainboard/google/nyan_blaze/pmic.c | 4 ++--
src/mainboard/google/nyan_blaze/reset.c | 5 ++---
src/mainboard/google/nyan_blaze/reset.h | 25 -------------------------
src/mainboard/google/nyan_blaze/romstage.c | 4 ++--
src/soc/nvidia/tegra124/Kconfig | 1 +
16 files changed, 22 insertions(+), 96 deletions(-)
diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
index de1e127..7ac11e8 100644
--- a/src/mainboard/google/nyan/Makefile.inc
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -38,6 +38,7 @@ romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += early_configs.c
+ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c
index 2a65719..b290871 100644
--- a/src/mainboard/google/nyan/pmic.c
+++ b/src/mainboard/google/nyan/pmic.c
@@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
-#include "reset.h"
+#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
- cpu_reset();
+ hard_reset();
} else {
if (do_delay)
udelay(500);
diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c
index 7f1fff9..05cca27 100644
--- a/src/mainboard/google/nyan/reset.c
+++ b/src/mainboard/google/nyan/reset.c
@@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
+#include <reset.h>
-#include "reset.h"
-
-void cpu_reset(void)
+void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);
diff --git a/src/mainboard/google/nyan/reset.h b/src/mainboard/google/nyan/reset.h
deleted file mode 100644
index debe838..0000000
--- a/src/mainboard/google/nyan/reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-
-void cpu_reset(void);
-
-#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index fffe0de..1ff500b 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <mainboard/google/nyan/reset.h>
+#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -79,7 +79,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
- cpu_reset();
+ hard_reset();
}
cbmem_initialize_empty();
diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc
index 1eb5404..8ca495c 100644
--- a/src/mainboard/google/nyan_big/Makefile.inc
+++ b/src/mainboard/google/nyan_big/Makefile.inc
@@ -37,6 +37,7 @@ romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += early_configs.c
+ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c
index ed855f1..c89db28 100644
--- a/src/mainboard/google/nyan_big/pmic.c
+++ b/src/mainboard/google/nyan_big/pmic.c
@@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
-#include "reset.h"
+#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
- cpu_reset();
+ hard_reset();
} else {
if (do_delay)
udelay(500);
diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c
index 7f1fff9..05cca27 100644
--- a/src/mainboard/google/nyan_big/reset.c
+++ b/src/mainboard/google/nyan_big/reset.c
@@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
+#include <reset.h>
-#include "reset.h"
-
-void cpu_reset(void)
+void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);
diff --git a/src/mainboard/google/nyan_big/reset.h b/src/mainboard/google/nyan_big/reset.h
deleted file mode 100644
index debe838..0000000
--- a/src/mainboard/google/nyan_big/reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-
-void cpu_reset(void);
-
-#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index fffe0de..1ff500b 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <mainboard/google/nyan/reset.h>
+#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -79,7 +79,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
- cpu_reset();
+ hard_reset();
}
cbmem_initialize_empty();
diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc
index 8cfa298..dc998d1 100644
--- a/src/mainboard/google/nyan_blaze/Makefile.inc
+++ b/src/mainboard/google/nyan_blaze/Makefile.inc
@@ -41,6 +41,7 @@ romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c
index ed855f1..c89db28 100644
--- a/src/mainboard/google/nyan_blaze/pmic.c
+++ b/src/mainboard/google/nyan_blaze/pmic.c
@@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
-#include "reset.h"
+#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
- cpu_reset();
+ hard_reset();
} else {
if (do_delay)
udelay(500);
diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c
index 7f1fff9..05cca27 100644
--- a/src/mainboard/google/nyan_blaze/reset.c
+++ b/src/mainboard/google/nyan_blaze/reset.c
@@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
+#include <reset.h>
-#include "reset.h"
-
-void cpu_reset(void)
+void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);
diff --git a/src/mainboard/google/nyan_blaze/reset.h b/src/mainboard/google/nyan_blaze/reset.h
deleted file mode 100644
index debe838..0000000
--- a/src/mainboard/google/nyan_blaze/reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
-
-void cpu_reset(void);
-
-#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index 65596a2..fca705d 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <mainboard/google/nyan/reset.h>
+#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -82,7 +82,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
- cpu_reset();
+ hard_reset();
}
cbmem_initialize_empty();
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 4fcc6b4..acc6e7e 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -6,6 +6,7 @@ config SOC_NVIDIA_TEGRA124
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_UART_SPECIAL
+ select HAVE_HARD_RESET
select BOOTBLOCK_CONSOLE
select ARM_BOOTBLOCK_CUSTOM
select ARM_LPAE
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9178
-gerrit
commit 7ddb8d129b939918d76be37061c3573012df47ca
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Thu Sep 18 13:47:33 2014 -0700
cbfs: more accurate size check for simple buffer mapping
currently, if the cache size is, for example, 4096 byte, mapping 4096 byte data
fails due to the overly strict check. this change allows cbfs_simple_buffer_map
to use all the cache space to the last byte.
BUG=None
TEST=Booted Nyan Blaze.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Change-Id: I0797b5010afd7316fdec605784e8f48e2d62c37f
Original-Reviewed-on: https://chromium-review.googlesource.com/218883
Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit b0b31da336fa2f87fe73f063782d6243f8262d10)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I15e11e574cd14484fe83c9c3674bb5c2d14422f6
---
src/lib/cbfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 90ddc31..ebcc134 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -144,7 +144,7 @@ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer,
"allocated=%zd, size=%zd, last_allocate=%zd\n",
offset, count, buffer->allocated, buffer->size,
buffer->last_allocate);
- if (buffer->allocated + count >= buffer->size)
+ if (buffer->allocated + count > buffer->size)
return CBFS_MEDIA_INVALID_MAP_ADDRESS;
if (media->read(media, address, offset, count) != count) {
ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n",
the following patch was just integrated into master:
commit bf5407cd4985119cd682ded72e9e634496d48201
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Aug 29 15:32:55 2014 -0700
chromeec: Clear post code before reboot to RO
When doing an EC requested reboot to RO mode clear the
saved post code in order to prevent confusing events in
the log where the system is rebooted intentionally.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus, run FAFT, check for odd
eventlog entries about last post code 0x31 when it is
rebooted during samus romstage entry point.
Original-Change-Id: I8bedc611712424bf1044cdca1972e34ffdd51abd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215681
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit e32d7a7e54e7006b84509dbc2bfe9b4b022eba71)
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Change-Id: Iad816669fb4054260f995f6f0bfb140121aaddff
Reviewed-on: http://review.coreboot.org/9176
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)google.com>
See http://review.coreboot.org/9176 for details.
-gerrit
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8986
-gerrit
commit f8545ad4a875da820ccba8d6ff7c7459e42557d8
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Mar 24 11:33:03 2015 -0500
baytrail: select PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
This platform supports PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
in that CAR region can be migrated and the data can be maintained
across the CAR tear down boundary.
Change-Id: I232613ebb641eb9d8fc61af4ba8d2e9b66ec5e51
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 214a1ac..fbd2b01 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
+ select PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE
select PARALLEL_MP
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8984
-gerrit
commit 83b90c961b6dbeba49e9a7b9fabe0a81ec44dbed
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Mar 25 10:44:53 2015 -0500
broadwell: select PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
This platform supports PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
in that CAR region can be migrated and the data can be maintained
across the CAR tear down boundary.
Change-Id: Iff3372fabc684bf8742e8f7fbfde9fbc105a7aa7
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index c147663..c81fa6e 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS
select IOAPIC
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
+ select PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE
select REG_SCRIPT
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8985
-gerrit
commit bc57305c86a2b818b366843fefddf5b643539768
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Mar 25 10:45:20 2015 -0500
haswell: select PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
This platform supports PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
in that CAR region can be migrated and the data can be maintained
across the CAR tear down boundary.
Change-Id: If131e26b719828647b9fe66f30fc0c87dbcb185f
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/cpu/intel/haswell/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 741b677..7352c63 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_CONSTANT_RATE
select SMM_TSEG
select SMM_MODULES
+ select PLATFORM_HAS_EARLY_WRITABLE_GLOBALS
select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE
select SUPPORT_CPU_UCODE_IN_CBFS