coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 1167064 arch/x86/boot/smbios: Add additional SMBIOS defines and enums
by Timothy Pearson 28 Mar '15

28 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9135 -gerrit commit 1167064cf1fd71d0a0b35aecc14ce9dcdeb6d31a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:47:25 2015 -0500 arch/x86/boot/smbios: Add additional SMBIOS defines and enums Change-Id: I337584d1f4ce32094c24478a99418e0775cf9ab5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/boot/smbios.c | 17 +++++++- src/include/smbios.h | 101 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 16e2531..9931ff3 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> * * This program is free software; you can redistribute it and/or @@ -125,6 +126,10 @@ static int smbios_processor_name(char *start) static void fill_dimm_manufacturer(uint16_t mod_id, struct smbios_type17 *t) { switch (mod_id) { + case 0x987f: + t->manufacturer = smbios_add_string(t->eos, + "Hynix"); + break; case 0xad80: t->manufacturer = smbios_add_string(t->eos, "Hynix/Hyundai"); @@ -137,10 +142,18 @@ static void fill_dimm_manufacturer(uint16_t mod_id, struct smbios_type17 *t) t->manufacturer = smbios_add_string(t->eos, "Elpida"); break; - default: + case 0xff2c: t->manufacturer = smbios_add_string(t->eos, - "Unknown"); + "Micron"); break; + default: { + char string_buffer[256]; + snprintf(string_buffer, sizeof(string_buffer), + "Unknown (%x)", mod_id); + t->manufacturer = smbios_add_string(t->eos, + string_buffer); + break; + } } } diff --git a/src/include/smbios.h b/src/include/smbios.h index bd7bef5..da38419 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) various authors, the coreboot project + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef SMBIOS_H #define SMBIOS_H @@ -34,6 +54,25 @@ u8 smbios_mainboard_enclosure_type(void); #define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) #define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) +#define BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING (1 << 3) +#define BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING (1 << 4) +#define BIOS_MEMORY_ECC_SCRUBBING (1 << 5) + +#define MEMORY_TYPE_DETAIL_OTHER (1 << 1) +#define MEMORY_TYPE_DETAIL_UNKNOWN (1 << 2) +#define MEMORY_TYPE_DETAIL_FAST_PAGED (1 << 3) +#define MEMORY_TYPE_DETAIL_STATIC_COLUMN (1 << 4) +#define MEMORY_TYPE_DETAIL_PSEUDO_STATIC (1 << 5) +#define MEMORY_TYPE_DETAIL_RAMBUS (1 << 6) +#define MEMORY_TYPE_DETAIL_SYNCHRONOUS (1 << 7) +#define MEMORY_TYPE_DETAIL_CMOS (1 << 8) +#define MEMORY_TYPE_DETAIL_EDO (1 << 9) +#define MEMORY_TYPE_DETAIL_WINDOW_DRAM (1 << 10) +#define MEMORY_TYPE_DETAIL_CACHE_DRAM (1 << 11) +#define MEMORY_TYPE_DETAIL_NON_VOLATILE (1 << 12) +#define MEMORY_TYPE_DETAIL_REGISTERED (1 << 13) +#define MEMORY_TYPE_DETAIL_UNBUFFERED (1 << 14) + typedef enum { MEMORY_FORMFACTOR_OTHER = 0x01, MEMORY_FORMFACTOR_UNKNOWN = 0x02, @@ -52,6 +91,68 @@ typedef enum { MEMORY_FORMFACTOR_FBDIMM = 0x0f, } smbios_memory_form_factor; +typedef enum { + MEMORY_TYPE_OTHER = 0x01, + MEMORY_TYPE_UNKNOWN = 0x02, + MEMORY_TYPE_DRAM = 0x03, + MEMORY_TYPE_EDRAM = 0x04, + MEMORY_TYPE_VRAM = 0x05, + MEMORY_TYPE_SRAM = 0x06, + MEMORY_TYPE_RAM = 0x07, + MEMORY_TYPE_ROM = 0x08, + MEMORY_TYPE_FLASH = 0x09, + MEMORY_TYPE_EEPROM = 0x0a, + MEMORY_TYPE_FEPROM = 0x0b, + MEMORY_TYPE_EPROM = 0x0c, + MEMORY_TYPE_CDRAM = 0x0d, + MEMORY_TYPE_3DRAM = 0x0e, + MEMORY_TYPE_SDRAM = 0x0f, + MEMORY_TYPE_SGRAM = 0x10, + MEMORY_TYPE_RDRAM = 0x11, + MEMORY_TYPE_DDR = 0x12, + MEMORY_TYPE_DDR2 = 0x13, + MEMORY_TYPE_DDR2_FBDIMM = 0x14, + MEMORY_TYPE_DDR3 = 0x18, + MEMORY_TYPE_FBD2 = 0x19, +} smbios_memory_type; + +typedef enum { + MEMORY_ARRAY_LOCATION_OTHER = 0x01, + MEMORY_ARRAY_LOCATION_UNKNOWN = 0x02, + MEMORY_ARRAY_LOCATION_SYSTEM_BOARD = 0x03, + MEMORY_ARRAY_LOCATION_ISA_ADD_ON = 0x04, + MEMORY_ARRAY_LOCATION_EISA_ADD_ON = 0x05, + MEMORY_ARRAY_LOCATION_PCI_ADD_ON = 0x06, + MEMORY_ARRAY_LOCATION_MCA_ADD_ON = 0x07, + MEMORY_ARRAY_LOCATION_PCMCIA_ADD_ON = 0x08, + MEMORY_ARRAY_LOCATION_PROPRIETARY_ADD_ON = 0x09, + MEMORY_ARRAY_LOCATION_NUBUS = 0x0a, + MEMORY_ARRAY_LOCATION_PC_98_C20_ADD_ON = 0xa0, + MEMORY_ARRAY_LOCATION_PC_98_C24_ADD_ON = 0xa1, + MEMORY_ARRAY_LOCATION_PC_98_E_ADD_ON = 0xa2, + MEMORY_ARRAY_LOCATION_PC_98_LOCAL_BUS_ADD_ON = 0xa3, +} smbios_memory_array_location; + +typedef enum { + MEMORY_ARRAY_USE_OTHER = 0x01, + MEMORY_ARRAY_USE_UNKNOWN = 0x02, + MEMORY_ARRAY_USE_SYSTEM = 0x03, + MEMORY_ARRAY_USE_VIDEO = 0x04, + MEMORY_ARRAY_USE_FLASH = 0x05, + MEMORY_ARRAY_USE_NVRAM = 0x06, + MEMORY_ARRAY_USE_CACHE = 0x07, +} smbios_memory_array_use; + +typedef enum { + MEMORY_ARRAY_ECC_OTHER = 0x01, + MEMORY_ARRAY_ECC_UNKNOWN = 0x02, + MEMORY_ARRAY_ECC_NONE = 0x03, + MEMORY_ARRAY_ECC_PARITY = 0x04, + MEMORY_ARRAY_ECC_SINGLE_BIT = 0x05, + MEMORY_ARRAY_ECC_MULTI_BIT = 0x06, + MEMORY_ARRAY_ECC_CRC = 0x07, +} smbios_memory_array_ecc; + #define SMBIOS_STATE_SAFE 3 typedef enum { SMBIOS_BIOS_INFORMATION=0,

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Patch merged into coreboot/master: b7cf115 storm: need larger CBFS cache
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit b7cf11573d51d277809649f748b796f103fa98dc Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 23 14:15:29 2014 -0700 storm: need larger CBFS cache With VPD blob of certain format, CBFS cache on storm proves to be not large enough. This patch makes it bigger, it is still well above the area preserved for the NSS. BUG=chrome-os-partner:32152 TEST=the system now boots with the VPD it used to fail booting. Change-Id: Iee1214b218ee3f8aca28797841501c227549affb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6f19ca8cb9a2efa1d295f038730ed06ec9ceb8c4 Original-Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219572 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9122 for details. -gerrit

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Patch merged into coreboot/master: f32ef13 storm: fix SW_RESET signal polarity
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit f32ef133dd0a905ebffb994da2797cf9bf6633f2 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 9 20:41:33 2014 -0700 storm: fix SW_RESET signal polarity The actual level required to take the ethernet switch out of reset is low, not high. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: If4004ac5c2dc837270d4cb840d96ce92021d231e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9fa69d22de901cd0843948de0f95a66a2aa99353 Original-Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217416 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/9121 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9121 for details. -gerrit

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Patch merged into coreboot/master: c7bbc04 storm: deassert SW_RESET signal at startup
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit c7bbc04544f60d5be44ea4c61899169406066a33 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 8 14:34:09 2014 -0700 storm: deassert SW_RESET signal at startup The proto0.2 hardware connects gpio26 (sw reset) to the ethernet switch reset pit. The output stays low (or high-z) after power up, which holds the switch in reset. Deassert the signal at startup on hardware rev 1 and later. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: I4c5a0cc499563a33aa7d29be7767d0ec5d93c20f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6788962172c6e29e193fa3e85ca79cb83a96e154 Original-Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217087 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/9120 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9120 for details. -gerrit

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Patch merged into coreboot/master: 2786ce0 storm: make sure board ID is calculated only once
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 2786ce0b485f39dd5c9fa0fc037fe214adb771e5 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 8 14:04:08 2014 -0700 storm: make sure board ID is calculated only once Figuring out board_id on storm requires reading tertiary gpios, which takes time. Let's calculate it once and reuse it when necessary. BUG=none TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2 respectively. Change-Id: I69f6afa3de8a175a1d723e95902efd15607e68b7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 080c839c1c0c1b5e389b2382144ef67535bb4ff1 Original-Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217086 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/9119 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9119 for details. -gerrit

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Patch merged into coreboot/master: 1de971d storm: reset TPM properly on proto0
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 1de971dd3202a02492e5738b40595afaa8aca153 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Aug 7 15:20:21 2014 -0700 storm: reset TPM properly on proto0 The proto0 storm hardware has the TPM reset line wired to the SOC GPIO22 pin instead of the system reset. This causes all kind of TPM behavior problems and requires frequent power cycles. Adding explicit TPM reset makes all those problems go away. BUG=chrome-os-partner:30705, chrome-os-partner:30829 TEST=tried resetting proto0 at different moments during boot up - the TPM does not fail anymore. Change-Id: Idfa16e6e868336f38861edeb75703fff3f35172c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d5e07815c227089b7f266ba5329812bf309b87e6 Original-Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211497 Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/9118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9118 for details. -gerrit

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Patch merged into coreboot/master: c6d3040 storm: supply vboot GPIO settings in coreboot table
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit c6d30405f2c3beb47690745eeae4684e18d4be05 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Aug 1 17:36:45 2014 -0700 storm: supply vboot GPIO settings in coreboot table Storm provides three real and two fake gpios. To keep things simple, define them all as active low and provide appropriate values for the fake ones. BUG=chrome-os-partner:30705 TEST=with the appropriate depthcharge change booted proto0, observed appropriate behavior following the dev switch setting Change-Id: I248b90ee06d226a223b6fc0993f209acdd58c77d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d48d1dcc88df0c1bd4c50f14dd2e7cd1dd4fba5d Original-Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210922 Reviewed-on: http://review.coreboot.org/9117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9117 for details. -gerrit

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Patch merged into coreboot/master: d9becd2 blaze: update EMC BCT table
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit d9becd2183da9f4174e2dc2d686ad5a66c4e4e22 Author: Neil Chen <neilc(a)nvidia.com> Date: Mon Jul 28 18:00:29 2014 +0800 blaze: update EMC BCT table This change updated the EMC tables with emc_reg_tool 5.0.18, for below memory SKUs: - Hynix H5TC4G63AFR-PBR 2GB, ramcode = 0 - Micron MT41K256M16HA-125 2GB, ramcode = 1 - Samsung K4B4G1646Q-HYK0 2GB, ramcode = 2 - Hynix H5TC8G63AFR-PBR 4GB, ramcode = 8 - Micron MT41K512M16TNA-125 4GB, ramcode = 9 - Samsung K4B8G1646Q-MYKO 4GB, ramcode = 10 BUG=chrome-os-partner:30963 BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Change-Id: Iee329ff09e35cddd3c868c0460a38ef56b2ac5bb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 158872ff7c0dd5274cfa8d63ec17b4423a4592ce Original-Change-Id: I44adfdb5b433e37e2d25095acdcce3d9c14eb897 Original-Signed-off-by: Neil Chen <neilc(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210024 Original-Tested-by: Ken Chang <kenc(a)nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Reviewed-on: http://review.coreboot.org/9116 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9116 for details. -gerrit

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Patch merged into coreboot/master: 4d9dc8c tegra132: Add support for pmc_rst_status get and print
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 4d9dc8cf50445e9e3e637edbe89daf6602dec62f Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Sep 30 20:34:18 2014 -0700 tegra132: Add support for pmc_rst_status get and print BUG=None BRANCH=None TEST=Compiles successfully and pmc rst status POR is seen. Change-Id: Ic09cb46d9be7670e467543e42b251efb1a4313d0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5dbfae6bbc0f4f30e216e37b515f4120f7833a38 Original-Change-Id: Id0c2b208222deaf099b8938ba583551979588d52 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220721 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9106 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9106 for details. -gerrit

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Patch merged into coreboot/master: c2115e3 tegra132: Replace use of clk_rst with CLK_RST_REG
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit c2115e3f383a0c5046f49497e1c48791b21d17d1 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Sep 30 19:49:01 2014 -0700 tegra132: Replace use of clk_rst with CLK_RST_REG Also, get rid of unused clk_rst variables. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I6487162454159a81b31fe0d6d39c2bdbed3f859a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 030081fe85fc9609fdf2003cf51b7350e08f0429 Original-Change-Id: I880ae5c396c33006f6b184cca7f171e4373f4016 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220720 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9105 for details. -gerrit

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coreboot-gerrit March 2015