coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 91b30ca broadwell: fix HAVE_REFCODE_BLOB build errors
by Aaron Durbin 28 Mar '15

28 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9142 -gerrit commit 91b30ca76aae81e52febd09c7a563a3d2f794305 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 27 21:01:52 2015 -0500 broadwell: fix HAVE_REFCODE_BLOB build errors When building HAVE_REFCODE_BLOB there are a couple of errors. One is a failure building !CHROME_OS. The other is from a header change where console_tx_byte() was declared. Change-Id: I4110debd6d3818d4a803ed22037166c226f2ed11 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/broadwell/refcode.c | 50 ++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index d66d036..1328f1a 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -21,11 +21,14 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> +#include <console/streams.h> #include <cpu/x86/tsc.h> #include <rmodule.h> #include <ramstage_cache.h> #include <string.h> +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/vboot_handoff.h> +#endif #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h> @@ -93,10 +96,24 @@ static void cache_refcode(const struct rmod_stage_load *rsl) memcpy(&c->program[0], (void *)c->load_address, c->size); } -static int load_refcode_from_vboot(struct rmod_stage_load *refcode, - struct cbfs_stage *stage) +#if IS_ENABLED(CONFIG_CHROMEOS) +static int load_refcode_from_vboot(struct rmod_stage_load *refcode) { + struct vboot_handoff *vboot_handoff; + const struct firmware_component *fwc; + struct cbfs_stage *stage; + + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + fwc = &vboot_handoff->components[CONFIG_VBOOT_REFCODE_INDEX]; + + if (vboot_handoff == NULL || + vboot_handoff->selected_firmware == VB_SELECT_FIRMWARE_READONLY || + CONFIG_VBOOT_REFCODE_INDEX >= MAX_PARSED_FW_COMPONENTS || + fwc->size == 0 || fwc->address == 0) + return -1; + printk(BIOS_DEBUG, "refcode loading from vboot rw area.\n"); + stage = (void *)(uintptr_t)fwc->address; if (rmodule_stage_load(refcode, stage) || refcode->entry == NULL) { printk(BIOS_DEBUG, "Error loading reference code.\n"); @@ -104,6 +121,12 @@ static int load_refcode_from_vboot(struct rmod_stage_load *refcode, } return 0; } +#else +static int load_refcode_from_vboot(struct rmod_stage_load *refcode) +{ + return -1; +} +#endif static int load_refcode_from_cbfs(struct rmod_stage_load *refcode) { @@ -119,35 +142,18 @@ static int load_refcode_from_cbfs(struct rmod_stage_load *refcode) static pei_wrapper_entry_t load_reference_code(void) { - struct vboot_handoff *vboot_handoff; - const struct firmware_component *fwc; struct rmod_stage_load refcode = { .cbmem_id = CBMEM_ID_REFCODE, .name = CONFIG_CBFS_PREFIX "/refcode", }; - int ret; if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); } - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - fwc = &vboot_handoff->components[CONFIG_VBOOT_REFCODE_INDEX]; - - if (vboot_handoff == NULL || - vboot_handoff->selected_firmware == VB_SELECT_FIRMWARE_READONLY || - CONFIG_VBOOT_REFCODE_INDEX >= MAX_PARSED_FW_COMPONENTS || - fwc->size == 0 || fwc->address == 0) { - ret = load_refcode_from_cbfs(&refcode); - } else { - ret = load_refcode_from_vboot(&refcode, (void *)fwc->address); - - if (ret < 0) - ret = load_refcode_from_cbfs(&refcode); - } - - if (ret < 0) - return NULL; + if (load_refcode_from_vboot(&refcode) || + load_refcode_from_cbfs(&refcode)) + return NULL; /* Cache loaded reference code. */ cache_refcode(&refcode);

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Patch set updated for coreboot: e9ee9f0 coreboot: differentiate on early reliable writable globals
by Aaron Durbin 28 Mar '15

28 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8943 -gerrit commit e9ee9f0f0180222dbe0c0fdc9d73469b9b4f7bb1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 24 09:20:45 2015 -0500 coreboot: differentiate on early reliable writable globals There is a big difference between the boards supported in coreboot and the properties they provide within each stage during the bootflow. The leads to core infrastructure relying on supporting the least common denominator when writing APIs. Therefore, provide PLATFORM_HAS_EARLY_WRITABLE_GLOBALS which indicates that the platform has reliable writable global variables in the early stages of boot. For x86 that would be romstage, and for the other architetures which have SRAM it would encompass bootblock and romstage. Change-Id: I2cefeaee0551ee241e138fcee0d199679002c3be Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 7aee478..2625266 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -293,6 +293,25 @@ config SYSTEM_TYPE_LAPTOP default n bool +config PLATFORM_HAS_EARLY_WRITABLE_GLOBALS + bool + default y if !ARCH_X86 + help + This option signals to the rest of the infrastructure that + the platform supports writable globals in bootblock and + romstage. Fox traditional x86 systems without any SRAM this + would mean cache-as-ram globals are migrated correctly from + the CAR area once memory is trained. After the migration the + variables are accessible using the CAR API. This behavior + puts such x86 systems on par with ARM and MIPS systems. + +config PLATFORM_NO_EARLY_WRITABLE_GLOBALS + bool + default y if !PLATFORM_HAS_EARLY_WRITABLE_GLOBALS + help + This is just the opposite of PLATFORM_HAS_EARLY_WRITABLE_GLOBALS + to enable cleaner Makefiles. + menu "Chipset" comment "CPU"

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New patch to review for coreboot: f1c3d92 mips: add verstage configuration
by Patrick Georgi 28 Mar '15

28 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9147 -gerrit commit f1c3d923f75f6b35ef5c40ea7a79bd031f5949f6 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Mar 28 16:01:14 2015 +0100 mips: add verstage configuration Change-Id: I79b4969c34500fd51b1ce2ad751bc0723ee0afa2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/arch/mips/Kconfig | 4 ++++ src/cpu/mips/Kconfig | 1 + 2 files changed, 5 insertions(+) diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index 5ee23d3..5c0fc5c 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -24,6 +24,10 @@ config ARCH_BOOTBLOCK_MIPS default n select ARCH_MIPS +config ARCH_VERSTAGE_MIPS + bool + default n + config ARCH_ROMSTAGE_MIPS bool default n diff --git a/src/cpu/mips/Kconfig b/src/cpu/mips/Kconfig index 4507977..093a1f0 100644 --- a/src/cpu/mips/Kconfig +++ b/src/cpu/mips/Kconfig @@ -22,6 +22,7 @@ config CPU_MIPS bool select ARCH_BOOTBLOCK_MIPS + select ARCH_VERSTAGE_MIPS select ARCH_ROMSTAGE_MIPS select ARCH_RAMSTAGE_MIPS

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Patch set updated for coreboot: 0dd1bb9 build system: mips is a valid nickname for mipsel
by Patrick Georgi 28 Mar '15

28 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9146 -gerrit commit 0dd1bb911b467d57cb83c4aac6f013a1a5189659 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Mar 28 15:49:46 2015 +0100 build system: mips is a valid nickname for mipsel Change-Id: I5829a96cbb0af0398113efbdf34dfa3d102bf4c8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/xcompile/xcompile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index fc221b1..5809ec0 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -209,10 +209,11 @@ arch_config_x86() { } arch_config_mipsel() { - TARCH="mipsel" + TARCH="mips" TBFDARCHS="tradlittlemips littlemips" TCLIST="mipsel" TWIDTH="32" + TSUPP="mips mipsel" TABI="elf" }

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New patch to review for coreboot: 9a9ca63 build system: mips is a valid nickname for mipsel
by Patrick Georgi 28 Mar '15

28 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9146 -gerrit commit 9a9ca63c0c082870b2a11604c81dfc534e65a986 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Mar 28 15:49:46 2015 +0100 build system: mips is a valid nickname for mipsel Change-Id: I5829a96cbb0af0398113efbdf34dfa3d102bf4c8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/xcompile/xcompile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index fc221b1..288f6f9 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -213,6 +213,7 @@ arch_config_mipsel() { TBFDARCHS="tradlittlemips littlemips" TCLIST="mipsel" TWIDTH="32" + TSUPP="mips" TABI="elf" }

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New patch to review for coreboot: a453f81 crossgcc: Fix calling outside util/crossgcc
by Patrick Georgi 28 Mar '15

28 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9145 -gerrit commit a453f81d3e2207643215cff5aa5216de37a725be Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 28 15:48:47 2015 +0100 crossgcc: Fix calling outside util/crossgcc Copy $0 contains the path, and we cd into that early. Change-Id: If4124d16dea97b5eee4996bdfa3eae3d5d94c5d1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/crossgcc/buildgcc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fde8bc6..8bcaf2f 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -614,8 +614,9 @@ printf "Building IASL ${IASL_VERSION} ... " ) 2>&1 | wait_for_build "$IASL_DIR/source/compiler" || exit 1 fi -rm -f $DESTDIR$TARGETDIR/$0.commit.* -cp $0 $DESTDIR$TARGETDIR/"$0.commit.`git describe`" +PROGNAME=`basename "$0"` +rm -f "$DESTDIR$TARGETDIR/$PROGNAME".commit.* +cp "$PROGNAME" $DESTDIR$TARGETDIR/"$PROGNAME.commit.`git describe`" if [ $SAVETEMPS -eq 0 ]; then printf "Cleaning up... "

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New patch to review for coreboot: 6f83482 crossgcc: Build mipsel-elf, not mips-elf
by Patrick Georgi 28 Mar '15

28 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9144 -gerrit commit 6f8348213a2b2db8986dda80472a55adf28459f2 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Mar 28 15:24:06 2015 +0100 crossgcc: Build mipsel-elf, not mips-elf The build system expects mipsel, and it's the more precise name, too. Change-Id: I9e1135385b3f1374b3179ecf5e11a1d60bc17ef7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/crossgcc/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 2f18b17..d0ab28a 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -13,7 +13,7 @@ build-aarch64: bash ./buildgcc -G -p aarch64-elf build-mips: - bash ./buildgcc -G -p mips-elf + bash ./buildgcc -G -p mipsel-elf build-riscv: bash ./buildgcc -G -p riscv-elf @@ -36,7 +36,7 @@ build-aarch64-without-gdb: .PHONY: build-mips-without-gdb build-mips-without-gdb: - bash ./buildgcc -p mips-elf + bash ./buildgcc -p mipsel-elf .PHONY: build-riscv-without-gdb build-riscv-without-gdb:

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Patch set updated for coreboot: 46142fe northbridge/amd/amdfam10: Collect DIMM information for ramstage use
by Timothy Pearson 28 Mar '15

28 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9137 -gerrit commit 46142fe082e164d3f988e76080b3c215a60afa1f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:50:09 2015 -0500 northbridge/amd/amdfam10: Collect DIMM information for ramstage use Allow MCT information structures to be copied to cbmem Retrieve DIMM vendor, model, and serial information Allow maximum installable memory to be set via devicetree Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10.h | 1 + src/northbridge/amd/amdfam10/amdfam10_util.c | 1 + src/northbridge/amd/amdfam10/chip.h | 29 +++++++++++++++++++++++++ src/northbridge/amd/amdfam10/raminit_amdmct.c | 27 +++++++++++++++++++++++ src/northbridge/amd/amdmct/mct/mct_d.c | 28 ++++++++++++++++++++++-- src/northbridge/amd/amdmct/mct/mct_d.h | 31 +++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 29 +++++++++++++++++++++++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 31 +++++++++++++++++++++++++++ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +- 9 files changed, 174 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index a77d036..238c45f 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -977,6 +977,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "raminit.h" +#include "../amdmct/wrappers/mcti.h" #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ #include "../amdmct/mct_ddr3/mct_d.h" #else diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 2726b28..9788e54 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <arch/cpu.h> +#include "northbridge/amd/amdmct/wrappers/mcti.h" #include <northbridge/amd/amdmct/mct/mct_d.h> #include <northbridge/amd/amdmct/amddefs.h> diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h new file mode 100644 index 0000000..ab853d6 --- /dev/null +++ b/src/northbridge/amd/amdfam10/chip.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_FAM10_CHIP_H_ +#define _AMD_FAM10_CHIP_H_ + +#include <stdint.h> + +struct northbridge_amd_amdfam10_config { + uint64_t maximum_memory_capacity; +}; + +#endif /* _AMD_FAM10_CHIP_H_ */ \ No newline at end of file diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 02dc956..d1d87ff 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -204,3 +204,30 @@ static void raminit_amdmct(struct sys_info *sysinfo) printk(BIOS_DEBUG, "raminit_amdmct end:\n"); } + +#if 0 +static void amdmct_cbmem_store_info(struct sys_info *sysinfo) +{ + /* Save memory info structures for use in ramstage */ + size_t i; + struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); + struct DCTStatStruc *pDCTstatA = 0; + + if (pMCTstat && sysinfo->DCTstatA) { + /* Initialize memory */ + struct amdmct_memory_info* mem_info; + mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); + memset(mem_info, 0, sizeof(struct amdmct_memory_info)); + + /* Copy data */ + memcpy(&mem_info->mct_stat, &(sysinfo->MCTstat), sizeof(struct MCTStatStruc)); + for (i = 0; i < MAX_NODES_SUPPORTED; i++) { + pDCTstatA = sysinfo->DCTstatA + i; + if (pDCTstatA) + memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc)); + } + mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP); + mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); + } +} +#endif diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index bf832da..64cb1bc 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -2122,7 +2122,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, * DATABload=number of ranks on the "B" bus slots. */ - u16 i, j; + u16 i, j, k; u8 smbaddr, Index; u16 Checksum; u8 SPDCtrl; @@ -2183,10 +2183,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid |= 1 << i; } } + /* Get module information for SMBIOS */ + if (pDCTstat->DIMMValid & (1 << i)) { + pDCTstat->DimmManufacturerID[i] = 0; + for (k = 0; k < 8; k++) + pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); + for (k = 0; k < SPD_PARTN_LENGTH; k++) + pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); + pDCTstat->DimmRevisionNumber[i] = 0; + for (k = 0; k < 2; k++) + pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); + pDCTstat->DimmSerialNumber[i] = 0; + for (k = 0; k < 4; k++) + pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); + pDCTstat->DimmRows[i] = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0xf; + pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_COLSZ) & 0xf; + pDCTstat->DimmRanks[i] = (mctRead_SPD(smbaddr, SPD_DMBANKS) & 0x7) + 1; + pDCTstat->DimmBanks[i] = mctRead_SPD(smbaddr, SPD_LBANKS); + pDCTstat->DimmWidth[i] = mctRead_SPD(smbaddr, SPD_DEVWIDTH); + } /* Check module type */ byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE); - if (byte & JED_REGADCMSK) + if (byte & JED_REGADCMSK) { RegDIMMPresent |= 1 << i; + pDCTstat->DimmRegistered[i] = 1; + } + else { + pDCTstat->DimmRegistered[i] = 0; + } /* Check ECC capable */ byte = mctRead_SPD(smbaddr, SPD_EDCTYPE); if (byte & JED_ECC) { diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 0a1f925..a200873 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -231,10 +232,17 @@ #define SPD_TRC 41 #define SPD_TRFC 42 +#define SPD_MANID_START 64 +#define SPD_PARTN_START 73 +#define SPD_PARTN_LENGTH 18 +#define SPD_REVNO_START 91 + #define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ +#define SPD_SERIAL_START 95 + /*----------------------------- Jedec DDR II related equates -----------------------------*/ @@ -512,6 +520,18 @@ struct DCTStatStruc { /* A per Node structure*/ u32 dev_map; u32 dev_dct; u32 dev_nbmisc; + + uint8_t DimmRows[8]; + uint8_t DimmCols[8]; + uint8_t DimmRanks[8]; + uint8_t DimmBanks[8]; + uint8_t DimmWidth[8]; + uint8_t DimmRegistered[8]; + + uint64_t DimmManufacturerID[8]; + char DimmPartNumber[8][SPD_PARTN_LENGTH]; + uint16_t DimmRevisionNumber[8]; + uint32_t DimmSerialNumber[8]; }; /*=============================================================================== @@ -666,6 +686,17 @@ struct DCTStatStruc { /* A per Node structure*/ xx0b = disable yy1b = enable with DctSelIntLvAddr set to yyb */ +/*=============================================================================== + CBMEM storage +===============================================================================*/ +struct amdmct_memory_info { + struct MCTStatStruc mct_stat; + struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; + uint16_t ecc_enabled; + uint16_t ecc_scrub_rate; +}; + +#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 770b663..0f4dd43 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -2030,7 +2031,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, * DATAAload=number of ranks on the "A" bus slots. * DATABload=number of ranks on the "B" bus slots. */ - u16 i, j; + u16 i, j, k; u8 smbaddr; u8 SPDCtrl; u16 RegDIMMPresent, MaxDimms; @@ -2077,10 +2078,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid |= 1 << i; } } + /* Get module information for SMBIOS */ + if (pDCTstat->DIMMValid & (1 << i)) { + pDCTstat->DimmManufacturerID[i] = 0; + for (k = 0; k < 8; k++) + pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); + for (k = 0; k < SPD_PARTN_LENGTH; k++) + pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); + pDCTstat->DimmRevisionNumber[i] = 0; + for (k = 0; k < 2; k++) + pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); + pDCTstat->DimmSerialNumber[i] = 0; + for (k = 0; k < 4; k++) + pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); + pDCTstat->DimmRows[i] = (mctRead_SPD(smbaddr, SPD_Addressing) & 0x38) >> 3; + pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_Addressing) & 0x7; + pDCTstat->DimmRanks[i] = ((mctRead_SPD(smbaddr, SPD_Organization) & 0x38) >> 3) + 1; + pDCTstat->DimmBanks[i] = 1ULL << (((mctRead_SPD(smbaddr, SPD_Density) & 0x70) >> 4) + 3); + pDCTstat->DimmWidth[i] = 1ULL << ((mctRead_SPD(smbaddr, SPD_BusWidth) & 0x7) + 3); + } /* Check module type */ byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE) & 0x7; - if (byte == JED_RDIMM || byte == JED_MiniRDIMM) + if (byte == JED_RDIMM || byte == JED_MiniRDIMM) { RegDIMMPresent |= 1 << i; + pDCTstat->DimmRegistered[i] = 1; + } + else { + pDCTstat->DimmRegistered[i] = 0; + } /* Check ECC capable */ byte = mctRead_SPD(smbaddr, SPD_BusWidth); if (byte & JED_ECC) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 42cca26..5e7f8a1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -262,6 +263,12 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ +#define SPD_MANID_START 117 +#define SPD_SERIAL_START 122 +#define SPD_PARTN_START 128 +#define SPD_PARTN_LENGTH 18 +#define SPD_REVNO_START 146 + /*----------------------------- Jedec DDR II related equates -----------------------------*/ @@ -575,6 +582,18 @@ struct DCTStatStruc { /* A per Node structure*/ struct _sMCTStruct s_C_MCTPtr; struct _sDCTStruct s_C_DCTPtr[2]; /* struct _sDCTStruct s_C_DCT1Ptr[8]; */ + + uint8_t DimmRows[8]; + uint8_t DimmCols[8]; + uint8_t DimmRanks[8]; + uint8_t DimmBanks[8]; + uint8_t DimmWidth[8]; + uint8_t DimmRegistered[8]; + + uint64_t DimmManufacturerID[8]; + char DimmPartNumber[8][SPD_PARTN_LENGTH]; + uint16_t DimmRevisionNumber[8]; + uint32_t DimmSerialNumber[8]; }; /*=============================================================================== @@ -727,6 +746,18 @@ struct DCTStatStruc { /* A per Node structure*/ xx0b = disable yy1b = enable with DctSelIntLvAddr set to yyb */ +/*=============================================================================== + CBMEM storage +===============================================================================*/ +struct amdmct_memory_info { + struct MCTStatStruc mct_stat; + struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; + uint16_t ecc_enabled; + uint16_t ecc_scrub_rate; +}; + +#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E + u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index b2cfad6..39acccf 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -570,4 +570,4 @@ static u8 mctSetNodeBoundary_D(void) { return 0; } -#endif +#endif \ No newline at end of file

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Patch set updated for coreboot: 249805a mainboard/asus/kfsn4-dre: Set maximum installable memory
by Timothy Pearson 28 Mar '15

28 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9139 -gerrit commit 249805a9f4938c4204bcdd5178e63128de64a92c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:48:51 2015 -0500 mainboard/asus/kfsn4-dre: Set maximum installable memory Change-Id: I480d6bfe29c77119892fcb1fbb9779fd7e3529c3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb index 928790b..50e2862 100644 --- a/src/mainboard/asus/kfsn4-dre/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -7,6 +7,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device domain 0 on # PCI domain subsystemid 0x1043 0x8162 inherit chip northbridge/amd/amdfam10 # Northbridge / RAM controller + register "maximum_memory_capacity" = "0x1000000000" # 64GB device pci 18.0 on end # Link 0 == LDT 0 device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] chip southbridge/nvidia/ck804 # Southbridge

1 0

Patch set updated for coreboot: 11aba66 mainboards/amdfam10: Copy DIMM information to cbmem after romstage
by Timothy Pearson 28 Mar '15

28 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9138 -gerrit commit 11aba66ceeff0a7438bc4d0188ddeb2b48d22d1f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:49:18 2015 -0500 mainboards/amdfam10: Copy DIMM information to cbmem after romstage Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/advansus/a785e-i/romstage.c | 3 +++ src/mainboard/amd/bimini_fam10/romstage.c | 3 +++ src/mainboard/amd/mahogany_fam10/romstage.c | 3 +++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 3 +++ src/mainboard/amd/tilapia_fam10/romstage.c | 3 +++ src/mainboard/asus/kfsn4-dre/romstage.c | 3 +++ src/mainboard/asus/m4a78-em/romstage.c | 3 +++ src/mainboard/asus/m4a785-m/romstage.c | 3 +++ src/mainboard/asus/m5a88-v/romstage.c | 3 +++ src/mainboard/avalue/eax-785e/romstage.c | 3 +++ src/mainboard/gigabyte/ma785gm/romstage.c | 3 +++ src/mainboard/gigabyte/ma785gmt/romstage.c | 3 +++ src/mainboard/gigabyte/ma78gm/romstage.c | 3 +++ src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +++ src/mainboard/iei/kino-780am2-fam10/romstage.c | 3 +++ src/mainboard/jetway/pa78vm5/romstage.c | 3 +++ src/mainboard/msi/ms9652_fam10/romstage.c | 3 +++ src/mainboard/supermicro/h8dmr_fam10/romstage.c | 3 +++ src/mainboard/supermicro/h8qme_fam10/romstage.c | 3 +++ src/mainboard/supermicro/h8scm_fam10/romstage.c | 3 +++ src/mainboard/tyan/s2912_fam10/romstage.c | 3 +++ src/northbridge/amd/amdfam10/raminit_amdmct.c | 2 -- 22 files changed, 63 insertions(+), 2 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index a70c269..a8459f2 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -210,6 +210,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index f4df3a3..5936bee 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -208,6 +208,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 501c8c3..23c611e 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -210,6 +210,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 2932c83..a09bff9 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -322,6 +322,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 97bf51a..b0588ef 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -210,6 +210,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index af6858f..f7db5fe 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -353,6 +353,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + printk(BIOS_DEBUG, "disable_spd()\n"); ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index da63c66..7c299a3 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -212,6 +212,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index e0c132f..e7b20b9 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -212,6 +212,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index cc4d04d..b98b7c7 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -207,6 +207,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 5cc9fb1..b54c41c 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -211,6 +211,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 991531d..68b8113 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -207,6 +207,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index a022a20..aad412d 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -207,6 +207,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 7675e25..ae72af9 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -210,6 +210,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index bf054d5..b748460 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -214,6 +214,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + bcm5785_early_setup(); timestamp_add_now(TS_END_ROMSTAGE); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 5f99df6..78956bd 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -210,6 +210,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 1686988..32a759f 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -215,6 +215,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index b2bfc8b..ac33b4e 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -241,6 +241,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + timestamp_add_now(TS_END_ROMSTAGE); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 980437b..1b0fdc4 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -238,6 +238,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + timestamp_add_now(TS_END_ROMSTAGE); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 20522e1..1b18bab 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -301,6 +301,9 @@ post_code(0x40); cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + timestamp_add_now(TS_END_ROMSTAGE); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 355cf82..3ce6d3b 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -222,6 +222,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 933d709..5f5e9eb 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -237,6 +237,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + timestamp_add_now(TS_END_ROMSTAGE); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index d1d87ff..ee190af 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -205,7 +205,6 @@ static void raminit_amdmct(struct sys_info *sysinfo) printk(BIOS_DEBUG, "raminit_amdmct end:\n"); } -#if 0 static void amdmct_cbmem_store_info(struct sys_info *sysinfo) { /* Save memory info structures for use in ramstage */ @@ -230,4 +229,3 @@ static void amdmct_cbmem_store_info(struct sys_info *sysinfo) mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); } } -#endif

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coreboot-gerrit March 2015