coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 08f2ab6 build system: rename mips/bootblock.inc to mips/bootblock.S
by gerrit＠coreboot.org 30 Mar '15

30 Mar '15

the following patch was just integrated into master: commit 08f2ab6aac9d4e5d0f992d25b9bc8d77620f03d9 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 14:03:22 2015 +0100 build system: rename mips/bootblock.inc to mips/bootblock.S This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I192fa50989b586fd8e967d4c22db56ac9de7a30e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9108 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/9108 for details. -gerrit

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Patch set updated for coreboot: 72fbb45 x86: fix SMM programs linked with gc-sections
by Aaron Durbin 30 Mar '15

30 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9160 -gerrit commit 72fbb452b2d2ae071d4f1163d4ce5dabd4ebbc1e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Mar 29 22:16:55 2015 -0500 x86: fix SMM programs linked with gc-sections Commit f69a99db (coreboot: x86: enable gc-sections) added gc-sections to the linker command line. The SMM-specific linker scripts were not interrogated to see if all the sections were being included properly. .data, .bss, and .sbss did not have the proper globs set to put the SMM programs in the expected order. Lastly, explicitly set the ENTRY for the SMM programs. Change-Id: Ibb579d18d4819af666d6ec7dfc30776e8c404b71 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/smm/smm.ld | 4 ++++ src/cpu/x86/smm/smm_tseg.ld | 4 ++++ src/cpu/x86/smm/smmhandler.S | 1 + src/cpu/x86/smm/smmhandler_tseg.S | 1 + 4 files changed, 10 insertions(+) diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 5d316a8..c198161 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -1,6 +1,7 @@ /* Maximum number of CPUs/cores */ CPUS = 4; +ENTRY(smm_handler_start); SECTIONS { @@ -25,11 +26,14 @@ SECTIONS /* C read-write data of the SMM handler */ . = ALIGN(4); *(.data) + *(.data.*) /* C uninitialized data of the SMM handler */ . = ALIGN(4); *(.bss) + *(.bss.*) *(.sbss) + *(.sbss.*) /* What is this? */ *(COMMON) diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld index 99f2aa0..b57461c 100644 --- a/src/cpu/x86/smm/smm_tseg.ld +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -1,5 +1,6 @@ /* Maximum number of CPUs/cores */ CPUS = 16; +ENTRY(smm_handler_start); SECTIONS { @@ -52,11 +53,14 @@ SECTIONS /* C read-write data of the SMM handler */ . = ALIGN(4); *(.data) + *(.data.*) /* C uninitialized data of the SMM handler */ . = ALIGN(4); *(.bss) + *(.bss.*) *(.sbss) + *(.sbss.*) *(COMMON) . = ALIGN(4); diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 5d3aae3..611c0f3 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -75,6 +75,7 @@ * * All the bad magic is not all that bad after all. */ +.global smm_handler_start smm_handler_start: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index c9d78b9..ee8bd26 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -91,6 +91,7 @@ * * All the bad magic is not all that bad after all. */ +.global smm_handler_start smm_handler_start: movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */

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Patch set updated for coreboot: 19a1b51 x86: fix SMM programs linked with gc-sections
by Aaron Durbin 30 Mar '15

30 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9160 -gerrit commit 19a1b51a2fd5e1cceb0a76b502641eacd5a9dbd9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Mar 29 22:16:55 2015 -0500 x86: fix SMM programs linked with gc-sections Commit f69a99db (coreboot: x86: enable gc-sections) added gc-sections to the linker command line. The SMM-specific linker scripts were not interrogated to see if all the sections were being included properly. .data, .bss, and .sbss were did not have the proper globs set to put the SMM programs in the expected order. Lastly, explicitly set the ENTRY for the SMM programs. Change-Id: Ibb579d18d4819af666d6ec7dfc30776e8c404b71 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/smm/smm.ld | 4 ++++ src/cpu/x86/smm/smm_tseg.ld | 4 ++++ src/cpu/x86/smm/smmhandler.S | 1 + src/cpu/x86/smm/smmhandler_tseg.S | 1 + 4 files changed, 10 insertions(+) diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 5d316a8..c198161 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -1,6 +1,7 @@ /* Maximum number of CPUs/cores */ CPUS = 4; +ENTRY(smm_handler_start); SECTIONS { @@ -25,11 +26,14 @@ SECTIONS /* C read-write data of the SMM handler */ . = ALIGN(4); *(.data) + *(.data.*) /* C uninitialized data of the SMM handler */ . = ALIGN(4); *(.bss) + *(.bss.*) *(.sbss) + *(.sbss.*) /* What is this? */ *(COMMON) diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld index 99f2aa0..b57461c 100644 --- a/src/cpu/x86/smm/smm_tseg.ld +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -1,5 +1,6 @@ /* Maximum number of CPUs/cores */ CPUS = 16; +ENTRY(smm_handler_start); SECTIONS { @@ -52,11 +53,14 @@ SECTIONS /* C read-write data of the SMM handler */ . = ALIGN(4); *(.data) + *(.data.*) /* C uninitialized data of the SMM handler */ . = ALIGN(4); *(.bss) + *(.bss.*) *(.sbss) + *(.sbss.*) *(COMMON) . = ALIGN(4); diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 5d3aae3..611c0f3 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -75,6 +75,7 @@ * * All the bad magic is not all that bad after all. */ +.global smm_handler_start smm_handler_start: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index c9d78b9..ee8bd26 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -91,6 +91,7 @@ * * All the bad magic is not all that bad after all. */ +.global smm_handler_start smm_handler_start: movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */

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Patch set updated for coreboot: e105eb1 x86: fix SMM programs linked with gc-sections
by Aaron Durbin 30 Mar '15

30 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9160 -gerrit commit e105eb1d04dfed049c4183b840ec57ccd5c90b7c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Mar 29 22:16:55 2015 -0500 x86: fix SMM programs linked with gc-sections Commit f69a99db (coreboot: x86: enable gc-sections) added gc-sections to the linker command line. The SMM-specific linker scripts were not interrogated to see if all the sections were being included properly. .data, .bss, and .sbss were did not have the proper globs set to put the SMM programs in the expected order. Lastly, explicitly set the ENTRY for the SMM programs. Change-Id: Ibb579d18d4819af666d6ec7dfc30776e8c404b71 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/smm/smm.ld | 1 + src/cpu/x86/smm/smm_tseg.ld | 6 ++++-- src/cpu/x86/smm/smmhandler.S | 1 + src/cpu/x86/smm/smmhandler_tseg.S | 1 + 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 5d316a8..6cbde09 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -1,6 +1,7 @@ /* Maximum number of CPUs/cores */ CPUS = 4; +ENTRY(smm_handler_start); SECTIONS { diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld index 99f2aa0..e8f067d 100644 --- a/src/cpu/x86/smm/smm_tseg.ld +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -1,5 +1,6 @@ /* Maximum number of CPUs/cores */ CPUS = 16; +ENTRY(smm_handler_start); SECTIONS { @@ -52,11 +53,12 @@ SECTIONS /* C read-write data of the SMM handler */ . = ALIGN(4); *(.data) + *(.data.*) /* C uninitialized data of the SMM handler */ . = ALIGN(4); - *(.bss) - *(.sbss) + *(.bss.*) + *(.sbss.*) *(COMMON) . = ALIGN(4); diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 5d3aae3..611c0f3 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -75,6 +75,7 @@ * * All the bad magic is not all that bad after all. */ +.global smm_handler_start smm_handler_start: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index c9d78b9..ee8bd26 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -91,6 +91,7 @@ * * All the bad magic is not all that bad after all. */ +.global smm_handler_start smm_handler_start: movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */

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Patch set updated for coreboot: 6242181 build system: add .xcompile to CBFS
by Idwer Vollering 30 Mar '15

30 Mar '15

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9159 -gerrit commit 62421817a38306089b2fe544e6c7a4d6d50c9af6 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Mon Mar 30 00:17:16 2015 +0200 build system: add .xcompile to CBFS Change-Id: I20407d3a5d3432bc7c2c20d0d6cdd88205f09177 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- Makefile.inc | 4 ++++ src/Kconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 838a680..9627048 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -577,6 +577,10 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " REVISION build.h\n" if [ -f $(obj)/build.h ]; then $(CBFSTOOL) $@.tmp add -f $(obj)/build.h -n revision -t raw; fi endif +ifeq ($(CONFIG_INCLUDE_XCOMPILE_FILE),y) + @printf " CONFIG $(DOTXCOMPILE)\n" + if [ -f $(DOTXCOMPILE) ]; then $(CBFSTOOL) $@.tmp add -f $(top)/.xcompile -n xcompile -t raw; fi +endif ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) endif diff --git a/src/Kconfig b/src/Kconfig index 7aee478..ceb89de 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -88,6 +88,10 @@ config ANY_TOOLCHAIN we'll have to assume that they use their distro compiler by mistake. Make sure that using patched compilers is a conscious decision. +config INCLUDE_XCOMPILE_FILE + bool "Include the coreboot .xcompile file into the ROM image" + default y + config CCACHE bool "Use ccache to speed up (re)compilation" default n

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Patch set updated for coreboot: 068bc0f build system: add .xcompile to coreboot.rom's CBFS
by Idwer Vollering 30 Mar '15

30 Mar '15

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9159 -gerrit commit 068bc0f2abe75572b6386955f0c255f20ea55fd4 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Mon Mar 30 00:17:16 2015 +0200 build system: add .xcompile to coreboot.rom's CBFS Change-Id: I20407d3a5d3432bc7c2c20d0d6cdd88205f09177 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- Makefile.inc | 4 ++++ src/Kconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 838a680..9627048 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -577,6 +577,10 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " REVISION build.h\n" if [ -f $(obj)/build.h ]; then $(CBFSTOOL) $@.tmp add -f $(obj)/build.h -n revision -t raw; fi endif +ifeq ($(CONFIG_INCLUDE_XCOMPILE_FILE),y) + @printf " CONFIG $(DOTXCOMPILE)\n" + if [ -f $(DOTXCOMPILE) ]; then $(CBFSTOOL) $@.tmp add -f $(top)/.xcompile -n xcompile -t raw; fi +endif ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) endif diff --git a/src/Kconfig b/src/Kconfig index 7aee478..ceb89de 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -88,6 +88,10 @@ config ANY_TOOLCHAIN we'll have to assume that they use their distro compiler by mistake. Make sure that using patched compilers is a conscious decision. +config INCLUDE_XCOMPILE_FILE + bool "Include the coreboot .xcompile file into the ROM image" + default y + config CCACHE bool "Use ccache to speed up (re)compilation" default n

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New patch to review for coreboot: 32fab03 mips: bring payload execution to current standards
by Patrick Georgi 30 Mar '15

30 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9167 -gerrit commit 32fab030103c4f3b63cb9c5de5a79c9b340a0f7d Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Mar 30 14:13:23 2015 +0200 mips: bring payload execution to current standards Change-Id: Id7f438a95fc7c7b41ce3d0fb419b0b455f8367a9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/arch/mips/boot.c | 7 ++++--- src/arch/mips/include/arch/stages.h | 1 - 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c index d322e99..b213ffc 100644 --- a/src/arch/mips/boot.c +++ b/src/arch/mips/boot.c @@ -19,9 +19,10 @@ #include <console/console.h> #include <arch/stages.h> +#include <program_loading.h> -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) +void arch_payload_run(const struct payload *payload) { - printk(BIOS_SPEW, "entry = %p\n", entry); - stage_exit(entry); + printk(BIOS_SPEW, "entry = %p\n", payload->entry); + stage_exit(payload->entry); } diff --git a/src/arch/mips/include/arch/stages.h b/src/arch/mips/include/arch/stages.h index b95ad1d..3015bb1 100644 --- a/src/arch/mips/include/arch/stages.h +++ b/src/arch/mips/include/arch/stages.h @@ -24,6 +24,5 @@ extern void main(void); void stage_entry(void); void stage_exit(void *); -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); #endif /* __MIPS_ARCH_STAGES_H */

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New patch to review for coreboot: b80a2cb mips: fix write_table
by Patrick Georgi 30 Mar '15

30 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9166 -gerrit commit b80a2cbf4a5a216c60b6654b7fa3db365491633d Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Mar 30 14:06:33 2015 +0200 mips: fix write_table This replicates commit 3f7ad7b216b4021c7cb93201a94b0fae46f5e19e and commit 823edda98e6512d3f455b61549efea6fa68ee2b0 for mips. Change-Id: Id97e1fefa20cfa3bcb2cf0336b5a4ff7d9fe813b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/arch/mips/tables.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c index 858fa79..9bd72d7 100644 --- a/src/arch/mips/tables.c +++ b/src/arch/mips/tables.c @@ -30,11 +30,7 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - -struct lb_memory *write_tables(void) +void write_tables(void) { unsigned long table_pointer, new_table_pointer; @@ -44,7 +40,7 @@ struct lb_memory *write_tables(void) MAX_COREBOOT_TABLE_SIZE); if (!table_pointer) { printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return NULL; + return; } new_table_pointer = write_coreboot_table(0UL, 0UL, table_pointer, @@ -62,6 +58,4 @@ struct lb_memory *write_tables(void) /* Print CBMEM sections */ cbmem_list(); - - return get_lb_mem(); }

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New patch to review for coreboot: 87de647 imgtec/pistachio: Bring uart driver to modern standards
by Patrick Georgi 30 Mar '15

30 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9165 -gerrit commit 87de647cfea532627f91bb2d695bf5ac2b924a81 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Mar 30 13:08:18 2015 +0200 imgtec/pistachio: Bring uart driver to modern standards The console interface changed in upstream, and the driver didn't reflect that yet. This wasn't obvious because the driver wasn't compiled at all. Change-Id: Id18391e62e7ebd8f5fc929838ce27bf414e364f9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/arch/mips/Makefile.inc | 1 - src/arch/mips/early_console.c | 38 ------------------ src/soc/imgtec/pistachio/Makefile.inc | 2 +- src/soc/imgtec/pistachio/uart.c | 75 ++++++++++------------------------- 4 files changed, 23 insertions(+), 93 deletions(-) diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index 9636333..18f98ab 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -37,7 +37,6 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_MIPS),y) bootblock-y += boot.c bootblock-y += bootblock.S bootblock-y += bootblock_simple.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c bootblock-y += stages.c bootblock-y += timer.c bootblock-y += ../../lib/memcpy.c diff --git a/src/arch/mips/early_console.c b/src/arch/mips/early_console.c deleted file mode 100644 index c699abc..0000000 --- a/src/arch/mips/early_console.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/vtxprintf.h> - -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_byte(byte); -#endif -} - -void console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_flush(); -#endif -} diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index e695abd..b91bb1b5 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -24,7 +24,7 @@ bootblock-y += spi.c romstage-y += spi.c ramstage-y += spi.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c romstage-y += uart.c ramstage-y += uart.c diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index 53bf21d..9c96b89 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -22,11 +22,12 @@ */ #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <console/console.h> +#include <console/uart.h> #include <device/device.h> #include <delay.h> -#include <uart.h> -#include <uart8250.h> +#include <drivers/uart/uart8250reg.h> /* Should support 8250, 16450, 16550, 16550A type UARTs */ @@ -115,13 +116,13 @@ static void uart8250_mem_init(unsigned base_port, unsigned divisor) write_lcr(base_port, CONFIG_TTYS0_LCS); } -static unsigned int uart_platform_refclk(void) +unsigned int uart_platform_refclk(void) { /* TODO: this is entirely arbitrary */ return 1000000; } -static unsigned int uart_platform_base(int idx) +uintptr_t uart_platform_base(int idx) { switch (idx) { case 0: @@ -135,16 +136,9 @@ static unsigned int uart_platform_base(int idx) } } -/* Calculate divisor. Do not floor but round to nearest integer. */ -static unsigned int uart_baudrate_divisor(unsigned int baudrate, - unsigned int refclk, unsigned int oversample) +void uart_init(int idx) { - return (1 + (2 * refclk) / (baudrate * oversample)) / 2; -} - -static void pistachio_uart_init(void) -{ - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; @@ -154,64 +148,39 @@ static void pistachio_uart_init(void) uart8250_mem_init(base, div); } -static void pistachio_uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_byte(base, data); } -static unsigned char pistachio_uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return 0xff; return uart8250_mem_rx_byte(base); } -static void pistachio_uart_tx_flush(void) +void uart_tx_flush(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_flush(base); } -#if !defined(__PRE_RAM__) - -static const struct console_driver pistachio_uart_console __console = { - .init = pistachio_uart_init, - .tx_byte = pistachio_uart_tx_byte, - .tx_flush = pistachio_uart_tx_flush, - .rx_byte = pistachio_uart_rx_byte, -}; - -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} - -#else /* __PRE_RAM__ */ - -void uart_init(void) -{ - pistachio_uart_init(); -} - -void uart_tx_byte(unsigned char data) +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) { - pistachio_uart_tx_byte(data); -} + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); -unsigned char uart_rx_byte(void) -{ - return pistachio_uart_rx_byte(); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } - -void uart_tx_flush(void) -{ - pistachio_uart_tx_flush(); -} - -#endif /* __PRE_RAM__ */ +#endif

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New patch to review for coreboot: 18cdea2 emulation/imgvp-pistachio: Drop board
by Patrick Georgi 30 Mar '15

30 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9164 -gerrit commit 18cdea24fa9c4a529aaa016035319792b830c8b3 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Mar 30 13:29:45 2015 +0200 emulation/imgvp-pistachio: Drop board This doesn't even compile in downstream. Change-Id: Ic7b3736db86e8de155e0f37afa970ce5095396fa Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/mainboard/emulation/Kconfig | 4 -- src/mainboard/emulation/imgvp-pistachio/Kconfig | 53 ---------------------- .../emulation/imgvp-pistachio/Makefile.inc | 22 --------- .../emulation/imgvp-pistachio/bootblock.c | 24 ---------- .../emulation/imgvp-pistachio/devicetree.cb | 26 ----------- .../emulation/imgvp-pistachio/mainboard.c | 33 -------------- src/mainboard/emulation/imgvp-pistachio/romstage.c | 29 ------------ 7 files changed, 191 deletions(-) diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index d2706fa..e48c242 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -14,9 +14,6 @@ config BOARD_EMULATION_QEMU_ARMV7 config BOARD_EMULATION_QEMU_UCB_RISCV bool "QEMU ucb riscv" -config BOARD_EMULATION_IMGVP_PISTACHIO - bool "ImgTec Pistachio Virtual Platform" - endchoice config BOARD_EMULATION_QEMU_X86 @@ -28,7 +25,6 @@ source "src/mainboard/emulation/qemu-i440fx/Kconfig" source "src/mainboard/emulation/qemu-q35/Kconfig" source "src/mainboard/emulation/qemu-armv7/Kconfig" source "src/mainboard/emulation/qemu-riscv/Kconfig" -source "src/mainboard/emulation/imgvp-pistachio/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/emulation/imgvp-pistachio/Kconfig b/src/mainboard/emulation/imgvp-pistachio/Kconfig deleted file mode 100644 index 068528e..0000000 --- a/src/mainboard/emulation/imgvp-pistachio/Kconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA -# - -if BOARD_EMULATION_IMGVP_PISTACHIO - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOOTBLOCK_CONSOLE - select CPU_IMGTEC_PISTACHIO - -config MAINBOARD_DIR - string - default emulation/imgvp-pistachio - -config MAINBOARD_PART_NUMBER - string - default "ImgTec Pistachio Virtual Platform" - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/emulation/imgvp-pistachio/bootblock.c" - -config SYS_SDRAM_BASE - hex "SDRAM base address" - default 0x80000000 - -config DRAM_SIZE_MB - int - default 256 - -config HEAP_SIZE - hex - default 0x08000000 - -endif diff --git a/src/mainboard/emulation/imgvp-pistachio/Makefile.inc b/src/mainboard/emulation/imgvp-pistachio/Makefile.inc deleted file mode 100644 index 8be1b22..0000000 --- a/src/mainboard/emulation/imgvp-pistachio/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright 2014 Imagination Technologies Ltd. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA -# - -romstage-y += romstage.c diff --git a/src/mainboard/emulation/imgvp-pistachio/bootblock.c b/src/mainboard/emulation/imgvp-pistachio/bootblock.c deleted file mode 100644 index 1784a02..0000000 --- a/src/mainboard/emulation/imgvp-pistachio/bootblock.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -void bootblock_mainboard_init(void) -{ -} diff --git a/src/mainboard/emulation/imgvp-pistachio/devicetree.cb b/src/mainboard/emulation/imgvp-pistachio/devicetree.cb deleted file mode 100644 index a328b9d..0000000 --- a/src/mainboard/emulation/imgvp-pistachio/devicetree.cb +++ /dev/null @@ -1,26 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA -# - -chip soc/imgtec/pistachio - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing - end -end diff --git a/src/mainboard/emulation/imgvp-pistachio/mainboard.c b/src/mainboard/emulation/imgvp-pistachio/mainboard.c deleted file mode 100644 index fdae940..0000000 --- a/src/mainboard/emulation/imgvp-pistachio/mainboard.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/device.h> - -static void mainboard_enable(device_t dev) -{ - printk(BIOS_INFO, "Enable imgvp-pistachio device...\n"); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - diff --git a/src/mainboard/emulation/imgvp-pistachio/romstage.c b/src/mainboard/emulation/imgvp-pistachio/romstage.c deleted file mode 100644 index 3fcf23d..0000000 --- a/src/mainboard/emulation/imgvp-pistachio/romstage.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <program_loading.h> -#include <console/console.h> - -void main(void) -{ - console_init(); - run_ramstage(); -}

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coreboot-gerrit March 2015