coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: coreinfo: Move screen dimensions to header
by Yasha Cherikovsky 14 Nov '15

14 Nov '15

Yasha Cherikovsky (yasha.che3(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12439 -gerrit commit 09a9082174fc759383aedb9b315e2be86479407d Author: Yasha Cherikovsky <yasha.cherikovsky(a)gmail.com> Date: Sat Nov 14 18:52:35 2015 +0200 coreinfo: Move screen dimensions to header The screen dimensions need to be known in other files. Change-Id: Idf6f02e4cadbece78096ccd464296ecec405574d Signed-off-by: Yasha Cherikovsky <yasha.che3(a)gmail.com> --- payloads/coreinfo/coreinfo.c | 3 --- payloads/coreinfo/coreinfo.h | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index a383330..41b5f12 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -15,9 +15,6 @@ #include "coreinfo.h" -#define SCREEN_Y 25 -#define SCREEN_X 80 - #define KEY_ESC 27 extern struct coreinfo_module cpuinfo_module; diff --git a/payloads/coreinfo/coreinfo.h b/payloads/coreinfo/coreinfo.h index b1f91aa..073c5f9 100644 --- a/payloads/coreinfo/coreinfo.h +++ b/payloads/coreinfo/coreinfo.h @@ -32,4 +32,7 @@ extern void docpuid(int, unsigned long *, unsigned long *, unsigned long *, void print_module_title(WINDOW *win, const char *title); +#define SCREEN_Y 25 +#define SCREEN_X 80 + #endif

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New patch to review for coreboot: coreinfo: Fix off-by-one in displayed month of year
by Yasha Cherikovsky 14 Nov '15

14 Nov '15

Yasha Cherikovsky (yasha.che3(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12438 -gerrit commit 3f889c80fa7bb21e530b5f0562c6eaa07bc17bf8 Author: Yasha Cherikovsky <yasha.cherikovsky(a)gmail.com> Date: Sat Nov 14 18:52:35 2015 +0200 coreinfo: Fix off-by-one in displayed month of year According to C documentation, the range of tm_mon in struct tm is [0, 11]. Before the patch, the displayed month was indeed incorrect. Change-Id: I9f95f1e978c45b3635e2edfe1ec496d7b0dec00a Signed-off-by: Yasha Cherikovsky <yasha.che3(a)gmail.com> --- payloads/coreinfo/coreinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 5137ce6..a383330 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -128,7 +128,7 @@ static void print_time_and_date(void) rtc_read_clock(&tm); mvwprintw(menuwin, 0, 57, "%02d/%02d/%04d - %02d:%02d:%02d", - tm.tm_mon, tm.tm_mday, 1900 + tm.tm_year, tm.tm_hour, + tm.tm_mon + 1, tm.tm_mday, 1900 + tm.tm_year, tm.tm_hour, tm.tm_min, tm.tm_sec); } #endif

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New patch to review for coreboot: coreinfo: Hide blinking cursor
by Yasha Cherikovsky 14 Nov '15

14 Nov '15

Yasha Cherikovsky (yasha.che3(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12437 -gerrit commit 579b7d67685f1231d0dbbe37527c8e44bfa43cbf Author: Yasha Cherikovsky <yasha.cherikovsky(a)gmail.com> Date: Sat Nov 14 18:52:35 2015 +0200 coreinfo: Hide blinking cursor Change-Id: I6297fc178203dcfbd0b2a4c78dd83359e7804933 Signed-off-by: Yasha Cherikovsky <yasha.che3(a)gmail.com> --- payloads/coreinfo/coreinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index beda918..5137ce6 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -294,6 +294,7 @@ int main(void) noecho(); /* don't let curses echo keyboard chars */ keypad(stdscr, TRUE); /* allow KEY_F(n) keys to be seen */ + curs_set(0); /* Hide blinking cursor */ loop();

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: Factor out code into toggle_io_reset
by Patrick Rudolph 14 Nov '15

14 Nov '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11916 -gerrit commit 69ecc51ce9d98a62e80c5b6919a4bda154499c2f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Oct 9 13:43:51 2015 +0200 nb/intel/sandybridge/raminit: Factor out code into toggle_io_reset Found while doing code review. Use a function to toggle IO reset signal. Change-Id: I4cb0885ed9be763fbc4069e4d015a36a7183c823 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 48 +++++++++-------------------- 1 file changed, 14 insertions(+), 34 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 23b34f5..4e3f93e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -224,6 +224,15 @@ static void sfence(void) asm volatile ("sfence"); } +static void toggle_io_reset(void) { + /* toggle IO reset bit */ + u32 r32 = read32(DEFAULT_MCHBAR + 0x5030); + write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); + udelay(1); + write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); + udelay(1); +} + /* * Dump in the log memory controller configuration as read from the memory * controller registers. @@ -1917,7 +1926,6 @@ static void read_training(ramctr_timing * ctrl) int channel, slotrank, lane; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - u32 r32; int all_high, some_high; int upperA[NUM_LANES]; struct timA_minmax mnmx; @@ -2000,12 +2008,7 @@ static void read_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x3400, 0); - /* toggle IO reset bit */ - r32 = read32(DEFAULT_MCHBAR + 0x5030); - write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); - udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); + toggle_io_reset(); } FOR_ALL_POPULATED_CHANNELS { @@ -2530,7 +2533,6 @@ static void write_op(ramctr_timing * ctrl, int channel) static void write_training(ramctr_timing * ctrl) { int channel, slotrank, lane; - u32 r32; FOR_ALL_POPULATED_CHANNELS write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, @@ -2560,12 +2562,7 @@ static void write_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x3400, 0x108052); - /* toggle IO reset bit */ - r32 = read32(DEFAULT_MCHBAR + 0x5030); - write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); - udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); + toggle_io_reset(); /* set any valid value for timB, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS @@ -2601,12 +2598,7 @@ static void write_training(ramctr_timing * ctrl) wait_428c(channel); } - /* toggle IO reset bit */ - r32 = read32(DEFAULT_MCHBAR + 0x5030); - write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); - udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); + toggle_io_reset(); printram("CPE\n"); precharge(ctrl); @@ -2754,7 +2746,6 @@ static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno) static void reprogram_320c(ramctr_timing * ctrl) { int channel, slotrank; - u32 r32; FOR_ALL_POPULATED_CHANNELS { wait_428c(channel); @@ -2804,12 +2795,7 @@ static void reprogram_320c(ramctr_timing * ctrl) /* mrs commands. */ dram_mrscommands(ctrl); - /* toggle IO reset bit */ - r32 = read32(DEFAULT_MCHBAR + 0x5030); - write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); - udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); + toggle_io_reset(); } #define MIN_C320C_LEN 13 @@ -2995,16 +2981,10 @@ static void discover_edges(ramctr_timing * ctrl) int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; - u32 r32; write32(DEFAULT_MCHBAR + 0x3400, 0); - /* toggle IO reset bit */ - r32 = read32(DEFAULT_MCHBAR + 0x5030); - write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); - udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); + toggle_io_reset(); FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { write32(DEFAULT_MCHBAR + 4 * lane +

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: Comment the code
by Patrick Rudolph 14 Nov '15

14 Nov '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11915 -gerrit commit b2fa5f636b7ece86661b9d3f7d2ebb94db760584 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Oct 9 13:33:25 2015 +0200 nb/intel/sandybridge/raminit: Comment the code Add lots of comments for better documentation. Change-Id: Ia203cb649857f979bb6c1c2d405b74f2ccc8f99d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 205 ++++++++++++++++++++++++++-- 1 file changed, 190 insertions(+), 15 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 76f62a6..b3b6d18 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -45,6 +45,38 @@ /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ +/* + * Register description: + * Intel provides a command queue of depth four. + * Every command is configured by using multiple registers. + * On executing the command queue you have to provide the depth used. + * + * Known registers: + * Channel X = [0, 1] + * Command queue index Y = [0, 1, 2, 3] + * + * DEFAULT_MCHBAR + 0x4220 + 0x400 * X + 4 * Y: command io register + * Controls the DRAM command signals + * Bit 0: !RAS + * Bit 1: !CAS + * Bit 2: !WE + * + * DEFAULT_MCHBAR + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register + * Controls the address, bank address and slotrank signals + * Bit 0-15 : Address + * Bit 20-22: Bank Address + * Bit 24-25: slotrank + * + * DEFAULT_MCHBAR + 0x4230 + 0x400 * X + 4 * Y: idle register + * Controls the idle time after issuing this DRAM command + * Bit 16-32: number of clock-cylces to idle + * + * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue + * Starts to execute all queued commands + * Bit 0 : start DRAM command execution + * Bit 16-20: (number of queued commands - 1) * 4 + */ + #define BASEFREQ 133 #define tDLLK 512 @@ -1119,6 +1151,7 @@ static void write_reset(ramctr_timing * ctrl) /* choose a populated rank. */ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; + /* DRAM command ZQCS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x80c01); @@ -1229,18 +1262,21 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank, printram("MRd: %x <= %x\n", reg, val); + /* DRAM command MRS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, (slotrank << 24) | (reg << 20) | val | 0x60000); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command MRS */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x41001); write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24) | (reg << 20) | val | 0x60000); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + /* DRAM command MRS */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x0f000); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x1001 | (ctrl->tMOD << 16)); @@ -1254,6 +1290,8 @@ static u32 make_mr0(ramctr_timing * ctrl, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; + + /* DLL Reset - self clearing - set after CLK frequency has been changed */ mr0reg = 0x100; // Convert CAS to MCH register friendly @@ -1270,7 +1308,8 @@ static u32 make_mr0(ramctr_timing * ctrl, u8 rank) mr0reg = (mr0reg & ~0x4) | (mch_cas & 0x1); mr0reg = (mr0reg & ~0x70) | ((mch_cas & 0xe) << 3); mr0reg = (mr0reg & ~0xe00) | (mch_wr << 9); - // Fast (desktop) 0x1 or slow (mobile) 0x0 + + // Precharge PD - Fast (desktop) 0x1 or slow (mobile) 0x0 - mostly power-saving feature mr0reg = (mr0reg & ~0x1000) | (!ctrl->mobile << 12); return mr0reg; } @@ -1385,14 +1424,19 @@ static void dram_mrscommands(ramctr_timing * ctrl) printram("done\n"); } + /* DRAM command NOP */ write32(DEFAULT_MCHBAR + 0x4e20, 0x7); write32(DEFAULT_MCHBAR + 0x4e30, 0xf1001); write32(DEFAULT_MCHBAR + 0x4e00, 0x60002); write32(DEFAULT_MCHBAR + 0x4e10, 0); + + /* DRAM command ZQCL */ write32(DEFAULT_MCHBAR + 0x4e24, 0x1f003); write32(DEFAULT_MCHBAR + 0x4e34, 0x1901001); write32(DEFAULT_MCHBAR + 0x4e04, 0x60400); write32(DEFAULT_MCHBAR + 0x4e14, 0x288); + + /* execute command queue on all channels ? */ write32(DEFAULT_MCHBAR + 0x4e84, 0x40004); // Drain @@ -1417,6 +1461,7 @@ static void dram_mrscommands(ramctr_timing * ctrl) // Drain wait_428c(channel); + /* DRAM command ZQCS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001); write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, @@ -1593,6 +1638,10 @@ static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) { wait_428c(channel); + /* DRAM command MRS + * write MR3 MPR enable + * in this mode only RD and RDA are allowed + * all reads return a predefined pattern */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, (0xc01 | (ctrl->tMOD << 16))); @@ -1600,11 +1649,13 @@ static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) (slotrank << 24) | 0x360004); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4040c01); write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x100f | ((ctrl->CAS + 36) << 16)); @@ -1612,6 +1663,8 @@ static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + /* DRAM command MRS + * write MR3 MPR disable */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, (0xc01 | (ctrl->tMOD << 16))); @@ -1843,6 +1896,23 @@ static void post_timA_change(ramctr_timing * ctrl, int channel, int slotrank, printram("4028 += %d;\n", shift_402x); } +/* Compensate the skew between DQS and DQs. + * To ease PCB design a small skew between Data Strobe signals and + * Data Signals is allowed. + * The controller has to measure and compensate this skew for every byte-lane. + * By delaying either all DQs signals or DQS signal, a full phase + * shift can be introduced. + * It is assumed that one byte-lane's DQs signals have the same routing delay. + * + * To measure the actual skew, the DRAM is placed in "read leveling" mode. + * In read leveling mode the DRAM-chip outputs an alternating periodic pattern. + * The memory controller iterates over all possible values to do a full phase shift + * and issues read commands. + * With DQS and DQs in phase the data read is expected to alternate on every byte: + * 0xFF 0x00 0xFF ... + * Once the controller has detected this pattern a bit in the result register is + * set for the current phase shift. + */ static void read_training(ramctr_timing * ctrl) { int channel, slotrank, lane; @@ -1854,6 +1924,8 @@ static void read_training(ramctr_timing * ctrl) struct timA_minmax mnmx; wait_428c(channel); + + /* DRAM command PREA */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0xc01 | (ctrl->tRP << 16)); @@ -1929,12 +2001,11 @@ static void read_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x3400, 0); + /* toggle IO reset bit */ r32 = read32(DEFAULT_MCHBAR + 0x5030); write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); } @@ -1958,6 +2029,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) wait_428c(channel); + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) @@ -1968,17 +2040,20 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); + /* DRAM command NOP */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8041001); write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24) | 8); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0); + /* DRAM command WR */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x80411f4); write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); + /* DRAM command NOP */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16)); @@ -1990,6 +2065,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) wait_428c(channel); + /* DRAM command PREA */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0xc01 | (ctrl->tRP << 16)); @@ -1997,6 +2073,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) (slotrank << 24) | 0x60400); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) @@ -2007,12 +2084,14 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x244); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x40011f4 | (max(ctrl->tRTP, 8) << 16)); write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); + /* DRAM command PREA */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xc01 | (ctrl->tRP << 16)); @@ -2031,6 +2110,7 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) wait_428c(channel); + /* DRAM command PREA */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0xc01 | (ctrl->tRP << 16)); @@ -2121,6 +2201,10 @@ static void precharge(ramctr_timing * ctrl) FOR_ALL_POPULATED_RANKS { wait_428c(channel); + /* DRAM command MRS + * write MR3 MPR enable + * in this mode only RD and RDA are allowed + * all reads return a predefined pattern */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, @@ -2129,6 +2213,7 @@ static void precharge(ramctr_timing * ctrl) (slotrank << 24) | 0x360004); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, @@ -2137,6 +2222,7 @@ static void precharge(ramctr_timing * ctrl) (slotrank << 24) | 0); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, @@ -2145,6 +2231,8 @@ static void precharge(ramctr_timing * ctrl) (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + /* DRAM command MRS + * write MR3 MPR disable */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, @@ -2169,7 +2257,10 @@ static void precharge(ramctr_timing * ctrl) FOR_ALL_POPULATED_RANKS { wait_428c(channel); - + /* DRAM command MRS + * write MR3 MPR enable + * in this mode only RD and RDA are allowed + * all reads return a predefined pattern */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, @@ -2178,6 +2269,7 @@ static void precharge(ramctr_timing * ctrl) (slotrank << 24) | 0x360004); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, @@ -2186,6 +2278,7 @@ static void precharge(ramctr_timing * ctrl) (slotrank << 24) | 0); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, @@ -2194,6 +2287,8 @@ static void precharge(ramctr_timing * ctrl) (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + /* DRAM command MRS + * write MR3 MPR disable */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, @@ -2212,10 +2307,12 @@ static void precharge(ramctr_timing * ctrl) static void test_timB(ramctr_timing * ctrl, int channel, int slotrank) { + /* enable DQs on this slotrank */ write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank)); wait_428c(channel); + /* DRAM command NOP */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f207); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16)); @@ -2223,6 +2320,7 @@ static void test_timB(ramctr_timing * ctrl, int channel, int slotrank) 8 | (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command NOP */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f107); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4000c01 | ((ctrl->CAS + 38) << 16)); @@ -2233,6 +2331,7 @@ static void test_timB(ramctr_timing * ctrl, int channel, int slotrank) write32(DEFAULT_MCHBAR + 0x400 * channel + 0x4284, 0x40001); wait_428c(channel); + /* disable DQs on this slotrank */ write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank)); } @@ -2310,6 +2409,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) wait_428c(channel); + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0xc01 | (ctrl->tRCD << 16)); @@ -2317,18 +2417,21 @@ static void adjust_high_timB(ramctr_timing * ctrl) (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command NOP */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8040c01); write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24) | 0x8); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0); + /* DRAM command WR */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x8041003); write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x3e2); + /* DRAM command NOP */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16)); @@ -2340,6 +2443,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) wait_428c(channel); + /* DRAM command PREA */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0xc01 | ((ctrl->tRP) << 16)); @@ -2347,6 +2451,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) (slotrank << 24) | 0x60400); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0xc01 | ((ctrl->tRCD) << 16)); @@ -2354,6 +2459,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x3f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x4000c01 | @@ -2396,6 +2502,7 @@ static void write_op(ramctr_timing * ctrl, int channel) /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); @@ -2408,6 +2515,18 @@ static void write_op(ramctr_timing * ctrl, int channel) wait_428c(channel); } +/* Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. + * DDR3 adopted the fly-by topology. The data and strobes signals reach + * the chips at different times with respect to command, address and + * clock signals. + * By delaying either all DQ/DQs or all CMD/ADDR/CLK signals, a full phase + * shift can be introduced. + * It is assumed that the CLK/ADDR/CMD signals have the same routing delay. + * + * To find the required phase shift the DRAM is placed in "write leveling" mode. + * In this mode the DRAM-chip samples the CLK on every DQS edge and feeds back the + * sampled value on the data lanes (DQs). + */ static void write_training(ramctr_timing * ctrl) { int channel, slotrank, lane; @@ -2424,11 +2543,16 @@ static void write_training(ramctr_timing * ctrl) read32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel) | 0x200000); } + + /* refresh disable */ write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } + /* enable write leveling on all ranks + * disable all DQ outputs + * only NOP is allowed in this mode */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel, slotrank, 1, @@ -2436,17 +2560,18 @@ static void write_training(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x3400, 0x108052); + /* toggle IO reset bit */ r32 = read32(DEFAULT_MCHBAR + 0x5030); write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); + /* set any valid value for timB, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS discover_timB(ctrl, channel, slotrank); + /* disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank)); @@ -2456,6 +2581,7 @@ static void write_training(ramctr_timing * ctrl) FOR_ALL_POPULATED_CHANNELS wait_428c(channel); + /* refresh enable */ write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) | 8); FOR_ALL_POPULATED_CHANNELS { @@ -2465,6 +2591,7 @@ static void write_training(ramctr_timing * ctrl) read32(DEFAULT_MCHBAR + 0x428c + 0x400 * channel); wait_428c(channel); + /* DRAM command ZQCS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001); write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, 0x60000); @@ -2474,12 +2601,11 @@ static void write_training(ramctr_timing * ctrl) wait_428c(channel); } + /* toggle IO reset bit */ r32 = read32(DEFAULT_MCHBAR + 0x5030); write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); printram("CPE\n"); @@ -2503,6 +2629,7 @@ static void write_training(ramctr_timing * ctrl) FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); + /* measure and adjust timB timings */ adjust_high_timB(ctrl); FOR_ALL_POPULATED_CHANNELS @@ -2536,7 +2663,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); wait_428c(channel); - + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) @@ -2546,7 +2673,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) (slotrank << 24) | ctr | 0x60000); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); - + /* DRAM command WR */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16)); @@ -2555,6 +2682,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) write32(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel, 0x389abcd); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x20e42); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x4001020 | (max(ctrl->tRTP, 8) << 16)); @@ -2563,6 +2691,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) write32(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel, 0x389abcd); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x20e42); + /* DRAM command PRE */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xf1001); write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, @@ -2633,6 +2762,7 @@ static void reprogram_320c(ramctr_timing * ctrl) /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + /* DRAM command ZQCS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); @@ -2647,6 +2777,8 @@ static void reprogram_320c(ramctr_timing * ctrl) read32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel) | 0x200000); } + + /* refresh disable */ write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8); FOR_ALL_POPULATED_CHANNELS { wait_428c(channel); @@ -2654,6 +2786,7 @@ static void reprogram_320c(ramctr_timing * ctrl) /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + /* DRAM command ZQCS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); @@ -2671,12 +2804,11 @@ static void reprogram_320c(ramctr_timing * ctrl) /* mrs commands. */ dram_mrscommands(ctrl); + /* toggle IO reset bit */ r32 = read32(DEFAULT_MCHBAR + 0x5030); write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); } @@ -2754,6 +2886,9 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) return 1; } +/* Adjust CMD phase shift and try multiple command rates. + * A command rate of 2T doubles the time needed for address and + * command decode. */ static void command_training(ramctr_timing * ctrl) { int channel; @@ -2799,7 +2934,10 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, } wait_428c(channel); - + /* DRAM command MRS + * write MR3 MPR enable + * in this mode only RD and RDA are allowed + * all reads return a predefined pattern */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, (0xc01 | (ctrl->tMOD << 16))); @@ -2807,12 +2945,14 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, (slotrank << 24) | 0x360004); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x40411f4); write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x1001 | ((ctrl->CAS + 8) << 16)); @@ -2820,6 +2960,8 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + /* DRAM command MRS + * MR3 disable MPR */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, (0xc01 | (ctrl->tMOD << 16))); @@ -2857,12 +2999,11 @@ static void discover_edges(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x3400, 0); + /* toggle IO reset bit */ r32 = read32(DEFAULT_MCHBAR + 0x5030); write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); - udelay(1); FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { @@ -2890,6 +3031,11 @@ static void discover_edges(ramctr_timing * ctrl) FOR_ALL_POPULATED_RANKS { wait_428c(channel); + /* DRAM command MRS + * MR3 enable MPR + * write MR3 MPR enable + * in this mode only RD and RDA are allowed + * all reads return a predefined pattern */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, @@ -2898,6 +3044,7 @@ static void discover_edges(ramctr_timing * ctrl) (slotrank << 24) | 0x360004); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, @@ -2906,6 +3053,7 @@ static void discover_edges(ramctr_timing * ctrl) (slotrank << 24) | 0); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, @@ -2914,6 +3062,8 @@ static void discover_edges(ramctr_timing * ctrl) (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + /* DRAM command MRS + * MR3 disable MPR */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, @@ -2927,6 +3077,8 @@ static void discover_edges(ramctr_timing * ctrl) wait_428c(channel); } + /* XXX: check any measured value ? */ + FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = 48; @@ -2939,6 +3091,11 @@ static void discover_edges(ramctr_timing * ctrl) FOR_ALL_POPULATED_RANKS { wait_428c(channel); + /* DRAM command MRS + * MR3 enable MPR + * write MR3 MPR enable + * in this mode only RD and RDA are allowed + * all reads return a predefined pattern */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, @@ -2947,6 +3104,7 @@ static void discover_edges(ramctr_timing * ctrl) (slotrank << 24) | 0x360004); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, @@ -2955,6 +3113,7 @@ static void discover_edges(ramctr_timing * ctrl) (slotrank << 24) | 0); write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, @@ -2963,6 +3122,8 @@ static void discover_edges(ramctr_timing * ctrl) (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + /* DRAM command MRS + * MR3 disable MPR */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, @@ -2976,6 +3137,8 @@ static void discover_edges(ramctr_timing * ctrl) wait_428c(channel); } + /* XXX: check any measured value ? */ + FOR_ALL_LANES { write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + lane * 4, @@ -3065,6 +3228,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, } wait_428c(channel); + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, @@ -3076,6 +3240,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); + /* DRAM command WR */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, @@ -3086,6 +3251,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x242); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, @@ -3095,6 +3261,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); + /* DRAM command PRE */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, @@ -3183,6 +3350,7 @@ static void discover_edges_write(ramctr_timing * ctrl) static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) { wait_428c(channel); + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) @@ -3191,6 +3359,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) (slotrank << 24) | 0x60000); write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); + /* DRAM command WR */ write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x80011e0 | @@ -3200,6 +3369,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x242); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); write32(DEFAULT_MCHBAR + 0x4238 + @@ -3210,6 +3380,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); + /* DRAM command PRE */ write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); write32(DEFAULT_MCHBAR + 0x423c + @@ -3371,21 +3542,25 @@ static void channel_test(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + (0x4d40 + 4 * lane), 0); } wait_428c(channel); + /* DRAM command ACT */ write32(DEFAULT_MCHBAR + 0x4220 + (channel << 10), 0x0001f006); write32(DEFAULT_MCHBAR + 0x4230 + (channel << 10), 0x0028a004); write32(DEFAULT_MCHBAR + 0x4200 + (channel << 10), 0x00060000 | (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4210 + (channel << 10), 0x00000244); + /* DRAM command WR */ write32(DEFAULT_MCHBAR + 0x4224 + (channel << 10), 0x0001f201); write32(DEFAULT_MCHBAR + 0x4234 + (channel << 10), 0x08281064); write32(DEFAULT_MCHBAR + 0x4204 + (channel << 10), 0x00000000 | (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4214 + (channel << 10), 0x00000242); + /* DRAM command RD */ write32(DEFAULT_MCHBAR + 0x4228 + (channel << 10), 0x0001f105); write32(DEFAULT_MCHBAR + 0x4238 + (channel << 10), 0x04281064); write32(DEFAULT_MCHBAR + 0x4208 + (channel << 10), 0x00000000 | (slotrank << 24)); write32(DEFAULT_MCHBAR + 0x4218 + (channel << 10), 0x00000242); + /* DRAM command PRE */ write32(DEFAULT_MCHBAR + 0x422c + (channel << 10), 0x0001f002); write32(DEFAULT_MCHBAR + 0x423c + (channel << 10), 0x00280c01); write32(DEFAULT_MCHBAR + 0x420c + (channel << 10),

1 0

New patch to review for coreboot: intel/fsp_model_406dx: Load APs microcode in model_406dx_init
by David Guckian 14 Nov '15

14 Nov '15

David Guckian (david.guckian(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12436 -gerrit commit a941e22e6d80945daaf22572e426e4efb06a927f Author: David Guckian <david.guckian(a)intel.com> Date: Sat Nov 14 16:01:33 2015 +0000 intel/fsp_model_406dx: Load APs microcode in model_406dx_init Load microcode to APs when performing model_406dx_init. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e Signed-off-by: David Guckian <david.guckian(a)intel.com> --- src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index b25c997..5482e74 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -22,6 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include "model_406dx.h" @@ -168,6 +169,9 @@ static void model_406dx_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); + /* Load microcode */ + intel_update_microcode_from_cbfs(); + /* Clear out pending MCEs */ configure_mca();

1 0

Patch set updated for coreboot: nb/intel/sandybridge: start PEG link training
by Patrick Rudolph 14 Nov '15

14 Nov '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11917 -gerrit commit bdede31d2726294d08c64d4df761683c0fd55bf9 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Oct 15 11:09:15 2015 +0200 nb/intel/sandybridge: start PEG link training Issue observed: The PCIe Root port shows up in GNU/Linux but no device. Test system: * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130) * Lenovo T530 (Intel Core i5-3320M CPU) Problem description: The PEG Root port link training on Ivy Bridge needs to be started by hand. (The PEG Root port on Sandy Bridge works out of the box.) Problem solution: The bits are set in early_init to meet PCIe reset timeout of 100msec. The bits should be set in PCI device enable function, but this causes the PCI enumeration to not detect the card, as it's still booting. Adding a fixed delay of 100msec resolves this problem, but this would increase boot time. Tested with: * Nvidia NVS 5400M (PCIe2) * ATI Radeon HD4780 (PCIe2) * Nvidia GeForce 8600 GT (PCIe1) Untested: * PCIe3 devices Final test results: The PEG device shows up under GNU/Linux and can be used without issues. Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/early_init.c | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b3a829d..7e5ace6 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -148,6 +148,39 @@ static void sandybridge_setup_graphics(void) MCHBAR32(0x5418) = reg32; } +static void start_peg_link_training(void) +{ + u32 tmp; + u32 deven; + + /* skip on SandyBridge */ + if ((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) & + BASE_REV_MASK) != BASE_REV_IVB) + return; + + deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + + if (deven & DEVEN_PEG10) { + tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG11) { + tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG12) { + tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG60) { + tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5)); + } +} + void sandybridge_early_initialization(int chipset_type) { u32 capid0_a; @@ -174,6 +207,15 @@ void sandybridge_early_initialization(int chipset_type) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); sandybridge_setup_graphics(); + + /* Write magic value to start PEG link training. + * This should be done in PCI device enumeration, but + * the PCIe specification requires to wait at least 100msec + * after reset for devices to come up. + * As we don't want to increase boot time, enable it early and + * assume the PEG is up as soon as PCI enumeration starts. + * TODO: use time stamps to ensure the timings are met */ + start_peg_link_training(); } void northbridge_romstage_finalize(int s3resume)

1 0

Patch set updated for coreboot: fsp1_0: Update rangeley to revision POSTGOLD4
by Marcin Wojciechowski 14 Nov '15

14 Nov '15

Marcin Wojciechowski (marcin.wojciechowski(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12418 -gerrit commit d9d6973948e1a736d96ad9de7ffa078b93d28de2 Author: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> Date: Thu Nov 12 16:05:42 2015 +0100 fsp1_0: Update rangeley to revision POSTGOLD4 Alignment of Intel Firmware Support Package 1.0 Rangeley header and source files to the revision: POSTGOLD4 Detail changelog can be found at http://www.intel.com/fsp FSP release date September 24, 2015 Change-Id: If1a6f95aed3e9a60af9af8cf9cd466a560ef0fe2 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> --- .../intel/fsp1_0/rangeley/include/fspguid.h | 69 +++++ .../intel/fsp1_0/rangeley/include/fspplatform.h | 3 +- .../intel/fsp1_0/rangeley/include/fspsupport.h | 95 +++++++ .../intel/fsp1_0/rangeley/include/fsptypes.h | 7 +- .../intel/fsp1_0/rangeley/include/fspvpd.h | 12 +- .../intel/fsp1_0/rangeley/srx/fsp_support.c | 288 +++++++++++++++++++++ 6 files changed, 467 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h new file mode 100644 index 0000000..b9a6183 --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h @@ -0,0 +1,69 @@ +/** @file + +Copyright (C) 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_GUID_H__ +#define __FSP_GUID_H__ + +/** + + FSP specific GUID HOB definitions + + **/ +#define FSP_INFO_HEADER_GUID \ + { \ + 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ + } + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + { \ + 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ + } + +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ + { \ + 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ + { \ + 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ + { \ + 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \ + } + +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ + { \ + 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ + } + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h index ce479bf..c35dca0 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013 - 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -74,6 +74,7 @@ typedef struct { UINT8 tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) UINT8 UpperNibbleFortFAW; // 28 Upper Nibble for tFAW UINT8 tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin) + UINT8 SdramThermalRefreshOption; // 31 SdramThermalRefreshOption UINT8 ModuleThermalSensor; // 32 ModuleThermalSensor UINT8 SDRAMDeviceType; // 33 SDRAM Device Type UINT8 tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h new file mode 100644 index 0000000..dbbbf77 --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h @@ -0,0 +1,95 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include "fsptypes.h" +#include "fspfv.h" +#include "fspffs.h" +#include "fspapi.h" +#include "fsphob.h" +#include "fspguid.h" +#include "fspplatform.h" +#include "fspinfoheader.h" +#include "fspbootmode.h" +#include "fspvpd.h" + +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobListPtr + ); + +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobListPtr + ); + +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid + ); + +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *FspMemoryBase, + UINT64 *FspMemoryLength, + EFI_GUID *FspReservedMemoryGuid + ); + +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +VOID* +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h index 5912e01..da19250 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h @@ -100,13 +100,18 @@ typedef struct { #define TRUE ((BOOLEAN)(1==1)) #define FALSE ((BOOLEAN)(0==1)) +static inline void DebugDeadLoop(void) { + for (;;); +} + #define FSPAPI __attribute__((cdecl)) #define EFIAPI __attribute__((cdecl)) +#define _ASSERT(Expression) DebugDeadLoop() #define ASSERT(Expression) \ do { \ if (!(Expression)) { \ - for (;;); \ + _ASSERT (Expression); \ } \ } while (FALSE) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h index fba38a0..4ba1a28 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013-2014 Intel Corporation +Copyright (C) 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -50,7 +50,8 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdSpdBaseAddress_0_1; /* Offset 0x0026 */ UINT8 PcdSpdBaseAddress_1_0; /* Offset 0x0027 */ UINT8 PcdSpdBaseAddress_1_1; /* Offset 0x0028 */ - UINT8 UnusedUpdSpace1[7]; /* Offset 0x0029 */ + UINT8 PcdExtendedTemperatureEnable; /* Offset 0x0029 */ + UINT8 UnusedUpdSpace1[6]; /* Offset 0x002A */ UINT8 PcdEnableLan; /* Offset 0x0030 */ UINT8 PcdEnableSata2; /* Offset 0x0031 */ UINT8 PcdEnableSata3; /* Offset 0x0032 */ @@ -65,13 +66,14 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT8 PcdSerialPortBaudRate; /* Offset 0x0043 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0044 */ + UINT8 UnusedUpdSpace3[12]; /* Offset 0x0064 */ UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000102 +#define VPD_IMAGE_REV 0x00000140 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */ diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c new file mode 100644 index 0000000..9f15b3e --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c @@ -0,0 +1,288 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#include <types.h> +#include <string.h> +#include "fspsupport.h" + +/** + This function retrieves the top of usable low memory. + + @param HobListPtr A HOB list pointer. + + @retval Usable low memory top. + +**/ +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobStart +) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT32 MemLen; + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobStart; + + /* + * Collect memory ranges + */ + MemLen = 0x100000; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + /* + * Need memory above 1MB to be collected here + */ + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 && + Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) { + MemLen += (UINT32) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return MemLen; +} + +/** + This function retrieves the top of usable high memory. + + @param HobListPtr A HOB list pointer. + + @retval Usable high memory top. + +**/ +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobStart +) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT64 MemTop; + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobStart; + + /* + * Collect memory ranges + */ + MemTop = 0x100000000; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + /* + * Need memory above 1MB to be collected here + */ + if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) { + MemTop += (UINT32) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return MemTop; +} + +/** + This function retrieves a special reserved memory region. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the GUID HOB data buffer length. If the GUID HOB is + located, the length will be updated. + @param OwnerGuid A pointer to the owner guild. + @retval Reserved region start address. 0 if this region does not exist. + +**/ +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *Base, + UINT64 *Length, + EFI_GUID *OwnerGuid +) +{ + EFI_PEI_HOB_POINTERS Hob; + + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobListPtr; + + /* + * Collect memory ranges + */ + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) { + if (CompareGuid(&Hob.ResourceDescriptor->Owner, OwnerGuid)) { + *Base = (EFI_PHYSICAL_ADDRESS) (Hob.ResourceDescriptor->PhysicalStart); + *Length = (UINT64) (Hob.ResourceDescriptor->ResourceLength); + break; + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } +} + +/** + This function retrieves the TSEG reserved normal memory. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the TSEG reserved memory length buffer. If the GUID HOB is + located, the length will be updated. + @param Guid A pointer to owner HOB GUID. + @retval NULL Failed to find the TSEG reserved memory. + @retval others TSEG reserved memory base. + +**/ +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID TsegOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; + UINT64 Length64 = 0; + EFI_PHYSICAL_ADDRESS Base = 0; + + GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&TsegOwnerHobGuid); + if ((Length != NULL) && (Base != 0)) { + *Length = (UINT32)Length64; + } + return (UINT32)Base; +} + +/** + This function retrieves the FSP reserved normal memory. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the FSP reserved memory length buffer. If the GUID HOB is + located, the length will be updated. + @param Guid A pointer to owner HOB GUID. + @retval NULL Failed to find the FSP reserved memory. + @retval others FSP reserved memory base. + +**/ +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + UINT64 Length64 = 0; + EFI_PHYSICAL_ADDRESS Base = 0; + + GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&FspOwnerHobGuid); + if ((Length != NULL) && (Base != 0)) { + *Length = (UINT32)Length64; + } + return (UINT32)Base; +} + + +/** + This function retrieves a GUIDed HOB data buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the GUID HOB data buffer length. If the + GUID HOB is located, the length will be updated. + @param Guid A pointer to HOB GUID. + @retval NULL Failed to find the GUID HOB. + @retval others GUID HOB data buffer pointer. + +**/ +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid +) +{ + UINT8 *GuidHob; + + /* FSP NVS DATA HOB */ + GuidHob = GetNextGuidHob(Guid, HobListPtr); + if (GuidHob == NULL) { + return NULL; + } else { + if (Length) { + *Length = GET_GUID_HOB_DATA_SIZE (GuidHob); + } + return GET_GUID_HOB_DATA (GuidHob); + } +} + +/** + This function retrieves FSP Non-volatile Storage HOB buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the NVS data buffer length. If the FSP NVS + HOB is located, the length will be updated. + @retval NULL Failed to find the NVS HOB. + @retval others FSP NVS data buffer pointer. + +**/ +VOID * +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspNvsHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspNvsHobGuid); +} + + +/** + This function retrieves Bootloader temporary stack buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the Bootloader temporary stack length. + If the HOB is located, the length will be updated. + @retval NULL Failed to find the Bootloader temporary stack HOB. + @retval others Bootloader temporary stackbuffer pointer. + +**/ +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; + return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspBootloaderTemporaryMemoryHobGuid); +}

1 0

Patch set updated for coreboot: AMD Hudson: Use amdfwtool to integrate firmwares.
by Zheng Bao 14 Nov '15

14 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12435 -gerrit commit be0a85d1a4188bff51ecf317d5b80cefc5635507 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Nov 13 12:03:47 2015 +0800 AMD Hudson: Use amdfwtool to integrate firmwares. Change-Id: Ie17a744b6ef4e5405b3dfcecc1deb6462220ec60 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 102 ++----- src/southbridge/amd/pi/hudson/Makefile.inc | 382 +++++--------------------- 2 files changed, 96 insertions(+), 388 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 9e42cf2..e638c39 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -39,84 +39,6 @@ HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-m HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) -#assume the cbfs header is less than 128 bytes. -ROMSIG_SIZE=16 -ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -HUDSON_XHCI_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128) -XHCI_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_XHCI_FWM_FILE)) -else -HUDSON_XHCI_POSITION=0 -XHCI_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -HUDSON_GEC_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128) -GEC_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_GEC_FWM_FILE)) -else -HUDSON_GEC_POSITION=0 -GEC_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_IMC_POSITION=$(call int-align,\ - $(call int-add,\ - $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE)\ - 128 $(GEC_FWM_SIZE) 128),\ - 65536) -else -HUDSON_IMC_POSITION=0 -endif - -$(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(obj)/config.h - echo " Hudson FW $@" - for fwm in 1437226410 \ - $(HUDSON_IMC_POSITION) \ - $(HUDSON_GEC_POSITION) \ - $(HUDSON_XHCI_POSITION) ; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $@ - -ifeq ($(CONFIG_HUDSON_FWM), y) -ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) -endif -ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) -endif -cbfs-files-y += hudson/fwm -hudson/fwm-file := $(obj)/coreboot_hudson_romsig.bin -hudson/fwm-position := $(HUDSON_FWM_POSITION) -hudson/fwm-type := raw -endif - -ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -cbfs-files-y += hudson/xhci -hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) -hudson/xhci-position := $(HUDSON_XHCI_POSITION) -hudson/xhci-type := raw -hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled) -endif - -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -cbfs-files-y += hudson/imc -hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) -hudson/imc-position := $(HUDSON_IMC_POSITION) -hudson/imc-type := raw -hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled) -endif - -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -cbfs-files-y += hudson/gec -hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) -hudson/gec-position := $(HUDSON_GEC_POSITION) -hudson/gec-type := raw -hudson/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) -endif - ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) cbfs-files-y += pci$(stripped_ahci_rom_id).rom @@ -124,3 +46,27 @@ pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FIL pci$(stripped_ahci_rom_id).rom-type := optionrom pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative) endif + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) +OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) +OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec) + +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ + $(AMDFWTOOL) + rm -f $@ + echo " AMDFWTOOL $@" + $(AMDFWTOOL) \ + $(OPT_HUDSON_XHCI_FWM_FILE) \ + $(OPT_HUDSON_IMC_FWM_FILE) \ + $(OPT_HUDSON_GEC_FWM_FILE) \ + --output $@ + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(HUDSON_FWM_POSITION) +apu/amdfw-type := raw + diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..6d86bf1 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -66,371 +66,133 @@ HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-m HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) -CBFS_HEADER_SIZE=0x60 - -#assume the cbfs header is less than $(CBFS_HEADER_SIZE) bytes. -ROMSIG_SIZE=4096 -ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -HUDSON_XHCI_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE)) -XHCI_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_XHCI_FWM_FILE)) -else -HUDSON_XHCI_POSITION=0 -XHCI_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -HUDSON_GEC_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) \ - $(XHCI_FWM_SIZE) $(CBFS_HEADER_SIZE)) -GEC_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_GEC_FWM_FILE)) -else -HUDSON_GEC_POSITION=0 -GEC_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_IMC_POSITION=$(call int-align,\ - $(call int-add,\ - $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ - $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ - 65536) -IMC_FWM_SIZE=$(call file-size,$(CONFIG_HUDSON_IMC_FWM_FILE)) -else -HUDSON_IMC_POSITION=0 -IMC_FWM_SIZE=0 -endif - -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ - $(call int-add,\ - $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ - $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ - 65536) -HUDSON_PSP_DIRECTORY_SIZE=256 -else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_PSP_OFFSET=131072 -else -HUDSON_PSP_OFFSET=0 -endif -HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ - $(call int-add,\ - $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ - $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(HUDSON_PSP_OFFSET)),\ - 65536) -HUDSON_PSP_DIRECTORY_SIZE=256 -else -HUDSON_PSP_DIRECTORY_POSITION=0 -HUDSON_PSP_DIRECTORY_SIZE=0 -endif - -$(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(obj)/config.h - echo " Hudson FW $@" - printf %d $(ROMSIG_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@; \ - for fwm in 1437226410 \ - $(HUDSON_IMC_POSITION) \ - $(HUDSON_GEC_POSITION) \ - $(HUDSON_XHCI_POSITION) \ - $(HUDSON_PSP_DIRECTORY_POSITION); do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $@.tmp; \ - dd if=$@.tmp of=$@ conv=notrunc status=noxfer 2>/dev/null; \ - rm $@.tmp - -ifeq ($(CONFIG_HUDSON_FWM), y) -ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) -endif -ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) -endif -cbfs-files-y += fch/fwm -fch/fwm-file := $(obj)/coreboot_hudson_romsig.bin -fch/fwm-position := $(HUDSON_FWM_POSITION) -fch/fwm-size := $(ROMSIZE_SIG) -fch/fwm-type := raw -endif - -ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -cbfs-files-y += fch/xhci -fch/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) -fch/xhci-position := $(HUDSON_XHCI_POSITION) -fch/xhci-type := raw -fch/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled) -endif - -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -cbfs-files-y += fch/imc -fch/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) -fch/imc-position := $(HUDSON_IMC_POSITION) -fch/imc-type := raw -fch/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled) -endif - -ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -cbfs-files-y += fch/gec -fch/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) -fch/gec-position := $(HUDSON_GEC_POSITION) -fch/gec-type := raw -fch/gec-required := Hudson Gigabit Ethernet Controller Firmware (Contact your AMD representative) -endif - -ifdef CONFIG_HUDSON_AHCI_ROM -stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) -cbfs-files-y += pci$(stripped_ahci_rom_id).rom -pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) -pci$(stripped_ahci_rom_id).rom-type := optionrom -pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative) -endif - +## ifeq ($(CONFIG_HUDSON_PSP), y) +## +### 0 -# 0 -# catenate the pubkey and pspdir together to save some space. -AMDPUBKEY_POS=$(call int-add,$(HUDSON_PSP_DIRECTORY_POSITION) $(HUDSON_PSP_DIRECTORY_SIZE)) -AMDPUBKEY_SIZE=$(call file-size,$(CONFIG_AMD_PUBKEY_FILE)) - +## ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE= endif - +## ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ endif -#5 +###5 CONFIG_PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -PUBSIGNEDKEY_POS=$(call int-align, \ - $(call int-add,$(AMDPUBKEY_POS) $(AMDPUBKEY_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PUBSIGNEDKEY_SIZE=$(call file-size,$(CONFIG_PUBSIGNEDKEY_FILE)) - -#1 +###1 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader$(FIRMWARE_TYPE).Bypass.sbin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin endif -PSPBTLDR_POS=$(call int-align, \ - $(call int-add,$(PUBSIGNEDKEY_POS) $(PUBSIGNEDKEY_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPBTLDR_SIZE=$(call file-size,$(CONFIG_PSPBTLDR_FILE)) -#3 +###3 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery$(FIRMWARE_TYPE).sbin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin endif -PSPRCVR_POS=$(call int-align, \ - $(call int-add,$(PSPBTLDR_POS) $(PSPBTLDR_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPRCVR_SIZE=$(call file-size,$(CONFIG_PSPRCVR_FILE)) -#2 +###2 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs$(FIRMWARE_TYPE).sbin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin endif -PSPSECUREOS_POS=$(call int-align, \ - $(call int-add,$(PSPRCVR_POS) $(PSPRCVR_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPSECUREOS_SIZE=$(call file-size,$(CONFIG_PSPSCUREOS_FILE)) -#4 +###4 CONFIG_PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -PSPNVRAM_POS=$(call int-align, \ - $(call int-add,$(PSPSECUREOS_POS) $(PSPSECUREOS_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPNVRAM_SIZE=$(call file-size,$(CONFIG_PSPNVRAM_FILE)) -#8 +###8 CONFIG_SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_POS=$(call int-align, \ - $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -SMUFWM_SIZE=$(call file-size,$(CONFIG_SMUFWM_FILE)) -#95 +###95 CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin -SMUSCS_POS=$(call int-align, \ - $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -SMUSCS_SIZE=$(call file-size,$(CONFIG_SMUSCS_FILE)) -#9 +###9 CONFIG_PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key -PSPSECUREDEBUG_POS=$(call int-align, \ - $(call int-add,$(SMUSCS_POS) $(SMUSCS_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPSECUREDEBUG_SIZE=$(call file-size,$(CONFIG_PSPSECUREDEBUG_FILE)) -#12 +###12 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin endif -PSPTRUSTLETS_POS=$(call int-align, \ - $(call int-add,$(PSPSECUREDEBUG_POS) $(PSPSECUREDEBUG_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -PSPTRUSTLETS_SIZE=$(call file-size,$(CONFIG_PSPTRUSTLETS_FILE)) -#13 +###13 ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin endif -TRUSTLETKEY_POS=$(call int-align, \ - $(call int-add,$(PSPTRUSTLETS_POS) $(PSPTRUSTLETS_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -TRUSTLETKEY_SIZE=$(call file-size,$(CONFIG_TRUSTLETKEY_FILE)) -#18 +###18 ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -SMUFIRMWARE2_POS=$(call int-align, \ - $(call int-add,$(TRUSTLETKEY_POS) $(TRUSTLETKEY_SIZE) $(CBFS_HEADER_SIZE)), \ - $(CBFS_HEADER_SIZE)) -SMUFIRMWARE2_SIZE=$(call file-size,$(CONFIG_SMUFIRMWARE2_FILE)) endif -define output_hex -echo $(1) | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}' -endef - -$(obj)/coreboot_psp_directory.bin: $(obj)/config.h $(FLETCHER) $(RTM_FILE) - echo " PSPDir $@" - for fwm in 0 $(AMDPUBKEY_SIZE) $(AMDPUBKEY_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $(a)_tail.tmp - for fwm in 1 $(PSPBTLDR_SIZE) $(PSPBTLDR_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 8 $(SMUFWM_SIZE) $(SMUFWM_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 3 $(PSPRCVR_SIZE) $(PSPRCVR_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 5 $(PUBSIGNEDKEY_SIZE) $(PUBSIGNEDKEY_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 2 $(PSPSECUREOS_SIZE) $(PSPSECUREOS_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 4 $(PSPNVRAM_SIZE) $(PSPNVRAM_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 9 $(PSPSECUREDEBUG_SIZE) $(PSPSECUREDEBUG_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 12 $(PSPTRUSTLETS_SIZE) $(PSPTRUSTLETS_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 13 $(TRUSTLETKEY_SIZE) $(TRUSTLETKEY_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) - for fwm in 18 $(SMUFIRMWARE2_SIZE) $(SMUFIRMWARE2_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp endif - for fwm in 95 $(SMUSCS_SIZE) $(SMUSCS_POS) 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 11 4294967295 1 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done >> $(a)_tail.tmp - for fwm in 1347637284 0 `ls -ln $(a)_tail.tmp | awk '{printf("%d", $$5/16);}'` 0; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $(a)_head.tmp - cat $(a)_head.tmp $(a)_tail.tmp > $@.tmp - $(FLETCHER) < $@.tmp > $@ - rm $(a)_head.tmp $(a)_tail.tmp $@.tmp - -$(obj)/coreboot_psp_directory_combine_pubkey.bin: $(obj)/coreboot_psp_directory.bin - cat $(obj)/coreboot_psp_directory.bin > $@ - ls -ln $(obj)/coreboot_psp_directory.bin | LC_ALL=C awk '{for (i=0; i<256-$$5; i++) {printf "%c", 255}}' >> $@ - cat $(top)/$(FIRMWARE_LOCATE)/AmdPubKey$(FIRMWARE_TYPE).bin >> $@ - -cbfs-files-y += apu/pspdir -apu/pspdir-file := $(obj)/coreboot_psp_directory_combine_pubkey.bin -apu/pspdir-position := $(HUDSON_PSP_DIRECTORY_POSITION) -apu/pspdir-type := raw - -# 5 -cbfs-files-y += apu/pubsignedkey -apu/pubsignedkey-file := $(CONFIG_PUBSIGNEDKEY_FILE) -apu/pubsignedkey-position := $(PUBSIGNEDKEY_POS) -apu/pubsignedkey-type := raw - -# 1 -cbfs-files-y += apu/pspbtldr -apu/pspbtldr-file := $(CONFIG_PSPBTLDR_FILE) -apu/pspbtldr-position := $(PSPBTLDR_POS) -apu/pspbtldr-type := raw -#3 -cbfs-files-y += apu/psprcvr -apu/psprcvr-file := $(CONFIG_PSPRCVR_FILE) -apu/psprcvr-position := $(PSPRCVR_POS) -apu/psprcvr-type := raw +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -# 2 -cbfs-files-y += apu/pspsecureos -apu/pspsecureos-file := $(CONFIG_PSPSCUREOS_FILE) -apu/pspsecureos-position := $(PSPSECUREOS_POS) -apu/pspsecureos-type := raw +OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) +OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) +OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec) +OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) +OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_PSPBTLDR_FILE), --bootloader) +OPT_SMUFWM_FILE=$(call add_opt_prefix, $(CONFIG_SMUFWM_FILE), --smufirmware) +OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(CONFIG_PSPRCVR_FILE), --recovery) +OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(CONFIG_PUBSIGNEDKEY_FILE), --rtmpubkey) +OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(CONFIG_PSPSCUREOS_FILE), --secureos) +OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(CONFIG_PSPNVRAM_FILE), --nvram) +OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(CONFIG_PSPSECUREDEBUG_FILE), --securedebug) +OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(CONFIG_PSPTRUSTLETS_FILE), --trustlets) +OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_TRUSTLETKEY_FILE), --trustletkey) +OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_SMUFIRMWARE2_FILE), --smufirmware2) +OPT_SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_SMUSCS_FILE), --smuscs) -# 4 -cbfs-files-y += apu/pspnvram -apu/pspnvram-file := $(CONFIG_PSPNVRAM_FILE) -apu/pspnvram-position := $(PSPNVRAM_POS) -apu/pspnvram-type := raw - -#8 -cbfs-files-y += apu/smufwm -apu/smufwm-file := $(CONFIG_SMUFWM_FILE) -apu/smufwm-position := $(SMUFWM_POS) -apu/smufwm-type := raw - -#95 -cbfs-files-y += apu/smuscs -apu/smuscs-file := $(CONFIG_SMUSCS_FILE) -apu/smuscs-position := $(SMUSCS_POS) -apu/smuscs-type := raw - -#9 -cbfs-files-y += apu/pspsecuredebug -apu/pspsecuredebug-file := $(CONFIG_PSPSECUREDEBUG_FILE) -apu/pspsecuredebug-position := $(PSPSECUREDEBUG_POS) -apu/pspsecuredebug-type := raw - -#12 -cbfs-files-y += apu/psptrustlets -apu/psptrustlets-file := $(CONFIG_PSPTRUSTLETS_FILE) -apu/psptrustlets-position := $(PSPTRUSTLETS_POS) -apu/psptrustlets-type := raw - -#13 -cbfs-files-y += apu/trustletkey -apu/trustletkey-file := $(CONFIG_TRUSTLETKEY_FILE) -apu/trustletkey-position := $(TRUSTLETKEY_POS) -apu/trustletkey-type := raw - -#18 -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -cbfs-files-y += apu/smufirmware2 -apu/smufirmware2-file := $(CONFIG_SMUFIRMWARE2_FILE) -apu/smufirmware2-position := $(SMUFIRMWARE2_POS) -apu/smufirmware2-type := raw -endif - -endif +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_PUBSIGNEDKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPBTLDR_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPRCVR_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPSCUREOS_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPNVRAM_FILE)) \ + $(call strip_quotes, $(CONFIG_SMUFWM_FILE)) \ + $(call strip_quotes, $(CONFIG_SMUSCS_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(CONFIG_PSPTRUSTLETS_FILE)) \ + $(call strip_quotes, $(CONFIG_TRUSTLETKEY_FILE)) \ + $(call strip_quotes, $(CONFIG_SMUFIRMWARE2_FILE)) \ + $(AMDFWTOOL) + rm -f $@ + echo " AMDFWTOOL $@" + $(AMDFWTOOL) \ + $(OPT_HUDSON_XHCI_FWM_FILE) \ + $(OPT_HUDSON_IMC_FWM_FILE) \ + $(OPT_HUDSON_GEC_FWM_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUSCS_FILE) \ + --output $@ + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(HUDSON_FWM_POSITION) +apu/amdfw-type := raw

1 0

Patch set updated for coreboot: Makefile: Set HOSTCC as gcc or cc respectively
by Zheng Bao 14 Nov '15

14 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12331 -gerrit commit 2cb9277c94d003c579c68bc7cadc4ae4c4f598be Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 15:33:33 2015 +0800 Makefile: Set HOSTCC as gcc or cc respectively The HOSTCC should be set in .xcompile, which tests the existence of gcc and cc. But the .xcompile has to be included after kconfig/Makefile. So building util/kconfig uses the seperated HOSTCC definition above it, instead of the one in .xcompile. For the system which clang is the default host compiler, gcc is not installed by default. In that case, we need to set HOSTCC as cc. Change-Id: I1e51a37c4426e2c97d36a31f26a18ab4b0d0608d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 421e919..d108654 100644 --- a/Makefile +++ b/Makefile @@ -79,7 +79,7 @@ endif # Disable implicit/built-in rules to make Makefile errors fail fast. .SUFFIXES: -HOSTCC := gcc +HOSTCC := $(if $(shell type gcc 2>/dev/null), gcc, cc) HOSTCXX = g++ HOSTCFLAGS := -g HOSTCXXFLAGS := -g

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coreboot-gerrit November 2015