coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values
by gerrit＠coreboot.org 15 Nov '15

15 Nov '15

the following patch was just integrated into master: commit f3aa375f44531ca4a504186d76e69b6d07dc4ae7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 26 14:15:57 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values The existing code did not set Rtt timing parameters when registered DIMMs were used with Family 15h processors. Set the Rtt values according to the BKDG recommendations. Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12010 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12010 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs
by gerrit＠coreboot.org 15 Nov '15

15 Nov '15

the following patch was just integrated into master: commit b7a8b8c6fb4a8b76942e1d8d1885c6f817376b65 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 26 12:17:48 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs Change-Id: Iaf826b6a0c8e929372519f6d97933515a80f0b39 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12009 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12009 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
by gerrit＠coreboot.org 15 Nov '15

15 Nov '15

the following patch was just integrated into master: commit 11739a48ce08d1ef11bfd54670ec23a1ee6daccd Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 18:37:45 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue AMD Opteron processors contain a very fragile phy phase detection circuit. Additionally, the algorithm given in the BKDG does not function as intended; this was verified both on real hardware via execution trace and on paper with values read back from multiple CPUs and DIMMs. As a result, the phy training algorithm given in the BKDG has been replaced with a phy training algorithm developed at Raptor Engineering. This particular patch is the first part of that algorithm; the code is updated in future patches but this should exist in the historical record in case something breaks down in the later sections of code. Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12007 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12007 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors
by gerrit＠coreboot.org 15 Nov '15

15 Nov '15

the following patch was just integrated into master: commit 9426e4fcf5f49c46fa1e5cbe9fc38d2575cfdb62 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 18:08:53 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors AMD's automatic phy phase detection hardware is very fragile and often produces incorrect results. Attempt to recover from obvious phase locking errors by retrying phy training on the failing link. Change-Id: Ia2c3022534c9ad44714eef6e118869f054bd9f6b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12006 for details. -gerrit

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Patch merged into coreboot/master: amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values
by gerrit＠coreboot.org 15 Nov '15

15 Nov '15

the following patch was just integrated into master: commit 5288cedac1a3f92876990c5693bda0db11debc0c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 17:07:57 2015 -0500 amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values The existing MCT code did not properly set up the On Die Termination (ODT) or timing values for registered DIMMs. Use the BKDG recommended values when registered DIMMs are installed. Change-Id: Ia9ee770d9f9c22e18c12e38b5bb4a7bae0a99062 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12005 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12005 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd: Fix AMD Family 15h ECC initialization reliability issues
by gerrit＠coreboot.org 15 Nov '15

15 Nov '15

the following patch was just integrated into master: commit 38508a0ff1b0bcdadc779ae8a8a422638d4612d9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 15:07:34 2015 -0500 cpu/amd: Fix AMD Family 15h ECC initialization reliability issues There were numerous issues surrounding AMD ECC initialization on Family 15h processors due to the incomplete derivation from Family 10h MCT code. Bring the Family 15h ECC initialization and supporting setup code in line with the BKDG recommendations. Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12003 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12003 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init
by gerrit＠coreboot.org 15 Nov '15

15 Nov '15

the following patch was just integrated into master: commit eb2f6fff3265b5be87e2dfc9e69ad465c742ec8c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 24 19:15:09 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init The existing ECC initialization algorithm contained several bugs on both Family 10h and Family 15h processors, including activation of ECC scrub before DRAM setup was completed, in violation of both BKDG and errata recommendations. Change-Id: I09a8ea83024186b7ece7d78a4bef1201ab34ff8a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12002 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12002 for details. -gerrit

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Patch set updated for coreboot: src/southbridge/amd/sr5650: Always configure lane director on startup
by Timothy Pearson 15 Nov '15

15 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12014 -gerrit commit daed610c48b0720ec8b5b2afb719b3247675708d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jul 3 17:16:22 2015 -0500 src/southbridge/amd/sr5650: Always configure lane director on startup On the ASUS KGPE-D16 it was noted that the pin straps did not properly configure the lane director hardware, causing link training failure on NIC B. Forcing coreboot to always reconfigure the lane director on startup resolves this problem. Change-Id: I5b78cef84960e0f42cc3e0406a7031d12d21f3ad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/pcie.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 9114c81..4161c18 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -858,8 +858,6 @@ void sr56x0_lock_hwinitreg(void) void config_gpp_core(device_t nb_dev, device_t sb_dev) { u32 reg; - struct southbridge_amd_sr5650_config *cfg = - (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; reg = nbmisc_read_index(nb_dev, 0x20); if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP) @@ -875,14 +873,9 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev) reg &= ~((1 << 31) | (1 << 15) | (1 << 13)); //De-asserts nbmisc_write_index(nb_dev, 0x8, reg); - reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG at bit 0-4 */ - if (cfg->gpp3a_configuration != (reg & 0x1F)) - switching_gpp3a_configurations(nb_dev, sb_dev); - reg = nbmisc_read_index(nb_dev, 0x8); /* get MULTIPORT_CONFIG_GPP1 MULTIPORT_CONFIG_CONFIG_GPP2 at bit 8,9 */ - if ((cfg->gpp1_configuration << 8) != (reg & (1 << 8))) - switching_gpp1_configurations(nb_dev, sb_dev); - if ((cfg->gpp2_configuration << 9) != (reg & (1 << 9))) - switching_gpp2_configurations(nb_dev, sb_dev); + switching_gpp3a_configurations(nb_dev, sb_dev); + switching_gpp1_configurations(nb_dev, sb_dev); + switching_gpp2_configurations(nb_dev, sb_dev); ValidatePortEn(nb_dev); }

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Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Properly indicate clobbered registers
by Timothy Pearson 15 Nov '15

15 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12012 -gerrit commit 018df93746a72823c36469222476bb2bfa1ae84c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 27 17:52:18 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Properly indicate clobbered registers Change-Id: Icb2754143762bd64ee1df5674fa071de1c595eaf Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index c4bfd3f..0d9c886 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -119,6 +119,9 @@ static void proc_CLFLUSH(u32 addr_hi) static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) { + uint32_t step = 16; + uint32_t count = line_num * 4; + __asm__ volatile ( /*prevent speculative execution of following instructions*/ /* FIXME: needed ? */ @@ -131,7 +134,7 @@ static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) "loop 1b\n\t" "mfence\n\t" - :: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a) + : "+a" (addr_lo), "+d" (step), "+c" (count), "+b" (buf_a) : : ); } @@ -251,6 +254,10 @@ static void ReadMaxRdLat1CLTestPattern_D(u32 addr) static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) { + uint32_t addr_phys = addr << 8; + uint32_t step = 16; + uint32_t count = 3 * 4; + SetUpperFSbase(addr); __asm__ volatile ( @@ -263,7 +270,7 @@ static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) "loop 1b\n\t" "mfence\n\t" - :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) + : "+a" (addr_phys), "+d" (step), "+c" (count), "+b" (buf) : : ); }

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Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure
by Timothy Pearson 15 Nov '15

15 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12013 -gerrit commit 1c015e333adff7c15eb2542b5c8024081e4af741 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 27 17:52:45 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure In the course of adding full Family 15h MCT support some Family 15h specific settings were inadvertently applied to Family 10h processors. Only apply Family15h specific settings to Family 15h processors. Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 28 +++++++++++++++++++++------- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 8 +++++++- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index e7fee19..c8d72c6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1635,6 +1635,11 @@ restartinit: HTMemMapInit_D(pMCTstat, pDCTstatA); /* Map local memory into system address space.*/ mctHookAfterHTMap(); + if (!is_fam15h()) { + printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); + CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ + } + printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n"); mctHookAfterCPU(); /* Setup external northbridge(s) */ @@ -1658,6 +1663,11 @@ restartinit: printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n"); DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/ + if (!is_fam15h()) { + printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); + UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ + } + if (!allow_config_restore) { printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n"); mct_OtherTiming(pMCTstat, pDCTstatA); @@ -1678,11 +1688,13 @@ restartinit: MCTMemClr_D(pMCTstat,pDCTstatA); } - printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); - CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ + if (is_fam15h()) { + printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); + CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); - UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ + printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); + UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ + } printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -6353,11 +6365,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, DramMRS |= 1 << 1; dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84); - dword |= DramMRS; - if (is_fam15h()) + if (is_fam15h()) { + dword |= DramMRS; dword &= ~0x00800003; - else + } else { dword &= ~0x00fc2f8f; + dword |= DramMRS; + } Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x84, dword); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 4397eba..38991c8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -904,9 +904,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, * Flush the receiver FIFO * Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO */ - + /* FIXME + * This does not seem to be needed, and has a tendency to lock up the + * boot process while attempting to write the test pattern. + */ +#if 0 + SetUpperFSbase(TestAddr0); WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1); mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0); +#endif } MaxDelay_CH[Channel] = CTLRMaxDelay; }

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coreboot-gerrit November 2015