coreboot-gerrit October 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: commonlib/helpers.h: handle interaction with other environments
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11773 -gerrit commit 68266e90a38bb22518362a7325893f911d28d33c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 1 14:20:57 2015 -0500 commonlib/helpers.h: handle interaction with other environments There are compiler settings and interactions with other header files that should be handled. First use __typeof__ instead of typeof because 'std' modes don't accept typeof. The __typeof__ variant works equally well on clang. The other change is to guard the helper macros so as not to trigger redefinition errors. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built cbfstool including commonlib/helpers.h Change-Id: I58890477cb17df14a9fa8b7af752a7c70769cf36 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/include/commonlib/helpers.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index 6ad767e..0e337c9 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -4,14 +4,18 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) +#define ALIGN(x,a) __ALIGN_MASK(x,(__typeof__(x))(a)-1UL) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x,a) ALIGN((x),(a)) -#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) -#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) +#define ALIGN_DOWN(x,a) ((x) & ~((__typeof__(x))(a)-1UL)) +#define IS_ALIGNED(x,a) (((x) & ((__typeof__(x))(a)-1UL)) == 0) +#ifndef MIN #define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif +#ifndef MAX #define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif #define ABS(a) (((a) < 0) ? (-(a)) : (a)) #define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) @@ -27,7 +31,9 @@ #define MHz (1000 * KHz) #define GHz (1000 * MHz) +#ifndef offsetof #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#endif #if !defined(__clang__) #define check_member(structure, member, offset) _Static_assert( \ @@ -45,7 +51,7 @@ * */ #define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + const __typeof__( ((type *)0)->member ) *__mptr = (ptr); \ (type *)( (char *)__mptr - offsetof(type,member) );}) #endif /* COMMONLIB_HELPERS_H */

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New patch to review for coreboot: fsp1_1: move relocation algorithm to commonlib
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11772 -gerrit commit 02753466107f7882f3a4bee3924dc23f43d53ba0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 17:49:04 2015 -0500 fsp1_1: move relocation algorithm to commonlib In order to support FSP 1.1 relocation within cbfstool the relocation code needs to be moved into commonlib. To that end, move it. The FSP 1.1 relocation code binds to edk2 UEFI 2.4 types unconditionally which is separate from the FSP's version binding. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: Ib2627d02af99092875ff885f7cb048f70ea73856 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/Makefile.inc | 2 + src/commonlib/fsp1_1_relocate.c | 540 +++++++++++++++++++++ src/commonlib/include/commonlib/fsp1_1.h | 48 ++ src/drivers/intel/fsp1_1/Makefile.inc | 1 - src/drivers/intel/fsp1_1/fsp1_1_relocate.c | 540 --------------------- src/drivers/intel/fsp1_1/fsp_relocate.c | 1 + src/drivers/intel/fsp1_1/include/fsp/api.h | 2 - src/drivers/intel/fsp1_1/include/fsp/util.h | 6 - .../fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h | 2 + 9 files changed, 593 insertions(+), 549 deletions(-) diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 70a9b1a..929bf8e 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -8,3 +8,5 @@ verstage-y += region.c romstage-y += region.c ramstage-y += region.c smm-y += region.c + +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1_relocate.c diff --git a/src/commonlib/fsp1_1_relocate.c b/src/commonlib/fsp1_1_relocate.c new file mode 100644 index 0000000..994da09 --- /dev/null +++ b/src/commonlib/fsp1_1_relocate.c @@ -0,0 +1,540 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <commonlib/endian.h> +#include <commonlib/fsp1_1.h> +#include <commonlib/helpers.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> + +#define FSP_DBG_LVL BIOS_NEVER + +/* + * UEFI defines everything as little endian. However, this piece of code + * can be integrated in a userland tool. That tool could be on a big endian + * machine so one needs to access the fields within UEFI structures using + * endian-aware accesses. + */ + +/* Return 0 if equal. Non-zero if not equal. */ +static int guid_compare(const EFI_GUID *le_guid, const EFI_GUID *native_guid) +{ + if (read_le32(&le_guid->Data1) != native_guid->Data1) + return 1; + if (read_le16(&le_guid->Data2) != native_guid->Data2) + return 1; + if (read_le16(&le_guid->Data3) != native_guid->Data3) + return 1; + return memcmp(le_guid->Data4, native_guid->Data4, + ARRAY_SIZE(le_guid->Data4)); +} + +/* Provide this for symmetry when accessing UEFI fields. */ +static inline uint8_t le8toh(uint8_t byte) +{ + return byte; +} + +static const EFI_GUID ffs2_guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID; +static const EFI_GUID fih_guid = FSP_INFO_HEADER_GUID; + +struct fsp_patch_table { + uint32_t signature; + uint16_t header_length; + uint8_t header_revision; + uint8_t reserved; + uint32_t patch_entry_num; + uint32_t patch_entries[0]; +} __attribute__((packed)); + +#define FSPP_SIG 0x50505346 + +static void *relative_offset(void *base, ssize_t offset) +{ + uintptr_t loc; + + loc = (uintptr_t)base; + loc += offset; + + return (void *)loc; +} + +static uint32_t *fspp_reloc(void *fsp, size_t fsp_size, uint32_t e) +{ + size_t offset; + + /* Offsets live in bits 23:0. */ + offset = e & 0xffffff; + + /* If bit 31 is set then the offset is considered a negative value + * relative to the end of the image using 16MiB as the offset's + * reference. */ + if (e & (1 << 31)) + offset = fsp_size - (16 * MiB - offset); + + /* Determine if offset falls within fsp_size for a 32 bit relocation. */ + if (offset > fsp_size - sizeof(uint32_t)) + return NULL; + + return relative_offset(fsp, offset); +} + +static int reloc_type(uint16_t reloc_entry) +{ + /* Reloc type in upper 4 bits */ + return reloc_entry >> 12; +} + +static size_t reloc_offset(uint16_t reloc_entry) +{ + /* Offsets are in low 12 bits. */ + return reloc_entry & ((1 << 12) - 1); +} + +static int te_relocate(uintptr_t new_addr, void *te) +{ + EFI_TE_IMAGE_HEADER *teih; + EFI_IMAGE_DATA_DIRECTORY *relocd; + EFI_IMAGE_BASE_RELOCATION *relocb; + uintptr_t image_base; + size_t fixup_offset; + size_t num_relocs; + uint16_t *reloc; + size_t relocd_offset; + uint8_t *te_base; + uint32_t adj; + + teih = te; + + if (read_le16(&teih->Signature) != EFI_TE_IMAGE_HEADER_SIGNATURE) { + printk(BIOS_ERR, "TE Signature mismatch: %x vs %x\n", + read_le16(&teih->Signature), + EFI_TE_IMAGE_HEADER_SIGNATURE); + return -1; + } + + /* + * A TE image is created by converting a PE file. Because of this + * the offsets within the headers are off. In order to calculate + * the correct releative offets one needs to subtract fixup_offset + * from the encoded offets. Similarly, the linked address of the + * program is found by adding the fixup_offset to the ImageBase. + */ + fixup_offset = read_le16(&teih->StrippedSize); + fixup_offset -= sizeof(EFI_TE_IMAGE_HEADER); + /* Keep track of a base that is correctly adjusted so that offsets + * can be used directly. */ + te_base = te; + te_base -= fixup_offset; + + image_base = read_le64(&teih->ImageBase); + adj = new_addr - (image_base + fixup_offset); + + printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n", + (void *)image_base, (void *)new_addr, adj); + + /* Adjust ImageBase for consistency. */ + write_le64(&teih->ImageBase, (uint32_t)(image_base + adj)); + + relocd = &teih->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC]; + + relocd_offset = 0; + /* Though the field name is VirtualAddress it's actually relative to + * the beginning of the image which is linked at ImageBase. */ + relocb = relative_offset(te, + read_le32(&relocd->VirtualAddress) - fixup_offset); + while (relocd_offset < read_le32(&relocd->Size)) { + size_t rva_offset = read_le32(&relocb->VirtualAddress); + + printk(FSP_DBG_LVL, "Relocs for RVA offset %zx\n", rva_offset); + num_relocs = read_le32(&relocb->SizeOfBlock) - sizeof(*relocb); + num_relocs /= sizeof(uint16_t); + reloc = relative_offset(relocb, sizeof(*relocb)); + + printk(FSP_DBG_LVL, "Num relocs in block: %zx\n", num_relocs); + + while (num_relocs > 0) { + uint16_t reloc_val = read_le16(reloc); + int type = reloc_type(reloc_val); + size_t offset = reloc_offset(reloc_val); + + printk(FSP_DBG_LVL, "reloc type %x offset %zx\n", + type, offset); + + if (type == EFI_IMAGE_REL_BASED_HIGHLOW) { + uint32_t *reloc_addr; + uint32_t val; + + offset += rva_offset; + reloc_addr = (void *)&te_base[offset]; + val = read_le32(reloc_addr); + + printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", + reloc_addr, val, val + adj); + write_le32(reloc_addr, val + adj); + } else if (type != EFI_IMAGE_REL_BASED_ABSOLUTE) { + printk(BIOS_ERR, "Unknown reloc type: %x\n", + type); + return -1; + } + num_relocs--; + reloc++; + } + + /* Track consumption of relocation directory contents. */ + relocd_offset += read_le32(&relocb->SizeOfBlock); + /* Get next relocation block to process. */ + relocb = relative_offset(relocb, + read_le32(&relocb->SizeOfBlock)); + } + + return 0; +} + +static size_t csh_size(const EFI_COMMON_SECTION_HEADER *csh) +{ + size_t size; + + /* Unpack the array into a type that can be used. */ + size = 0; + size |= read_le8(&csh->Size[0]) << 0; + size |= read_le8(&csh->Size[1]) << 8; + size |= read_le8(&csh->Size[2]) << 16; + + return size; +} + +static size_t section_data_offset(const EFI_COMMON_SECTION_HEADER *csh) +{ + if (csh_size(csh) == 0x00ffffff) + return sizeof(EFI_COMMON_SECTION_HEADER2); + else + return sizeof(EFI_COMMON_SECTION_HEADER); +} + +static size_t section_data_size(const EFI_COMMON_SECTION_HEADER *csh) +{ + size_t section_size; + + if (csh_size(csh) == 0x00ffffff) + section_size = read_le32(&SECTION2_SIZE(csh)); + else + section_size = csh_size(csh); + + return section_size - section_data_offset(csh); +} + +static size_t file_section_offset(const EFI_FFS_FILE_HEADER *ffsfh) +{ + if (IS_FFS_FILE2(ffsfh)) + return sizeof(EFI_FFS_FILE_HEADER2); + else + return sizeof(EFI_FFS_FILE_HEADER); +} + +static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh) +{ + size_t size; + + if (IS_FFS_FILE2(ffsfh)) + size = read_le32(&FFS_FILE2_SIZE(ffsfh)); + else { + size = read_le8(&ffsfh->Size[0]) << 0; + size |= read_le8(&ffsfh->Size[1]) << 8; + size |= read_le8(&ffsfh->Size[2]) << 16; + } + return size; +} + +static int relocate_patch_table(void *fsp, size_t size, size_t offset, + ssize_t adjustment) +{ + struct fsp_patch_table *table; + size_t num; + size_t num_entries; + + table = relative_offset(fsp, offset); + + if ((offset + sizeof(*table) > size) || + (read_le16(&table->header_length) + offset) > size) { + printk(BIOS_ERR, "FSPP not entirely contained in region.\n"); + return -1; + } + + num_entries = read_le32(&table->patch_entry_num); + printk(FSP_DBG_LVL, "FSPP relocs: %zx\n", num_entries); + + for (num = 0; num < num_entries; num++) { + uint32_t *reloc; + uint32_t reloc_val; + + reloc = fspp_reloc(fsp, size, + read_le32(&table->patch_entries[num])); + + if (reloc == NULL) { + printk(BIOS_ERR, "Ignoring FSPP entry: %x\n", + read_le32(&table->patch_entries[num])); + continue; + } + + reloc_val = read_le32(reloc); + printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", + reloc, reloc_val, + (unsigned int)(reloc_val + adjustment)); + + write_le32(reloc, reloc_val + adjustment); + } + + return 0; +} + +static ssize_t relocate_remaining_items(void *fsp, size_t size, + uintptr_t new_addr, size_t fih_offset) +{ + EFI_FFS_FILE_HEADER *ffsfh; + EFI_COMMON_SECTION_HEADER *csh; + FSP_INFO_HEADER *fih; + ssize_t adjustment; + size_t offset; + + printk(FSP_DBG_LVL, "FSP_INFO_HEADER offset is %zx\n", fih_offset); + + if (fih_offset == 0) { + printk(BIOS_ERR, "FSP_INFO_HEADER offset is 0.\n"); + return -1; + } + + /* FSP_INFO_HEADER at first file in FV within first RAW section. */ + ffsfh = relative_offset(fsp, fih_offset); + fih_offset += file_section_offset(ffsfh); + csh = relative_offset(fsp, fih_offset); + fih_offset += section_data_offset(csh); + fih = relative_offset(fsp, fih_offset); + + if (guid_compare(&ffsfh->Name, &fih_guid)) { + printk(BIOS_ERR, "Bad FIH GUID.\n"); + return -1; + } + + if (read_le8(&csh->Type) != EFI_SECTION_RAW) { + printk(BIOS_ERR, "FIH file should have raw section: %x\n", + read_le8(&csh->Type)); + return -1; + } + + if (read_le32(&fih->Signature) != FSP_SIG) { + printk(BIOS_ERR, "Unexpected FIH signature: %08x\n", + read_le32(&fih->Signature)); + return -1; + } + + adjustment = (intptr_t)new_addr - read_le32(&fih->ImageBase); + + /* Update ImageBase to reflect FSP's new home. */ + write_le32(&fih->ImageBase, adjustment + read_le32(&fih->ImageBase)); + + /* Need to find patch table and adjust each entry. The tables + * following FSP_INFO_HEADER have a 32-bit signature and header + * length. The patch table is denoted as having a 'FSPP' signature; + * the table format doesn't follow the other tables. */ + offset = fih_offset + read_le32(&fih->HeaderLength); + while (offset + 2 * sizeof(uint32_t) <= size) { + uint32_t *table_headers; + + table_headers = relative_offset(fsp, offset); + + printk(FSP_DBG_LVL, "Checking offset %zx for 'FSPP'\n", + offset); + + if (read_le32(&table_headers[0]) != FSPP_SIG) { + offset += read_le32(&table_headers[1]); + continue; + } + + if (relocate_patch_table(fsp, size, offset, adjustment)) { + printk(BIOS_ERR, "FSPP relocation failed.\n"); + return -1; + } + + return fih_offset; + } + + printk(BIOS_ERR, "Could not find the FSP patch table.\n"); + return -1; +} + +static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, + size_t fvh_offset, size_t *fih_offset) +{ + EFI_FIRMWARE_VOLUME_HEADER *fvh; + EFI_FFS_FILE_HEADER *ffsfh; + EFI_COMMON_SECTION_HEADER *csh; + size_t offset; + size_t file_offset; + size_t size; + size_t fv_length; + + offset = fvh_offset; + fvh = relative_offset(fsp, offset); + + if (read_le32(&fvh->Signature) != EFI_FVH_SIGNATURE) + return -1; + + fv_length = read_le64(&fvh->FvLength); + + printk(FSP_DBG_LVL, "FVH length: %zx Offset: %zx Mapping length: %zx\n", + fv_length, offset, fsp_size); + + if (fv_length + offset > fsp_size) + return -1; + + /* Parse only this FV. However, the algorithm uses offsets into the + * entire FSP region so make size include the starting offset. */ + size = fv_length + offset; + + if (guid_compare(&fvh->FileSystemGuid, &ffs2_guid)) { + printk(BIOS_ERR, "FVH not an FFS2 type.\n"); + return -1; + } + + if (read_le16(&fvh->ExtHeaderOffset) != 0) { + EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh; + + offset += read_le16(&fvh->ExtHeaderOffset); + fveh = relative_offset(fsp, offset); + printk(FSP_DBG_LVL, "Extended Header Offset: %zx Size: %zx\n", + (size_t)read_le16(&fvh->ExtHeaderOffset), + (size_t)read_le32(&fveh->ExtHeaderSize)); + offset += read_le32(&fveh->ExtHeaderSize); + /* FFS files are 8 byte aligned after extended header. */ + offset = ALIGN_UP(offset, 8); + } else { + offset += read_le16(&fvh->HeaderLength); + } + + file_offset = offset; + while (file_offset + sizeof(*ffsfh) < size) { + offset = file_offset; + printk(FSP_DBG_LVL, "file offset: %zx\n", file_offset); + + /* First file and section should be FSP info header. */ + if (fih_offset != NULL && *fih_offset == 0) + *fih_offset = file_offset; + + ffsfh = relative_offset(fsp, file_offset); + + printk(FSP_DBG_LVL, "file type = %x\n", read_le8(&ffsfh->Type)); + printk(FSP_DBG_LVL, "file attribs = %x\n", + read_le8(&ffsfh->Attributes)); + + /* Exit FV relocation when empty space found */ + if (read_le8(&ffsfh->Type) == EFI_FV_FILETYPE_FFS_MAX) + break; + + /* Next file on 8 byte alignment. */ + file_offset += ffs_file_size(ffsfh); + file_offset = ALIGN_UP(file_offset, 8); + + /* Padding files have no section information. */ + if (read_le8(&ffsfh->Type) == EFI_FV_FILETYPE_FFS_PAD) + continue; + + offset += file_section_offset(ffsfh); + + while (offset + sizeof(*csh) < file_offset) { + size_t data_size; + size_t data_offset; + + csh = relative_offset(fsp, offset); + + printk(FSP_DBG_LVL, "section offset: %zx\n", offset); + printk(FSP_DBG_LVL, "section type: %x\n", + read_le8(&csh->Type)); + + data_size = section_data_size(csh); + data_offset = section_data_offset(csh); + + if (data_size + data_offset + offset > file_offset) { + printk(BIOS_ERR, "Section exceeds FV size.\n"); + return -1; + } + + /* + * The entire FSP 1.1 image can be thought of as one + * program with a single link address even though there + * are multiple TEs linked separately. The reason is + * that each TE is linked for XIP. So in order to + * relocate the TE properly we need to form the + * relocated address based on the TE offset within + * FSP proper. + */ + if (read_le8(&csh->Type) == EFI_SECTION_TE) { + void *te; + size_t te_offset = offset + data_offset; + uintptr_t te_addr = new_addr + te_offset; + + printk(FSP_DBG_LVL, "TE image at offset %zx\n", + te_offset); + te = relative_offset(fsp, te_offset); + te_relocate(te_addr, te); + } + + offset += data_size + data_offset; + /* Sections are aligned to 4 bytes. */ + offset = ALIGN_UP(offset, 4); + } + } + + /* Return amount of buffer parsed: FV size. */ + return fv_length; +} + +ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size) +{ + size_t offset; + size_t fih_offset; + + offset = 0; + fih_offset = 0; + while (offset < size) { + ssize_t nparsed; + + /* Relocate each FV within the FSP region. The FSP_INFO_HEADER + * should only be located in the first FV. */ + if (offset == 0) + nparsed = relocate_fvh(new_addr, fsp, size, offset, + &fih_offset); + else + nparsed = relocate_fvh(new_addr, fsp, size, offset, + NULL); + + /* FV should be larger than 0 or failed to parse. */ + if (nparsed <= 0) { + printk(BIOS_ERR, "FV @ offset %zx relocation failed\n", + offset); + return -1; + } + + offset += nparsed; + } + + return relocate_remaining_items(fsp, size, new_addr, fih_offset); +} diff --git a/src/commonlib/include/commonlib/fsp1_1.h b/src/commonlib/include/commonlib/fsp1_1.h new file mode 100644 index 0000000..8d8dcf0 --- /dev/null +++ b/src/commonlib/include/commonlib/fsp1_1.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _COMMONLIB_FSP1_1_H_ +#define _COMMONLIB_FSP1_1_H_ + +#include <stddef.h> +#include <stdint.h> + +/* + * Intel's code does not have a handle on changing global packing state. + * Therefore, one needs to protect against packing policies that are set + * globally for a compliation unit just by including a header file. + */ +#pragma pack(push) + +/* Default bind FSP 1.1 API to edk2 UEFI 2.4 types. */ +#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h> + +#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h> +#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h> + +/* Restore original packing policy. */ +#pragma pack(pop) + +/* + * Relocate FSP held within buffer defined by size to new_addr. Returns < 0 + * on error, offset to FSP_INFO_HEADER on success. + */ +ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size); + +#endif diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index dffb6d2..bab68e1 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -23,7 +23,6 @@ romstage-y += hob.c ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c ramstage-y += fsp_relocate.c -ramstage-y += fsp1_1_relocate.c ramstage-y += fsp_util.c ramstage-y += hob.c diff --git a/src/drivers/intel/fsp1_1/fsp1_1_relocate.c b/src/drivers/intel/fsp1_1/fsp1_1_relocate.c deleted file mode 100644 index 994da09..0000000 --- a/src/drivers/intel/fsp1_1/fsp1_1_relocate.c +++ /dev/null @@ -1,540 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <console/console.h> -#include <commonlib/endian.h> -#include <commonlib/fsp1_1.h> -#include <commonlib/helpers.h> -#include <stdlib.h> -#include <stdint.h> -#include <string.h> - -#define FSP_DBG_LVL BIOS_NEVER - -/* - * UEFI defines everything as little endian. However, this piece of code - * can be integrated in a userland tool. That tool could be on a big endian - * machine so one needs to access the fields within UEFI structures using - * endian-aware accesses. - */ - -/* Return 0 if equal. Non-zero if not equal. */ -static int guid_compare(const EFI_GUID *le_guid, const EFI_GUID *native_guid) -{ - if (read_le32(&le_guid->Data1) != native_guid->Data1) - return 1; - if (read_le16(&le_guid->Data2) != native_guid->Data2) - return 1; - if (read_le16(&le_guid->Data3) != native_guid->Data3) - return 1; - return memcmp(le_guid->Data4, native_guid->Data4, - ARRAY_SIZE(le_guid->Data4)); -} - -/* Provide this for symmetry when accessing UEFI fields. */ -static inline uint8_t le8toh(uint8_t byte) -{ - return byte; -} - -static const EFI_GUID ffs2_guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID; -static const EFI_GUID fih_guid = FSP_INFO_HEADER_GUID; - -struct fsp_patch_table { - uint32_t signature; - uint16_t header_length; - uint8_t header_revision; - uint8_t reserved; - uint32_t patch_entry_num; - uint32_t patch_entries[0]; -} __attribute__((packed)); - -#define FSPP_SIG 0x50505346 - -static void *relative_offset(void *base, ssize_t offset) -{ - uintptr_t loc; - - loc = (uintptr_t)base; - loc += offset; - - return (void *)loc; -} - -static uint32_t *fspp_reloc(void *fsp, size_t fsp_size, uint32_t e) -{ - size_t offset; - - /* Offsets live in bits 23:0. */ - offset = e & 0xffffff; - - /* If bit 31 is set then the offset is considered a negative value - * relative to the end of the image using 16MiB as the offset's - * reference. */ - if (e & (1 << 31)) - offset = fsp_size - (16 * MiB - offset); - - /* Determine if offset falls within fsp_size for a 32 bit relocation. */ - if (offset > fsp_size - sizeof(uint32_t)) - return NULL; - - return relative_offset(fsp, offset); -} - -static int reloc_type(uint16_t reloc_entry) -{ - /* Reloc type in upper 4 bits */ - return reloc_entry >> 12; -} - -static size_t reloc_offset(uint16_t reloc_entry) -{ - /* Offsets are in low 12 bits. */ - return reloc_entry & ((1 << 12) - 1); -} - -static int te_relocate(uintptr_t new_addr, void *te) -{ - EFI_TE_IMAGE_HEADER *teih; - EFI_IMAGE_DATA_DIRECTORY *relocd; - EFI_IMAGE_BASE_RELOCATION *relocb; - uintptr_t image_base; - size_t fixup_offset; - size_t num_relocs; - uint16_t *reloc; - size_t relocd_offset; - uint8_t *te_base; - uint32_t adj; - - teih = te; - - if (read_le16(&teih->Signature) != EFI_TE_IMAGE_HEADER_SIGNATURE) { - printk(BIOS_ERR, "TE Signature mismatch: %x vs %x\n", - read_le16(&teih->Signature), - EFI_TE_IMAGE_HEADER_SIGNATURE); - return -1; - } - - /* - * A TE image is created by converting a PE file. Because of this - * the offsets within the headers are off. In order to calculate - * the correct releative offets one needs to subtract fixup_offset - * from the encoded offets. Similarly, the linked address of the - * program is found by adding the fixup_offset to the ImageBase. - */ - fixup_offset = read_le16(&teih->StrippedSize); - fixup_offset -= sizeof(EFI_TE_IMAGE_HEADER); - /* Keep track of a base that is correctly adjusted so that offsets - * can be used directly. */ - te_base = te; - te_base -= fixup_offset; - - image_base = read_le64(&teih->ImageBase); - adj = new_addr - (image_base + fixup_offset); - - printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n", - (void *)image_base, (void *)new_addr, adj); - - /* Adjust ImageBase for consistency. */ - write_le64(&teih->ImageBase, (uint32_t)(image_base + adj)); - - relocd = &teih->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC]; - - relocd_offset = 0; - /* Though the field name is VirtualAddress it's actually relative to - * the beginning of the image which is linked at ImageBase. */ - relocb = relative_offset(te, - read_le32(&relocd->VirtualAddress) - fixup_offset); - while (relocd_offset < read_le32(&relocd->Size)) { - size_t rva_offset = read_le32(&relocb->VirtualAddress); - - printk(FSP_DBG_LVL, "Relocs for RVA offset %zx\n", rva_offset); - num_relocs = read_le32(&relocb->SizeOfBlock) - sizeof(*relocb); - num_relocs /= sizeof(uint16_t); - reloc = relative_offset(relocb, sizeof(*relocb)); - - printk(FSP_DBG_LVL, "Num relocs in block: %zx\n", num_relocs); - - while (num_relocs > 0) { - uint16_t reloc_val = read_le16(reloc); - int type = reloc_type(reloc_val); - size_t offset = reloc_offset(reloc_val); - - printk(FSP_DBG_LVL, "reloc type %x offset %zx\n", - type, offset); - - if (type == EFI_IMAGE_REL_BASED_HIGHLOW) { - uint32_t *reloc_addr; - uint32_t val; - - offset += rva_offset; - reloc_addr = (void *)&te_base[offset]; - val = read_le32(reloc_addr); - - printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", - reloc_addr, val, val + adj); - write_le32(reloc_addr, val + adj); - } else if (type != EFI_IMAGE_REL_BASED_ABSOLUTE) { - printk(BIOS_ERR, "Unknown reloc type: %x\n", - type); - return -1; - } - num_relocs--; - reloc++; - } - - /* Track consumption of relocation directory contents. */ - relocd_offset += read_le32(&relocb->SizeOfBlock); - /* Get next relocation block to process. */ - relocb = relative_offset(relocb, - read_le32(&relocb->SizeOfBlock)); - } - - return 0; -} - -static size_t csh_size(const EFI_COMMON_SECTION_HEADER *csh) -{ - size_t size; - - /* Unpack the array into a type that can be used. */ - size = 0; - size |= read_le8(&csh->Size[0]) << 0; - size |= read_le8(&csh->Size[1]) << 8; - size |= read_le8(&csh->Size[2]) << 16; - - return size; -} - -static size_t section_data_offset(const EFI_COMMON_SECTION_HEADER *csh) -{ - if (csh_size(csh) == 0x00ffffff) - return sizeof(EFI_COMMON_SECTION_HEADER2); - else - return sizeof(EFI_COMMON_SECTION_HEADER); -} - -static size_t section_data_size(const EFI_COMMON_SECTION_HEADER *csh) -{ - size_t section_size; - - if (csh_size(csh) == 0x00ffffff) - section_size = read_le32(&SECTION2_SIZE(csh)); - else - section_size = csh_size(csh); - - return section_size - section_data_offset(csh); -} - -static size_t file_section_offset(const EFI_FFS_FILE_HEADER *ffsfh) -{ - if (IS_FFS_FILE2(ffsfh)) - return sizeof(EFI_FFS_FILE_HEADER2); - else - return sizeof(EFI_FFS_FILE_HEADER); -} - -static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh) -{ - size_t size; - - if (IS_FFS_FILE2(ffsfh)) - size = read_le32(&FFS_FILE2_SIZE(ffsfh)); - else { - size = read_le8(&ffsfh->Size[0]) << 0; - size |= read_le8(&ffsfh->Size[1]) << 8; - size |= read_le8(&ffsfh->Size[2]) << 16; - } - return size; -} - -static int relocate_patch_table(void *fsp, size_t size, size_t offset, - ssize_t adjustment) -{ - struct fsp_patch_table *table; - size_t num; - size_t num_entries; - - table = relative_offset(fsp, offset); - - if ((offset + sizeof(*table) > size) || - (read_le16(&table->header_length) + offset) > size) { - printk(BIOS_ERR, "FSPP not entirely contained in region.\n"); - return -1; - } - - num_entries = read_le32(&table->patch_entry_num); - printk(FSP_DBG_LVL, "FSPP relocs: %zx\n", num_entries); - - for (num = 0; num < num_entries; num++) { - uint32_t *reloc; - uint32_t reloc_val; - - reloc = fspp_reloc(fsp, size, - read_le32(&table->patch_entries[num])); - - if (reloc == NULL) { - printk(BIOS_ERR, "Ignoring FSPP entry: %x\n", - read_le32(&table->patch_entries[num])); - continue; - } - - reloc_val = read_le32(reloc); - printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", - reloc, reloc_val, - (unsigned int)(reloc_val + adjustment)); - - write_le32(reloc, reloc_val + adjustment); - } - - return 0; -} - -static ssize_t relocate_remaining_items(void *fsp, size_t size, - uintptr_t new_addr, size_t fih_offset) -{ - EFI_FFS_FILE_HEADER *ffsfh; - EFI_COMMON_SECTION_HEADER *csh; - FSP_INFO_HEADER *fih; - ssize_t adjustment; - size_t offset; - - printk(FSP_DBG_LVL, "FSP_INFO_HEADER offset is %zx\n", fih_offset); - - if (fih_offset == 0) { - printk(BIOS_ERR, "FSP_INFO_HEADER offset is 0.\n"); - return -1; - } - - /* FSP_INFO_HEADER at first file in FV within first RAW section. */ - ffsfh = relative_offset(fsp, fih_offset); - fih_offset += file_section_offset(ffsfh); - csh = relative_offset(fsp, fih_offset); - fih_offset += section_data_offset(csh); - fih = relative_offset(fsp, fih_offset); - - if (guid_compare(&ffsfh->Name, &fih_guid)) { - printk(BIOS_ERR, "Bad FIH GUID.\n"); - return -1; - } - - if (read_le8(&csh->Type) != EFI_SECTION_RAW) { - printk(BIOS_ERR, "FIH file should have raw section: %x\n", - read_le8(&csh->Type)); - return -1; - } - - if (read_le32(&fih->Signature) != FSP_SIG) { - printk(BIOS_ERR, "Unexpected FIH signature: %08x\n", - read_le32(&fih->Signature)); - return -1; - } - - adjustment = (intptr_t)new_addr - read_le32(&fih->ImageBase); - - /* Update ImageBase to reflect FSP's new home. */ - write_le32(&fih->ImageBase, adjustment + read_le32(&fih->ImageBase)); - - /* Need to find patch table and adjust each entry. The tables - * following FSP_INFO_HEADER have a 32-bit signature and header - * length. The patch table is denoted as having a 'FSPP' signature; - * the table format doesn't follow the other tables. */ - offset = fih_offset + read_le32(&fih->HeaderLength); - while (offset + 2 * sizeof(uint32_t) <= size) { - uint32_t *table_headers; - - table_headers = relative_offset(fsp, offset); - - printk(FSP_DBG_LVL, "Checking offset %zx for 'FSPP'\n", - offset); - - if (read_le32(&table_headers[0]) != FSPP_SIG) { - offset += read_le32(&table_headers[1]); - continue; - } - - if (relocate_patch_table(fsp, size, offset, adjustment)) { - printk(BIOS_ERR, "FSPP relocation failed.\n"); - return -1; - } - - return fih_offset; - } - - printk(BIOS_ERR, "Could not find the FSP patch table.\n"); - return -1; -} - -static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, - size_t fvh_offset, size_t *fih_offset) -{ - EFI_FIRMWARE_VOLUME_HEADER *fvh; - EFI_FFS_FILE_HEADER *ffsfh; - EFI_COMMON_SECTION_HEADER *csh; - size_t offset; - size_t file_offset; - size_t size; - size_t fv_length; - - offset = fvh_offset; - fvh = relative_offset(fsp, offset); - - if (read_le32(&fvh->Signature) != EFI_FVH_SIGNATURE) - return -1; - - fv_length = read_le64(&fvh->FvLength); - - printk(FSP_DBG_LVL, "FVH length: %zx Offset: %zx Mapping length: %zx\n", - fv_length, offset, fsp_size); - - if (fv_length + offset > fsp_size) - return -1; - - /* Parse only this FV. However, the algorithm uses offsets into the - * entire FSP region so make size include the starting offset. */ - size = fv_length + offset; - - if (guid_compare(&fvh->FileSystemGuid, &ffs2_guid)) { - printk(BIOS_ERR, "FVH not an FFS2 type.\n"); - return -1; - } - - if (read_le16(&fvh->ExtHeaderOffset) != 0) { - EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh; - - offset += read_le16(&fvh->ExtHeaderOffset); - fveh = relative_offset(fsp, offset); - printk(FSP_DBG_LVL, "Extended Header Offset: %zx Size: %zx\n", - (size_t)read_le16(&fvh->ExtHeaderOffset), - (size_t)read_le32(&fveh->ExtHeaderSize)); - offset += read_le32(&fveh->ExtHeaderSize); - /* FFS files are 8 byte aligned after extended header. */ - offset = ALIGN_UP(offset, 8); - } else { - offset += read_le16(&fvh->HeaderLength); - } - - file_offset = offset; - while (file_offset + sizeof(*ffsfh) < size) { - offset = file_offset; - printk(FSP_DBG_LVL, "file offset: %zx\n", file_offset); - - /* First file and section should be FSP info header. */ - if (fih_offset != NULL && *fih_offset == 0) - *fih_offset = file_offset; - - ffsfh = relative_offset(fsp, file_offset); - - printk(FSP_DBG_LVL, "file type = %x\n", read_le8(&ffsfh->Type)); - printk(FSP_DBG_LVL, "file attribs = %x\n", - read_le8(&ffsfh->Attributes)); - - /* Exit FV relocation when empty space found */ - if (read_le8(&ffsfh->Type) == EFI_FV_FILETYPE_FFS_MAX) - break; - - /* Next file on 8 byte alignment. */ - file_offset += ffs_file_size(ffsfh); - file_offset = ALIGN_UP(file_offset, 8); - - /* Padding files have no section information. */ - if (read_le8(&ffsfh->Type) == EFI_FV_FILETYPE_FFS_PAD) - continue; - - offset += file_section_offset(ffsfh); - - while (offset + sizeof(*csh) < file_offset) { - size_t data_size; - size_t data_offset; - - csh = relative_offset(fsp, offset); - - printk(FSP_DBG_LVL, "section offset: %zx\n", offset); - printk(FSP_DBG_LVL, "section type: %x\n", - read_le8(&csh->Type)); - - data_size = section_data_size(csh); - data_offset = section_data_offset(csh); - - if (data_size + data_offset + offset > file_offset) { - printk(BIOS_ERR, "Section exceeds FV size.\n"); - return -1; - } - - /* - * The entire FSP 1.1 image can be thought of as one - * program with a single link address even though there - * are multiple TEs linked separately. The reason is - * that each TE is linked for XIP. So in order to - * relocate the TE properly we need to form the - * relocated address based on the TE offset within - * FSP proper. - */ - if (read_le8(&csh->Type) == EFI_SECTION_TE) { - void *te; - size_t te_offset = offset + data_offset; - uintptr_t te_addr = new_addr + te_offset; - - printk(FSP_DBG_LVL, "TE image at offset %zx\n", - te_offset); - te = relative_offset(fsp, te_offset); - te_relocate(te_addr, te); - } - - offset += data_size + data_offset; - /* Sections are aligned to 4 bytes. */ - offset = ALIGN_UP(offset, 4); - } - } - - /* Return amount of buffer parsed: FV size. */ - return fv_length; -} - -ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size) -{ - size_t offset; - size_t fih_offset; - - offset = 0; - fih_offset = 0; - while (offset < size) { - ssize_t nparsed; - - /* Relocate each FV within the FSP region. The FSP_INFO_HEADER - * should only be located in the first FV. */ - if (offset == 0) - nparsed = relocate_fvh(new_addr, fsp, size, offset, - &fih_offset); - else - nparsed = relocate_fvh(new_addr, fsp, size, offset, - NULL); - - /* FV should be larger than 0 or failed to parse. */ - if (nparsed <= 0) { - printk(BIOS_ERR, "FV @ offset %zx relocation failed\n", - offset); - return -1; - } - - offset += nparsed; - } - - return relocate_remaining_items(fsp, size, new_addr, fih_offset); -} diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c index da0b341..80dc825 100644 --- a/src/drivers/intel/fsp1_1/fsp_relocate.c +++ b/src/drivers/intel/fsp1_1/fsp_relocate.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <cbmem.h> +#include <commonlib/fsp1_1.h> #include <fsp/util.h> int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src) diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h index 414532c..ec227b5 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/api.h +++ b/src/drivers/intel/fsp1_1/include/fsp/api.h @@ -20,8 +20,6 @@ #ifndef _FSP1_1_API_H_ #define _FSP1_1_API_H_ -#define FSP_SIG 0x48505346 /* 'FSPH' */ - /* All the FSP headers need to have UEFI types provided before inclusion. */ #include <fsp/uefi_binding.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 79c348a..b3772a2 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -53,12 +53,6 @@ void *get_first_resource_hob(const EFI_GUID *guid); */ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src); -/* - * Relocate FSP held within buffer defined by size to new_addr. Returns < 0 - * on error, offset to FSP_INFO_HEADER on success. - */ -ssize_t fsp1_1_relocate(uintptr_t new_addr, void *fsp, size_t size); - /* Additional HOB types not included in the FSP: * #define EFI_HOB_TYPE_HANDOFF 0x0001 * #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 diff --git a/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h b/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h index 47d463c..04d6d64 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h +++ b/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h @@ -22,6 +22,8 @@ #define FSPE_HEADER_REVISION_1 1 #define FSPP_HEADER_REVISION_1 1 +#define FSP_SIG 0x48505346 /* 'FSPH' */ + /// /// Fixed FSP header offset in the FSP image ///

1 0

New patch to review for coreboot: fsp1_1: use commonlib/endian.h routines
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11771 -gerrit commit 44120dc726410c8adc7dec38453448f7dbafa672 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 16:48:26 2015 -0500 fsp1_1: use commonlib/endian.h routines Now that the commonlib/endian.h routines have landed utilize those in the FSP relocation code. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: If431d64fd2843bea864d971ca1ea06b07c0d6435 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/fsp1_1_relocate.c | 123 +++++++++++++++-------------- 1 file changed, 62 insertions(+), 61 deletions(-) diff --git a/src/drivers/intel/fsp1_1/fsp1_1_relocate.c b/src/drivers/intel/fsp1_1/fsp1_1_relocate.c index d57a18c..994da09 100644 --- a/src/drivers/intel/fsp1_1/fsp1_1_relocate.c +++ b/src/drivers/intel/fsp1_1/fsp1_1_relocate.c @@ -18,9 +18,9 @@ */ #include <console/console.h> -#include <endian.h> -#include <fsp/api.h> -#include <fsp/util.h> +#include <commonlib/endian.h> +#include <commonlib/fsp1_1.h> +#include <commonlib/helpers.h> #include <stdlib.h> #include <stdint.h> #include <string.h> @@ -37,11 +37,11 @@ /* Return 0 if equal. Non-zero if not equal. */ static int guid_compare(const EFI_GUID *le_guid, const EFI_GUID *native_guid) { - if (le32toh(le_guid->Data1) != native_guid->Data1) + if (read_le32(&le_guid->Data1) != native_guid->Data1) return 1; - if (le16toh(le_guid->Data2) != native_guid->Data2) + if (read_le16(&le_guid->Data2) != native_guid->Data2) return 1; - if (le16toh(le_guid->Data3) != native_guid->Data3) + if (read_le16(&le_guid->Data3) != native_guid->Data3) return 1; return memcmp(le_guid->Data4, native_guid->Data4, ARRAY_SIZE(le_guid->Data4)); @@ -109,7 +109,7 @@ static size_t reloc_offset(uint16_t reloc_entry) return reloc_entry & ((1 << 12) - 1); } -static int te_relocate(uintptr_t new_addr, void *te, size_t size) +static int te_relocate(uintptr_t new_addr, void *te) { EFI_TE_IMAGE_HEADER *teih; EFI_IMAGE_DATA_DIRECTORY *relocd; @@ -124,9 +124,9 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size) teih = te; - if (le16toh(teih->Signature) != EFI_TE_IMAGE_HEADER_SIGNATURE) { + if (read_le16(&teih->Signature) != EFI_TE_IMAGE_HEADER_SIGNATURE) { printk(BIOS_ERR, "TE Signature mismatch: %x vs %x\n", - le16toh(teih->Signature), + read_le16(&teih->Signature), EFI_TE_IMAGE_HEADER_SIGNATURE); return -1; } @@ -138,21 +138,21 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size) * from the encoded offets. Similarly, the linked address of the * program is found by adding the fixup_offset to the ImageBase. */ - fixup_offset = le16toh(teih->StrippedSize); + fixup_offset = read_le16(&teih->StrippedSize); fixup_offset -= sizeof(EFI_TE_IMAGE_HEADER); /* Keep track of a base that is correctly adjusted so that offsets * can be used directly. */ te_base = te; te_base -= fixup_offset; - image_base = le64toh(teih->ImageBase); + image_base = read_le64(&teih->ImageBase); adj = new_addr - (image_base + fixup_offset); printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n", (void *)image_base, (void *)new_addr, adj); /* Adjust ImageBase for consistency. */ - teih->ImageBase = htole32(image_base + adj); + write_le64(&teih->ImageBase, (uint32_t)(image_base + adj)); relocd = &teih->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC]; @@ -160,19 +160,19 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size) /* Though the field name is VirtualAddress it's actually relative to * the beginning of the image which is linked at ImageBase. */ relocb = relative_offset(te, - le32toh(relocd->VirtualAddress) - fixup_offset); - while (relocd_offset < relocd->Size) { - size_t rva_offset = le32toh(relocb->VirtualAddress); + read_le32(&relocd->VirtualAddress) - fixup_offset); + while (relocd_offset < read_le32(&relocd->Size)) { + size_t rva_offset = read_le32(&relocb->VirtualAddress); printk(FSP_DBG_LVL, "Relocs for RVA offset %zx\n", rva_offset); - num_relocs = le32toh(relocb->SizeOfBlock) - sizeof(*relocb); + num_relocs = read_le32(&relocb->SizeOfBlock) - sizeof(*relocb); num_relocs /= sizeof(uint16_t); reloc = relative_offset(relocb, sizeof(*relocb)); printk(FSP_DBG_LVL, "Num relocs in block: %zx\n", num_relocs); while (num_relocs > 0) { - uint16_t reloc_val = le16toh(*reloc); + uint16_t reloc_val = read_le16(reloc); int type = reloc_type(reloc_val); size_t offset = reloc_offset(reloc_val); @@ -185,11 +185,11 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size) offset += rva_offset; reloc_addr = (void *)&te_base[offset]; - val = le32toh(*reloc_addr); + val = read_le32(reloc_addr); printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", reloc_addr, val, val + adj); - *reloc_addr = htole32(val + adj); + write_le32(reloc_addr, val + adj); } else if (type != EFI_IMAGE_REL_BASED_ABSOLUTE) { printk(BIOS_ERR, "Unknown reloc type: %x\n", type); @@ -200,9 +200,10 @@ static int te_relocate(uintptr_t new_addr, void *te, size_t size) } /* Track consumption of relocation directory contents. */ - relocd_offset += le32toh(relocb->SizeOfBlock); + relocd_offset += read_le32(&relocb->SizeOfBlock); /* Get next relocation block to process. */ - relocb = relative_offset(relocb, le32toh(relocb->SizeOfBlock)); + relocb = relative_offset(relocb, + read_le32(&relocb->SizeOfBlock)); } return 0; @@ -214,9 +215,9 @@ static size_t csh_size(const EFI_COMMON_SECTION_HEADER *csh) /* Unpack the array into a type that can be used. */ size = 0; - size |= le8toh(csh->Size[0]) << 0; - size |= le8toh(csh->Size[1]) << 8; - size |= le8toh(csh->Size[2]) << 16; + size |= read_le8(&csh->Size[0]) << 0; + size |= read_le8(&csh->Size[1]) << 8; + size |= read_le8(&csh->Size[2]) << 16; return size; } @@ -234,7 +235,7 @@ static size_t section_data_size(const EFI_COMMON_SECTION_HEADER *csh) size_t section_size; if (csh_size(csh) == 0x00ffffff) - section_size = le32toh(SECTION2_SIZE(csh)); + section_size = read_le32(&SECTION2_SIZE(csh)); else section_size = csh_size(csh); @@ -254,11 +255,11 @@ static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh) size_t size; if (IS_FFS_FILE2(ffsfh)) - size = le32toh(FFS_FILE2_SIZE(ffsfh)); + size = read_le32(&FFS_FILE2_SIZE(ffsfh)); else { - size = le8toh(ffsfh->Size[0]) << 0; - size |= le8toh(ffsfh->Size[1]) << 8; - size |= le8toh(ffsfh->Size[2]) << 16; + size = read_le8(&ffsfh->Size[0]) << 0; + size |= read_le8(&ffsfh->Size[1]) << 8; + size |= read_le8(&ffsfh->Size[2]) << 16; } return size; } @@ -273,33 +274,33 @@ static int relocate_patch_table(void *fsp, size_t size, size_t offset, table = relative_offset(fsp, offset); if ((offset + sizeof(*table) > size) || - (le16toh(table->header_length) + offset) > size) { + (read_le16(&table->header_length) + offset) > size) { printk(BIOS_ERR, "FSPP not entirely contained in region.\n"); return -1; } - num_entries = le32toh(table->patch_entry_num); + num_entries = read_le32(&table->patch_entry_num); printk(FSP_DBG_LVL, "FSPP relocs: %zx\n", num_entries); - for (num = 0; num < table->patch_entry_num; num++) { + for (num = 0; num < num_entries; num++) { uint32_t *reloc; uint32_t reloc_val; reloc = fspp_reloc(fsp, size, - le32toh(table->patch_entries[num])); + read_le32(&table->patch_entries[num])); if (reloc == NULL) { printk(BIOS_ERR, "Ignoring FSPP entry: %x\n", - le32toh(table->patch_entries[num])); + read_le32(&table->patch_entries[num])); continue; } - reloc_val = le32toh(*reloc); + reloc_val = read_le32(reloc); printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", reloc, reloc_val, (unsigned int)(reloc_val + adjustment)); - *reloc = htole32(reloc_val + adjustment); + write_le32(reloc, reloc_val + adjustment); } return 0; @@ -333,28 +334,28 @@ static ssize_t relocate_remaining_items(void *fsp, size_t size, return -1; } - if (le8toh(csh->Type) != EFI_SECTION_RAW) { + if (read_le8(&csh->Type) != EFI_SECTION_RAW) { printk(BIOS_ERR, "FIH file should have raw section: %x\n", - csh->Type); + read_le8(&csh->Type)); return -1; } - if (le32toh(fih->Signature) != FSP_SIG) { + if (read_le32(&fih->Signature) != FSP_SIG) { printk(BIOS_ERR, "Unexpected FIH signature: %08x\n", - le32toh(fih->Signature)); + read_le32(&fih->Signature)); return -1; } - adjustment = (intptr_t)new_addr - le32toh(fih->ImageBase); + adjustment = (intptr_t)new_addr - read_le32(&fih->ImageBase); /* Update ImageBase to reflect FSP's new home. */ - fih->ImageBase = htole32(adjustment + le32toh(fih->ImageBase)); + write_le32(&fih->ImageBase, adjustment + read_le32(&fih->ImageBase)); /* Need to find patch table and adjust each entry. The tables * following FSP_INFO_HEADER have a 32-bit signature and header * length. The patch table is denoted as having a 'FSPP' signature; * the table format doesn't follow the other tables. */ - offset = fih_offset + le32toh(fih->HeaderLength); + offset = fih_offset + read_le32(&fih->HeaderLength); while (offset + 2 * sizeof(uint32_t) <= size) { uint32_t *table_headers; @@ -363,8 +364,8 @@ static ssize_t relocate_remaining_items(void *fsp, size_t size, printk(FSP_DBG_LVL, "Checking offset %zx for 'FSPP'\n", offset); - if (le32toh(table_headers[0]) != FSPP_SIG) { - offset += le32toh(table_headers[1]); + if (read_le32(&table_headers[0]) != FSPP_SIG) { + offset += read_le32(&table_headers[1]); continue; } @@ -394,15 +395,15 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, offset = fvh_offset; fvh = relative_offset(fsp, offset); - if (le32toh(fvh->Signature) != EFI_FVH_SIGNATURE) + if (read_le32(&fvh->Signature) != EFI_FVH_SIGNATURE) return -1; - fv_length = le64toh(fvh->FvLength); + fv_length = read_le64(&fvh->FvLength); printk(FSP_DBG_LVL, "FVH length: %zx Offset: %zx Mapping length: %zx\n", fv_length, offset, fsp_size); - if (fvh->FvLength + offset > fsp_size) + if (fv_length + offset > fsp_size) return -1; /* Parse only this FV. However, the algorithm uses offsets into the @@ -414,19 +415,19 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, return -1; } - if (le16toh(fvh->ExtHeaderOffset) != 0) { + if (read_le16(&fvh->ExtHeaderOffset) != 0) { EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh; - offset += le16toh(fvh->ExtHeaderOffset); + offset += read_le16(&fvh->ExtHeaderOffset); fveh = relative_offset(fsp, offset); printk(FSP_DBG_LVL, "Extended Header Offset: %zx Size: %zx\n", - (size_t)le16toh(fvh->ExtHeaderOffset), - (size_t)le32toh(fveh->ExtHeaderSize)); - offset += le32toh(fveh->ExtHeaderSize); + (size_t)read_le16(&fvh->ExtHeaderOffset), + (size_t)read_le32(&fveh->ExtHeaderSize)); + offset += read_le32(&fveh->ExtHeaderSize); /* FFS files are 8 byte aligned after extended header. */ offset = ALIGN_UP(offset, 8); } else { - offset += le16toh(fvh->HeaderLength); + offset += read_le16(&fvh->HeaderLength); } file_offset = offset; @@ -440,12 +441,12 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, ffsfh = relative_offset(fsp, file_offset); - printk(FSP_DBG_LVL, "file type = %x\n", le8toh(ffsfh->Type)); + printk(FSP_DBG_LVL, "file type = %x\n", read_le8(&ffsfh->Type)); printk(FSP_DBG_LVL, "file attribs = %x\n", - le8toh(ffsfh->Attributes)); + read_le8(&ffsfh->Attributes)); /* Exit FV relocation when empty space found */ - if (le8toh(ffsfh->Type) == EFI_FV_FILETYPE_FFS_MAX) + if (read_le8(&ffsfh->Type) == EFI_FV_FILETYPE_FFS_MAX) break; /* Next file on 8 byte alignment. */ @@ -453,7 +454,7 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, file_offset = ALIGN_UP(file_offset, 8); /* Padding files have no section information. */ - if (le8toh(ffsfh->Type) == EFI_FV_FILETYPE_FFS_PAD) + if (read_le8(&ffsfh->Type) == EFI_FV_FILETYPE_FFS_PAD) continue; offset += file_section_offset(ffsfh); @@ -466,7 +467,7 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, printk(FSP_DBG_LVL, "section offset: %zx\n", offset); printk(FSP_DBG_LVL, "section type: %x\n", - le8toh(csh->Type)); + read_le8(&csh->Type)); data_size = section_data_size(csh); data_offset = section_data_offset(csh); @@ -485,7 +486,7 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, * relocated address based on the TE offset within * FSP proper. */ - if (le8toh(csh->Type) == EFI_SECTION_TE) { + if (read_le8(&csh->Type) == EFI_SECTION_TE) { void *te; size_t te_offset = offset + data_offset; uintptr_t te_addr = new_addr + te_offset; @@ -493,7 +494,7 @@ static ssize_t relocate_fvh(uintptr_t new_addr, void *fsp, size_t fsp_size, printk(FSP_DBG_LVL, "TE image at offset %zx\n", te_offset); te = relative_offset(fsp, te_offset); - te_relocate(te_addr, te, data_size); + te_relocate(te_addr, te); } offset += data_size + data_offset;

1 0

Patch set updated for coreboot: cbmem: add coreboot table records for each cbmem entry
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11757 -gerrit commit 0cc5f5920643c5127ef5a9bf0a99b33f2cfc2315 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 12:26:54 2015 -0500 cbmem: add coreboot table records for each cbmem entry In order to not expose the cbmem data structures to userland that are used by coreboot internally add each of the cbmem entries to a coreboot table record. The payload ABI uses coreboot tables so this just provides a shortcut for cbmem entries which were manually added previously by doing the work on behalf of all entries. A cursor structure and associated functions are added to the imd code for walking the entries in order to be placed in the coreboot tables. Additionally a struct lb_cbmem_entry is added that lists the base address, size, and id of the cbmem entry. BUG=chrome-os-partner:43731 BRANCH=None TEST=Booted glados. View coreboot table entries with cbmem. Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/include/commonlib/coreboot_tables.h | 13 +++++++ src/include/cbmem.h | 4 +-- src/include/imd.h | 16 +++++++++ src/lib/coreboot_table.c | 3 ++ src/lib/imd.c | 44 +++++++++++++++++++++++ src/lib/imd_cbmem.c | 43 ++++++++++++++++++++-- 6 files changed, 119 insertions(+), 4 deletions(-) diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 2ed4d7f..5e0c87c 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -308,6 +308,19 @@ struct lb_boot_media_params { uint64_t boot_media_size; }; +/* + * There can be more than one of these records as there is one per cbmem entry. + */ +#define LB_TAG_CBMEM_ENTRY 0x0031 +struct lb_cbmem_entry { + uint32_t tag; + uint32_t size; + + uint64_t address; + uint32_t entry_size; + uint32_t id; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 60de5a7..b34cf06 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -41,6 +41,7 @@ #ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> +#include <boot/coreboot_tables.h> struct cbmem_entry; @@ -118,12 +119,11 @@ typedef void (* const cbmem_init_hook_t)(int is_recovery); void cbmem_run_init_hooks(int is_recovery); void cbmem_fail_resume(void); -#ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); -#endif /* __PRE_RAM__ */ +void cbmem_add_records_to_cbtable(struct lb_header *header); #if ENV_RAMSTAGE #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ diff --git a/src/include/imd.h b/src/include/imd.h index a444b4f..b373ab5 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -124,6 +124,9 @@ size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry); /* Returns pointer to region described by entry or NULL on failure. */ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry); +/* Returns id for the imd entry. */ +uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry); + /* Attempt to remove entry from imd. */ int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry); @@ -136,6 +139,13 @@ struct imd_lookup { int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup, size_t size); +struct imd_cursor; +/* Initialize an imd_cursor object to walk the IMD entries. */ +int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor); + +/* Retrieve the next imd entry the cursor is referencing. Returns NULL when + * no more entries exist. */ +const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor); /* * The struct imd is a handle for working with an in-memory directory. @@ -152,4 +162,10 @@ struct imd { struct imdr sm; }; +struct imd_cursor { + size_t current_imdr; + size_t current_entry; + const struct imdr *imdr[2]; +}; + #endif /* _IMD_H_ */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6859bf2..1bd356d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -517,6 +517,9 @@ unsigned long write_coreboot_table( lb_boot_media_params(head); + /* Add all cbmem entries into the coreboot tables. */ + cbmem_add_records_to_cbtable(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } diff --git a/src/lib/imd.c b/src/lib/imd.c index 612e3f1..67a76a4 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -627,6 +627,11 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) return imdr_entry_at(imdr, entry); } +uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry) +{ + return entry->id; +} + int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry) { struct imd_root *r; @@ -702,3 +707,42 @@ int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup, return 0; } + +int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor) +{ + if (imd == NULL || cursor == NULL) + return -1; + + memset(cursor, 0, sizeof(*cursor)); + + cursor->imdr[0] = &imd->lg; + cursor->imdr[1] = &imd->sm; + + return 0; +} + +const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor) +{ + struct imd_root *r; + const struct imd_entry *e; + + if (cursor->current_imdr >= ARRAY_SIZE(cursor->imdr)) + return NULL; + + r = imdr_root(cursor->imdr[cursor->current_imdr]); + + if (r == NULL) + return NULL; + + if (cursor->current_entry >= r->num_entries) { + /* Try next imdr. */ + cursor->current_imdr++; + cursor->current_entry = 0; + return imd_cursor_next(cursor); + } + + e = &r->entries[cursor->current_entry]; + cursor->current_entry++; + + return e; +} diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index fa65334..d60acc9 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -267,7 +267,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) return imd_entry_at(imd, cbmem_to_imd(entry)); } -#if ENV_RAMSTAGE void cbmem_add_bootmem(void) { void *base = NULL; @@ -277,10 +276,50 @@ void cbmem_add_bootmem(void) bootmem_add_range((uintptr_t)base, size, LB_MEM_TABLE); } +#if ENV_RAMSTAGE +/* + * -fdata-sections doesn't work so well on read only strings. They all + * get put in the same section even though those strings may never be + * referenced in the final binary. + */ void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup)); } -#endif /* __PRE_RAM__ */ +#endif + +void cbmem_add_records_to_cbtable(struct lb_header *header) +{ + struct imd_cursor cursor; + struct imd *imd; + + imd = cbmem_get_imd(); + + if (imd_cursor_init(imd, &cursor)) + return; + + while (1) { + const struct imd_entry *e; + struct lb_cbmem_entry *lbe; + uint32_t id; + + e = imd_cursor_next(&cursor); + + if (e == NULL) + break; + + id = imd_entry_id(imd, e); + /* Don't add these metadata entries. */ + if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL) + continue; + + lbe = (struct lb_cbmem_entry *)lb_new_record(header); + lbe->tag = LB_TAG_CBMEM_ENTRY; + lbe->size = sizeof(*lbe); + lbe->address = (uintptr_t)imd_entry_at(imd, e); + lbe->entry_size = imd_entry_size(imd, e); + lbe->id = id; + } +}

1 0

Patch set updated for coreboot: util/cbmem: remove duplicated cbmem data structure logic.
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11758 -gerrit commit 1f76840ff6472428121a3d66e9fd53465ebf4602 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 12:33:01 2015 -0500 util/cbmem: remove duplicated cbmem data structure logic. The cbmem utility shouldn't be using the intra coreboot data structures for obtaining the produced data/information. Instead use the newly added cbmem records in the coreboot tables for pulling out the data one wants by using the generic indexing of coreboot table entries. BUG=chrome-os-partner:43731 BRANCH=None TEST=Interrogated cbmem table of contents with updated code. Change-Id: I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c --- util/cbmem/cbmem.c | 203 +++++++++++++++++++++-------------------------------- 1 file changed, 80 insertions(+), 123 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 74cb52d..3e4b8a0 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -60,8 +60,8 @@ static int verbose = 0; /* File handle used to access /dev/mem */ static int mem_fd; -/* IMD root pointer location */ -static uint64_t rootptr = 0; +static uint64_t lbtable_address; +static size_t lbtable_size; /* * calculate ip checksum (16 bit quantities) on a passed in buffer. In case @@ -171,9 +171,57 @@ static void *map_memory_size(u64 physical, size_t size) return v; } -static void *map_memory(u64 physical) +static void *map_lbtable(void) { - return map_memory_size(physical, MAP_BYTES); + if (lbtable_address == 0 || lbtable_size == 0) { + fprintf(stderr, "No coreboot table area found!\n"); + return NULL; + } + + return map_memory_size(lbtable_address, lbtable_size); +} + +static void unmap_lbtable(void) +{ + unmap_memory(); +} + +/* Find the first cbmem entry filling in the details. */ +static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size) +{ + uint8_t *table; + size_t offset; + int ret = -1; + + table = map_lbtable(); + + if (table == NULL) + return -1; + + offset = 0; + + while (offset < lbtable_size) { + struct lb_record *lbr; + struct lb_cbmem_entry *lbe; + + lbr = (void *)(table + offset); + offset += lbr->size; + + if (lbr->tag != LB_TAG_CBMEM_ENTRY) + continue; + + lbe = (void *)lbr; + if (lbe->id != id) + continue; + + *addr = lbe->address; + *size = lbe->entry_size; + ret = 0; + break; + } + + unmap_lbtable(); + return ret; } /* @@ -244,6 +292,11 @@ static int parse_cbtable(u64 address, size_t table_size) found = 1; debug("Found!\n"); + /* Keep reference to lbtable. */ + lbtable_address = address; + lbtable_address += ((uint8_t *)lbtable - (uint8_t *)lbh); + lbtable_size = lbh->table_bytes; + for (j = 0; j < lbh->table_bytes; j += lbr_p->size) { lbr_p = (struct lb_record*) ((char *)lbtable + j); debug(" coreboot table entry 0x%02x\n", lbr_p->tag); @@ -692,44 +745,6 @@ static void dump_cbmem_hex(void) hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size)); } -/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ -#define DYN_CBMEM_ALIGN_SIZE (4096) -#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE -#define CBMEM_POINTER_MAGIC 0xc0389481 -#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC) - -struct cbmem_root_pointer { - uint32_t magic; - /* Relative to upper limit/offset. */ - int32_t root_offset; -} __attribute__((packed)); - -struct dynamic_cbmem_entry { - uint32_t magic; - int32_t start_offset; - uint32_t size; - uint32_t id; -} __attribute__((packed)); - -struct cbmem_root { - uint32_t max_entries; - uint32_t num_entries; - uint32_t flags; - uint32_t entry_align; - int32_t max_offset; - struct dynamic_cbmem_entry entries[0]; -} __attribute__((packed)); - -#define CBMEM_MAGIC 0x434f5245 -#define MAX_CBMEM_ENTRIES 16 - -struct cbmem_entry { - uint32_t magic; - uint32_t id; - uint64_t base; - uint64_t size; -} __attribute__((packed)); - struct cbmem_id_to_name { uint32_t id; const char *name; @@ -758,74 +773,39 @@ void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) printf(" %08" PRIx64 "\n", size); } -static void dump_static_cbmem_toc(struct cbmem_entry *entries) +static void dump_cbmem_toc(void) { int i; + uint8_t *table; + size_t offset; - printf("CBMEM table of contents:\n"); - printf(" ID START LENGTH\n"); - - for (i=0; i<MAX_CBMEM_ENTRIES; i++) { - if (entries[i].magic != CBMEM_MAGIC) - break; - cbmem_print_entry(i, entries[i].id, - entries[i].base, entries[i].size); - } -} + table = map_lbtable(); -static void dump_dynamic_cbmem_toc(struct cbmem_root *root) -{ - int i; - debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n", - root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset); + if (table == NULL) + return; printf("CBMEM table of contents:\n"); printf(" ID START LENGTH\n"); - for (i = 0; i < root->num_entries; i++) { - if(root->entries[i].magic != CBMEM_ENTRY_MAGIC) - break; - cbmem_print_entry(i, root->entries[i].id, - rootptr + root->entries[i].start_offset, root->entries[i].size); - } -} - -static void dump_cbmem_toc(void) -{ - uint64_t start; - void *cbmem_area; - struct cbmem_entry *entries; + i = 0; + offset = 0; - if (cbmem.type != LB_MEM_TABLE) { - fprintf(stderr, "No coreboot CBMEM area found!\n"); - return; - } + while (offset < lbtable_size) { + struct lb_record *lbr; + struct lb_cbmem_entry *lbe; - start = unpack_lb64(cbmem.start); + lbr = (void *)(table + offset); + offset += lbr->size; - cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size)); - entries = (struct cbmem_entry *)cbmem_area; + if (lbr->tag != LB_TAG_CBMEM_ENTRY) + continue; - if (entries[0].magic == CBMEM_MAGIC) { - dump_static_cbmem_toc(entries); - } else { - rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size); - rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1); - rootptr -= sizeof(struct cbmem_root_pointer); - unmap_memory(); - struct cbmem_root_pointer *r = - map_memory_size(rootptr, sizeof(*r)); - if (r->magic == CBMEM_POINTER_MAGIC) { - struct cbmem_root *root; - uint64_t rootaddr = rootptr + r->root_offset; - unmap_memory(); - root = map_memory_size(rootaddr, ROOT_MIN_SIZE); - dump_dynamic_cbmem_toc(root); - } else - fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n"); + lbe = (void *)lbr; + cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size); + i++; } - unmap_memory(); + unmap_lbtable(); } #define COVERAGE_MAGIC 0x584d4153 @@ -857,42 +837,19 @@ static int mkpath(char *path, mode_t mode) static void dump_coverage(void) { - int i, found = 0; uint64_t start; - struct cbmem_entry *entries; + size_t size; void *coverage; unsigned long phys_offset; #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset) - if (cbmem.type != LB_MEM_TABLE) { - fprintf(stderr, "No coreboot table area found!\n"); + if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) { + fprintf(stderr, "No coverage information found\n"); return; } - start = unpack_lb64(cbmem.start); - - entries = (struct cbmem_entry *)map_memory(start); - - for (i=0; i<MAX_CBMEM_ENTRIES; i++) { - if (entries[i].magic != CBMEM_MAGIC) - break; - if (entries[i].id == CBMEM_ID_COVERAGE) { - found = 1; - break; - } - } - - if (!found) { - unmap_memory(); - fprintf(stderr, "No coverage information found in" - " CBMEM area.\n"); - return; - } - - start = entries[i].base; - unmap_memory(); /* Map coverage area */ - coverage = map_memory(start); + coverage = map_memory_size(start, size); phys_offset = (unsigned long)coverage - (unsigned long)start; printf("Dumping coverage data...\n");

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Patch merged into coreboot/master: tegra132/tegra210: remove verstage.c
by gerrit＠coreboot.org 02 Oct '15

02 Oct '15

the following patch was just integrated into master: commit 77051f108a88532c13792492d904599c1e453e32 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 13:29:15 2015 -0500 tegra132/tegra210: remove verstage.c I missed these Makefile.inc changes. As verstage.c was removed remove the references within the Makefile.incs. Change-Id: I5d38c0a87d057622a3706bf3bde1142944c3b17c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11759 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11759 for details. -gerrit

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Patch merged into coreboot/master: cbfstool: Add support for hashes as file metadata
by gerrit＠coreboot.org 01 Oct '15

01 Oct '15

the following patch was just integrated into master: commit 89f20340d5a4c14ab76d3612cd33fff8894602ec Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Oct 1 15:54:04 2015 +0200 cbfstool: Add support for hashes as file metadata They allow optimizing a verification of a whole CBFS image by only dealing with the headers (assuming you choose to trust the hash algorithm(s)). The format allows for multiple hashes for a single file, and cbfstool can handle them, but right now it can't generate such headers. Loosely based on Sol's work in http://review.coreboot.org/#/c/10147/, but using the compatible file attribute format. vboot is now a hard dependency of the build process, but we import it into the tree for quite a while now. Change-Id: I9f14f30537d676ce209ad612e7327c6f4810b313 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/11767 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11767 for details. -gerrit

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Patch merged into coreboot/master: kconfig: fix build for xconfig, too
by gerrit＠coreboot.org 01 Oct '15

01 Oct '15

the following patch was just integrated into master: commit 44853371f108b85a36775b72b894c93b24d7b7f7 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Oct 1 17:46:19 2015 +0200 kconfig: fix build for xconfig, too Change-Id: I1c5e3424cb56f1f10e75bb07db084c3500f3ba07 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/11768 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11768 for details. -gerrit

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Patch set updated for coreboot: northbridge/intel/gm45: Use IS_ENABLED macro to increase build coverage
by Audrey Pearson 01 Oct '15

01 Oct '15

Audrey Pearson (apearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11760 -gerrit commit c9e83aebdd8a503586e489d13a83339480cc507a Author: Audrey Pearson <apearson(a)raptorengineeringinc.com> Date: Wed Sep 30 14:44:13 2015 -0500 northbridge/intel/gm45: Use IS_ENABLED macro to increase build coverage Change-Id: I4bd689af5459b23ebc74c7623fefd56785af96f0 Signed-off-by: Audrey Pearson <apearson(a)raptorengineeringinc.com> --- src/northbridge/intel/gm45/gma.c | 780 +++++++++++++++++++-------------------- 1 file changed, 390 insertions(+), 390 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 42b340a..e661d5a 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -46,392 +46,392 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - static void power_port(u8 *mmio) { - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - write32(mmio + 0x00061100, 0x00010000); - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - read32(mmio + 0x00061100); // = 0x00000000 - read32(mmio + 0x00064200); // = 0x0000001c - write32(mmio + 0x00064210, 0x8004003e); - write32(mmio + 0x00064214, 0x80060002); - write32(mmio + 0x00064218, 0x01000000); - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - write32(mmio + 0x00064f00, 0x0100030c); - write32(mmio + 0x00064f04, 0x00b8230c); - write32(mmio + 0x00064f08, 0x06f8930c); - write32(mmio + 0x00064f0c, 0x09f8e38e); - write32(mmio + 0x00064f10, 0x00b8030c); - write32(mmio + 0x00064f14, 0x0b78830c); - write32(mmio + 0x00064f18, 0x0ff8d3cf); - write32(mmio + 0x00064f1c, 0x01e8030c); - write32(mmio + 0x00064f20, 0x0ff863cf); - write32(mmio + 0x00064f24, 0x0ff803cf); - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x00044000); // = 0x00000000 - write32(mmio + 0x00044030, 0x00001000); - read32(mmio + 0x00061150); // = 0x0000001c - write32(mmio + 0x00061150, 0x0000089c); - write32(mmio + 0x000fcc00, 0x01986f00); - write32(mmio + 0x000fcc0c, 0x01986f00); - write32(mmio + 0x000fcc18, 0x01986f00); - write32(mmio + 0x000fcc24, 0x01986f00); - read32(mmio + 0x00044000); // = 0x00000000 - read32(mmio + LVDS); // = 0x40000002 + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + read32(mmio + 0x00061100); // = 0x00000000 + write32(mmio + 0x00061100, 0x00000000); + write32(mmio + 0x00061100, 0x00010000); + read32(mmio + 0x00061100); // = 0x00010000 + read32(mmio + 0x00061100); // = 0x00010000 + read32(mmio + 0x00061100); // = 0x00000000 + write32(mmio + 0x00061100, 0x00000000); + read32(mmio + 0x00061100); // = 0x00000000 + read32(mmio + 0x00064200); // = 0x0000001c + write32(mmio + 0x00064210, 0x8004003e); + write32(mmio + 0x00064214, 0x80060002); + write32(mmio + 0x00064218, 0x01000000); + read32(mmio + 0x00064210); // = 0x5144003e + write32(mmio + 0x00064210, 0x5344003e); + read32(mmio + 0x00064210); // = 0x0144003e + write32(mmio + 0x00064210, 0x8074003e); + read32(mmio + 0x00064210); // = 0x5144003e + read32(mmio + 0x00064210); // = 0x5144003e + write32(mmio + 0x00064210, 0x5344003e); + read32(mmio + 0x00064210); // = 0x0144003e + write32(mmio + 0x00064210, 0x8074003e); + read32(mmio + 0x00064210); // = 0x5144003e + read32(mmio + 0x00064210); // = 0x5144003e + write32(mmio + 0x00064210, 0x5344003e); + read32(mmio + 0x00064210); // = 0x0144003e + write32(mmio + 0x00064210, 0x8074003e); + read32(mmio + 0x00064210); // = 0x5144003e + read32(mmio + 0x00064210); // = 0x5144003e + write32(mmio + 0x00064210, 0x5344003e); + write32(mmio + 0x00064f00, 0x0100030c); + write32(mmio + 0x00064f04, 0x00b8230c); + write32(mmio + 0x00064f08, 0x06f8930c); + write32(mmio + 0x00064f0c, 0x09f8e38e); + write32(mmio + 0x00064f10, 0x00b8030c); + write32(mmio + 0x00064f14, 0x0b78830c); + write32(mmio + 0x00064f18, 0x0ff8d3cf); + write32(mmio + 0x00064f1c, 0x01e8030c); + write32(mmio + 0x00064f20, 0x0ff863cf); + write32(mmio + 0x00064f24, 0x0ff803cf); + write32(mmio + 0x000c4030, 0x00001000); + read32(mmio + 0x00044000); // = 0x00000000 + write32(mmio + 0x00044030, 0x00001000); + read32(mmio + 0x00061150); // = 0x0000001c + write32(mmio + 0x00061150, 0x0000089c); + write32(mmio + 0x000fcc00, 0x01986f00); + write32(mmio + 0x000fcc0c, 0x01986f00); + write32(mmio + 0x000fcc18, 0x01986f00); + write32(mmio + 0x000fcc24, 0x01986f00); + read32(mmio + 0x00044000); // = 0x00000000 + read32(mmio + LVDS); // = 0x40000002 + } } static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + int i; + u8 edid_data[128]; + struct edid edid; + struct edid_mode *mode; + u32 hactive, vactive, right_border, bottom_border; + int hpolarity, vpolarity; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + + vga_gr_write(0x18, 0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } - int i; - u8 edid_data[128]; - struct edid edid; - struct edid_mode *mode; - u32 hactive, vactive, right_border, bottom_border; - int hpolarity, vpolarity; - u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; - u32 candp1, candn; - u32 best_delta = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00080000; - - vga_gr_write(0x18, 0); - - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } + write32(mmio + ADPA, 0x40008c18); + write32(mmio + 0x7041c, 0x0); + write32(mmio + _DPLL_B_MD, 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + power_port(mmio); + + intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); + decode_edid(edid_data, + sizeof(edid_data), &edid); + mode = &edid.mode; + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + + target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock + : (2 * mode->pixel_clock); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } - write32(mmio + ADPA, 0x40008c18); - write32(mmio + 0x7041c, 0x0); - write32(mmio + _DPLL_B_MD, 0x3); - - vga_misc_write(0x67); - - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); - - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - - power_port(mmio); - - intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); - decode_edid(edid_data, - sizeof(edid_data), &edid); - mode = &edid.mode; - - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; - vactive = edid.y_resolution; - right_border = mode->hborder; - bottom_border = mode->vborder; - hpolarity = (mode->phsync == '-'); - vpolarity = (mode->pvsync == '-'); - vsync = mode->vspw; - hsync = mode->hspw; - vblank = mode->vbl; - hblank = mode->hbl; - hfront_porch = mode->hso; - vfront_porch = mode->vso; - - target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -#else - vga_textmode_init(); -#endif - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesnt overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom + 60000) / 120000; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (120000 * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } } } - } - if (best_delta == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return; - } + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); - - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", - hactive, vactive); - printk(BIOS_DEBUG, "Borders %d x %d\n", - right_border, bottom_border); - printk(BIOS_DEBUG, "Blank %d x %d\n", - hblank, vblank); - printk(BIOS_DEBUG, "Sync %d x %d\n", - hsync, vsync); - printk(BIOS_DEBUG, "Front porch %d x %d\n", - hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock - ? "Spread spectrum clock\n" : "DREF clock\n")); - printk(BIOS_DEBUG, - info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); - printk(BIOS_DEBUG, "Polarities %d, %d\n", - hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); - - write32(mmio + LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); - mdelay(1); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(mmio + FP0(0), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - /* Re-lock the registers. */ - write32(mmio + PP_CONTROL, - (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - - write32(mmio + LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); - - write32(mmio + HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); - write32(mmio + PF_CTL(0),0); - write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0x20000000); -#else - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); -#endif - - mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); -#else - write32(mmio + VGACNTRL, 0x22c4008e); -#endif - - write32(mmio + TRANS_HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + TRANS_HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + TRANS_HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + TRANS_VTOTAL(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + TRANS_VBLANK(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + TRANS_VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + 0x00060100, 0xb01c4000); - write32(mmio + 0x000f000c, 0xb01a2050); - mdelay(1); - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC - ); - write32(mmio + LVDS, - LVDS_PORT_ENABLE - | (hpolarity << 20) | (vpolarity << 21) - | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); - - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); - mdelay(1); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS - | PANEL_POWER_ON | PANEL_POWER_RESET); - - printk (BIOS_DEBUG, "waiting for panel powerup\n"); - while (1) { - u32 reg32; - reg32 = read32(mmio + PP_STATUS); - if (((reg32 >> 28) & 3) == 0) - break; - } - printk (BIOS_DEBUG, "panel powered up\n"); + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(mmio + LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + mdelay(1); + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmio + FP0(0), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + /* Re-lock the registers. */ + write32(mmio + PP_CONTROL, + (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(mmio + LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + + write32(mmio + HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0x20000000); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + } + + mdelay(1); + + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f0008, 0x00000040); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0x22c4008e); + } + + write32(mmio + TRANS_HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + TRANS_HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + TRANS_HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + TRANS_VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + TRANS_VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + TRANS_VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + 0x00060100, 0xb01c4000); + write32(mmio + 0x000f000c, 0xb01a2050); + mdelay(1); + write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC + ); + write32(mmio + LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(mmio + PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); - write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); - set_vbe_mode_info_valid(&edid, lfb); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } + } } -#endif static void gma_func0_init(struct device *dev) { @@ -447,30 +447,30 @@ static void gma_func0_init(struct device *dev) struct northbridge_intel_gm45_config *conf = dev->chip_info; -#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); -#else - u32 physbase; - struct resource *lfb_res; - struct resource *pio_res; - - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base - && lfb_res && lfb_res->base) { - printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); - } + if (!CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) { + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); + } else { + u32 physbase; + struct resource *lfb_res; + struct resource *pio_res; + + lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); + + physbase = pci_read_config32(dev, 0x5c) & ~0xf; - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); -#endif + if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base + && lfb_res && lfb_res->base) { + printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, + pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); + } /* Post VBIOS init */ /* Enable Backlight */

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New patch to review for coreboot: kconfig: fix build for xconfig, too
by Patrick Georgi 01 Oct '15

01 Oct '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11768 -gerrit commit 2d8d66cfde1acbe95c00120dd6560c103da82ca0 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Oct 1 17:46:19 2015 +0200 kconfig: fix build for xconfig, too Change-Id: I1c5e3424cb56f1f10e75bb07db084c3500f3ba07 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/kconfig/qconf.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/kconfig/qconf.cc b/util/kconfig/qconf.cc index 9d3b04b..be1423e 100644 --- a/util/kconfig/qconf.cc +++ b/util/kconfig/qconf.cc @@ -54,6 +54,8 @@ # define _ qgettext #endif +int kconfig_warnings = 0; + static QApplication *configApp; static ConfigSettings *configSettings;

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coreboot-gerrit October 2015