coreboot-gerrit October 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: cbfstool: Allow anonymous structs/unions for older gcc versions
by gerrit＠coreboot.org 02 Oct '15

02 Oct '15

the following patch was just integrated into master: commit 8c3780a1423e5435178b989de25f015d785ee71e Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Oct 2 09:56:32 2015 +0200 cbfstool: Allow anonymous structs/unions for older gcc versions Older gcc versions throws a warning when a struct or union is declared without a valid name (anonymous). This patch enables the feature for older gcc versions so that no warning will be issued. Change-Id: Idc5481f4d5723c5090a6f7d7dbb0686a737e11fc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: http://review.coreboot.org/11779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11779 for details. -gerrit

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New patch to review for coreboot: cbfstool: Allow anonymous structs/unions for older gcc versions
by Werner Zeh 02 Oct '15

02 Oct '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11779 -gerrit commit f03d757bfb85af6ac4c70a6bc10a3dd949dee009 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Oct 2 09:56:32 2015 +0200 cbfstool: Allow anonymous structs/unions for older gcc versions Older gcc versions throws a warning when a struct or union is declared without a valid name (anonymous). This patch enables the feature for older gcc versions so that no warning will be issued. Change-Id: Idc5481f4d5723c5090a6f7d7dbb0686a737e11fc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- util/cbfstool/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 4994757..32c9282 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -60,6 +60,7 @@ TOOLCPPFLAGS += -DNEED_VB2_SHA_LIBRARY TOOLCPPFLAGS += -I$(top)/3rdparty/vboot/firmware/include TOOLCPPFLAGS += -I$(top)/3rdparty/vboot/firmware/2lib/include TOOLLDFLAGS ?= +HOSTCFLAGS += -fms-extensions ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32) TOOLCFLAGS += -mno-ms-bitfields

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Patch merged into coreboot/master: mc_tcu3: Remove dummy blocks from hwinfo.hex
by gerrit＠coreboot.org 02 Oct '15

02 Oct '15

the following patch was just integrated into master: commit f74d77a67371365149ab60b22a50c56a05d2f476 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Oct 1 13:36:24 2015 +0200 mc_tcu3: Remove dummy blocks from hwinfo.hex Remove dummy data from hwinfo.hex as it is not needed anymore in the system. Change-Id: I4f328a4ef61741039eb2c030e23fea33f539c2bb Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: http://review.coreboot.org/11763 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> See http://review.coreboot.org/11763 for details. -gerrit

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Patch merged into coreboot/master: mc_tcu3: Enable the usage of blobs.
by gerrit＠coreboot.org 02 Oct '15

02 Oct '15

the following patch was just integrated into master: commit 538c6c9ddfba65287e4da0d981ba77471fe949e3 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Oct 1 13:50:23 2015 +0200 mc_tcu3: Enable the usage of blobs. Since microcode was moved to 3rdparty/blobs, we need to select USE_BLOBS in Kconfig to get the submodule 3rdparty/blobs automaticaly. Change-Id: I25e574fd90b830448cacccd16d01a5a2dbc8517d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: http://review.coreboot.org/11764 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> See http://review.coreboot.org/11764 for details. -gerrit

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Patch set updated for coreboot: Add EM100 'hyper term' spi console support in ramstage & smm
by Martin Roth 02 Oct '15

02 Oct '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11743 -gerrit commit 4e2ed01d3d9a239afe702739942401582f6fdc66 Author: Martin Roth <martinroth(a)google.com> Date: Mon Sep 28 15:27:24 2015 -0600 Add EM100 'hyper term' spi console support in ramstage & smm The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 1 + src/console/Kconfig | 8 ++++ src/console/console.c | 3 ++ src/drivers/spi/Kconfig | 4 ++ src/drivers/spi/Makefile.inc | 5 +++ src/drivers/spi/spiconsole.c | 71 ++++++++++++++++++++++++++++++++ src/include/console/spi.h | 72 +++++++++++++++++++++++++++++++++ src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/braswell/Kconfig | 1 + src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 + src/southbridge/intel/lynxpoint/Kconfig | 1 + 12 files changed, 169 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 2c75750..868ed08 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -777,6 +777,7 @@ config DEBUG_SMI bool "Output verbose SMI debug messages" default n depends on HAVE_SMI_HANDLER + select SPI_FLASH_SMM if SPI_CONSOLE help This option enables additional SMI related debug messages. diff --git a/src/console/Kconfig b/src/console/Kconfig index 7d6fa0e..a2f893a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -211,6 +211,14 @@ config CONSOLE_QEMU_DEBUGCON_PORT depends on CONSOLE_QEMU_DEBUGCON default 0x402 +config SPI_CONSOLE + bool "SPI debug console output" + depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH + help + Enable support for the debug console on the Dediprog EM100Pro. + This is currently working only in ramstage due to how the spi + drivers are written. + choice prompt "Default console log level" default DEFAULT_CONSOLE_LOGLEVEL_8 diff --git a/src/console/console.c b/src/console/console.c index 00c0f1c..855de64 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -24,6 +24,7 @@ #include <console/streams.h> #include <console/uart.h> #include <console/usb.h> +#include <console/spi.h> #include <rules.h> void console_hw_init(void) @@ -35,6 +36,7 @@ void console_hw_init(void) __uart_init(); __ne2k_init(); __usbdebug_init(); + __spiconsole_init(); } void console_tx_byte(unsigned char byte) @@ -54,6 +56,7 @@ void console_tx_byte(unsigned char byte) __uart_tx_byte(byte); __ne2k_tx_byte(byte); __usb_tx_byte(byte); + __spiconsole_tx_byte(byte); } void console_tx_flush(void) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 4052bb4..dedb88f 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -137,3 +137,7 @@ config SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B to the chip on MOSI and data is received on both MOSI and MISO. endif # SPI_FLASH + +config HAVE_SPI_CONSOLE_SUPPORT + def_bool n + diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index ade34a2..6697c70 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -1,5 +1,10 @@ # SPI flash driver interface +ifeq ($(CONFIG_SPI_CONSOLE),y) +ramstage-y += spiconsole.c +smm-$(CONFIG_DEBUG_SMI) += spiconsole.c +endif + ifeq ($(CONFIG_COMMON_CBFS_SPI_WRAPPER),y) bootblock-y += spi_flash.c bootblock-$(CONFIG_SPI_FLASH_EON) += eon.c diff --git a/src/drivers/spi/spiconsole.c b/src/drivers/spi/spiconsole.c new file mode 100644 index 0000000..39a574c --- /dev/null +++ b/src/drivers/spi/spiconsole.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <spi-generic.h> +#include <spi_flash.h> +#include <console/spi.h> + +void spiconsole_init(void) { + spi_init(); + return; +} + +/* + * The EM100 'hyper terminal' specification defines a header of 9 characters. + * Because of this, devices with a spi_crop_chunk of less than 10 characters + * can't be supported by this standard. + * + * To add support in romstage, the static struct here and the ones used by + * spi_xfer will need to be modified - removed, or mapped into cbmem. + * + * Because the Dediprog software expects strings, not single characters, and + * because of the header overhead, this builds up a buffer to send. + */ +void spiconsole_tx_byte(unsigned char c) { + static struct em100_msg msg = { + .header.spi_command = EM100_DEDICATED_CMD, + .header.em100_command = EM100_UFIFO_CMD, + .header.msg_signature = EM100_MSG_SIGNATURE, + .header.msg_type = EM100_MSG_ASCII, + .header.msg_length = 0 + }; + + /* Verify the spi buffer is big enough to send even a single byte */ + if (spi_crop_chunk(0,MAX_MSG_LENGTH) < + sizeof(struct em100_msg_header) + 1) + return; + + msg.data[msg.header.msg_length] = c; + msg.header.msg_length++; + + /* Send the data on newline or when the max spi length is reached */ + if (c == '\n' || (sizeof(struct em100_msg_header) + + msg.header.msg_length == spi_crop_chunk(0, + MAX_MSG_LENGTH))) { + struct spi_slave spi = {.rw = SPI_READ_FLAG}; + + spi_xfer(&spi, &msg, sizeof(struct em100_msg_header) + + msg.header.msg_length, NULL, 0); + + msg.header.msg_length = 0; + } + + return; +} + diff --git a/src/include/console/spi.h b/src/include/console/spi.h new file mode 100644 index 0000000..c47fec5 --- /dev/null +++ b/src/include/console/spi.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef CONSOLE_SPI_H +#define CONSOLE_SPI_H 1 + +#include <rules.h> +#include <stdint.h> + +void spiconsole_init(void); +void spiconsole_tx_byte(unsigned char c); + +#define __CONSOLE_SPI_ENABLE__ CONFIG_SPI_CONSOLE && \ + (ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) + +#if __CONSOLE_SPI_ENABLE__ +static inline void __spiconsole_init(void) { spiconsole_init(); } +static inline void __spiconsole_tx_byte(u8 data) { spiconsole_tx_byte(data); } +#else +static inline void __spiconsole_init(void) {} +static inline void __spiconsole_tx_byte(u8 data) {} +#endif /* __CONSOLE_SPI_ENABLE__ */ + +#define MAX_MSG_LENGTH 128 + +#define EM100_DEDICATED_CMD 0x11 +#define EM100_UFIFO_CMD 0xC0 +#define EM100_MSG_SIGNATURE 0x47364440 + +enum em100_message_types { + EM100_MSG_CHECKPOINT_1B = 0x01, + EM100_MSG_CHECKPOINT_2B, + EM100_MSG_CHECKPOINT_4B, + EM100_MSG_HEX, + EM100_MSG_ASCII, + EM100_MSG_TIMESTAMP, + EM100_MSG_LOOKUP +}; + +struct em100_msg_header { + uint8_t spi_command; + uint8_t reserved; + uint8_t em100_command; + uint32_t msg_signature; + uint8_t msg_type; + uint8_t msg_length; +} __attribute__ ((packed)); + +struct em100_msg { + struct em100_msg_header header; + char data[MAX_MSG_LENGTH]; +} __attribute__ ((packed)); + + + +#endif /* CONSOLE_SPI_H */ diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 921f568..8de32de 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE + select HAVE_SPI_CONSOLE_SUPPORT config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index f76b9b2..5a41056 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select USE_GENERIC_FSP_CAR_INC select HAVE_INTEL_FIRMWARE + select HAVE_SPI_CONSOLE_SUPPORT config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6561fe2..33644e8 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select HAVE_SPI_CONSOLE_SUPPORT config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index d51a238..cc09e1f 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_INTEL_FIRMWARE + select HAVE_SPI_CONSOLE_SUPPORT config SOC_INTEL_FSP_BAYTRAIL_MD bool diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 3c8ae11..3221cff 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select HAVE_INTEL_FIRMWARE + select HAVE_SPI_CONSOLE_SUPPORT config INTEL_LYNXPOINT_LP bool

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New patch to review for coreboot: cbfstool: relocate FSP blobs on cbfstool add
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11778 -gerrit commit 393bdd983a0c7f4732f81216aefbcc2e96c32b71 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 1 17:02:45 2015 -0500 cbfstool: relocate FSP blobs on cbfstool add When adding an FSP blob relocate it to its final destination. This allows FSP to not be hard coded in the cbfs. In order for the include paths to work correctly w/ the edk 2 headers we need to supply a neutered ProcessorBind.h to match up with the tool environment such that one can get the UEFI Platform Initialization type definitions. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados and booted. Also added FSP with -b and manually adjusted location in fsp cache-as-ram. Booted as well. Change-Id: I830d93578fdf745a51195109cf18d94a83ee8cd3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/Makefile.inc | 10 ++++ util/cbfstool/ProcessorBind.h | 103 ++++++++++++++++++++++++++++++++++++++++++ util/cbfstool/cbfstool.c | 46 ++++++++++++++++++- 3 files changed, 158 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 4994757..093636a 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -10,6 +10,7 @@ cbfsobj += rmodule.o cbfsobj += xdr.o cbfsobj += fit.o cbfsobj += partitioned_file.o +cbfsobj += fsp1_1_relocate.o # LZMA cbfsobj += lzma.o cbfsobj += LzFind.o @@ -59,6 +60,11 @@ TOOLCPPFLAGS += -I$(top)/src/commonlib/include TOOLCPPFLAGS += -DNEED_VB2_SHA_LIBRARY TOOLCPPFLAGS += -I$(top)/3rdparty/vboot/firmware/include TOOLCPPFLAGS += -I$(top)/3rdparty/vboot/firmware/2lib/include +# UEFI header file support. It's not pretty, but that's what we currently +# have right now. +TOOLCPPFLAGS += -I$(top)/src +TOOLCPPFLAGS += -I$(top)/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include + TOOLLDFLAGS ?= ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32) @@ -89,6 +95,10 @@ $(objutil)/cbfstool/%.o: $(top)/3rdparty/vboot/firmware/2lib/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< +$(objutil)/cbfstool/%.o: $(top)/src/commonlib/%.c + printf " HOSTCC $(subst $(objutil)/,,$(@))\n" + $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + $(objutil)/cbfstool/cbfstool: $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) diff --git a/util/cbfstool/ProcessorBind.h b/util/cbfstool/ProcessorBind.h new file mode 100644 index 0000000..68463fb --- /dev/null +++ b/util/cbfstool/ProcessorBind.h @@ -0,0 +1,103 @@ +/** @file + Processor or Compiler specific defines and types for IA-32 architecture. + +Copyright 2015 Google Inc. +Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PROCESSOR_BIND_H__ +#define __PROCESSOR_BIND_H__ + + +/* + * This to mimic a processor binding for EDK. This is just to provide the + * processor types. + */ +#include <inttypes.h> + +/// +/// Define the processor type so other code can make processor based choices. +/// +#define MDE_CPU_IA32 + +/// +/// 8-byte unsigned value. +/// +typedef uint64_t UINT64; +/// +/// 8-byte signed value. +/// +typedef int64_t INT64; +/// +/// 4-byte unsigned value. +/// +typedef uint32_t UINT32; +/// +/// 4-byte signed value. +/// +typedef int32_t INT32; +/// +/// 2-byte unsigned value. +/// +typedef uint16_t UINT16; +/// +/// 2-byte Character. Unless otherwise specified all strings are stored in the +/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. +/// +typedef uint16_t CHAR16; +/// +/// 2-byte signed value. +/// +typedef int16_t INT16; +/// +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other +/// values are undefined. +/// +typedef unsigned char BOOLEAN; +/// +/// 1-byte unsigned value. +/// +typedef unsigned char UINT8; +/// +/// 1-byte Character +/// +typedef char CHAR8; +/// +/// 1-byte signed value +/// +typedef signed char INT8; + +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions; +/// 8 bytes on supported 64-bit processor instructions.) +/// +typedef uintptr_t UINTN; +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions; +/// 8 bytes on supported 64-bit processor instructions.) +/// +typedef intptr_t INTN; + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +// Not needed for non-runtime, but it shouldb +/// +//#define MAX_BIT 0x80000000 + +// No API requirements as this is not for runtime. +#define EFIAPI + +#endif + diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 2876702..8048c83 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -32,6 +32,7 @@ #include "cbfs_sections.h" #include "fit.h" #include "partitioned_file.h" +#include <commonlib/fsp1_1.h> #define SECTION_WITH_FIT_TABLE "BOOTBLOCK" @@ -387,6 +388,38 @@ static int cbfstool_convert_raw(struct buffer *buffer, return 0; } +static int cbfstool_convert_fsp(struct buffer *buffer, + uint32_t *offset, struct cbfs_file *header) +{ + uint32_t address; + struct buffer fsp; + + address = *offset; + + /* Ensure the address is a memory mapped one. */ + if (!IS_TOP_ALIGNED_ADDRESS(address)) + address = -convert_to_from_top_aligned(param.image_region, + address); + + /* Create a copy of the buffer to attempt relocation. */ + if (buffer_create(&fsp, buffer_size(buffer), "fsp")) + return -1; + + memcpy(buffer_get(&fsp), buffer_get(buffer), buffer_size(buffer)); + + /* Replace the buffer contents w/ the relocated ones on success. */ + if (fsp1_1_relocate(address, buffer_get(&fsp), buffer_size(&fsp)) > 0) { + buffer_delete(buffer); + buffer_clone(buffer, &fsp); + } else { + buffer_delete(&fsp); + WARN("FSP was not a 1.1 variant.\n"); + } + + /* Let the raw path handle all the cbfs metadata logic. */ + return cbfstool_convert_raw(buffer, offset, header); +} + static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset, struct cbfs_file *header) { @@ -472,12 +505,23 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer, static int cbfs_add(void) { int32_t address; + convert_buffer_t convert; if (param.alignment && param.baseaddress) { ERROR("Cannot specify both alignment and base address\n"); return 1; } + convert = cbfstool_convert_raw; + + /* Set the alignment to 4KiB minimum for FSP blobs when no base address + * is provided so that relocation can occur. */ + if (param.type == CBFS_COMPONENT_FSP) { + if (!param.baseaddress_assigned) + param.alignment = 4*1024; + convert = cbfstool_convert_fsp; + } + if (param.alignment) { /* CBFS compression file attribute is unconditionally added. */ size_t metadata_sz = sizeof(struct cbfs_file_attr_compression); @@ -491,7 +535,7 @@ static int cbfs_add(void) param.type, param.baseaddress, param.headeroffset, - cbfstool_convert_raw); + convert); } static int cbfs_add_stage(void)

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New patch to review for coreboot: vboot: provide CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL option
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11777 -gerrit commit 6c3cbff6cecd8594581662fe442a735b7a9c1612 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 1 16:27:55 2015 -0500 vboot: provide CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL option Certain chipsets provide their own main symbol for verstage. Therefore, it's necessary to know this so that those chipsets can leverage the common verstage flow. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built nyan using this option. Change-Id: If80784aa47b27f0ad286babcf0f42ce198b929e9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/Kconfig | 7 +++++++ src/vendorcode/google/chromeos/vboot2/verstage.c | 2 ++ 2 files changed, 9 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index c5c46e5..33c33a5 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -65,6 +65,13 @@ config RETURN_FROM_VERSTAGE reused by the succeeding stage. This is useful if a ram space is too small to fit both the verstage and the succeeding stage. +config CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL + bool "The chipset provides the main() entry point for verstage" + default n + depends on SEPARATE_VERSTAGE + help + The chipset code provides their own main() entry point. + # These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index # table is created by cros_bundle_firmware at build time based on the positions # of the blobs listed in fmap.dts and stored at the top of FW_MAIN_A/B region. diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c index 9556359..751f588 100644 --- a/src/vendorcode/google/chromeos/vboot2/verstage.c +++ b/src/vendorcode/google/chromeos/vboot2/verstage.c @@ -42,5 +42,7 @@ void verstage(void) } } +#if !IS_ENABLED(CONFIG_CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL) /* This is for boards that rely on main() for an entry point of a stage. */ void main(void) __attribute__((alias ("verstage"))); +#endif

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New patch to review for coreboot: tegra124: use the common verstage flow
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11776 -gerrit commit b82447c7634bcc9fe87e91770a2eea0798e9becb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 1 16:24:28 2015 -0500 tegra124: use the common verstage flow Though the tegra124 SoC makes their faster cpus come up in verstage it can still use the common flow. Therefore, use the common verstage API for performing thenecessary steps to initialize the caches on the faster cores. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built nyan. Change-Id: I93023ec92a9de111db688742b057b5c64143f0b3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/nvidia/tegra124/verstage.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 0012766..e2092e4 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -27,6 +27,7 @@ #include <soc/early_configs.h> #include <stdlib.h> #include <symbols.h> +#include <vendorcode/google/chromeos/chromeos.h> static void enable_cache(void) { @@ -40,27 +41,17 @@ static void enable_cache(void) dcache_mmu_enable(); } -/* Do the minimum to run vboot at full speed */ -static void soc_init(void) +void verstage_mainboard_init(void) { + /* Do the minimum to run vboot at full speed */ configure_l2_cache(); - console_init(); - exception_init(); enable_cache(); -} - -static void verstage(void) -{ - soc_init(); early_mainboard_init(); - run_romstage(); } void main(void) { asm volatile ("bl arm_init_caches" : : : "r0", "r1", "r2", "r3", "r4", "r5", "ip"); - verstage(); - hlt(); }

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New patch to review for coreboot: broadcom/cygnus: remove verstage.c
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11775 -gerrit commit be55648b90ab95196c7032168e29599dde7d6c0c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 1 16:23:16 2015 -0500 broadcom/cygnus: remove verstage.c The file was not referenced or used. Kill it. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I30285d523ef3ca4dd3ce38b53aeb42862d929c90 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/broadcom/cygnus/verstage.c | 32 -------------------------------- 1 file changed, 32 deletions(-) diff --git a/src/soc/broadcom/cygnus/verstage.c b/src/soc/broadcom/cygnus/verstage.c deleted file mode 100644 index 434ea34..0000000 --- a/src/soc/broadcom/cygnus/verstage.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/cache.h> -#include <arch/exception.h> -#include <console/console.h> -#include <program_loading.h> - -void main(void) -{ - void *entry; - - console_init(); - exception_init(); - run_romstage(); -}

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New patch to review for coreboot: cbfstool: provide printk() to cbfstool code
by Aaron Durbin 02 Oct '15

02 Oct '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11774 -gerrit commit a084e3715ce5848f13cd90aea7ef47340bda9627 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 1 14:25:19 2015 -0500 cbfstool: provide printk() to cbfstool code For shared compilation units between coreboot proper and cbfstool that means one needs to provide printk logging. Therefore, provide printk() at <console/console.h> to mimic coreboot's environment. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built cbfstool with code that includes and uses <console/console.h>. Change-Id: I8e54d403526a397e4fd117738a367a0a7bb71637 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/common.h | 10 ++------- util/cbfstool/console/console.h | 49 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 8 deletions(-) diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 86ae484..b638653 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -26,17 +26,11 @@ #include <string.h> #include <assert.h> +#include <console/console.h> + /* Endianess */ #include "swab.h" -/* Message output */ -extern int verbose; -#define ERROR(...) { fprintf(stderr, "E: " __VA_ARGS__); } -#define WARN(...) { fprintf(stderr, "W: " __VA_ARGS__); } -#define LOG(...) { fprintf(stderr, __VA_ARGS__); } -#define INFO(...) { if (verbose > 0) fprintf(stderr, "INFO: " __VA_ARGS__); } -#define DEBUG(...) { if (verbose > 1) fprintf(stderr, "DEBUG: " __VA_ARGS__); } - /* Helpers */ #define ARRAY_SIZE(a) (int)(sizeof(a) / sizeof((a)[0])) #define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) diff --git a/util/cbfstool/console/console.h b/util/cbfstool/console/console.h new file mode 100644 index 0000000..c51ab0a --- /dev/null +++ b/util/cbfstool/console/console.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _CBFSTOOL_CONSOLE_H_ +#define _CBFSTOOL_CONSOLE_H_ + +#include <stdio.h> +#include <commonlib/loglevel.h> + +/* Message output */ +extern int verbose; +#define ERROR(...) { fprintf(stderr, "E: " __VA_ARGS__); } +#define WARN(...) { fprintf(stderr, "W: " __VA_ARGS__); } +#define LOG(...) { fprintf(stderr, __VA_ARGS__); } +#define INFO(...) { if (verbose > 0) fprintf(stderr, "INFO: " __VA_ARGS__); } +#define DEBUG(...) { if (verbose > 1) fprintf(stderr, "DEBUG: " __VA_ARGS__); } + + +#define printk(lvl, ...) \ + { \ + if ((lvl) <= BIOS_ERR) { \ + ERROR(__VA_ARGS__); \ + } else if ((lvl) <= BIOS_NOTICE) { \ + WARN(__VA_ARGS__); \ + } else if ((lvl) <= BIOS_INFO) { \ + INFO(__VA_ARGS__); \ + } else if ((lvl) <= BIOS_DEBUG) { \ + DEBUG(__VA_ARGS__); \ + } \ + } + +#endif +

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coreboot-gerrit October 2015