coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 84e8e47 nvidia/ck804: Add ability to bypass register 0x78 initialization
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8272 -gerrit commit 84e8e472c2f256f59bc763ece88c5466c9df5f7b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 24 13:46:46 2015 -0600 nvidia/ck804: Add ability to bypass register 0x78 initialization Change-Id: I833603adea580cb3f4441e35044d1e17d2d67852 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/nvidia/ck804/early_setup_car.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 8a9c4c5..c135dc1 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -151,7 +151,9 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, CK804_MB_SETUP #endif +#ifndef CK804_SKIP_PCI_REG_78_INIT RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, +#endif RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,

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Patch set updated for coreboot: 2b51996 nvidia/ck804: Add ability to override CK804 base unit ID
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8273 -gerrit commit 2b51996d63872d53becce00ad0e04cdb1b117c91 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 24 13:45:52 2015 -0600 nvidia/ck804: Add ability to override CK804 base unit ID Change-Id: Ic1b35b6bdd9c6d9ab672242e40b73aff1d626e81 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/nvidia/ck804/bootblock.c | 4 ++++ src/southbridge/nvidia/ck804/early_setup.c | 4 ++++ src/southbridge/nvidia/ck804/early_setup_car.c | 2 ++ src/southbridge/nvidia/ck804/enable_usbdebug.c | 3 +++ 4 files changed, 13 insertions(+) diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 6e68404..45db5cb 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * Copyright (C) 2004 Tyan Computer * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * @@ -20,11 +22,13 @@ #include <arch/io.h> +#ifndef CK804_DEVN_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +#endif static void ck804_enable_rom(void) { diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index 84b6bfb..792644e 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * Copyright (C) 2004 Tyan Computer * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * @@ -76,11 +78,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, #define CK804_CHIP_REV 3 +#ifndef CK804_DEVN_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +#endif #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY #define CK804B_DEVN_BASE 1 diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index c135dc1..186424c 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -70,11 +70,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, #define CK804_CHIP_REV 3 +#ifndef CK804_DEVN_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +#endif #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY #define CK804B_DEVN_BASE 1 diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 97e8ecb..5bb16a3 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -5,6 +5,7 @@ * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * Copyright (C) 2006,2007 AMD * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,11 +31,13 @@ #include <device/pci_def.h> #include "ck804.h" +#ifndef CK804_DEVN_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +#endif pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) {

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Patch set updated for coreboot: cfe3876 ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8259 -gerrit commit cfe3876b416d5762fea7805685c54d68a4387c3e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:18:56 2015 -0600 ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Change-Id: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9 --- src/northbridge/amd/amdfam10/acpi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 463fb7c..9ffea36 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -187,6 +188,22 @@ void update_ssdtx(void *ssdtx, int i) void northbridge_acpi_write_vars(void) { + /* + * If more than one physical CPU is installed, northbridge_acpi_write_vars() + * is called more than once and the resultant SSDT table is corrupted + * (duplicated entries). + * This prevents Linux from booting, with log messages like these: + * ACPI Error: [BUSN] Namespace lookup failure, AE_ALREADY_EXISTS (/dswload-353) + * ACPI Exception: AE_ALREADY_EXISTS, During name lookup/catalog (/psobject-222) + * followed by a slew of ACPI method failures and a hang when the invalid PCI + * resource entries are used. + * This routine prevents the SSDT table from being corrupted. + */ + static uint8_t ssdt_generated = 0; + if (ssdt_generated) + return; + ssdt_generated = 1; + msr_t msr; char pscope[] = "\\_SB.PCI0"; int i;

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Patch set updated for coreboot: 3ac4c36 nvidia/ck804/lpc.c: Fix power restoration control
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8258 -gerrit commit 3ac4c368f9b8c9e31eb37c55d66c0b32a9619081 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:18:19 2015 -0600 nvidia/ck804/lpc.c: Fix power restoration control Control bits located by changing tristate power restoration value in proprietary BIOS, booting into Linux, dumping the entire CK804 configuration space, then comparing values against those dumped earlier. "Last state" control bit(s) are unknown at this time. TEST: Boot ASUS KFSN4-DRE with both coreboot power on and power off after power failure settings, then pull power plug / reinsert power plug and verify mainboard behaviour matches setting. Change-Id: I737bdd35632fe786968a1cb8458e56c785363cfa Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/nvidia/ck804/lpc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..b24da6d 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2003 Linux Networx * Copyright (C) 2003 SuSE Linux AG * Copyright (C) 2004 Tyan Computer @@ -40,9 +41,12 @@ #define NMI_OFF 0 -// 0x7a or e3 +// Power restoration control register is at 0x7a #define PREVIOUS_POWER_STATE 0x7A + // Auxiliary power control register possibly located at 0xe3 +#define PREVIOUS_POWER_STATE_AUX 0xe3 + #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 #define SLOW_CPU_OFF 0 @@ -123,9 +127,9 @@ static void lpc_init(device_t dev) on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x40; + byte &= ~0x45; if (!on) - byte |= 0x40; + byte |= 0x45; pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");

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Patch set updated for coreboot: 13e6118 device/device.c: Correct PCI register space location
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8261 -gerrit commit 13e611895da6f0eebd6d938d2ac14401c6f0ec9e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:20:56 2015 -0600 device/device.c: Correct PCI register space location Fix the incorrect PCI register space location causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems. Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/device/device.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/device/device.c b/src/device/device.c index 00e323a..94390b7 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -13,6 +13,7 @@ * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) * Copyright (C) 2005-2006 Stefan Reinauer <stepan(a)openbios.org> * Copyright (C) 2009 Myles Watson <mylesgw(a)gmail.com> + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering */ /* @@ -685,6 +686,25 @@ static void constrain_resources(struct device *dev, struct constraints* limits) } } +/* + * In this function there is a provision to shrink the potential PCI address + * space to the resource specified value. + * + * Without this the PCI address space attempts to reserve roughly all 32-bit + * addressable RAM, leading to allocation below the AMD fixed resource window + * instead of above it. When allocated below the fixed resource window it + * is not protected by the e820 map and the PCI configuration is overwritten, + * causing all PCI devices to become unusable! + * + * This bug is only exposed when the top of system RAM touches the bottom of + * the fixed resource window. If less than ~3.5GB of memory is installed there + * is a gap between system RAM and the fixed resource window which protects + * the incorrectly allocated PCI configuration registers and hides this bug. + * + * On non-AMD systems this may not matter as much, but the code below is generic + * and should not harm other systems. + */ + static void avoid_fixed_resources(struct device *dev) { struct constraints limits; @@ -712,6 +732,12 @@ static void avoid_fixed_resources(struct device *dev) if ((res->flags & MEM_MASK) == MEM_TYPE && (res->limit < limits.mem.limit)) limits.mem.limit = res->limit; + /* Shrink PCI address space */ + if ((res->flags & MEM_MASK) == MEM_TYPE && + (res->size < (limits.mem.limit - limits.mem.base + 1))) { + limits.mem.base = (limits.mem.limit - res->size + 1); + limits.mem.size = res->size; + } if ((res->flags & IO_MASK) == IO_TYPE && (res->limit < limits.io.limit)) limits.io.limit = res->limit;

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Patch set updated for coreboot: 44940ac amd/amdfam10: Fix reset during AMD Family 10h FID/VID setup
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8260 -gerrit commit 44940ac68042f57d7cda3031caa29ff5db743fc8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:19:44 2015 -0600 amd/amdfam10: Fix reset during AMD Family 10h FID/VID setup Reset was caused by invalid MSR access due to index off-by-one error. Verified against AMD BKDG. TEST: ASUS KFSN4-DRE booted K10 CPUs with proper FID/VID values. Change-Id: I943748a9a0389a75102675e1722ab3a7d1ce6a49 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/fidvid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index d3c67a9..ad31b8d 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -322,7 +323,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* Get PSmax's index */ msr = rdmsr(0xC0010061); - bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3); + bValue = (u8) (((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3) - 1); /* Get PSmax's VID */ msr = rdmsr(0xC0010064 + bValue);

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Patch merged into coreboot/master: 5ec1153 northbridge/amd: Add Kconfig options for ECC redirection
by gerrit＠coreboot.org 25 Jan '15

25 Jan '15

the following patch was just integrated into master: commit 5ec1153200c70138eb7ee9b36f5c1032bf310a22 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 24 14:13:30 2015 -0600 northbridge/amd: Add Kconfig options for ECC redirection Change-Id: I83e7605650b13e82a2e6c2822cbd237b4e473b5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8271 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8271 for details. -gerrit

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Patch merged into coreboot/master: 6f2caa0 northbridge/amd: Add Kconfig options for ECC scrub rate
by gerrit＠coreboot.org 25 Jan '15

25 Jan '15

the following patch was just integrated into master: commit 6f2caa0ffac653ae7455040429f70f71e9f38ccc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:24:30 2015 -0600 northbridge/amd: Add Kconfig options for ECC scrub rate Change-Id: Icbbba0037c19bdc279813e51c72f54a10e4dc55a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8263 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8263 for details. -gerrit

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New patch to review for coreboot: 78749ab ck804: make Message Signaled Interrupts work
by Jonathan A. Kollasch 25 Jan '15

25 Jan '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8276 -gerrit commit 78749aba4b7fabe5ef230b8d0cb1b899ebfcd025 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sun Jan 25 12:57:43 2015 -0600 ck804: make Message Signaled Interrupts work Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/nvidia/ck804/ht.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index 41e2998..b7a4826 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -52,11 +52,20 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif +static void ht_init(struct device *dev) +{ + u32 htmsi; + + htmsi = pci_read_config32(dev, 0xe0); + htmsi |= (1<<16); + pci_write_config32(dev, 0xe0, htmsi); +} + static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = ht_init, .scan_bus = 0, .ops_pci = &ck804_pci_ops, };

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Patch set updated for coreboot: 1f29668 amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8265 -gerrit commit 1f29668637fa8bbb43114ba2c571ef02aa956912 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:26:03 2015 -0600 amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM Remove declaration of unused variable `io`. Change-Id: I750fc3a135f7634ad16c0f6a1a5bdb16ac702977 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a8a8155..51cfee7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -858,7 +859,7 @@ static void setup_uma_memory(void) static void amdfam10_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; + struct resource *mem1, *mem2; struct resource *res; #endif unsigned long mmio_basek; @@ -914,7 +915,7 @@ static void amdfam10_domain_set_resources(device_t dev) mem2->base, mem2->limit, mem2->size, mem2->align); } - for(res = &dev->resource_list; res; res = res->next) + for(res = dev->resource_list; res; res = res->next) { res->flags |= IORESOURCE_ASSIGNED; res->flags |= IORESOURCE_STORED;

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coreboot-gerrit January 2015