coreboot-gerrit January 2015

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Patch set updated for coreboot: 77c04d0 mainboards: Add support for the Asus KFSN4-DRE series of motherboards
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8270 -gerrit commit 77c04d07aa22c8d6577fa5f1928cde457e0df693 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:35:48 2015 -0600 mainboards: Add support for the Asus KFSN4-DRE series of motherboards Status: Tested with KFSN4-DRE PCB v1.04G Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work. Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank). Video, network, USB, SATA, and serial have received thorough testing. Known issues: RAM initialization is a bit flaky with multiple high-density modules; this is probably a generic MCT training issue. The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device works after Linux boots and initializes the device. PCIe PME# does not function for an unknown reason, so Wake on Lan is broken. Suspend/resume are not yet functional pending additional work on the DSDT. Change-Id: I0709f822eea8ed877f55db9443143028a5400472 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/kfsn4-dre/Kconfig | 104 +++ src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl | 230 +++++++ src/mainboard/asus/kfsn4-dre/acpi_tables.c | 70 ++ src/mainboard/asus/kfsn4-dre/board_info.txt | 5 + src/mainboard/asus/kfsn4-dre/cmos.layout | 117 ++++ src/mainboard/asus/kfsn4-dre/devicetree.cb | 126 ++++ src/mainboard/asus/kfsn4-dre/dsdt.asl | 920 ++++++++++++++++++++++++++ src/mainboard/asus/kfsn4-dre/get_bus_conf.c | 133 ++++ src/mainboard/asus/kfsn4-dre/irq_tables.c | 208 ++++++ src/mainboard/asus/kfsn4-dre/mb_sysconf.h | 30 + src/mainboard/asus/kfsn4-dre/mptable.c | 156 +++++ src/mainboard/asus/kfsn4-dre/resourcemap.c | 282 ++++++++ src/mainboard/asus/kfsn4-dre/romstage.c | 369 +++++++++++ src/mainboard/asus/kfsn4-dre/spd_notes.txt | 34 + 15 files changed, 2787 insertions(+) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index edd8f5d..9bc4e35 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -33,6 +33,8 @@ config BOARD_ASUS_F2A85_M bool "F2A85-M" config BOARD_ASUS_F2A85_M_LE bool "F2A85-M LE" +config BOARD_ASUS_KFSN4_DRE + bool "KFSN4-DRE" config BOARD_ASUS_K8V_X bool "K8V-X" config BOARD_ASUS_M2N_E @@ -76,6 +78,7 @@ source "src/mainboard/asus/a8v-e_deluxe/Kconfig" source "src/mainboard/asus/f2a85-m/Kconfig" source "src/mainboard/asus/f2a85-m_le/Kconfig" source "src/mainboard/asus/k8v-x/Kconfig" +source "src/mainboard/asus/kfsn4-dre/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig new file mode 100644 index 0000000..de3f9b8 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -0,0 +1,104 @@ +if BOARD_ASUS_KFSN4_DRE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_SOCKET_F_1207 + select DIMM_DDR2 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_WINBOND_W83627THG + select PARALLEL_CPU_INIT + select HAVE_HARD_RESET + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select LIFT_BSP_APIC_ID + select BOARD_ROMSIZE_KB_1024 + select ENABLE_APIC_EXT_ID + select AMDMCT + select MMCONF_SUPPORT_DEFAULT + +config MAINBOARD_DIR + string + default asus/kfsn4-dre + +config DCACHE_RAM_BASE + hex + default 0xc4000 + +config DCACHE_RAM_SIZE + hex + default 0x0c000 + +config APIC_ID_OFFSET + hex + default 0 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "KFSN4-DRE" + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config PCI_64BIT_PREF_MEM + bool + default n + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config IRQ_SLOT_COUNT + int + default 13 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + +config CK804_PCI_E_X + int + default 1 + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "18ca:0020" + +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + default 0x06 + +endif # BOARD_ASUS_KFSN4_DRE diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl new file mode 100644 index 0000000..78c9e4d --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * WARNING: Sleep/Wake is a work in progress and does not yet function! + */ + + /* SuperIO control port */ + Name (SPIO, 0x2E) + + /* SuperIO control map */ + OperationRegion (IOID, SystemIO, SPIO, 0x02) + Field (IOID, ByteAcc, NoLock, Preserve) { + INDX, 8, + DATA, 8 + } + + /* SuperIO control registers */ + IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { + Offset (0x07), + } + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + , 7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + // FIXME + + Return(WKST) + } /* End Method(\_WAK) */ + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + // FIXME + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ \ No newline at end of file diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c new file mode 100644 index 0000000..85e01db --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c @@ -0,0 +1,70 @@ +/* + * ACPI support + * written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + */ + +#include <console/console.h> +#include <string.h> +#include <assert.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h> + +/* APIC */ +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + struct resource *res; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write NVIDIA CK804 IOAPIC. */ + dev = dev_find_slot(0x0, PCI_DEVFN(sysconf.sbdn + 0x1, 0)); + ASSERT(dev != NULL); + + res = find_resource(dev, PCI_BASE_ADDRESS_1); + ASSERT(res != NULL); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0); + + /* Initialize interrupt mapping if mptable.c didn't. */ +#if (!CONFIG_GENERATE_MP_TABLE) + /* Copied from mptable.c */ + /* Enable interrupts for commonly used devices (USB, SATA, etc.) */ + pci_write_config32(dev, 0x7c, 0x0d800018); + pci_write_config32(dev, 0x80, 0xd8002009); + pci_write_config32(dev, 0x84, 0x00000001); +#endif + +// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */ +// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) +// current, 0, 0, 2, 0); + /* IRQ9 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + /* IRQ14 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 14, 14, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + /* IRQ15 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 15, 15, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + + /* create all subtables for processors */ + /* acpi_create_madt_lapic_nmis returns current, not size. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} diff --git a/src/mainboard/asus/kfsn4-dre/board_info.txt b/src/mainboard/asus/kfsn4-dre/board_info.txt new file mode 100644 index 0000000..788888e --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/board_info.txt @@ -0,0 +1,5 @@ +Category: server +ROM package: PLCC-32 +ROM protocol: LPC +ROM socketed: y +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout new file mode 100644 index 0000000..1f1cab0 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -0,0 +1,117 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb new file mode 100644 index 0000000..d455675 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -0,0 +1,126 @@ +chip northbridge/amd/amdfam10/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1043 0x8162 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 on # Floppy + # Set up interface resources + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # Com1 + # Set up interface resources + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + # Set up interface resources + io 0x60 = 0x2f8 + irq 0x70 = 3 + # Select correct package I/O pins + io 0xf1 = 0x04 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + # Set up interface resources + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 2e.8 off end # GPIO 2 + device pnp 2e.9 on # GPIO 3, GPIO 4 + # Set GP37 to output + io 0xf0 = 0x7f + # Set GP37 + io 0xf1 = 0x80 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + # Set up interface resources + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM n-0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM n-0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM n-0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM n-1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM n-1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM n-1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM n-1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on end # SM 1 + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # AC'97 Audio (N/A) + device pci 4.1 off end # AC'97 Modem (N/A) + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 0 + device pci 8.0 on end # SATA 1 + device pci 9.0 on # Bridge + device pci 4.0 on end # VGA + end + device pci a.0 off end + device pci b.0 on # Bridge + device pci 0.0 on end # NIC A + end + device pci c.0 on # Bridge + device pci 0.0 on end # LSI SAS + end + device pci d.0 on # Bridge + device pci 0.0 on end # NIC B + end + device pci e.0 on # Bridge + # Slot # PCI E 0 + end + device pci f.0 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end +end diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl new file mode 100644 index 0000000..928b282 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -0,0 +1,920 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * WARNING: Sleep/Wake is a work in progress and does not yet function! + * Everything else does to the best of my knowledge... (T.P. 01/21/2015) + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +/* + * PCI link routing templates taken from ck804.asl and modified for this board + */ + +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) +{ + #include "northbridge/amd/amdfam10/amdfam10_util.asl" + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PICM, One) /* Assume APIC */ + + /* HPET control */ + Name (SHPB, 0xFED00000) + Name (SHPL, 0x1000) + + Scope (\_PR) + { + Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} + Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} + Processor (\_PR.CPU2, 0x02, 0x000000, 0x00) {} + Processor (\_PR.CPU3, 0x03, 0x000000, 0x00) {} + Processor (\_PR.CPU4, 0x04, 0x000000, 0x00) {} + Processor (\_PR.CPU5, 0x05, 0x000000, 0x00) {} + Processor (\_PR.CPU6, 0x06, 0x000000, 0x00) {} + Processor (\_PR.CPU7, 0x07, 0x000000, 0x00) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + /* Name (_S1, Package (0x04) { 0x01, 0x00, 0x00, 0x00 }) */ + /* Name (_S4, Package (0x04) { 0x06, 0x00, 0x00, 0x00 }) */ + Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) /* Hard power off */ + + /* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + Method (_PIC, 1, Serialized) { + Store (Arg0, PICM) + } + + /* _PR CPU0 is dynamically supplied by SSDT */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* VGA controller PME# */ + Method(_L00) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.VGAC, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L03) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB2 PME# */ + Method(_L05) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Slot PME# */ + Method(_L0B) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.PCIE.SLT1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.LSIC.SLT2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* USB0 PME# */ + Method(_L0D) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Keyboard controller PME# */ + Method(_L10) { + /* Level-Triggered GPE */ + Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* PCIe PME# */ + Method(_L11) { + /* Level-Triggered GPE */ + Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.PCIE, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PCI0.LSIC, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + } /* End Scope GPE */ + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device (CK804) */ + Device (PCI0) + { + /* BUS0 root bus */ + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180001) + Name (_UID, 0x00) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + External (CBST) + + /* PCI Routing Tables */ + Name (PR00, Package () { + /* PIC */ + /* ISA Bridge */ + Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, + + /* USB */ + Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, + + /* SATA 0 */ + Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, + + /* SATA 1 */ + Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x03, LNKA, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x03, LNKD, 0x00 }, + + /* LSI SAS Controller (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x03, LNKC, 0x00 }, + + /* PCI-E Slot (Bridge) */ + Package (0x04) { 0x000EFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x03, LNKB, 0x00 }, + }) + + Name (AR00, Package () { + /* APIC */ + /* ISA Bridge */ + Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 }, + + /* USB */ + Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 }, + + /* SATA 0 */ + Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 }, + + /* SATA 1 */ + Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 }, + + /* NIC A (Bridge) */ + Package (0x04) { 0x000BFFFF, 0x00, LNIB, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x01, LNIC, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x02, LNND, 0x00 }, + Package (0x04) { 0x000BFFFF, 0x03, LNIA, 0x00 }, + + /* NIC B (Bridge) */ + Package (0x04) { 0x000CFFFF, 0x00, LNIA, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x01, LNIB, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x02, LNIC, 0x00 }, + Package (0x04) { 0x000CFFFF, 0x03, LNND, 0x00 }, + + /* LSI SAS Controller (Bridge) */ + Package (0x04) { 0x000DFFFF, 0x00, LNND, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x01, LNIA, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x02, LNIB, 0x00 }, + Package (0x04) { 0x000DFFFF, 0x03, LNIC, 0x00 }, + + /* PCI-E Slot (Bridge) */ + Package (0x04) { 0x000EFFFF, 0x00, LNIC, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x01, LNND, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x02, LNIA, 0x00 }, + Package (0x04) { 0x000EFFFF, 0x03, LNIB, 0x00 }, + }) + + Name (PR01, Package () { + /* PIC */ + Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + }) + + Name (AR01, Package () { + /* APIC */ + Package (0x04) { 0x0004FFFF, 0x00, LNIA, 0x00 }, + }) + + Name (PR02, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 }, + }) + + Name (AR02, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIA, 0x00 }, + }) + + Name (PR03, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, + }) + + Name (AR03, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNND, 0x00 }, + }) + + Name (PR04, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 }, + }) + + Name (AR04, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIC, 0x00 }, + }) + + Name (PR05, Package () { + /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKB, 0x00 }, + }) + + Name (AR05, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, LNIC, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNND, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNIA, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNIB, 0x00 }, + }) + + /* PCI Resource Tables */ + + Name (RSIA, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {8} + }) + + Name (RSMA, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {16} + }) + + Name (RSIB, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {1} + }) + + Name (RSMB, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {17} + }) + + Name (RSIC, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {2} + }) + + Name (RSMC, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {18} + }) + + Name (RSND, ResourceTemplate () { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) {13} + }) + + Name (RSMD, ResourceTemplate () { + /* APIC */ + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {19} + }) + + Name (RSS2, ResourceTemplate () + { + /* PIC */ + IRQ (Level, ActiveLow, Shared, ) + {3, 4, 5, 7, 9, 10, 11, 12, 14, 15} + }) + + Name (RSA1, ResourceTemplate () + { + /* APIC */ + IRQ (Level, ActiveLow, Shared, ) + {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} + }) + + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods below use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + \_SB.GXXX(node, link) + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + +#include "southbridge/nvidia/ck804/acpi/ck804.asl" + + /* PCI Routing Table Access */ + Method (_PRT, 0, NotSerialized) { + If (PICM) { + Return (AR00) + } Else { + Return (PR00) + } + } + + /* USB0 */ + Device (LUB0) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTQ) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTQ) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (PRSC) + } Else { + Return (RSA1) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSC(\_SB.PCI0.LPCB.INTQ)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTQ)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ) + } + } + } + + /* USB2 */ + Device (LUB2) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTL) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTL) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (PRSC) + } Else { + Return (RSA1) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSC(\_SB.PCI0.LPCB.INTL)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTL)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL) + } + } + } + + /* ISA Bridge */ + Device (LKSM) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTK) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTK) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSA1) + } Else { + Return (RSS2) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTK)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTK)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTK) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK) + } + } + } + + /* Bridge device link (NIC A) */ + Device (LNIA) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTA) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTA) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMA) + } Else { + Return (RSIA) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTA)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTA)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA) + } + } + } + + /* Bridge device link (NIC B) */ + Device (LNIB) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTB) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTB) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMB) + } Else { + Return (RSIB) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTB)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTB)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB) + } + } + } + + /* Bridge device link */ + Device (LNIC) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTC) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTC) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMC) + } Else { + Return (RSIC) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTC)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTC)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC) + } + } + } + + /* Bridge device link */ + Device (LNND) + { + Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + + Method (_STA, 0, Serialized) { + If (\_SB.PCI0.LPCB.INTD) { + Return (0xb) + } Else { + Return (0x9) + } + } + Method (_DIS, 0, Serialized) { + Store (0, \_SB.PCI0.LPCB.INTD) + } + Method (_PRS, 0, Serialized) { + If (PICM) { + Return (RSMD) + } Else { + Return (RSND) + } + } + Method (_CRS, 0, Serialized) { + If (PICM) { + Return (CRSB(\_SB.PCI0.LPCB.INTD)) + } Else { + Return (CRSA(\_SB.PCI0.LPCB.INTD)) + } + } + Method (_SRS, 1, Serialized) { + If (PICM) { + Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD) + } Else { + Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD) + } + } + } + + /* 0:02.0 CK804 USB 0 */ + Device (USB0) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + + /* 0:02.0 CK804 USB 2 */ + Device (USB2) + { + Name (_ADR, 0x00020001) // _ADR: Address + } + + /* 1:04.0 VGA Controller */ + Device (VGAC) + { + Name (_ADR, 0x00090000) // _ADR: Address + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR01) + } Else { + Return (PR01) + } + } + } + + /* 2:00.0 PCIe NIC A */ + Device (NICA) + { + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR02) + } Else { + Return (PR02) + } + } + Device (BDC1) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 3:00.0 PCIe NIC B */ + Device (NICB) + { + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR03) + } Else { + Return (PR03) + } + } + Device (BDC2) + { + Name (_ADR, Zero) // _ADR: Address + } + } + + /* 4:00.0 PCIe LSI SAS Controller */ + Device (LSIC) + { + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR04) + } Else { + Return (PR04) + } + } + + Device (SLT2) + { + Name (_ADR, 0xFFFF) // _ADR: Address + } + } + + /* 5:00.0 PCIe x16 */ + Device (PCIE) + { + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR05) + } Else { + Return (PR05) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + } + } + + Device (LPC) { + Name (_HID, EisaId ("PNP0A05")) + Name (_ADR, 0x00010000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, EisaId ("PNP030B")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F03")) + Name (_CID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LP0) + { + Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (TMP, ResourceTemplate () { + FixedIO (0x0378, 0x10) + IRQNoFlags () {7} + }) + Return (TMP) + } + } + + /* Floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, Serialized) + { + Name (BUF0, ResourceTemplate () { + FixedIO (0x03F0, 0x08) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } +#if 0 + Device (HPET) + { + Name (_HID, EisaId ("PNP0103")) + Name (CRS, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, + 0x00001000, + _Y02) + IRQNoFlags () {0} + IRQNoFlags () {8} + }) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1) + CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2) + Store (ETBA, HPT1) + Store (ETBB, HPT2) + Return (CRS) + } + + } +#endif + } + } + + Device (PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } + +#include "acpi/pm_ctrl.asl" + +} diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c new file mode 100644 index 0000000..45ba408 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#if CONFIG_LOGICAL_CPUS +#include <cpu/amd/multicore.h> +#endif +#include <cpu/amd/amdfam10_sysconf.h> +#include <stdlib.h> + +/* + * Global variables for MB layouts and these will be shared by irqtable, + * mptable and acpi_tables. + */ +/* busnum is default */ +unsigned char bus_ck804[6]; +unsigned apicid_ck804; + +/* Here you only need to set value in pci1234 for HT-IO that could be +installed or not You may need to preset pci1234 for HTIO board, please +refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +static u32 pci1234x[] = { + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, + }; + + +/* HT Chain device num, actually it is unit id base of every ht device +in chain, assume every chain only have 4 ht device at most */ + +static unsigned hcdnx[] = { + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, +}; + +extern void get_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + unsigned apicid_base, sbdn; + device_t dev; + int i; + + if (get_bus_conf_done == 1) + return; /* Do it only once. */ + + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sbdn = sysconf.sbdn; + + for (i = 0; i < 6; i++) + bus_ck804[i] = 0; + + /* CK804 */ + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0)); + if (dev) { + bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_ck804[2]++; + } else { + printk + (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09); + bus_ck804[1] = 2; + bus_ck804[2] = 3; + } + + for (i = 2; i < 6; i++) { + dev = dev_find_slot(bus_ck804[0], + PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); + if (dev) { + bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804[0], sbdn + 0x0b + i - 2); + } + } + +#if CONFIG_LOGICAL_CPUS + apicid_base = get_apicid_base(1); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); +#endif + apicid_ck804 = apicid_base + 0; +} diff --git a/src/mainboard/asus/kfsn4-dre/irq_tables.c b/src/mainboard/asus/kfsn4-dre/irq_tables.c new file mode 100644 index 0000000..bcb58c2 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/irq_tables.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// WARNING +// These tables are INVALID for this mainboard! +// The ACPI tables are correct; a backport to these PIR tables is needed... + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern unsigned char bus_isa; +extern unsigned char bus_ck804[6]; + + +/** + * Add one line to IRQ table. + */ +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, + uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, + uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +/** + * Create the IRQ routing table. + * Values are derived from getpir generated code. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num, sbdn; + uint8_t *v, sum = 0; + int i; + + /* get_bus_conf() will find out all bus num and APIC that share with + * mptable.c and mptable.c. + */ + get_bus_conf(); + sbdn = sysconf.sbdn; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000. */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + pirq->rtr_bus = bus_ck804[0]; + pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; + pirq->exclusive_irqs = 0x828; + pirq->rtr_vendor = 0x10de; + pirq->rtr_device = 0x005c; + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* Slot1 PCIE 16x */ + write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, + 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); + pirq_info++; + slot_num++; + + + /* Slot2 PCIE 1x */ + write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); + pirq_info++; + slot_num++; + + /* Slot3 PCIE 1x */ + write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); + pirq_info++; + slot_num++; + + /* Slot4 PCIE 4x */ + write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); + pirq_info++; + slot_num++; + + /* Slot5 - Slot7 PCI */ + for (i = 0; i < 3; i++) { + write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0, + ((i + 0) % 4) + 1, 0xdeb8, + ((i + 1) % 4) + 1, 0xdeb8, + ((i + 2) % 4) + 1, 0xdeb8, + ((i + 3) % 4) + 1, 0xdeb8, i, 0); + pirq_info++; + slot_num++; + } + + /* PCI bridge */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); + pirq_info++; + slot_num++; + + /* SMBus */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* USB */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, + 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + +#if 0 + /* Audio */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; +#endif + + /* SATA */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + + /* SATA */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; + +#if 0 + /* On board NIC */ + write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1, + 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; +#endif + +#if 0 + /* Firewire? */ + write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdeb8, 0, + 0, 0, 0, 0, 0, 0, 0); + pirq_info++; + slot_num++; +#endif + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/kfsn4-dre/mb_sysconf.h b/src/mainboard/asus/kfsn4-dre/mb_sysconf.h new file mode 100644 index 0000000..ad78ef6 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/mb_sysconf.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MB_SYSCONF_H +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_mcp55[8]; //1 + unsigned apicid_mcp55; +}; + +#endif diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c new file mode 100644 index 0000000..b676cfc --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/mptable.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// WARNING +// These tables are INCOMPLETE for this mainboard! +// The ACPI tables are correct; a backport to these MP tables is needed... + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern unsigned char bus_ck804[6]; +extern unsigned apicid_ck804; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + unsigned sbdn; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + get_bus_conf(); + sbdn = sysconf.sbdn; + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + { + device_t dev; + struct resource *res; + + dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); + } + + /* Initialize interrupt mapping. */ + + /* + LPC bridge PCI config registers: + + 0x7c:0x0000ffff + - bitmap of masked pci irqs? + - PIRQ[ABCD] possibly? + + 0x7c:0x00f00000 + - sata at f8 - port 1 + + 0x7c:0x0f000000 + - sata at f7 - port 1 + + 0x80:0xf0000000 + - sata at f7 - port 0 + + 0x80:0x0f000000 + - sata at f8 - port 0 + + 0x80:0x0000f000 + - EHCI + + 0x84:0x00000f00 + - NIC + + 0x84:0x0000000f + - OHCI + + known values of nibbles: + + 0 - unrouted? + 1 - irq 23 + 8 - irq 20 + c - irq 12 + d - irq 21 + e - irq 14 + f - irq 15 + */ + + // Enable interrupts for commonly used devices (USB, SATA, etc.) + pci_write_config32(dev, 0x7c, 0x0d800018); + pci_write_config32(dev, 0x80, 0xd8002009); + pci_write_config32(dev, 0x84, 0x00000001); + } + } + + mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); + + // Onboard ck804 smbus + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, + 0xa); + + // Onboard ck804 USB 1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, + 0x15); + + // Onboard ck804 USB 2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, + 0x14); + + // Onboard ck804 SATA 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, + 0x17); + + // Onboard ck804 SATA 1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, + 0x16); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_ck804[0]); + + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c new file mode 100644 index 0000000..82fa667 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -0,0 +1,282 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void setup_mb_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00007000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00008033, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c new file mode 100644 index 0000000..c040092 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -0,0 +1,369 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 1 + +unsigned int get_sbdn(unsigned bus); + +#include <stdint.h> +#include <string.h> +#include <reset.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <lib.h> +#include <spd.h> +#include <cpu/amd/model_10xxx_rev.h> +#include "southbridge/nvidia/ck804/early_smbus.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "lib/delay.c" +#include <cpu/x86/lapic.h> +#include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <cpu/x86/bist.h> +// #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdfam10/debug.c" +#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +static void activate_spd_rom(const struct mem_controller *ctrl); + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/pci.c" +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +/* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x(). + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#define CK804_SKIP_PCI_REG_78_INIT 1 + +#define CK804_MB_SETUP \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ + +#include <southbridge/nvidia/ck804/early_setup_ss.h> +#include "southbridge/nvidia/ck804/early_setup_car.c" +#include <cpu/amd/microcode.h> + +#include "cpu/amd/model_10xxx/init_cpus.c" +#include "northbridge/amd/amdfam10/early_ht.c" + +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); + return (dev >> 15) & 0x1f; +} + +/* + * ASUS KFSN4-DRE specific SPD enable/disable magic. + * + * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the + * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD + * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which + * will make RAM init fail. + * + * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets + * which is required e.g. by lm-sensors. + */ + +#define CK804_BOARD_BOOT_BASE_UNIT_UID 1 + +static const unsigned int ctrl_conf_enable_spd_node0[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_enable_spd_node1[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_disable_spd[] = { + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ +}; + +static const unsigned int ctrl_conf_fix_pci_numbering[] = { + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */ +}; + +static const unsigned int ctrl_conf_enable_msi_mapping[] = { + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ +}; + +static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) +{ + unsigned busn[4], io_base[4]; + int i, ck804_num = 0; + + for (i = 0; i < 4; i++) { + u32 id; + device_t dev; + if (i == 0) /* SB chain */ + dev = PCI_DEV(i * 0x40, bus_unit_id, 0); + else + dev = 0; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (id == 0x005e10de) { + busn[ck804_num] = i * 0x40; + io_base[ck804_num] = i * 0x4000; + ck804_num++; + } + } + + if (ck804_num < 1) + printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); + + ck804_early_set_port(ck804_num, busn, io_base); + + setup_resource_map_x_offset(values, + size, + PCI_DEV(0, bus_unit_id, 0), io_base[0]); + + ck804_early_clear_port(ck804_num, busn, io_base); +} + +static void sio_setup(void) +{ + u32 dword; + u8 byte; + + /* Subject decoding */ + byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte); + + /* LPC Positive Decode 0 */ + dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0); + /* Serial 0, Serial 1 */ + dword |= (1 << 0) | (1 << 1); + pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword); +} + +static const uint8_t spd_addr[] = { + // Node 0 + RC00, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 + RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, +#endif +}; + +static void activate_spd_rom(const struct mem_controller *ctrl) { + printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); + if (ctrl->node_id == 0) { + printk(BIOS_DEBUG, "enable_spd_node0()\n"); + ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE); + } + else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); + ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE); + } +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sys_info *sysinfo = &sysinfo_car; + + u32 bsp_apicid = 0, val, wants_reset; + msr_t msr; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + sio_setup(); + } + + post_code(0x30); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + post_code(0x32); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + + post_code(0x33); + + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fix up prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ + wait_all_core0_started(); + +#if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); +#endif + + printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); + ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); + + post_code(0x38); + +#if CONFIG_SET_FIDVID + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); +#endif + + init_timer(); // Need to use TMICT to synconize FID/VID + + wants_reset = ck804_early_setup_x(); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + if (wants_reset) { + printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); + } + + post_code(0x3B); + + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + post_code(0x3D); + + printk(BIOS_DEBUG, "enable_smbus()\n"); + enable_smbus(); + +#if CONFIG_DEBUG_SMBUS + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); +#endif + + post_code(0x40); + + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + + printk(BIOS_DEBUG, "disable_spd()\n"); + ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); + + printk(BIOS_DEBUG, "enable_msi_mapping()\n"); + ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE); + + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. + post_code(0x43); // Should never see this post code. +} + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + return 0; +} diff --git a/src/mainboard/asus/kfsn4-dre/spd_notes.txt b/src/mainboard/asus/kfsn4-dre/spd_notes.txt new file mode 100644 index 0000000..06372f1 --- /dev/null +++ b/src/mainboard/asus/kfsn4-dre/spd_notes.txt @@ -0,0 +1,34 @@ +==================================================================================================== +SPD mux +==================================================================================================== + +DIMM_A1 SDA signal traced to U6 pin 1 +Destructive testing of failed board (removal of U7 northbridge!) yielded the following information: +U6 S0 <--> U7 W2 +U6 S1 <--> U7 W3 + +Proprietary BIOS enables the SPD during POST with: +S0: LOW +S1: LOW + +then temporarily switches to: +S0: LOW +S1: HIGH + +then switches to runtime mode with: +S0: HIGH +S1: LOW + +After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found: +CK804 pin W2 <--> GPIO43 +CK804 pin W3 <--> GPIO44 + +==================================================================================================== +Other hardware +==================================================================================================== + +CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10) +MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3) + +U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor) +PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD) \ No newline at end of file

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Patch set updated for coreboot: 429df72 nvidia/ck804: Add ability to bypass register 0x78 initialization
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8272 -gerrit commit 429df72bc599c4d080e651eca54fcd39aafdd16f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 24 13:46:46 2015 -0600 nvidia/ck804: Add ability to bypass register 0x78 initialization Change-Id: I833603adea580cb3f4441e35044d1e17d2d67852 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/nvidia/ck804/early_setup_car.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 8a9c4c5..c135dc1 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -151,7 +151,9 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, CK804_MB_SETUP #endif +#ifndef CK804_SKIP_PCI_REG_78_INIT RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, +#endif RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,

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Patch set updated for coreboot: 7ec53da nvidia/ck804: Add ability to override CK804 base unit ID
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8273 -gerrit commit 7ec53dac2b9c57b21782d7cc9b9614c7a5c3e499 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 24 13:45:52 2015 -0600 nvidia/ck804: Add ability to override CK804 base unit ID Change-Id: Ic1b35b6bdd9c6d9ab672242e40b73aff1d626e81 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/nvidia/ck804/bootblock.c | 4 ++++ src/southbridge/nvidia/ck804/early_setup.c | 4 ++++ src/southbridge/nvidia/ck804/early_setup_car.c | 2 ++ src/southbridge/nvidia/ck804/enable_usbdebug.c | 3 +++ 4 files changed, 13 insertions(+) diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 6e68404..45db5cb 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * Copyright (C) 2004 Tyan Computer * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * @@ -20,11 +22,13 @@ #include <arch/io.h> +#ifndef CK804_DEVN_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +#endif static void ck804_enable_rom(void) { diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index 84b6bfb..792644e 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * Copyright (C) 2004 Tyan Computer * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * @@ -76,11 +78,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, #define CK804_CHIP_REV 3 +#ifndef CK804_DEVN_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +#endif #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY #define CK804B_DEVN_BASE 1 diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index c135dc1..186424c 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -70,11 +70,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, #define CK804_CHIP_REV 3 +#ifndef CK804_DEVN_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +#endif #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY #define CK804B_DEVN_BASE 1 diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 97e8ecb..5bb16a3 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -5,6 +5,7 @@ * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * Copyright (C) 2006,2007 AMD * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,11 +31,13 @@ #include <device/pci_def.h> #include "ck804.h" +#ifndef CK804_DEVN_BASE #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif +#endif pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) {

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Patch set updated for coreboot: eb3150e ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8259 -gerrit commit eb3150e6cc6f8dfa7ea63ef37a97a575732b4789 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:18:56 2015 -0600 ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Change-Id: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9 --- src/northbridge/amd/amdfam10/acpi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 463fb7c..23308d8 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -187,6 +188,22 @@ void update_ssdtx(void *ssdtx, int i) void northbridge_acpi_write_vars(void) { + /* + * If more than one physical CPU is installed, northbridge_acpi_write_vars() + * is called more than once and the resultant SSDT table is corrupted + * (duplicated entries). + * This prevents Linux from booting, with log messages like these: + * ACPI Error: [BUSN] Namespace lookup failure, AE_ALREADY_EXISTS (/dswload-353) + * ACPI Exception: AE_ALREADY_EXISTS, During name lookup/catalog (/psobject-222) + * followed by a slew of ACPI method failures and a hang when the invalid PCI + * resource entries are used. + * This routine prevents the SSDT table from being corrupted. + */ + static char ssdt_generated = 0; + if (ssdt_generated) + return; + ssdt_generated = 1; + msr_t msr; char pscope[] = "\\_SB.PCI0"; int i;

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Patch set updated for coreboot: e86fe1e device/device.c: Correct PCI register space location
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8261 -gerrit commit e86fe1e676c2730391ba3b97cd41bbd3030ecf54 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:20:56 2015 -0600 device/device.c: Correct PCI register space location Fix the incorrect PCI register space location causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems. Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/device/device.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/device/device.c b/src/device/device.c index 00e323a..94390b7 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -13,6 +13,7 @@ * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) * Copyright (C) 2005-2006 Stefan Reinauer <stepan(a)openbios.org> * Copyright (C) 2009 Myles Watson <mylesgw(a)gmail.com> + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering */ /* @@ -685,6 +686,25 @@ static void constrain_resources(struct device *dev, struct constraints* limits) } } +/* + * In this function there is a provision to shrink the potential PCI address + * space to the resource specified value. + * + * Without this the PCI address space attempts to reserve roughly all 32-bit + * addressable RAM, leading to allocation below the AMD fixed resource window + * instead of above it. When allocated below the fixed resource window it + * is not protected by the e820 map and the PCI configuration is overwritten, + * causing all PCI devices to become unusable! + * + * This bug is only exposed when the top of system RAM touches the bottom of + * the fixed resource window. If less than ~3.5GB of memory is installed there + * is a gap between system RAM and the fixed resource window which protects + * the incorrectly allocated PCI configuration registers and hides this bug. + * + * On non-AMD systems this may not matter as much, but the code below is generic + * and should not harm other systems. + */ + static void avoid_fixed_resources(struct device *dev) { struct constraints limits; @@ -712,6 +732,12 @@ static void avoid_fixed_resources(struct device *dev) if ((res->flags & MEM_MASK) == MEM_TYPE && (res->limit < limits.mem.limit)) limits.mem.limit = res->limit; + /* Shrink PCI address space */ + if ((res->flags & MEM_MASK) == MEM_TYPE && + (res->size < (limits.mem.limit - limits.mem.base + 1))) { + limits.mem.base = (limits.mem.limit - res->size + 1); + limits.mem.size = res->size; + } if ((res->flags & IO_MASK) == IO_TYPE && (res->limit < limits.io.limit)) limits.io.limit = res->limit;

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Patch set updated for coreboot: e23b22a amd/amdfam10: Fix reset during AMD Family 10h FID/VID setup
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8260 -gerrit commit e23b22ae72a7c23af1e712bc147b3a989d4bc4e8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:19:44 2015 -0600 amd/amdfam10: Fix reset during AMD Family 10h FID/VID setup Reset was caused by invalid MSR access due to index off-by-one error. Verified against AMD BKDG. TEST: ASUS KFSN4-DRE booted K10 CPUs with proper FID/VID values. Change-Id: I943748a9a0389a75102675e1722ab3a7d1ce6a49 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/fidvid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index d3c67a9..ad31b8d 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -322,7 +323,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* Get PSmax's index */ msr = rdmsr(0xC0010061); - bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3); + bValue = (u8) (((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3) - 1); /* Get PSmax's VID */ msr = rdmsr(0xC0010064 + bValue);

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Patch set updated for coreboot: 0000721 northbridge/amd: Add Kconfig options for ECC scrub rate
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8263 -gerrit commit 000072168f24bc6cd07153e9d46aa0364ab01d80 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:24:30 2015 -0600 northbridge/amd: Add Kconfig options for ECC scrub rate Change-Id: Icbbba0037c19bdc279813e51c72f54a10e4dc55a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/Kconfig | 33 +++++++++++++++++++ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 49 +++++++++++++++------------- 2 files changed, 59 insertions(+), 23 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index e9b3796..ef8a16a 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -98,4 +98,37 @@ config LIMIT_HT_UP_WIDTH_16 bool "16 bits" endchoice +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + depends on CPU_AMD_MODEL_10XXX + default 0x00 + help + This option sets the background ECC memory scub rate + + Permissible values are: + + 0x00; Disabled + 0x01; 40ns + 0x02; 80ns + 0x03; 160ns + 0x04; 320ns + 0x05; 640ns + 0x06; 1.28us + 0x07; 2.56us + 0x08; 5.12us + 0x09; 10.2us + 0x0a; 20.5us + 0x0b; 41us + 0x0c; 81.9us + 0x0d; 163.8us + 0x0e; 327.7us + 0x0f; 655.4us + 0x10; 1.31ms + 0x11; 2.62ms + 0x12; 5.24ms + 0x13; 10.49ms + 0x14; 20.97sms + 0x15; 42ms + 0x16; 84ms + endmenu diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index e127322..96cef4e 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -171,29 +171,32 @@ static u16 mctGet_NVbits(u8 index) //val = 1; /* Enable */ break; case NV_DramBKScrub: - val = 0x00; /* Disabled */ - //val = 0x01; /* 40ns */ - //val = 0x02; /* 80ns */ - //val = 0x03; /* 160ns */ - //val = 0x04; /* 320ns */ - //val = 0x05; /* 640ns */ - //val = 0x06; /* 1.28us */ - //val = 0x07; /* 2.56us */ - //val = 0x08; /* 5.12us */ - //val = 0x09; /* 10.2us */ - //val = 0x0a; /* 20.5us */ - //val = 0x0b; /* 41us */ - //val = 0x0c; /* 81.9us */ - //val = 0x0d; /* 163.8us */ - //val = 0x0e; /* 327.7us */ - //val = 0x0f; /* 655.4us */ - //val = 0x10; /* 1.31ms */ - //val = 0x11; /* 2.62ms */ - //val = 0x12; /* 5.24ms */ - //val = 0x13; /* 10.49ms */ - //val = 0x14; /* 20.97sms */ - //val = 0x15; /* 42ms */ - //val = 0x16; /* 84ms */ + /* + * 0x00: Disabled + * 0x01: 40ns + * 0x02: 80ns + * 0x03: 160ns + * 0x04: 320ns + * 0x05: 640ns + * 0x06: 1.28us + * 0x07: 2.56us + * 0x08: 5.12us + * 0x09: 10.2us + * 0x0a: 20.5us + * 0x0b: 41us + * 0x0c: 81.9us + * 0x0d: 163.8us + * 0x0e: 327.7us + * 0x0f: 655.4us + * 0x10: 1.31ms + * 0x11: 2.62ms + * 0x12: 5.24ms + * 0x13: 10.49ms + * 0x14: 20.97sms + * 0x15: 42ms + * 0x16: 84ms + */ + val = CONFIG_AMDMCT_BACKGROUND_SCRUB_RATE; break; case NV_L2BKScrub: val = 0; /* Disabled - See L2Scrub in BKDG */

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Patch set updated for coreboot: 963ce0a amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8265 -gerrit commit 963ce0a6e1742825cec0a54ae24964f6b6ed0427 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:26:03 2015 -0600 amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM Remove declaration of unused variable `io`. Change-Id: I750fc3a135f7634ad16c0f6a1a5bdb16ac702977 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a8a8155..51cfee7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -858,7 +859,7 @@ static void setup_uma_memory(void) static void amdfam10_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; + struct resource *mem1, *mem2; struct resource *res; #endif unsigned long mmio_basek; @@ -914,7 +915,7 @@ static void amdfam10_domain_set_resources(device_t dev) mem2->base, mem2->limit, mem2->size, mem2->align); } - for(res = &dev->resource_list; res; res = res->next) + for(res = dev->resource_list; res; res = res->next) { res->flags |= IORESOURCE_ASSIGNED; res->flags |= IORESOURCE_STORED;

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Patch set updated for coreboot: 12d1ecb amd/amdfam10: Serialize mutable ASL methods
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8264 -gerrit commit 12d1ecba95dec72079870f5735deecb88dbb22da Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:25:15 2015 -0600 amd/amdfam10: Serialize mutable ASL methods Fix three IASL warnings in ASL utility code by making the methods `GWBM`, `GWEM` and `GIOR` serialized. TEST: Built and booted on ASUS KFSN4-DRE. Change-Id: Ia98088bea7e3e21c33252c98a675799d52edb809 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10_util.asl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl index 8e02510..a0f4170 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.asl +++ b/src/northbridge/amd/amdfam10/amdfam10_util.asl @@ -1,6 +1,7 @@ // // This file is part of the coreboot project. // +// Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering // Copyright (C) 2007 Advanced Micro Devices, Inc. // // This program is free software; you can redistribute it and/or modify @@ -122,7 +123,7 @@ Scope (\_SB) Return (0x00) } - Method (GWBN, 2, NotSerialized) + Method (GWBN, 2, Serialized) { Name (BUF0, ResourceTemplate () { @@ -161,7 +162,7 @@ Scope (\_SB) Return (RTAG (BUF0)) } - Method (GMEM, 2, NotSerialized) + Method (GMEM, 2, Serialized) { Name (BUF0, ResourceTemplate () { @@ -222,7 +223,7 @@ Scope (\_SB) Return (Local3) } - Method (GIOR, 2, NotSerialized) + Method (GIOR, 2, Serialized) { Name (BUF0, ResourceTemplate () {

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Patch set updated for coreboot: dd43ea9 northbridge/amd/amdht: Initialize variable `currentBUID`
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8267 -gerrit commit dd43ea98ecca015b6d3d39a866ad7858ddb206be Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:27:26 2015 -0600 northbridge/amd/amdht: Initialize variable `currentBUID` Fix uninitialized variable when manual non-coherent BUID selection is used. Change-Id: Id19745b29486aef5297fdbb3324ae36bf9b8f466 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/h3finit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index ff57033..88d5b6a 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -963,6 +964,7 @@ static void processLink(u8 node, u8 link, sMainData *pDat) && pDat->HtBlock->AMD_CB_ManualBUIDSwapList(node, link, &pSwapPtr)) { /* Manual non-coherent BUID assignment */ + currentBUID = 1; /* Assign BUID's per manual override */ while (*pSwapPtr != 0xFF)

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coreboot-gerrit January 2015