coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

1 participants
1236 discussions

Patch set updated for coreboot: 17e21b5 device/device.c: Correct PCI register space location
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8261 -gerrit commit 17e21b5fa1c3568fe0491e27549c03ce040f994f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:20:56 2015 -0600 device/device.c: Correct PCI register space location Fix the incorrect PCI register space location causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems. Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/device/device.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/device/device.c b/src/device/device.c index 00e323a..94390b7 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -13,6 +13,7 @@ * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) * Copyright (C) 2005-2006 Stefan Reinauer <stepan(a)openbios.org> * Copyright (C) 2009 Myles Watson <mylesgw(a)gmail.com> + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering */ /* @@ -685,6 +686,25 @@ static void constrain_resources(struct device *dev, struct constraints* limits) } } +/* + * In this function there is a provision to shrink the potential PCI address + * space to the resource specified value. + * + * Without this the PCI address space attempts to reserve roughly all 32-bit + * addressable RAM, leading to allocation below the AMD fixed resource window + * instead of above it. When allocated below the fixed resource window it + * is not protected by the e820 map and the PCI configuration is overwritten, + * causing all PCI devices to become unusable! + * + * This bug is only exposed when the top of system RAM touches the bottom of + * the fixed resource window. If less than ~3.5GB of memory is installed there + * is a gap between system RAM and the fixed resource window which protects + * the incorrectly allocated PCI configuration registers and hides this bug. + * + * On non-AMD systems this may not matter as much, but the code below is generic + * and should not harm other systems. + */ + static void avoid_fixed_resources(struct device *dev) { struct constraints limits; @@ -712,6 +732,12 @@ static void avoid_fixed_resources(struct device *dev) if ((res->flags & MEM_MASK) == MEM_TYPE && (res->limit < limits.mem.limit)) limits.mem.limit = res->limit; + /* Shrink PCI address space */ + if ((res->flags & MEM_MASK) == MEM_TYPE && + (res->size < (limits.mem.limit - limits.mem.base + 1))) { + limits.mem.base = (limits.mem.limit - res->size + 1); + limits.mem.size = res->size; + } if ((res->flags & IO_MASK) == IO_TYPE && (res->limit < limits.io.limit)) limits.io.limit = res->limit;

1 0

Patch set updated for coreboot: 10dbe8f amd/amdfam10: Fix reset during AMD Family 10h FID/VID setup
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8260 -gerrit commit 10dbe8f659296c9b903371f25c12d6c083a73677 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:19:44 2015 -0600 amd/amdfam10: Fix reset during AMD Family 10h FID/VID setup Reset was caused by invalid MSR access due to index off-by-one error. Verified against AMD BKDG. TEST: ASUS KFSN4-DRE booted K10 CPUs with proper FID/VID values. Change-Id: I943748a9a0389a75102675e1722ab3a7d1ce6a49 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/fidvid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index d3c67a9..ad31b8d 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -322,7 +323,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* Get PSmax's index */ msr = rdmsr(0xC0010061); - bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3); + bValue = (u8) (((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3) - 1); /* Get PSmax's VID */ msr = rdmsr(0xC0010064 + bValue);

1 0

Patch set updated for coreboot: 859e94c northbridge/amd: Add Kconfig options for ECC scrub rate
by Timothy Pearson 25 Jan '15

25 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8263 -gerrit commit 859e94c987c8692f8473b12b510cfb68a8c2c17a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:24:30 2015 -0600 northbridge/amd: Add Kconfig options for ECC scrub rate Change-Id: Icbbba0037c19bdc279813e51c72f54a10e4dc55a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/Kconfig | 33 +++++++++++++++++++ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 49 +++++++++++++++------------- 2 files changed, 59 insertions(+), 23 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index e9b3796..ef8a16a 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -98,4 +98,37 @@ config LIMIT_HT_UP_WIDTH_16 bool "16 bits" endchoice +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + depends on CPU_AMD_MODEL_10XXX + default 0x00 + help + This option sets the background ECC memory scub rate + + Permissible values are: + + 0x00; Disabled + 0x01; 40ns + 0x02; 80ns + 0x03; 160ns + 0x04; 320ns + 0x05; 640ns + 0x06; 1.28us + 0x07; 2.56us + 0x08; 5.12us + 0x09; 10.2us + 0x0a; 20.5us + 0x0b; 41us + 0x0c; 81.9us + 0x0d; 163.8us + 0x0e; 327.7us + 0x0f; 655.4us + 0x10; 1.31ms + 0x11; 2.62ms + 0x12; 5.24ms + 0x13; 10.49ms + 0x14; 20.97sms + 0x15; 42ms + 0x16; 84ms + endmenu diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index e127322..96cef4e 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -171,29 +171,32 @@ static u16 mctGet_NVbits(u8 index) //val = 1; /* Enable */ break; case NV_DramBKScrub: - val = 0x00; /* Disabled */ - //val = 0x01; /* 40ns */ - //val = 0x02; /* 80ns */ - //val = 0x03; /* 160ns */ - //val = 0x04; /* 320ns */ - //val = 0x05; /* 640ns */ - //val = 0x06; /* 1.28us */ - //val = 0x07; /* 2.56us */ - //val = 0x08; /* 5.12us */ - //val = 0x09; /* 10.2us */ - //val = 0x0a; /* 20.5us */ - //val = 0x0b; /* 41us */ - //val = 0x0c; /* 81.9us */ - //val = 0x0d; /* 163.8us */ - //val = 0x0e; /* 327.7us */ - //val = 0x0f; /* 655.4us */ - //val = 0x10; /* 1.31ms */ - //val = 0x11; /* 2.62ms */ - //val = 0x12; /* 5.24ms */ - //val = 0x13; /* 10.49ms */ - //val = 0x14; /* 20.97sms */ - //val = 0x15; /* 42ms */ - //val = 0x16; /* 84ms */ + /* + * 0x00: Disabled + * 0x01: 40ns + * 0x02: 80ns + * 0x03: 160ns + * 0x04: 320ns + * 0x05: 640ns + * 0x06: 1.28us + * 0x07: 2.56us + * 0x08: 5.12us + * 0x09: 10.2us + * 0x0a: 20.5us + * 0x0b: 41us + * 0x0c: 81.9us + * 0x0d: 163.8us + * 0x0e: 327.7us + * 0x0f: 655.4us + * 0x10: 1.31ms + * 0x11: 2.62ms + * 0x12: 5.24ms + * 0x13: 10.49ms + * 0x14: 20.97sms + * 0x15: 42ms + * 0x16: 84ms + */ + val = CONFIG_AMDMCT_BACKGROUND_SCRUB_RATE; break; case NV_L2BKScrub: val = 0; /* Disabled - See L2Scrub in BKDG */

1 0

Patch set updated for coreboot: 224ff6c amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8265 -gerrit commit 224ff6c2f3e3b610ea2cf3151faafec0ea2013a8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:26:03 2015 -0600 amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM Remove declaration of unused variable `io`. Change-Id: I750fc3a135f7634ad16c0f6a1a5bdb16ac702977 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a8a8155..51cfee7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -858,7 +859,7 @@ static void setup_uma_memory(void) static void amdfam10_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; + struct resource *mem1, *mem2; struct resource *res; #endif unsigned long mmio_basek; @@ -914,7 +915,7 @@ static void amdfam10_domain_set_resources(device_t dev) mem2->base, mem2->limit, mem2->size, mem2->align); } - for(res = &dev->resource_list; res; res = res->next) + for(res = dev->resource_list; res; res = res->next) { res->flags |= IORESOURCE_ASSIGNED; res->flags |= IORESOURCE_STORED;

1 0

Patch set updated for coreboot: f3a2599 amd/amdfam10: Serialize mutable ASL methods
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8264 -gerrit commit f3a259906c1323ff49c1aeeaa92366593500a548 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:25:15 2015 -0600 amd/amdfam10: Serialize mutable ASL methods Fix three IASL warnings in ASL utility code by making the methods `GWBM`, `GWEM` and `GIOR` serialized. TEST: Built and booted on ASUS KFSN4-DRE. Change-Id: Ia98088bea7e3e21c33252c98a675799d52edb809 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10_util.asl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl index 8e02510..a0f4170 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.asl +++ b/src/northbridge/amd/amdfam10/amdfam10_util.asl @@ -1,6 +1,7 @@ // // This file is part of the coreboot project. // +// Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering // Copyright (C) 2007 Advanced Micro Devices, Inc. // // This program is free software; you can redistribute it and/or modify @@ -122,7 +123,7 @@ Scope (\_SB) Return (0x00) } - Method (GWBN, 2, NotSerialized) + Method (GWBN, 2, Serialized) { Name (BUF0, ResourceTemplate () { @@ -161,7 +162,7 @@ Scope (\_SB) Return (RTAG (BUF0)) } - Method (GMEM, 2, NotSerialized) + Method (GMEM, 2, Serialized) { Name (BUF0, ResourceTemplate () { @@ -222,7 +223,7 @@ Scope (\_SB) Return (Local3) } - Method (GIOR, 2, NotSerialized) + Method (GIOR, 2, Serialized) { Name (BUF0, ResourceTemplate () {

1 0

Patch set updated for coreboot: 4803448 northbridge/amd/amdht: Initialize variable `currentBUID`
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8267 -gerrit commit 4803448eb2cb282bebe7a367022af0a52b3dd7b2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:27:26 2015 -0600 northbridge/amd/amdht: Initialize variable `currentBUID` Fix uninitialized variable when manual non-coherent BUID selection is used. Change-Id: Id19745b29486aef5297fdbb3324ae36bf9b8f466 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/h3finit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index ff57033..88d5b6a 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -963,6 +964,7 @@ static void processLink(u8 node, u8 link, sMainData *pDat) && pDat->HtBlock->AMD_CB_ManualBUIDSwapList(node, link, &pSwapPtr)) { /* Manual non-coherent BUID assignment */ + currentBUID = 1; /* Assign BUID's per manual override */ while (*pSwapPtr != 0xFF)

1 0

Patch set updated for coreboot: d8ad848 amd/amdfam10: Enhance resource debugging when enabled
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8266 -gerrit commit d8ad8488d46dbdc3a50797574f7c98926bba6760 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:26:31 2015 -0600 amd/amdfam10: Enhance resource debugging when enabled Change-Id: Ie39652bded9a42d1d816ca5198db59a83e5c083a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/setup_resource_map.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index ca7f964..8a7ef51 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -94,9 +96,15 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; where = register_values[i+1] & 0xfff; reg = pci_read_config32(dev, where); +#if RES_DEBUG + printk(BIOS_DEBUG, "WAS: %08x\n", reg); +#endif reg &= register_values[i+2]; reg |= register_values[i+3]; pci_write_config32(dev, where, reg); +#if RES_DEBUG + printk(BIOS_DEBUG, "NOW: %08x\n", reg); +#endif } break; case RES_PORT_IO_8: // io 8 @@ -105,9 +113,15 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset u32 reg; where = register_values[i+1] + offset_io_base; reg = inb(where); +#if RES_DEBUG + printk(BIOS_DEBUG, "WAS: %08x\n", reg); +#endif reg &= register_values[i+2]; reg |= register_values[i+3]; outb(reg, where); +#if RES_DEBUG + printk(BIOS_DEBUG, "NOW: %08x\n", reg); +#endif } break; case RES_PORT_IO_32: //io32 @@ -116,9 +130,15 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset u32 reg; where = register_values[i+1] + offset_io_base; reg = inl(where); +#if RES_DEBUG + printk(BIOS_DEBUG, "WAS: %08x\n", reg); +#endif reg &= register_values[i+2]; reg |= register_values[i+3]; outl(reg, where); +#if RES_DEBUG + printk(BIOS_DEBUG, "NOW: %08x\n", reg); +#endif } break; } // switch

1 0

Patch set updated for coreboot: 6c4cc64 nvidia/ck804: Fix FTBFS with AMD Family 10h systems
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8269 -gerrit commit 6c4cc647e32949012f37461119a86ee77fa30f5a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:29:46 2015 -0600 nvidia/ck804: Fix FTBFS with AMD Family 10h systems Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/nvidia/ck804/early_setup_car.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 9ba98c9..8a9c4c5 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * Copyright (C) 2004 Tyan Computer * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * @@ -18,6 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if IS_ENABLED( CONFIG_NORTHBRIDGE_AMD_AMDK8 ) static int set_ht_link_ck804(u8 ht_c_num) { unsigned vendorid = 0x10de; @@ -46,6 +49,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, val |= 1; outl(val, control); } +#endif #define ANACTRL_IO_BASE 0x3000 #define ANACTRL_REG_POS 0x68 @@ -297,6 +301,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); } +#if IS_ENABLED( CONFIG_NORTHBRIDGE_AMD_AMDK8 ) for (j = 0; j < ck804_num; j++) { /* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */ /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */ @@ -314,6 +319,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); } +#endif } static int ck804_early_setup_x(void) @@ -340,7 +346,11 @@ static int ck804_early_setup_x(void) ck804_early_setup(ck804_num, busn, io_base); ck804_early_clear_port(ck804_num, busn, io_base); +#if IS_ENABLED( CONFIG_NORTHBRIDGE_AMD_AMDK8 ) return set_ht_link_ck804(4); +#else + return 0; +#endif } void hard_reset(void)

1 0

Patch set updated for coreboot: 54d292e amd/amdht: Compile in multiprocessor support when selected
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8268 -gerrit commit 54d292e30c13ed085b4de6f928051250d2f68085 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:28:13 2015 -0600 amd/amdht: Compile in multiprocessor support when selected Fix multiprocessor support not being compiled in when selected via Kconfig on AMD systems. Change-Id: I44c22f2e11096247285b0fb469ccf51963eace2b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/ht_wrapper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 5742494..6a01e14 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -28,7 +29,7 @@ */ /* Single CPU system? */ -#if CONFIG_MAX_PHYSICAL_CPUS +#if (CONFIG_MAX_PHYSICAL_CPUS == 1) #define HT_BUILD_NC_ONLY 1 #endif

1 0

Patch set updated for coreboot: 2c83927 northbridge/amd: Add Kconfig options for ECC redirection
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8271 -gerrit commit 2c839271eeb252a0a9f60af563e2cbcd82a24778 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jan 24 14:13:30 2015 -0600 northbridge/amd: Add Kconfig options for ECC redirection Change-Id: I83e7605650b13e82a2e6c2822cbd237b4e473b5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/Kconfig | 5 +++++ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 7 +++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index ef8a16a..17f15c3 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -98,6 +98,11 @@ config LIMIT_HT_UP_WIDTH_16 bool "16 bits" endchoice +config AMDMCT_ENABLE_ECC_REDIR + bool + depends on CPU_AMD_MODEL_10XXX + default n + config AMDMCT_BACKGROUND_SCRUB_RATE hex depends on CPU_AMD_MODEL_10XXX diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 96cef4e..3615676 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -167,8 +167,11 @@ static u16 mctGet_NVbits(u8 index) #endif break; case NV_ECCRedir: - val = 0; /* Disable */ - //val = 1; /* Enable */ + /* + * 0: Disable + * 1: Enable + */ + val = CONFIG_AMDMCT_ENABLE_ECC_REDIR; break; case NV_DramBKScrub: /*

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2015