coreboot-gerrit September 2014

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Patch set updated for coreboot: 6160d12 snow: Rename snow to daisy.
by Isaac Christensen 23 Sep '14

23 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6929 -gerrit commit 6160d12dd259ee893876fdfd180034d557a86309 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jan 22 21:06:32 2014 -0800 snow: Rename snow to daisy. The name snow goes by in many places in chromeos is daisy. Snow is technically a variant of daisy and should really be called daisy_snow, but for historical reasons the daisy board with no variant was used instead. To make it easier to work with within chromeos, this change renames the snow board to daisy. Change-Id: I569b31bf417db55be91832f15271bea4bc30f163 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/183553 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 13f24d967251c18dce2a00bcea915f448c4c6aa7) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/Kconfig | 6 +- src/mainboard/google/daisy/Kconfig | 58 ++++ src/mainboard/google/daisy/Makefile.inc | 28 ++ src/mainboard/google/daisy/chromeos.c | 101 ++++++ src/mainboard/google/daisy/devicetree.cb | 33 ++ src/mainboard/google/daisy/exynos5250.h | 32 ++ src/mainboard/google/daisy/mainboard.c | 364 +++++++++++++++++++++ src/mainboard/google/daisy/memory.c | 545 +++++++++++++++++++++++++++++++ src/mainboard/google/daisy/romstage.c | 178 ++++++++++ src/mainboard/google/daisy/wakeup.c | 28 ++ src/mainboard/google/snow/Kconfig | 58 ---- src/mainboard/google/snow/Makefile.inc | 28 -- src/mainboard/google/snow/chromeos.c | 101 ------ src/mainboard/google/snow/devicetree.cb | 33 -- src/mainboard/google/snow/exynos5250.h | 32 -- src/mainboard/google/snow/mainboard.c | 364 --------------------- src/mainboard/google/snow/memory.c | 545 ------------------------------- src/mainboard/google/snow/romstage.c | 178 ---------- src/mainboard/google/snow/wakeup.c | 28 -- 19 files changed, 1370 insertions(+), 1370 deletions(-) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 538f0d8..3dbeada 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -25,6 +25,8 @@ config BOARD_GOOGLE_BOLT bool "Bolt" config BOARD_GOOGLE_BUTTERFLY bool "Butterfly" +config BOARD_GOOGLE_DAISY + bool "Daisy" config BOARD_GOOGLE_FALCO bool "Falco" config BOARD_GOOGLE_LINK @@ -45,8 +47,6 @@ config BOARD_GOOGLE_SAMUS bool "Samus" config BOARD_GOOGLE_SLIPPY bool "Slippy" -config BOARD_GOOGLE_SNOW - bool "Snow" config BOARD_GOOGLE_STOUT bool "Stout" @@ -54,6 +54,7 @@ endchoice source "src/mainboard/google/bolt/Kconfig" source "src/mainboard/google/butterfly/Kconfig" +source "src/mainboard/google/daisy/Kconfig" source "src/mainboard/google/falco/Kconfig" source "src/mainboard/google/link/Kconfig" source "src/mainboard/google/nyan/Kconfig" @@ -64,7 +65,6 @@ source "src/mainboard/google/pit/Kconfig" source "src/mainboard/google/rambi/Kconfig" source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" -source "src/mainboard/google/snow/Kconfig" source "src/mainboard/google/stout/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig new file mode 100644 index 0000000..41b37b3 --- /dev/null +++ b/src/mainboard/google/daisy/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_DAISY + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_SAMSUNG_EXYNOS5250 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_I2C + select BOARD_ROMSIZE_KB_4096 + select DRIVER_MAXIM_MAX77686 + select MAINBOARD_HAS_CHROMEOS + select DRIVER_TI_TPS65090 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT + +config MAINBOARD_DIR + string + default google/daisy + +config MAINBOARD_PART_NUMBER + string + default "Daisy" + +config MAX_CPUS + int + default 2 + +config DRAM_SIZE_MB + int + default 2048 + +config EC_GOOGLE_CHROMEEC_I2C_BUS + hex + default 4 + +config UART_FOR_CONSOLE + int + default 3 + +endif # BOARD_GOOGLE_DAISY diff --git a/src/mainboard/google/daisy/Makefile.inc b/src/mainboard/google/daisy/Makefile.inc new file mode 100644 index 0000000..df9b797 --- /dev/null +++ b/src/mainboard/google/daisy/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bootblock-y += wakeup.c + +romstage-y += memory.c +romstage-y += romstage.c +romstage-y += wakeup.c +romstage-y += chromeos.c + +ramstage-y += mainboard.c +ramstage-y += chromeos.c diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c new file mode 100644 index 0000000..f7443be --- /dev/null +++ b/src/mainboard/google/daisy/chromeos.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> +#include <soc/samsung/exynos5250/cpu.h> +#include <soc/samsung/exynos5250/gpio.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = EXYNOS5_GPD1; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active low */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Lid: active high */ + gpios->gpios[count].port = EXYNOS5_GPX3; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; + + /* Power: virtual GPIO active low */ + gpios->gpios[count].port = EXYNOS5_GPX1; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = + gpio_get_value(GPIO_X13); // POWER_GPIO + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + uint32_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_value(GPIO_D16); +} diff --git a/src/mainboard/google/daisy/devicetree.cb b/src/mainboard/google/daisy/devicetree.cb new file mode 100644 index 0000000..2552e07 --- /dev/null +++ b/src/mainboard/google/daisy/devicetree.cb @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/samsung/exynos5250 + device cpu_cluster 0 on end + register "xres" = "1366" + register "yres" = "768" + register "framebuffer_bits_per_pixel" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" +end diff --git a/src/mainboard/google/daisy/exynos5250.h b/src/mainboard/google/daisy/exynos5250.h new file mode 100644 index 0000000..0f71a36 --- /dev/null +++ b/src/mainboard/google/daisy/exynos5250.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* I2C */ +#define I2C_0_SPEED 100000 +#define I2C_SLAVE 0 + +/* Voltages */ +#define VDD_ARM_MV 1300 // 1.3V +#define VDD_INT_UV 1012500 // 1.0125V +#define VDD_MIF_MV 1000 // 1.0V +#define VDD_G3D_MV 1200 // 1.2V +#define VDD_LDO2_MV 1500 // 1.5V +#define VDD_LDO3_MV 1800 // 1.8V +#define VDD_LDO5_MV 1800 // 1.8V +#define VDD_LDO10_MV 1800 // 1.8V diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c new file mode 100644 index 0000000..0adadb6 --- /dev/null +++ b/src/mainboard/google/daisy/mainboard.c @@ -0,0 +1,364 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/i2c.h> +#include <drivers/ti/tps65090/tps65090.h> +#include <cbmem.h> +#include <delay.h> +#include <edid.h> +#include <vbe.h> +#include <boot/coreboot_tables.h> +#include <arch/cache.h> +#include <soc/samsung/exynos5250/tmu.h> +#include <soc/samsung/exynos5250/clk.h> +#include <soc/samsung/exynos5250/gpio.h> +#include <soc/samsung/exynos5250/power.h> +#include <soc/samsung/exynos5250/i2c.h> +#include <soc/samsung/exynos5250/dp-core.h> +#include <soc/samsung/exynos5250/dp.h> +#include <soc/samsung/exynos5250/usb.h> + +#include "exynos5250.h" + +#define MMC0_GPIO_PIN (58) + +/* convenient shorthand (in MB) */ +#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) +#define DRAM_SIZE CONFIG_DRAM_SIZE_MB +#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ + +/* Arbitrary range of DMA memory for depthcharge's drivers */ +#define DMA_START (0x77300000) +#define DMA_SIZE (0x00100000) + +static struct edid edid = { + .ha = 1366, + .va = 768, + .framebuffer_bits_per_pixel = 16, + .x_resolution = 1366, + .y_resolution = 768, + .bytes_per_line = 2 * 1366 +}; + +/* TODO: transplanted DP stuff, clean up once we have something that works */ +static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ +static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ +static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ + +static void exynos_dp_bridge_setup(void) +{ + exynos_pinmux_dphpd(); + + gpio_set_value(dp_pd_l, 1); + gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); + gpio_set_pull(dp_pd_l, GPIO_PULL_NONE); + + gpio_set_value(dp_rst_l, 0); + gpio_cfg_pin(dp_rst_l, GPIO_OUTPUT); + gpio_set_pull(dp_rst_l, GPIO_PULL_NONE); + udelay(10); + gpio_set_value(dp_rst_l, 1); +} + +static void exynos_dp_bridge_init(void) +{ + /* De-assert PD (and possibly RST) to power up the bridge */ + gpio_set_value(dp_pd_l, 1); + gpio_set_value(dp_rst_l, 1); + + /* + * We need to wait for 90ms after bringing up the bridge since + * there is a phantom "high" on the HPD chip during its + * bootup. The phantom high comes within 7ms of de-asserting + * PD and persists for at least 15ms. The real high comes + * roughly 50ms after PD is de-asserted. The phantom high + * makes it hard for us to know when the NXP chip is up. + */ + udelay(90000); +} + +static int exynos_dp_hotplug(void) +{ + /* Check HPD. If it's high, we're all good. */ + return gpio_get_value(dp_hpd) ? 0 : 1; +} + +static void exynos_dp_reset(void) +{ + gpio_set_value(dp_pd_l, 0); + gpio_set_value(dp_rst_l, 0); + /* paranoid delay period (300ms) */ + udelay(300 * 1000); +} + +/* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ +#define LCD_T3_DELAY_MS 60 + +#define LCD_T5_DELAY_MS 10 +#define LCD_T6_DELAY_MS 10 + +static void backlight_pwm(void) +{ + /*Configure backlight PWM as a simple output high (100% brightness) */ + gpio_direction_output(GPIO_B20, 1); + udelay(LCD_T6_DELAY_MS * 1000); +} + +static void backlight_en(void) +{ + /* Configure GPIO for LCD_BL_EN */ + gpio_direction_output(GPIO_X30, 1); +} + +#define TPS65090_BUS 4 /* Daisy-specific */ + +#define FET1_CTRL 0x0f +#define FET4_CTRL 0x12 +#define FET6_CTRL 0x14 + +static void lcd_vdd(void) +{ + /* Enable FET6, lcd panel */ + tps65090_fet_enable(TPS65090_BUS, FET6_CTRL); +} + +static void backlight_vdd(void) +{ + /* Enable FET1, backlight */ + tps65090_fet_enable(TPS65090_BUS, FET1_CTRL); + udelay(LCD_T5_DELAY_MS * 1000); +} + +static void sdmmc_vdd(void) +{ + /* Enable FET4, P3.3V_SDCARD */ + tps65090_fet_enable(TPS65090_BUS, FET4_CTRL); +} + +static enum exynos5_gpio_pin usb_host_vbus = GPIO_X11; +static enum exynos5_gpio_pin usb_drd_vbus = GPIO_X27; +/* static enum exynos5_gpio_pin hsic_reset_l = GPIO_E10; */ + +static void prepare_usb(void) +{ + /* Kick this reset off early so it gets at least 100ms to settle */ + reset_usb_drd_dwc3(); +} + +static void setup_usb(void) +{ + /* HSIC not needed in firmware on this board */ + setup_usb_drd_phy(); + setup_usb_drd_dwc3(); + setup_usb_host_phy(0); + + gpio_direction_output(usb_host_vbus, 1); + gpio_direction_output(usb_drd_vbus, 1); +} + +//static struct video_info smdk5250_dp_config = { +static struct video_info dp_video_info = { + /* FIXME: fix video_info struct to use const for name */ + .name = (char *)"eDP-LVDS NXP PTN3460", + + .h_sync_polarity = 0, + .v_sync_polarity = 0, + .interlaced = 0, + + .color_space = COLOR_RGB, + .dynamic_range = VESA, + .ycbcr_coeff = COLOR_YCBCR601, + .color_depth = COLOR_8, + + .link_rate = LINK_RATE_2_70GBPS, + .lane_count = LANE_COUNT2, +}; + +/* FIXME: move some place more appropriate */ +#define MAX_DP_TRIES 5 + +/* + * This function disables the USB3.0 PLL to save power + */ +static void disable_usb30_pll(void) +{ + enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11; + + gpio_direction_output(usb3_pll_l, 0); +} + +static void setup_storage(void) +{ + /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ + if (clock_set_mshci(PERIPH_ID_SDMMC0)) + printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); + if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { + printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__); + } + gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE); + gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X); + exynos_pinmux_sdmmc0(); + + /* MMC2: Removable, 4 bit mode, no GPIO. */ + /* (Must be after romstage to avoid breaking SDMMC boot.) */ + clock_set_mshci(PERIPH_ID_SDMMC2); + exynos_pinmux_sdmmc2(); +} + +static void gpio_init(void) +{ + /* Set up the I2C busses. */ + exynos_pinmux_i2c0(); + exynos_pinmux_i2c1(); + exynos_pinmux_i2c2(); + exynos_pinmux_i2c3(); + exynos_pinmux_i2c4(); + exynos_pinmux_i2c7(); + + /* Set up the GPIOs used to arbitrate for I2C bus 4. */ + gpio_set_pull(GPIO_F03, GPIO_PULL_NONE); + gpio_set_pull(GPIO_E04, GPIO_PULL_NONE); + gpio_direction_output(GPIO_F03, 1); + gpio_direction_input(GPIO_E04); + + /* Set up the GPIO used to enable the audio codec. */ + gpio_set_pull(GPIO_X17, GPIO_PULL_NONE); + gpio_set_pull(GPIO_X15, GPIO_PULL_NONE); + gpio_direction_output(GPIO_X17, 1); + gpio_direction_output(GPIO_X15, 1); + + /* Set up the I2S busses. */ + exynos_pinmux_i2s0(); + exynos_pinmux_i2s1(); +} + +/* this happens after cpu_init where exynos resources are set */ +static void mainboard_init(device_t dev) +{ + int dp_tries; + struct s5p_dp_device dp_device = { + .base = exynos_dp1, + .video_info = &dp_video_info, + }; + void *fb_addr = (void *)(get_fb_base_kb() * KiB); + + prepare_usb(); + gpio_init(); + setup_storage(); + + i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE); + i2c_init(7, I2C_0_SPEED, I2C_SLAVE); + + tmu_init(&exynos5250_tmu_info); + + /* Clock Gating all the unused IP's to save power */ + clock_gate(); + + /* Disable USB3.0 PLL to save 250mW of power */ + disable_usb30_pll(); + + sdmmc_vdd(); + + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + + lcd_vdd(); + + // FIXME: should timeout + do { + udelay(50); + } while (!exynos_dp_hotplug()); + + exynos_dp_bridge_setup(); + for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { + exynos_dp_bridge_init(); + if (exynos_dp_hotplug()) { + exynos_dp_reset(); + continue; + } + + if (dp_controller_init(&dp_device)) + continue; + + udelay(LCD_T3_DELAY_MS * 1000); + + backlight_vdd(); + backlight_pwm(); + backlight_en(); + /* if we're here, we're successful */ + break; + } + + if (dp_tries > MAX_DP_TRIES) + printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); + + setup_usb(); + + // Uncomment to get excessive GPIO output: + // gpio_info(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; + + /* set up dcache and MMU */ + /* FIXME: this should happen via resource allocator */ + exynos5250_config_l2_cache(); + mmu_init(); + mmu_config_range(0, DRAM_START, DCACHE_OFF); + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + dcache_invalidate_all(); + dcache_mmu_enable(); + + const unsigned epll_hz = 192000000; + const unsigned sample_rate = 48000; + const unsigned lr_frame_size = 256; + clock_epll_set_rate(epll_hz); + clock_select_i2s_clk_source(); + clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); + + power_enable_xclkout(); +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM Chromebook", + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (intptr_t)DMA_START; + dma->range_size = DMA_SIZE; +} diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c new file mode 100644 index 0000000..5640f31 --- /dev/null +++ b/src/mainboard/google/daisy/memory.c @@ -0,0 +1,545 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Samsung Electronics + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <stdlib.h> +#include <console/console.h> + +#include <soc/samsung/exynos5250/gpio.h> +#include <soc/samsung/exynos5250/setup.h> +#include <soc/samsung/exynos5250/dmc.h> +#include <soc/samsung/exynos5250/clk.h> + +const struct mem_timings mem_timings[] = { + { + .mem_manuf = MEM_MANUF_ELPIDA, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x64, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x0, + .use_bpll = 0, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010042, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x4, + .phy1_tFS = 0x4, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 0, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_30_OHM, + .gate_leveling_enable = 0, + }, { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x64, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x0, + .use_bpll = 0, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010000, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x5, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_40_OHM, + .gate_leveling_enable = 1, + }, + { + .mem_manuf = MEM_MANUF_ELPIDA, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 780, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x82, + .bpll_pdiv = 0x4, + .bpll_sdiv = 0x0, + .use_bpll = 1, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010042, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x4, + .phy1_tFS = 0x4, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 0, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_30_OHM, + .gate_leveling_enable = 0, + }, { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 780, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x82, + .bpll_pdiv = 0x4, + .bpll_sdiv = 0x0, + .use_bpll = 1, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010000, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x5, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_40_OHM, + .gate_leveling_enable = 1, + } +}; + +#define BOARD_ID0_GPIO 88 /* GPD0, pin 0 */ +#define BOARD_ID1_GPIO 89 /* GPD0, pin 1 */ + +enum board_config { + DAISY_CONFIG_UNKNOWN = -1, + DAISY_CONFIG_SAMSUNG_EVT, + DAISY_CONFIG_ELPIDA_EVT, + DAISY_CONFIG_SAMSUNG_DVT, + DAISY_CONFIG_ELPIDA_DVT, + DAISY_CONFIG_SAMSUNG_PVT, + DAISY_CONFIG_ELPIDA_PVT, + DAISY_CONFIG_SAMSUNG_MP, + DAISY_CONFIG_ELPIDA_MP, + DAISY_CONFIG_RSVD, +}; + +struct { + enum mvl3 id0, id1; + enum board_config config; +} id_map[] = { + /* ID0 ID1 config */ + { LOGIC_0, LOGIC_0, DAISY_CONFIG_SAMSUNG_MP }, + { LOGIC_0, LOGIC_1, DAISY_CONFIG_ELPIDA_MP }, + { LOGIC_1, LOGIC_0, DAISY_CONFIG_SAMSUNG_DVT }, + { LOGIC_1, LOGIC_1, DAISY_CONFIG_ELPIDA_DVT }, + { LOGIC_0, LOGIC_Z, DAISY_CONFIG_SAMSUNG_PVT }, + { LOGIC_1, LOGIC_Z, DAISY_CONFIG_ELPIDA_PVT }, + { LOGIC_Z, LOGIC_0, DAISY_CONFIG_SAMSUNG_MP }, + { LOGIC_Z, LOGIC_Z, DAISY_CONFIG_ELPIDA_MP }, + { LOGIC_Z, LOGIC_1, DAISY_CONFIG_RSVD }, +}; + +static int board_get_config(void) +{ + int i; + int id0, id1; + enum board_config config = DAISY_CONFIG_UNKNOWN; + + id0 = gpio_read_mvl3(BOARD_ID0_GPIO); + id1 = gpio_read_mvl3(BOARD_ID1_GPIO); + if (id0 < 0 || id1 < 0) + return -1; + + for (i = 0; i < ARRAY_SIZE(id_map); i++) { + if (id0 == id_map[i].id0 && id1 == id_map[i].id1) { + config = id_map[i].config; + break; + } + } + + return config; +} + +struct mem_timings *get_mem_timings(void) +{ + int i; + enum board_config config; + enum ddr_mode mem_type; + unsigned int frequency_mhz; + enum mem_manuf mem_manuf; + const struct mem_timings *mem; + + config = board_get_config(); + switch (config) { + case DAISY_CONFIG_ELPIDA_EVT: + case DAISY_CONFIG_ELPIDA_DVT: + case DAISY_CONFIG_ELPIDA_PVT: + case DAISY_CONFIG_ELPIDA_MP: + mem_manuf = MEM_MANUF_ELPIDA; + mem_type = DDR_MODE_DDR3; + frequency_mhz = 800; + break; + case DAISY_CONFIG_SAMSUNG_EVT: + case DAISY_CONFIG_SAMSUNG_DVT: + case DAISY_CONFIG_SAMSUNG_PVT: + case DAISY_CONFIG_SAMSUNG_MP: + mem_manuf = MEM_MANUF_SAMSUNG; + mem_type = DDR_MODE_DDR3; + frequency_mhz = 800; + break; + default: + printk(BIOS_CRIT, "Unknown board configuration.\n"); + return NULL; + } + + for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); + i++, mem++) { + if (mem->mem_type == mem_type && + mem->frequency_mhz == frequency_mhz && + mem->mem_manuf == mem_manuf) + return (struct mem_timings *)mem; + } + + return NULL; +} diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c new file mode 100644 index 0000000..9b35c4a --- /dev/null +++ b/src/mainboard/google/daisy/romstage.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> + +#include <armv7.h> +#include <cbfs.h> +#include <cbmem.h> + +#include <arch/cache.h> +#include <arch/exception.h> +#include <soc/samsung/exynos5250/i2c.h> +#include <soc/samsung/exynos5250/clk.h> +#include <soc/samsung/exynos5250/cpu.h> +#include <soc/samsung/exynos5250/dmc.h> +#include <soc/samsung/exynos5250/gpio.h> +#include <soc/samsung/exynos5250/setup.h> +#include <soc/samsung/exynos5250/periph.h> +#include <soc/samsung/exynos5250/power.h> +#include <soc/samsung/exynos5250/trustzone.h> +#include <soc/samsung/exynos5250/wakeup.h> +#include <console/console.h> +#include <arch/stages.h> + +#include <drivers/maxim/max77686/max77686.h> +#include <device/i2c.h> + +#include "exynos5250.h" + +#define PMIC_BUS 0 + +static void setup_power(int is_resume) +{ + int error = 0; + + power_init(); + + if (is_resume) { + return; + } + + /* Initialize I2C bus to configure PMIC. */ + exynos_pinmux_i2c0(); + i2c_init(0, I2C_0_SPEED, 0x00); + + printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); + /* + * We're using CR1616 coin cell battery that is non-rechargeable + * battery. But, BBCHOSTEN bit of the BBAT Charger Register in + * MAX77686 is enabled by default for charging coin cell. + * + * Also, we cannot meet the coin cell reverse current spec. in UL + * standard if BBCHOSTEN bit is enabled. + * + * Disable Coin BATT Charging + */ + error = max77686_disable_backup_batt(PMIC_BUS); + + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, VDD_INT_UV, + REG_ENABLE, MAX77686_UV); + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV, + REG_ENABLE, MAX77686_MV); + + error |= max77686_enable_32khz_cp(PMIC_BUS); + + if (error) { + printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); + die("Failed to intialize PMIC.\n"); + } +} + +static void setup_graphics(void) +{ + exynos_pinmux_dphpd(); +} + +static void setup_gpio(void) +{ + gpio_direction_input(GPIO_D16); // WP_GPIO + gpio_set_pull(GPIO_D16, GPIO_PULL_NONE); + + gpio_direction_input(GPIO_Y10); // RECMODE_GPIO + gpio_set_pull(GPIO_Y10, GPIO_PULL_NONE); + + gpio_direction_input(GPIO_X35); // LID_GPIO + gpio_set_pull(GPIO_X35, GPIO_PULL_NONE); + + gpio_direction_input(GPIO_X13); // POWER_GPIO + gpio_set_pull(GPIO_X13, GPIO_PULL_NONE); +} + +static void setup_memory(struct mem_timings *mem, int is_resume) +{ + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz); + + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { + die("Failed to initialize memory controller.\n"); + } +} + +static struct mem_timings *setup_clock(void) +{ + struct mem_timings *mem = get_mem_timings(); + struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); + if (!mem) { + die("Unable to auto-detect memory timings\n"); + } + system_clock_init(mem, arm_ratios); + return mem; +} + +void main(void) +{ + struct mem_timings *mem; + void *entry; + int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); + + /* Clock must be initialized before console_init, otherwise you may need + * to re-initialize serial console drivers again. */ + mem = setup_clock(); + + console_init(); + exception_init(); + + setup_power(is_resume); + setup_memory(mem, is_resume); + + /* This needs to happen on normal boots and on resume. */ + trustzone_init(); + + if (is_resume) { + wakeup(); + } + + setup_gpio(); + setup_graphics(); + + /* Set SPI (primary CBFS media) clock to 50MHz and configure pinmux. */ + exynos_pinmux_spi1(); + clock_set_rate(PERIPH_ID_SPI1, 50000000); + + cbmem_initialize_empty(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +} diff --git a/src/mainboard/google/daisy/wakeup.c b/src/mainboard/google/daisy/wakeup.c new file mode 100644 index 0000000..8b7fc4b --- /dev/null +++ b/src/mainboard/google/daisy/wakeup.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/samsung/exynos5250/gpio.h> +#include <soc/samsung/exynos5250/wakeup.h> + +int wakeup_need_reset(void) +{ + /* The "wake up" event is not reliable (known as "bad wakeup") and needs + * reset if GPIO value is high. */ + return gpio_get_value(GPIO_Y10); +} diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig deleted file mode 100644 index e636df9..0000000 --- a/src/mainboard/google/snow/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -if BOARD_GOOGLE_SNOW - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_SAMSUNG_EXYNOS5250 - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_I2C - select BOARD_ROMSIZE_KB_4096 - select DRIVER_MAXIM_MAX77686 - select MAINBOARD_HAS_CHROMEOS - select DRIVER_TI_TPS65090 - select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT - -config MAINBOARD_DIR - string - default google/snow - -config MAINBOARD_PART_NUMBER - string - default "Snow" - -config MAX_CPUS - int - default 2 - -config DRAM_SIZE_MB - int - default 2048 - -config EC_GOOGLE_CHROMEEC_I2C_BUS - hex - default 4 - -config UART_FOR_CONSOLE - int - default 3 - -endif # BOARD_GOOGLE_SNOW diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc deleted file mode 100644 index df9b797..0000000 --- a/src/mainboard/google/snow/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -bootblock-y += wakeup.c - -romstage-y += memory.c -romstage-y += romstage.c -romstage-y += wakeup.c -romstage-y += chromeos.c - -ramstage-y += mainboard.c -ramstage-y += chromeos.c diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c deleted file mode 100644 index f7443be..0000000 --- a/src/mainboard/google/snow/chromeos.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <boot/coreboot_tables.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <bootmode.h> -#include <soc/samsung/exynos5250/cpu.h> -#include <soc/samsung/exynos5250/gpio.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPD1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Lid: active high */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: virtual GPIO active low */ - gpios->gpios[count].port = EXYNOS5_GPX1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = - gpio_get_value(GPIO_X13); // POWER_GPIO - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); -} - -int get_developer_mode_switch(void) -{ - return 0; -} - -int get_recovery_mode_switch(void) -{ - uint32_t ec_events; - - /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -} - -int get_write_protect_state(void) -{ - return !gpio_get_value(GPIO_D16); -} diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb deleted file mode 100644 index 2552e07..0000000 --- a/src/mainboard/google/snow/devicetree.cb +++ /dev/null @@ -1,33 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -chip soc/samsung/exynos5250 - device cpu_cluster 0 on end - register "xres" = "1366" - register "yres" = "768" - register "framebuffer_bits_per_pixel" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" -end diff --git a/src/mainboard/google/snow/exynos5250.h b/src/mainboard/google/snow/exynos5250.h deleted file mode 100644 index 0f71a36..0000000 --- a/src/mainboard/google/snow/exynos5250.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* I2C */ -#define I2C_0_SPEED 100000 -#define I2C_SLAVE 0 - -/* Voltages */ -#define VDD_ARM_MV 1300 // 1.3V -#define VDD_INT_UV 1012500 // 1.0125V -#define VDD_MIF_MV 1000 // 1.0V -#define VDD_G3D_MV 1200 // 1.2V -#define VDD_LDO2_MV 1500 // 1.5V -#define VDD_LDO3_MV 1800 // 1.8V -#define VDD_LDO5_MV 1800 // 1.8V -#define VDD_LDO10_MV 1800 // 1.8V diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c deleted file mode 100644 index 0b6cf4a..0000000 --- a/src/mainboard/google/snow/mainboard.c +++ /dev/null @@ -1,364 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/i2c.h> -#include <drivers/ti/tps65090/tps65090.h> -#include <cbmem.h> -#include <delay.h> -#include <edid.h> -#include <vbe.h> -#include <boot/coreboot_tables.h> -#include <arch/cache.h> -#include <soc/samsung/exynos5250/tmu.h> -#include <soc/samsung/exynos5250/clk.h> -#include <soc/samsung/exynos5250/gpio.h> -#include <soc/samsung/exynos5250/power.h> -#include <soc/samsung/exynos5250/i2c.h> -#include <soc/samsung/exynos5250/dp-core.h> -#include <soc/samsung/exynos5250/dp.h> -#include <soc/samsung/exynos5250/usb.h> - -#include "exynos5250.h" - -#define MMC0_GPIO_PIN (58) - -/* convenient shorthand (in MB) */ -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ - -/* Arbitrary range of DMA memory for depthcharge's drivers */ -#define DMA_START (0x77300000) -#define DMA_SIZE (0x00100000) - -static struct edid edid = { - .ha = 1366, - .va = 768, - .framebuffer_bits_per_pixel = 16, - .x_resolution = 1366, - .y_resolution = 768, - .bytes_per_line = 2 * 1366 -}; - -/* TODO: transplanted DP stuff, clean up once we have something that works */ -static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ -static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ -static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ - -static void exynos_dp_bridge_setup(void) -{ - exynos_pinmux_dphpd(); - - gpio_set_value(dp_pd_l, 1); - gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); - gpio_set_pull(dp_pd_l, GPIO_PULL_NONE); - - gpio_set_value(dp_rst_l, 0); - gpio_cfg_pin(dp_rst_l, GPIO_OUTPUT); - gpio_set_pull(dp_rst_l, GPIO_PULL_NONE); - udelay(10); - gpio_set_value(dp_rst_l, 1); -} - -static void exynos_dp_bridge_init(void) -{ - /* De-assert PD (and possibly RST) to power up the bridge */ - gpio_set_value(dp_pd_l, 1); - gpio_set_value(dp_rst_l, 1); - - /* - * We need to wait for 90ms after bringing up the bridge since - * there is a phantom "high" on the HPD chip during its - * bootup. The phantom high comes within 7ms of de-asserting - * PD and persists for at least 15ms. The real high comes - * roughly 50ms after PD is de-asserted. The phantom high - * makes it hard for us to know when the NXP chip is up. - */ - udelay(90000); -} - -static int exynos_dp_hotplug(void) -{ - /* Check HPD. If it's high, we're all good. */ - return gpio_get_value(dp_hpd) ? 0 : 1; -} - -static void exynos_dp_reset(void) -{ - gpio_set_value(dp_pd_l, 0); - gpio_set_value(dp_rst_l, 0); - /* paranoid delay period (300ms) */ - udelay(300 * 1000); -} - -/* - * This delay is T3 in the LCD timing spec (defined as >200ms). We set - * this down to 60ms since that's the approximate maximum amount of time - * it'll take a bridge to start outputting LVDS data. The delay of - * >200ms is just a conservative value to avoid turning on the backlight - * when there's random LCD data on the screen. Shaving 140ms off the - * boot is an acceptable trade-off. - */ -#define LCD_T3_DELAY_MS 60 - -#define LCD_T5_DELAY_MS 10 -#define LCD_T6_DELAY_MS 10 - -static void backlight_pwm(void) -{ - /*Configure backlight PWM as a simple output high (100% brightness) */ - gpio_direction_output(GPIO_B20, 1); - udelay(LCD_T6_DELAY_MS * 1000); -} - -static void backlight_en(void) -{ - /* Configure GPIO for LCD_BL_EN */ - gpio_direction_output(GPIO_X30, 1); -} - -#define TPS65090_BUS 4 /* Snow-specific */ - -#define FET1_CTRL 0x0f -#define FET4_CTRL 0x12 -#define FET6_CTRL 0x14 - -static void lcd_vdd(void) -{ - /* Enable FET6, lcd panel */ - tps65090_fet_enable(TPS65090_BUS, FET6_CTRL); -} - -static void backlight_vdd(void) -{ - /* Enable FET1, backlight */ - tps65090_fet_enable(TPS65090_BUS, FET1_CTRL); - udelay(LCD_T5_DELAY_MS * 1000); -} - -static void sdmmc_vdd(void) -{ - /* Enable FET4, P3.3V_SDCARD */ - tps65090_fet_enable(TPS65090_BUS, FET4_CTRL); -} - -static enum exynos5_gpio_pin usb_host_vbus = GPIO_X11; -static enum exynos5_gpio_pin usb_drd_vbus = GPIO_X27; -/* static enum exynos5_gpio_pin hsic_reset_l = GPIO_E10; */ - -static void prepare_usb(void) -{ - /* Kick this reset off early so it gets at least 100ms to settle */ - reset_usb_drd_dwc3(); -} - -static void setup_usb(void) -{ - /* HSIC not needed in firmware on this board */ - setup_usb_drd_phy(); - setup_usb_drd_dwc3(); - setup_usb_host_phy(0); - - gpio_direction_output(usb_host_vbus, 1); - gpio_direction_output(usb_drd_vbus, 1); -} - -//static struct video_info smdk5250_dp_config = { -static struct video_info dp_video_info = { - /* FIXME: fix video_info struct to use const for name */ - .name = (char *)"eDP-LVDS NXP PTN3460", - - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - - .link_rate = LINK_RATE_2_70GBPS, - .lane_count = LANE_COUNT2, -}; - -/* FIXME: move some place more appropriate */ -#define MAX_DP_TRIES 5 - -/* - * This function disables the USB3.0 PLL to save power - */ -static void disable_usb30_pll(void) -{ - enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11; - - gpio_direction_output(usb3_pll_l, 0); -} - -static void setup_storage(void) -{ - /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ - if (clock_set_mshci(PERIPH_ID_SDMMC0)) - printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); - if (gpio_direction_output(MMC0_GPIO_PIN, 1)) { - printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__); - } - gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE); - gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X); - exynos_pinmux_sdmmc0(); - - /* MMC2: Removable, 4 bit mode, no GPIO. */ - /* (Must be after romstage to avoid breaking SDMMC boot.) */ - clock_set_mshci(PERIPH_ID_SDMMC2); - exynos_pinmux_sdmmc2(); -} - -static void gpio_init(void) -{ - /* Set up the I2C busses. */ - exynos_pinmux_i2c0(); - exynos_pinmux_i2c1(); - exynos_pinmux_i2c2(); - exynos_pinmux_i2c3(); - exynos_pinmux_i2c4(); - exynos_pinmux_i2c7(); - - /* Set up the GPIOs used to arbitrate for I2C bus 4. */ - gpio_set_pull(GPIO_F03, GPIO_PULL_NONE); - gpio_set_pull(GPIO_E04, GPIO_PULL_NONE); - gpio_direction_output(GPIO_F03, 1); - gpio_direction_input(GPIO_E04); - - /* Set up the GPIO used to enable the audio codec. */ - gpio_set_pull(GPIO_X17, GPIO_PULL_NONE); - gpio_set_pull(GPIO_X15, GPIO_PULL_NONE); - gpio_direction_output(GPIO_X17, 1); - gpio_direction_output(GPIO_X15, 1); - - /* Set up the I2S busses. */ - exynos_pinmux_i2s0(); - exynos_pinmux_i2s1(); -} - -/* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) -{ - int dp_tries; - struct s5p_dp_device dp_device = { - .base = exynos_dp1, - .video_info = &dp_video_info, - }; - void *fb_addr = (void *)(get_fb_base_kb() * KiB); - - prepare_usb(); - gpio_init(); - setup_storage(); - - i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE); - i2c_init(7, I2C_0_SPEED, I2C_SLAVE); - - tmu_init(&exynos5250_tmu_info); - - /* Clock Gating all the unused IP's to save power */ - clock_gate(); - - /* Disable USB3.0 PLL to save 250mW of power */ - disable_usb30_pll(); - - sdmmc_vdd(); - - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); - - lcd_vdd(); - - // FIXME: should timeout - do { - udelay(50); - } while (!exynos_dp_hotplug()); - - exynos_dp_bridge_setup(); - for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { - exynos_dp_bridge_init(); - if (exynos_dp_hotplug()) { - exynos_dp_reset(); - continue; - } - - if (dp_controller_init(&dp_device)) - continue; - - udelay(LCD_T3_DELAY_MS * 1000); - - backlight_vdd(); - backlight_pwm(); - backlight_en(); - /* if we're here, we're successful */ - break; - } - - if (dp_tries > MAX_DP_TRIES) - printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); - - setup_usb(); - - // Uncomment to get excessive GPIO output: - // gpio_info(); -} - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = &mainboard_init; - - /* set up dcache and MMU */ - /* FIXME: this should happen via resource allocator */ - exynos5250_config_l2_cache(); - mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); - mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); - mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); - dcache_invalidate_all(); - dcache_mmu_enable(); - - const unsigned epll_hz = 192000000; - const unsigned sample_rate = 48000; - const unsigned lr_frame_size = 256; - clock_epll_set_rate(epll_hz); - clock_select_i2s_clk_source(); - clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); - - power_enable_xclkout(); -} - -struct chip_operations mainboard_ops = { - .name = "Samsung/Google ARM Chromebook", - .enable_dev = mainboard_enable, -}; - -void lb_board(struct lb_header *header) -{ - struct lb_range *dma; - - dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; - dma->size = sizeof(*dma); - dma->range_start = (intptr_t)DMA_START; - dma->range_size = DMA_SIZE; -} diff --git a/src/mainboard/google/snow/memory.c b/src/mainboard/google/snow/memory.c deleted file mode 100644 index 1cb87d4..0000000 --- a/src/mainboard/google/snow/memory.c +++ /dev/null @@ -1,545 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Samsung Electronics - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stddef.h> -#include <stdlib.h> -#include <console/console.h> - -#include <soc/samsung/exynos5250/gpio.h> -#include <soc/samsung/exynos5250/setup.h> -#include <soc/samsung/exynos5250/dmc.h> -#include <soc/samsung/exynos5250/clk.h> - -const struct mem_timings mem_timings[] = { - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x5, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, - .gate_leveling_enable = 1, - }, - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 780, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x82, - .bpll_pdiv = 0x4, - .bpll_sdiv = 0x0, - .use_bpll = 1, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 780, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x82, - .bpll_pdiv = 0x4, - .bpll_sdiv = 0x0, - .use_bpll = 1, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x5, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, - .gate_leveling_enable = 1, - } -}; - -#define BOARD_ID0_GPIO 88 /* GPD0, pin 0 */ -#define BOARD_ID1_GPIO 89 /* GPD0, pin 1 */ - -enum board_config { - SNOW_CONFIG_UNKNOWN = -1, - SNOW_CONFIG_SAMSUNG_EVT, - SNOW_CONFIG_ELPIDA_EVT, - SNOW_CONFIG_SAMSUNG_DVT, - SNOW_CONFIG_ELPIDA_DVT, - SNOW_CONFIG_SAMSUNG_PVT, - SNOW_CONFIG_ELPIDA_PVT, - SNOW_CONFIG_SAMSUNG_MP, - SNOW_CONFIG_ELPIDA_MP, - SNOW_CONFIG_RSVD, -}; - -struct { - enum mvl3 id0, id1; - enum board_config config; -} id_map[] = { - /* ID0 ID1 config */ - { LOGIC_0, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP }, - { LOGIC_0, LOGIC_1, SNOW_CONFIG_ELPIDA_MP }, - { LOGIC_1, LOGIC_0, SNOW_CONFIG_SAMSUNG_DVT }, - { LOGIC_1, LOGIC_1, SNOW_CONFIG_ELPIDA_DVT }, - { LOGIC_0, LOGIC_Z, SNOW_CONFIG_SAMSUNG_PVT }, - { LOGIC_1, LOGIC_Z, SNOW_CONFIG_ELPIDA_PVT }, - { LOGIC_Z, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP }, - { LOGIC_Z, LOGIC_Z, SNOW_CONFIG_ELPIDA_MP }, - { LOGIC_Z, LOGIC_1, SNOW_CONFIG_RSVD }, -}; - -static int board_get_config(void) -{ - int i; - int id0, id1; - enum board_config config = SNOW_CONFIG_UNKNOWN; - - id0 = gpio_read_mvl3(BOARD_ID0_GPIO); - id1 = gpio_read_mvl3(BOARD_ID1_GPIO); - if (id0 < 0 || id1 < 0) - return -1; - - for (i = 0; i < ARRAY_SIZE(id_map); i++) { - if (id0 == id_map[i].id0 && id1 == id_map[i].id1) { - config = id_map[i].config; - break; - } - } - - return config; -} - -struct mem_timings *get_mem_timings(void) -{ - int i; - enum board_config config; - enum ddr_mode mem_type; - unsigned int frequency_mhz; - enum mem_manuf mem_manuf; - const struct mem_timings *mem; - - config = board_get_config(); - switch (config) { - case SNOW_CONFIG_ELPIDA_EVT: - case SNOW_CONFIG_ELPIDA_DVT: - case SNOW_CONFIG_ELPIDA_PVT: - case SNOW_CONFIG_ELPIDA_MP: - mem_manuf = MEM_MANUF_ELPIDA; - mem_type = DDR_MODE_DDR3; - frequency_mhz = 800; - break; - case SNOW_CONFIG_SAMSUNG_EVT: - case SNOW_CONFIG_SAMSUNG_DVT: - case SNOW_CONFIG_SAMSUNG_PVT: - case SNOW_CONFIG_SAMSUNG_MP: - mem_manuf = MEM_MANUF_SAMSUNG; - mem_type = DDR_MODE_DDR3; - frequency_mhz = 800; - break; - default: - printk(BIOS_CRIT, "Unknown board configuration.\n"); - return NULL; - } - - for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); - i++, mem++) { - if (mem->mem_type == mem_type && - mem->frequency_mhz == frequency_mhz && - mem->mem_manuf == mem_manuf) - return (struct mem_timings *)mem; - } - - return NULL; -} diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c deleted file mode 100644 index 9b35c4a..0000000 --- a/src/mainboard/google/snow/romstage.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> - -#include <armv7.h> -#include <cbfs.h> -#include <cbmem.h> - -#include <arch/cache.h> -#include <arch/exception.h> -#include <soc/samsung/exynos5250/i2c.h> -#include <soc/samsung/exynos5250/clk.h> -#include <soc/samsung/exynos5250/cpu.h> -#include <soc/samsung/exynos5250/dmc.h> -#include <soc/samsung/exynos5250/gpio.h> -#include <soc/samsung/exynos5250/setup.h> -#include <soc/samsung/exynos5250/periph.h> -#include <soc/samsung/exynos5250/power.h> -#include <soc/samsung/exynos5250/trustzone.h> -#include <soc/samsung/exynos5250/wakeup.h> -#include <console/console.h> -#include <arch/stages.h> - -#include <drivers/maxim/max77686/max77686.h> -#include <device/i2c.h> - -#include "exynos5250.h" - -#define PMIC_BUS 0 - -static void setup_power(int is_resume) -{ - int error = 0; - - power_init(); - - if (is_resume) { - return; - } - - /* Initialize I2C bus to configure PMIC. */ - exynos_pinmux_i2c0(); - i2c_init(0, I2C_0_SPEED, 0x00); - - printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); - /* - * We're using CR1616 coin cell battery that is non-rechargeable - * battery. But, BBCHOSTEN bit of the BBAT Charger Register in - * MAX77686 is enabled by default for charging coin cell. - * - * Also, we cannot meet the coin cell reverse current spec. in UL - * standard if BBCHOSTEN bit is enabled. - * - * Disable Coin BATT Charging - */ - error = max77686_disable_backup_batt(PMIC_BUS); - - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, VDD_INT_UV, - REG_ENABLE, MAX77686_UV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV, - REG_ENABLE, MAX77686_MV); - - error |= max77686_enable_32khz_cp(PMIC_BUS); - - if (error) { - printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); - die("Failed to intialize PMIC.\n"); - } -} - -static void setup_graphics(void) -{ - exynos_pinmux_dphpd(); -} - -static void setup_gpio(void) -{ - gpio_direction_input(GPIO_D16); // WP_GPIO - gpio_set_pull(GPIO_D16, GPIO_PULL_NONE); - - gpio_direction_input(GPIO_Y10); // RECMODE_GPIO - gpio_set_pull(GPIO_Y10, GPIO_PULL_NONE); - - gpio_direction_input(GPIO_X35); // LID_GPIO - gpio_set_pull(GPIO_X35, GPIO_PULL_NONE); - - gpio_direction_input(GPIO_X13); // POWER_GPIO - gpio_set_pull(GPIO_X13, GPIO_PULL_NONE); -} - -static void setup_memory(struct mem_timings *mem, int is_resume) -{ - printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); - - if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { - die("Failed to initialize memory controller.\n"); - } -} - -static struct mem_timings *setup_clock(void) -{ - struct mem_timings *mem = get_mem_timings(); - struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); - if (!mem) { - die("Unable to auto-detect memory timings\n"); - } - system_clock_init(mem, arm_ratios); - return mem; -} - -void main(void) -{ - struct mem_timings *mem; - void *entry; - int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); - - /* Clock must be initialized before console_init, otherwise you may need - * to re-initialize serial console drivers again. */ - mem = setup_clock(); - - console_init(); - exception_init(); - - setup_power(is_resume); - setup_memory(mem, is_resume); - - /* This needs to happen on normal boots and on resume. */ - trustzone_init(); - - if (is_resume) { - wakeup(); - } - - setup_gpio(); - setup_graphics(); - - /* Set SPI (primary CBFS media) clock to 50MHz and configure pinmux. */ - exynos_pinmux_spi1(); - clock_set_rate(PERIPH_ID_SPI1, 50000000); - - cbmem_initialize_empty(); - - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); - stage_exit(entry); -} diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c deleted file mode 100644 index 8b7fc4b..0000000 --- a/src/mainboard/google/snow/wakeup.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <soc/samsung/exynos5250/gpio.h> -#include <soc/samsung/exynos5250/wakeup.h> - -int wakeup_need_reset(void) -{ - /* The "wake up" event is not reliable (known as "bad wakeup") and needs - * reset if GPIO value is high. */ - return gpio_get_value(GPIO_Y10); -}

1 0

Patch set updated for coreboot: 4cc92bf pit: Rename pit to peach_pit.
by Isaac Christensen 23 Sep '14

23 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6928 -gerrit commit 4cc92bf8e22de0d4deacfa6f9cc9a0474e905353 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jan 22 20:50:27 2014 -0800 pit: Rename pit to peach_pit. The name pit goes by in many places in chromeos is peach_pit, where peach is the base name and pit is the name of this particular variant. To make it easier to work with within chromeos and to make the board names a little less ambiguous, this change renames the pit board to peach_pit, and from Pit to Peach Pit. Change-Id: I51c89ba3785cf4cb9769a989b1cac71bcd1b0a05 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/183552 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit cbbe1e9f04e34436a1bbae28628e0b5630d41054) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/Kconfig | 6 +- src/mainboard/google/peach_pit/Kconfig | 53 +++ src/mainboard/google/peach_pit/Makefile.inc | 28 ++ src/mainboard/google/peach_pit/chromeos.c | 101 ++++++ src/mainboard/google/peach_pit/devicetree.cb | 33 ++ src/mainboard/google/peach_pit/mainboard.c | 498 +++++++++++++++++++++++++++ src/mainboard/google/peach_pit/memory.c | 116 +++++++ src/mainboard/google/peach_pit/romstage.c | 279 +++++++++++++++ src/mainboard/google/peach_pit/wakeup.c | 28 ++ src/mainboard/google/pit/Kconfig | 53 --- src/mainboard/google/pit/Makefile.inc | 28 -- src/mainboard/google/pit/chromeos.c | 101 ------ src/mainboard/google/pit/devicetree.cb | 33 -- src/mainboard/google/pit/mainboard.c | 498 --------------------------- src/mainboard/google/pit/memory.c | 116 ------- src/mainboard/google/pit/romstage.c | 279 --------------- src/mainboard/google/pit/wakeup.c | 28 -- 17 files changed, 1139 insertions(+), 1139 deletions(-) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 538f0d8..08a2b26 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -35,10 +35,10 @@ config BOARD_GOOGLE_PANTHER bool "Panther" config BOARD_GOOGLE_PARROT bool "Parrot" +config BOARD_GOOGLE_PEACH_PIT + bool "Peach Pit" config BOARD_GOOGLE_PEPPY bool "Peppy" -config BOARD_GOOGLE_PIT - bool "Pit" config BOARD_GOOGLE_RAMBI bool "Rambi" config BOARD_GOOGLE_SAMUS @@ -59,8 +59,8 @@ source "src/mainboard/google/link/Kconfig" source "src/mainboard/google/nyan/Kconfig" source "src/mainboard/google/panther/Kconfig" source "src/mainboard/google/parrot/Kconfig" +source "src/mainboard/google/peach_pit/Kconfig" source "src/mainboard/google/peppy/Kconfig" -source "src/mainboard/google/pit/Kconfig" source "src/mainboard/google/rambi/Kconfig" source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig new file mode 100644 index 0000000..66ab6a7 --- /dev/null +++ b/src/mainboard/google/peach_pit/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_PEACH_PIT + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_SAMSUNG_EXYNOS5420 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select BOARD_ROMSIZE_KB_4096 + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT + select DRIVER_PARADE_PS8625 + +config MAINBOARD_DIR + string + default google/peach_pit + +config MAINBOARD_PART_NUMBER + string + default "Peach Pit" + +config DRAM_SIZE_MB + int + default 2048 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 2 + +config UART_FOR_CONSOLE + int + default 3 + +endif # BOARD_GOOGLE_PEACH_PIT diff --git a/src/mainboard/google/peach_pit/Makefile.inc b/src/mainboard/google/peach_pit/Makefile.inc new file mode 100644 index 0000000..df9b797 --- /dev/null +++ b/src/mainboard/google/peach_pit/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bootblock-y += wakeup.c + +romstage-y += memory.c +romstage-y += romstage.c +romstage-y += wakeup.c +romstage-y += chromeos.c + +ramstage-y += mainboard.c +ramstage-y += chromeos.c diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c new file mode 100644 index 0000000..7b0807c --- /dev/null +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> +#include <soc/samsung/exynos5420/cpu.h> +#include <soc/samsung/exynos5420/gpio.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = EXYNOS5_GPX3; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_value(GPIO_X30); // WP_GPIO + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active low */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Lid: active high */ + gpios->gpios[count].port = EXYNOS5_GPX3; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = gpio_get_value(GPIO_X34); // LID_GPIO + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; + + /* Power: virtual GPIO active low */ + gpios->gpios[count].port = EXYNOS5_GPX1; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = + gpio_get_value(GPIO_X12); // POWER_GPIO + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + uint32_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_value(GPIO_X30); +} diff --git a/src/mainboard/google/peach_pit/devicetree.cb b/src/mainboard/google/peach_pit/devicetree.cb new file mode 100644 index 0000000..568daf8 --- /dev/null +++ b/src/mainboard/google/peach_pit/devicetree.cb @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/samsung/exynos5420 + device cpu_cluster 0 on end + register "xres" = "1366" + register "yres" = "768" + register "framebuffer_bits_per_pixel" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" +end diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c new file mode 100644 index 0000000..1fb441d --- /dev/null +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -0,0 +1,498 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c.h> +#include <cbmem.h> +#include <delay.h> +#include <edid.h> +#include <vbe.h> +#include <boot/coreboot_tables.h> +#include <arch/cache.h> +#include <soc/samsung/exynos5420/tmu.h> +#include <soc/samsung/exynos5420/clk.h> +#include <soc/samsung/exynos5420/cpu.h> +#include <soc/samsung/exynos5420/gpio.h> +#include <soc/samsung/exynos5420/power.h> +#include <soc/samsung/exynos5420/i2c.h> +#include <soc/samsung/exynos5420/dp.h> +#include <soc/samsung/exynos5420/fimd.h> +#include <soc/samsung/exynos5420/usb.h> +#include <drivers/parade/ps8625/ps8625.h> +#include <ec/google/chromeec/ec.h> +#include <stdlib.h> + +/* convenient shorthand (in MB) */ +#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) +#define DRAM_SIZE CONFIG_DRAM_SIZE_MB + +/* Arbitrary range of DMA memory for depthcharge's drivers */ +#define DMA_START (0x77300000) +#define DMA_SIZE (0x00100000) + +static struct edid edid = { + .ha = 1366, + .va = 768, + .framebuffer_bits_per_pixel = 16, + .x_resolution = 1366, + .y_resolution = 768, + .bytes_per_line = 2 * 1366 +}; + +/* from the fdt */ +static struct vidinfo vidinfo = { + .vl_freq = 60, + .vl_col = 1366, + .vl_row = 768, + .vl_width = 1366, + .vl_height = 768, + .vl_clkp = 1, + .vl_dp = 1, + .vl_bpix = 4, + .vl_hspw = 32, + .vl_hbpd = 40, + .vl_hfpd = 40, + .vl_vspw = 6, + .vl_vbpd = 10, + .vl_vfpd = 12, + .vl_cmd_allow_len = 0xf, + .win_id = 3, + .dp_enabled = 1, + .dual_lcd_enabled = 0, + .interface_mode = FIMD_RGB_INTERFACE, +}; + +static unsigned char panel_edid[] = { + 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00, + 0x06,0xaf,0x5c,0x31,0x00,0x00,0x00,0x00, + 0x00,0x16,0x01,0x03,0x80,0x1a,0x0e,0x78, + 0x0a,0x99,0x85,0x95,0x55,0x56,0x92,0x28, + 0x22,0x50,0x54,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, + 0x01,0x01,0x01,0x01,0x01,0x01,0xa3,0x1b, + 0x56,0x7e,0x50,0x00,0x16,0x30,0x30,0x20, + 0x36,0x00,0x00,0x90,0x10,0x00,0x00,0x18, + 0x6d,0x12,0x56,0x7e,0x50,0x00,0x16,0x30, + 0x30,0x20,0x36,0x00,0x00,0x90,0x10,0x00, + 0x00,0x18,0x00,0x00,0x00,0xfe,0x00,0x41, + 0x55,0x4f,0x0a,0x20,0x20,0x20,0x20,0x20, + 0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xfe, + 0x00,0x42,0x31,0x31,0x36,0x58,0x57,0x30, + 0x33,0x20,0x56,0x31,0x20,0x0a,0x00,0x3d, + 0x00,0xc0,0x00,0x00,0x27,0xfd,0x00,0x20, + 0x02,0x59,0x07,0x00,0x64,0x3e,0x07,0x02, + 0x00,0x00,0xcd,0x12,0x59,0xff,0x10,0x03, + 0x00,0x00,0x00,0x00,0x64,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x05,0x00,0x00,0x00, + 0x9c,0x3f,0x07,0x02,0x31,0xf9,0x00,0x20, + 0x59,0xff,0x10,0x03,0x00,0x00,0x00,0x00, + 0xbc,0x3e,0x07,0x02,0xc0,0x9b,0x01,0x20, + 0x00,0x00,0x00,0x00,0xdb,0xf8,0x00,0x20, + 0x98,0x3e,0x07,0x02,0x8b,0xaf,0x00,0x20, + 0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0xe5,0xcd,0x16,0x00,0xe9,0xcd,0x16,0x00, + 0xe8,0x03,0x00,0x00,0x6c,0x55,0x01,0x20, + 0x2c,0x01,0x00,0x00,0x85,0xbb,0x00,0x20, + 0xe8,0x03,0x00,0x00,0xe9,0xcd,0x16,0x00, +}; + +static const struct parade_write parade_writes[] = { + { 0x02, 0xa1, 0x01 }, /* HPD low */ + /* + * SW setting + * [1:0] SW output 1.2V voltage is lower to 96% + */ + { 0x04, 0x14, 0x01 }, + /* + * RCO SS setting + * [5:4] = b01 0.5%, b10 1%, b11 1.5% + */ + { 0x04, 0xe3, 0x20 }, + { 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */ + /* + * RPHY Setting + * [3:2] CDR tune wait cycle before + * measure for fine tune b00: 1us, + * 01: 0.5us, 10:2us, 11:4us. + */ + { 0x04, 0x8a, 0x0c }, + { 0x04, 0x89, 0x08 }, /* [3] RFD always on */ + /* + * CTN lock in/out: + * 20000ppm/80000ppm. Lock out 2 + * times. + */ + { 0x04, 0x71, 0x2d }, + /* + * 2.7G CDR settings + * NOF=40LSB for HBR CDR setting + */ + { 0x04, 0x7d, 0x07 }, + { 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */ + { 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */ + /* + * 1.62G CDR settings + * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 + */ + { 0x04, 0xc0, 0x12 }, + { 0x04, 0xc1, 0x92 }, /* Gitune=-37% */ + { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */ + { 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */ + /* + * RPIO Setting + * [7:4] LVDS driver bias current : + * 75% (250mV swing) + */ + { 0x04, 0x00, 0xb0 }, + /* + * [7:6] Right-bar GPIO output strength is 8mA + */ + { 0x04, 0x15, 0x40 }, + /* EQ Training State Machine Setting */ + { 0x04, 0x54, 0x10 }, /* RCO calibration start */ + /* [4:0] MAX_LANE_COUNT set to one lane */ + { 0x01, 0x02, 0x81 }, + /* [4:0] LANE_COUNT_SET set to one lane */ + { 0x01, 0x21, 0x81 }, + { 0x00, 0x52, 0x20 }, + { 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */ + { 0x00, 0x62, 0x41 }, + /* Counter number, add 1ms counter delay */ + { 0x00, 0xf6, 0x01 }, + /* + * [6]PWM function control by + * DPCD0040f[7], default is PWM + * block always works. + */ + { 0x00, 0x77, 0x06 }, + /* + * 04h Adjust VTotal tolerance to + * fix the 30Hz no display issue + */ + { 0x00, 0x4c, 0x04 }, + /* DPCD00400='h00, Parade OUI = 'h001cf8 */ + { 0x01, 0xc0, 0x00 }, + { 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */ + { 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */ + /* + * DPCD403~408 = ASCII code + * D2SLV5='h4432534c5635 + */ + { 0x01, 0xc3, 0x44 }, + { 0x01, 0xc4, 0x32 }, /* DPCD404 */ + { 0x01, 0xc5, 0x53 }, /* DPCD405 */ + { 0x01, 0xc6, 0x4c }, /* DPCD406 */ + { 0x01, 0xc7, 0x56 }, /* DPCD407 */ + { 0x01, 0xc8, 0x35 }, /* DPCD408 */ + /* + * DPCD40A, Initial Code major revision + * '01' + */ + { 0x01, 0xca, 0x01 }, + /* DPCD40B, Initial Code minor revision '05' */ + { 0x01, 0xcb, 0x05 }, + /* DPCD720, Select external PWM */ + { 0x01, 0xa5, 0x80 }, + /* + * Set LVDS output as 6bit-VESA mapping, + * single LVDS channel + */ + { 0x01, 0xcc, 0x13 }, + /* Enable SSC set by register */ + { 0x02, 0xb1, 0x20 }, + /* + * Set SSC enabled and +/-1% central + * spreading + */ + { 0x04, 0x10, 0x16 }, + /* MPU Clock source: LC => RCO */ + { 0x04, 0x59, 0x60 }, + { 0x04, 0x54, 0x14 }, /* LC -> RCO */ + { 0x02, 0xa1, 0x91 } /* HPD high */ +}; + +/* TODO: transplanted DP stuff, clean up once we have something that works */ +static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */ +static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */ +static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */ +static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ +static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ + +static void parade_dp_bridge_setup(void) +{ + int i; + + gpio_set_value(dp_pd_l, 1); + gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); + gpio_set_pull(dp_pd_l, GPIO_PULL_NONE); + + gpio_set_value(dp_rst_l, 0); + gpio_cfg_pin(dp_rst_l, GPIO_OUTPUT); + gpio_set_pull(dp_rst_l, GPIO_PULL_NONE); + udelay(10); + gpio_set_value(dp_rst_l, 1); + + + gpio_set_pull(dp_hpd, GPIO_PULL_NONE); + gpio_cfg_pin(dp_hpd, GPIO_INPUT); + + /* De-assert PD (and possibly RST) to power up the bridge. */ + gpio_set_value(dp_pd_l, 1); + gpio_set_value(dp_rst_l, 1); + + /* Hang around for the bridge to come up. */ + mdelay(40); + + /* Configure the bridge chip. */ + exynos_pinmux_i2c7(); + i2c_init(7, 100000, 0x00); + + parade_ps8625_bridge_setup(7, 0x48, parade_writes, + ARRAY_SIZE(parade_writes)); + /* Spin until the display is ready. + * It's quite important to try really hard to get the display up, + * so be generous. It will typically be ready in only 5 ms. and + * we're out of here. + * If it's not ready after a second, then we're in big trouble. + */ + for(i = 0; i < 1000; i++){ + if (gpio_get_value(dp_hpd)) + break; + mdelay(1); + } +} + +/* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ +#define LCD_T3_DELAY_MS 60 + +#define LCD_T5_DELAY_MS 10 +#define LCD_T6_DELAY_MS 10 + +static void backlight_pwm(void) +{ + /*Configure backlight PWM as a simple output high (100% brightness) */ + gpio_direction_output(bl_pwm, 1); + udelay(LCD_T6_DELAY_MS * 1000); +} + +static void backlight_en(void) +{ + /* Configure GPIO for LCD_BL_EN */ + gpio_direction_output(bl_en, 1); +} + +static enum exynos5_gpio_pin usb_drd0_vbus = GPIO_H00; +static enum exynos5_gpio_pin usb_drd1_vbus = GPIO_H01; +/* static enum exynos5_gpio_pin hsic_reset_l = GPIO_X24; */ + +static void prepare_usb(void) +{ + /* Kick these resets off early so they get at least 100ms to settle */ + reset_usb_drd0_dwc3(); + reset_usb_drd1_dwc3(); +} + +static void setup_usb(void) +{ + /* HSIC and USB HOST port not needed in firmware on this board */ + setup_usb_drd0_phy(); + setup_usb_drd1_phy(); + + setup_usb_drd0_dwc3(); + setup_usb_drd1_dwc3(); + + gpio_direction_output(usb_drd0_vbus, 1); + gpio_direction_output(usb_drd1_vbus, 1); +} + +static struct edp_video_info dp_video_info = { + .master_mode = 0, + .h_sync_polarity = 0, + .v_sync_polarity = 0, + .interlaced = 0, + .color_space = COLOR_RGB, + .dynamic_range = VESA, + .ycbcr_coeff = COLOR_YCBCR601, + .color_depth = COLOR_8, +}; + +/* FIXME: move some place more appropriate */ +#define MAX_DP_TRIES 5 + +static void setup_storage(void) +{ + /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ + if (clock_set_dwmci(PERIPH_ID_SDMMC0)) + printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); + exynos_pinmux_sdmmc0(); + + /* MMC2: Removable, 4 bit mode, no GPIO. */ + /* (Must be after romstage to avoid breaking SDMMC boot.) */ + clock_set_dwmci(PERIPH_ID_SDMMC2); + exynos_pinmux_sdmmc2(); +} + +static void gpio_init(void) +{ + /* Set up the I2C busses. */ + exynos_pinmux_i2c2(); + exynos_pinmux_i2c4(); + exynos_pinmux_i2c7(); + exynos_pinmux_i2c8(); + exynos_pinmux_i2c9(); + exynos_pinmux_i2c10(); +} + +enum { + FET_CTRL_WAIT = 3 << 2, + FET_CTRL_ADENFET = 1 << 1, + FET_CTRL_ENFET = 1 << 0 +}; + +static void tps65090_thru_ec_fet_set(int index) +{ + uint8_t value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET; + + if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { + printk(BIOS_ERR, + "Error sending i2c pass through command to EC.\n"); + return; + } +} + +static void lcd_vdd(void) +{ + /* Enable FET6, lcd panel */ + tps65090_thru_ec_fet_set(6); +} + +static void backlight_vdd(void) +{ + /* Enable FET1, backlight */ + tps65090_thru_ec_fet_set(1); +} + +static void sdmmc_vdd(void) +{ + /* Enable FET4, P3.3V_SDCARD */ + tps65090_thru_ec_fet_set(4); +} + +/* this happens after cpu_init where exynos resources are set */ +static void mainboard_init(device_t dev) +{ + /* we'll stick with the crummy u-boot struct for now.*/ + /* doing this as an auto since the struct has to be writeable */ + struct edp_device_info device_info; + + void *fb_addr = (void *)(get_fb_base_kb() * KiB); + + prepare_usb(); + gpio_init(); + setup_storage(); + tmu_init(&exynos5420_tmu_info); + + /* Clock Gating all the unused IP's to save power */ + clock_gate(); + + sdmmc_vdd(); + + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + + /* + * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 + * should be 0 according to the datasheet, but has experimentally + * been found to come up as 3. This means FIMD SYSMMU is on by + * default on Exynos5420. For now we are disabling FIMD SYSMMU. + */ + writel(0x0, (void *)0x14640000); + writel(0x0, (void *)0x14680000); + + lcd_vdd(); + + /* Start the fimd running before you do the phy and lcd setup. + * why do fimd before training etc? + * because we need a data stream from + * the fimd or the clock recovery step fails. + */ + vidinfo.screen_base = fb_addr; + exynos_fimd_lcd_init(&vidinfo); + + parade_dp_bridge_setup(); + + /* this might get more dynamic in future ... */ + memset(&device_info, 0, sizeof(device_info)); + device_info.disp_info.name = (char *)"Peach Pit display"; + device_info.disp_info.h_total = 1366; + device_info.disp_info.v_total = 768; + device_info.video_info = dp_video_info; + device_info.raw_edid = panel_edid; + exynos_init_dp(&device_info); + + backlight_vdd(); + backlight_pwm(); + backlight_en(); + + setup_usb(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; + + /* set up caching for the DRAM */ + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); + tlb_invalidate_all(); + + const unsigned epll_hz = 192000000; + const unsigned sample_rate = 48000; + const unsigned lr_frame_size = 256; + clock_epll_set_rate(epll_hz); + clock_select_i2s_clk_source(); + clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); + + power_enable_xclkout(); +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM Chromebook", + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (intptr_t)DMA_START; + dma->range_size = DMA_SIZE; +} diff --git a/src/mainboard/google/peach_pit/memory.c b/src/mainboard/google/peach_pit/memory.c new file mode 100644 index 0000000..8a9f454 --- /dev/null +++ b/src/mainboard/google/peach_pit/memory.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Samsung Electronics + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <stdlib.h> +#include <console/console.h> + +#include <soc/samsung/exynos5420/gpio.h> +#include <soc/samsung/exynos5420/dmc.h> +#include <soc/samsung/exynos5420/setup.h> +#include <soc/samsung/exynos5420/clk.h> + +const struct mem_timings mem_timings = { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010046, 0x00000d70, + 0x00000c70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x6836650f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a26, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_DSREF_DISABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + /* + * For channel interleaving, the chip_base needs to be set to + * half the bus address. So for a base address of 0x2000_0000, + * the chip_base value is 0x20 without interleaving and 0x10 + * with channel interleaving. See note in section 17.14. + */ + .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB, + .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 1, + .chips_per_channel = 1, + .chips_to_configure = 1, + .send_zq_init = 1, + .gate_leveling_enable = 1, +}; diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c new file mode 100644 index 0000000..16dc997 --- /dev/null +++ b/src/mainboard/google/peach_pit/romstage.c @@ -0,0 +1,279 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <stdlib.h> + +#include <armv7.h> +#include <cbfs.h> +#include <cbmem.h> + +#include <arch/cache.h> +#include <arch/exception.h> +#include <soc/samsung/exynos5420/i2c.h> +#include <soc/samsung/exynos5420/clk.h> +#include <soc/samsung/exynos5420/cpu.h> +#include <soc/samsung/exynos5420/dmc.h> +#include <soc/samsung/exynos5420/gpio.h> +#include <soc/samsung/exynos5420/setup.h> +#include <soc/samsung/exynos5420/periph.h> +#include <soc/samsung/exynos5420/power.h> +#include <soc/samsung/exynos5420/trustzone.h> +#include <soc/samsung/exynos5420/wakeup.h> +#include <console/console.h> +#include <arch/stages.h> + +#include <drivers/maxim/max77802/max77802.h> +#include <device/i2c.h> + +#define PMIC_I2C_BUS 4 + +struct pmic_write +{ + int or_orig; // Whether to or in the original value. + uint8_t reg; // Register to write. + uint8_t val; // Value to write. +}; + +/* + * Use read-modify-write for MAX77802 control registers and clobber the + * output voltage setting (BUCK?DVS?) registers. + */ +struct pmic_write pmic_writes[] = +{ + { 1, MAX77802_REG_PMIC_32KHZ, MAX77802_32KHCP_EN }, + { 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON | + MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, + { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1_2625V }, + { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON | + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK3CTRL1, MAX77802_BUCK_TYPE2_ON | + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + { 0, MAX77802_REG_PMIC_BUCK4DVS1, MAX77802_BUCK4DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK4CTRL1, MAX77802_BUCK_TYPE2_ON | + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | + MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, + /* Disable Boost(bypass) OUTPUT */ + { 0, MAX77802_REG_PMIC_BOOSTCTRL, MAX77802_BOOSTCTRL_OFF}, +}; + +static int setup_power(int is_resume) +{ + int error = 0; + int i; + + power_init(); + + if (is_resume) { + return 0; + } + + /* Initialize I2C bus to configure PMIC. */ + exynos_pinmux_i2c4(); + i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ + + for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { + uint8_t data = 0; + uint8_t reg = pmic_writes[i].reg; + + if (pmic_writes[i].or_orig) + error |= i2c_read(4, MAX77802_I2C_ADDR, + reg, sizeof(reg), + &data, sizeof(data)); + data |= pmic_writes[i].val; + error |= i2c_write(4, MAX77802_I2C_ADDR, + reg, sizeof(reg), + &data, sizeof(data)); + } + + return error; +} + +static void setup_ec(void) +{ + /* SPI2 (EC) is slower and needs to work in half-duplex mode with + * single byte bus width. */ + clock_set_rate(PERIPH_ID_SPI2, 5000000); + exynos_pinmux_spi2(); +} + +static void setup_gpio(void) +{ + gpio_direction_input(GPIO_X30); // WP_GPIO + gpio_set_pull(GPIO_X30, GPIO_PULL_NONE); + + gpio_direction_input(GPIO_X07); // RECMODE_GPIO + gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); + + gpio_direction_input(GPIO_X34); // LID_GPIO + gpio_set_pull(GPIO_X34, GPIO_PULL_NONE); + + gpio_direction_input(GPIO_X12); // POWER_GPIO + gpio_set_pull(GPIO_X12, GPIO_PULL_NONE); +} + +static void setup_memory(struct mem_timings *mem, int is_resume) +{ + printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz); + + if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { + die("Failed to initialize memory controller.\n"); + } +} + +#define PRIMITIVE_MEM_TEST 0 +#if PRIMITIVE_MEM_TEST +static unsigned long primitive_mem_test(void) +{ + unsigned long *l = (void *)0x40000000; + int bad = 0; + unsigned long i; + for(i = 0; i < 256*1048576; i++){ + if (! (i%1048576)) + printk(BIOS_SPEW, "%lu ...", i); + l[i] = 0xffffffff - i; + } + + for(i = 0; i < 256*1048576; i++){ + if (! (i%1048576)) + printk(BIOS_SPEW, "%lu ...", i); + if (l[i] != (0xffffffff - i)){ + printk(BIOS_SPEW, "%p: want %08lx got %08lx\n", l, l[i], 0xffffffff - i); + bad++; + } + } + + printk(BIOS_SPEW, "%d errors\n", bad); + + return bad; +} +#else +#define primitive_mem_test() +#endif + +#define SIMPLE_SPI_TEST 0 +#if SIMPLE_SPI_TEST +/* here is a simple SPI debug test, known to fid trouble */ +static void simple_spi_test(void) +{ + struct cbfs_media default_media, *media; + int i, amt = 4 * MiB, errors = 0; + //u32 *data = (void *)0x40000000; + u32 data[1024]; + u32 in; + + amt = sizeof(data); + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + printk(BIOS_SPEW, "Failed to initialize default media.\n"); + return; + } + + + media->open(media); + if (media->read(media, data, (size_t) 0, amt) < amt){ + printk(BIOS_SPEW, "simple_spi_test fails\n"); + return; + } + + + for(i = 0; i < amt; i += 4){ + if (media->read(media, &in, (size_t) i, 4) < 1){ + printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); + return; + } + if (data[i/4] != in){ + errors++; + printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n", + i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); + /* reread it to see which is wrong. */ + if (media->read(media, &in, (size_t) i, 4) < 1){ + printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); + return; + } + printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n", + i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); + } + + } + printk(BIOS_SPEW, "%d errors\n", errors); +} +#else +#define simple_spi_test() +#endif + +void main(void) +{ + + extern struct mem_timings mem_timings; + void *entry; + int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); + int power_init_failed; + + exynos5420_config_smp(); + power_init_failed = setup_power(is_resume); + + /* Clock must be initialized before console_init, otherwise you may need + * to re-initialize serial console drivers again. */ + system_clock_init(); + + exynos_pinmux_uart3(); + console_init(); + exception_init(); + + if (power_init_failed) + die("Failed to intialize power.\n"); + + /* re-initialize PMIC I2C channel after (re-)setting system clocks */ + i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ + + setup_memory(&mem_timings, is_resume); + + primitive_mem_test(); + + trustzone_init(); + + if (is_resume) { + wakeup(); + } + + setup_gpio(); + setup_ec(); + + simple_spi_test(); + /* Set SPI (primary CBFS media) clock to 50MHz. */ + /* if this is uncommented SPI will not work correctly. */ + clock_set_rate(PERIPH_ID_SPI1, 50000000); + exynos_pinmux_spi1(); + simple_spi_test(); + + cbmem_initialize_empty(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + simple_spi_test(); + stage_exit(entry); +} diff --git a/src/mainboard/google/peach_pit/wakeup.c b/src/mainboard/google/peach_pit/wakeup.c new file mode 100644 index 0000000..130282c --- /dev/null +++ b/src/mainboard/google/peach_pit/wakeup.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/samsung/exynos5420/gpio.h> +#include <soc/samsung/exynos5420/wakeup.h> + +int wakeup_need_reset(void) +{ + /* The "wake up" event is not reliable (known as "bad wakeup") and needs + * reset if the TPM reset mask GPIO value is high. */ + return gpio_get_value(GPIO_X06); +} diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig deleted file mode 100644 index 5196c2c..0000000 --- a/src/mainboard/google/pit/Kconfig +++ /dev/null @@ -1,53 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -if BOARD_GOOGLE_PIT - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_SAMSUNG_EXYNOS5420 - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_SPI - select BOARD_ROMSIZE_KB_4096 - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT - select DRIVER_PARADE_PS8625 - -config MAINBOARD_DIR - string - default google/pit - -config MAINBOARD_PART_NUMBER - string - default "Pit" - -config DRAM_SIZE_MB - int - default 2048 - -config EC_GOOGLE_CHROMEEC_SPI_BUS - hex - default 2 - -config UART_FOR_CONSOLE - int - default 3 - -endif # BOARD_GOOGLE_PIT diff --git a/src/mainboard/google/pit/Makefile.inc b/src/mainboard/google/pit/Makefile.inc deleted file mode 100644 index df9b797..0000000 --- a/src/mainboard/google/pit/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -bootblock-y += wakeup.c - -romstage-y += memory.c -romstage-y += romstage.c -romstage-y += wakeup.c -romstage-y += chromeos.c - -ramstage-y += mainboard.c -ramstage-y += chromeos.c diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c deleted file mode 100644 index 7b0807c..0000000 --- a/src/mainboard/google/pit/chromeos.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <boot/coreboot_tables.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <bootmode.h> -#include <soc/samsung/exynos5420/cpu.h> -#include <soc/samsung/exynos5420/gpio.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - int count = 0; - - /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_X30); // WP_GPIO - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Recovery: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Lid: active high */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X34); // LID_GPIO - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: virtual GPIO active low */ - gpios->gpios[count].port = EXYNOS5_GPX1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = - gpio_get_value(GPIO_X12); // POWER_GPIO - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* Developer: virtual GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "developer", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); -} - -int get_developer_mode_switch(void) -{ - return 0; -} - -int get_recovery_mode_switch(void) -{ - uint32_t ec_events; - - /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -} - -int get_write_protect_state(void) -{ - return !gpio_get_value(GPIO_X30); -} diff --git a/src/mainboard/google/pit/devicetree.cb b/src/mainboard/google/pit/devicetree.cb deleted file mode 100644 index 568daf8..0000000 --- a/src/mainboard/google/pit/devicetree.cb +++ /dev/null @@ -1,33 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -chip soc/samsung/exynos5420 - device cpu_cluster 0 on end - register "xres" = "1366" - register "yres" = "768" - register "framebuffer_bits_per_pixel" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" -end diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c deleted file mode 100644 index c07db7b..0000000 --- a/src/mainboard/google/pit/mainboard.c +++ /dev/null @@ -1,498 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <console/console.h> -#include <device/device.h> -#include <device/i2c.h> -#include <cbmem.h> -#include <delay.h> -#include <edid.h> -#include <vbe.h> -#include <boot/coreboot_tables.h> -#include <arch/cache.h> -#include <soc/samsung/exynos5420/tmu.h> -#include <soc/samsung/exynos5420/clk.h> -#include <soc/samsung/exynos5420/cpu.h> -#include <soc/samsung/exynos5420/gpio.h> -#include <soc/samsung/exynos5420/power.h> -#include <soc/samsung/exynos5420/i2c.h> -#include <soc/samsung/exynos5420/dp.h> -#include <soc/samsung/exynos5420/fimd.h> -#include <soc/samsung/exynos5420/usb.h> -#include <drivers/parade/ps8625/ps8625.h> -#include <ec/google/chromeec/ec.h> -#include <stdlib.h> - -/* convenient shorthand (in MB) */ -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB - -/* Arbitrary range of DMA memory for depthcharge's drivers */ -#define DMA_START (0x77300000) -#define DMA_SIZE (0x00100000) - -static struct edid edid = { - .ha = 1366, - .va = 768, - .framebuffer_bits_per_pixel = 16, - .x_resolution = 1366, - .y_resolution = 768, - .bytes_per_line = 2 * 1366 -}; - -/* from the fdt */ -static struct vidinfo vidinfo = { - .vl_freq = 60, - .vl_col = 1366, - .vl_row = 768, - .vl_width = 1366, - .vl_height = 768, - .vl_clkp = 1, - .vl_dp = 1, - .vl_bpix = 4, - .vl_hspw = 32, - .vl_hbpd = 40, - .vl_hfpd = 40, - .vl_vspw = 6, - .vl_vbpd = 10, - .vl_vfpd = 12, - .vl_cmd_allow_len = 0xf, - .win_id = 3, - .dp_enabled = 1, - .dual_lcd_enabled = 0, - .interface_mode = FIMD_RGB_INTERFACE, -}; - -static unsigned char panel_edid[] = { - 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00, - 0x06,0xaf,0x5c,0x31,0x00,0x00,0x00,0x00, - 0x00,0x16,0x01,0x03,0x80,0x1a,0x0e,0x78, - 0x0a,0x99,0x85,0x95,0x55,0x56,0x92,0x28, - 0x22,0x50,0x54,0x00,0x00,0x00,0x01,0x01, - 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, - 0x01,0x01,0x01,0x01,0x01,0x01,0xa3,0x1b, - 0x56,0x7e,0x50,0x00,0x16,0x30,0x30,0x20, - 0x36,0x00,0x00,0x90,0x10,0x00,0x00,0x18, - 0x6d,0x12,0x56,0x7e,0x50,0x00,0x16,0x30, - 0x30,0x20,0x36,0x00,0x00,0x90,0x10,0x00, - 0x00,0x18,0x00,0x00,0x00,0xfe,0x00,0x41, - 0x55,0x4f,0x0a,0x20,0x20,0x20,0x20,0x20, - 0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xfe, - 0x00,0x42,0x31,0x31,0x36,0x58,0x57,0x30, - 0x33,0x20,0x56,0x31,0x20,0x0a,0x00,0x3d, - 0x00,0xc0,0x00,0x00,0x27,0xfd,0x00,0x20, - 0x02,0x59,0x07,0x00,0x64,0x3e,0x07,0x02, - 0x00,0x00,0xcd,0x12,0x59,0xff,0x10,0x03, - 0x00,0x00,0x00,0x00,0x64,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x05,0x00,0x00,0x00, - 0x9c,0x3f,0x07,0x02,0x31,0xf9,0x00,0x20, - 0x59,0xff,0x10,0x03,0x00,0x00,0x00,0x00, - 0xbc,0x3e,0x07,0x02,0xc0,0x9b,0x01,0x20, - 0x00,0x00,0x00,0x00,0xdb,0xf8,0x00,0x20, - 0x98,0x3e,0x07,0x02,0x8b,0xaf,0x00,0x20, - 0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0xe5,0xcd,0x16,0x00,0xe9,0xcd,0x16,0x00, - 0xe8,0x03,0x00,0x00,0x6c,0x55,0x01,0x20, - 0x2c,0x01,0x00,0x00,0x85,0xbb,0x00,0x20, - 0xe8,0x03,0x00,0x00,0xe9,0xcd,0x16,0x00, -}; - -static const struct parade_write parade_writes[] = { - { 0x02, 0xa1, 0x01 }, /* HPD low */ - /* - * SW setting - * [1:0] SW output 1.2V voltage is lower to 96% - */ - { 0x04, 0x14, 0x01 }, - /* - * RCO SS setting - * [5:4] = b01 0.5%, b10 1%, b11 1.5% - */ - { 0x04, 0xe3, 0x20 }, - { 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */ - /* - * RPHY Setting - * [3:2] CDR tune wait cycle before - * measure for fine tune b00: 1us, - * 01: 0.5us, 10:2us, 11:4us. - */ - { 0x04, 0x8a, 0x0c }, - { 0x04, 0x89, 0x08 }, /* [3] RFD always on */ - /* - * CTN lock in/out: - * 20000ppm/80000ppm. Lock out 2 - * times. - */ - { 0x04, 0x71, 0x2d }, - /* - * 2.7G CDR settings - * NOF=40LSB for HBR CDR setting - */ - { 0x04, 0x7d, 0x07 }, - { 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */ - { 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */ - /* - * 1.62G CDR settings - * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 - */ - { 0x04, 0xc0, 0x12 }, - { 0x04, 0xc1, 0x92 }, /* Gitune=-37% */ - { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */ - { 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */ - /* - * RPIO Setting - * [7:4] LVDS driver bias current : - * 75% (250mV swing) - */ - { 0x04, 0x00, 0xb0 }, - /* - * [7:6] Right-bar GPIO output strength is 8mA - */ - { 0x04, 0x15, 0x40 }, - /* EQ Training State Machine Setting */ - { 0x04, 0x54, 0x10 }, /* RCO calibration start */ - /* [4:0] MAX_LANE_COUNT set to one lane */ - { 0x01, 0x02, 0x81 }, - /* [4:0] LANE_COUNT_SET set to one lane */ - { 0x01, 0x21, 0x81 }, - { 0x00, 0x52, 0x20 }, - { 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */ - { 0x00, 0x62, 0x41 }, - /* Counter number, add 1ms counter delay */ - { 0x00, 0xf6, 0x01 }, - /* - * [6]PWM function control by - * DPCD0040f[7], default is PWM - * block always works. - */ - { 0x00, 0x77, 0x06 }, - /* - * 04h Adjust VTotal tolerance to - * fix the 30Hz no display issue - */ - { 0x00, 0x4c, 0x04 }, - /* DPCD00400='h00, Parade OUI = 'h001cf8 */ - { 0x01, 0xc0, 0x00 }, - { 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */ - { 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */ - /* - * DPCD403~408 = ASCII code - * D2SLV5='h4432534c5635 - */ - { 0x01, 0xc3, 0x44 }, - { 0x01, 0xc4, 0x32 }, /* DPCD404 */ - { 0x01, 0xc5, 0x53 }, /* DPCD405 */ - { 0x01, 0xc6, 0x4c }, /* DPCD406 */ - { 0x01, 0xc7, 0x56 }, /* DPCD407 */ - { 0x01, 0xc8, 0x35 }, /* DPCD408 */ - /* - * DPCD40A, Initial Code major revision - * '01' - */ - { 0x01, 0xca, 0x01 }, - /* DPCD40B, Initial Code minor revision '05' */ - { 0x01, 0xcb, 0x05 }, - /* DPCD720, Select external PWM */ - { 0x01, 0xa5, 0x80 }, - /* - * Set LVDS output as 6bit-VESA mapping, - * single LVDS channel - */ - { 0x01, 0xcc, 0x13 }, - /* Enable SSC set by register */ - { 0x02, 0xb1, 0x20 }, - /* - * Set SSC enabled and +/-1% central - * spreading - */ - { 0x04, 0x10, 0x16 }, - /* MPU Clock source: LC => RCO */ - { 0x04, 0x59, 0x60 }, - { 0x04, 0x54, 0x14 }, /* LC -> RCO */ - { 0x02, 0xa1, 0x91 } /* HPD high */ -}; - -/* TODO: transplanted DP stuff, clean up once we have something that works */ -static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */ -static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */ -static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */ -static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ -static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ - -static void parade_dp_bridge_setup(void) -{ - int i; - - gpio_set_value(dp_pd_l, 1); - gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); - gpio_set_pull(dp_pd_l, GPIO_PULL_NONE); - - gpio_set_value(dp_rst_l, 0); - gpio_cfg_pin(dp_rst_l, GPIO_OUTPUT); - gpio_set_pull(dp_rst_l, GPIO_PULL_NONE); - udelay(10); - gpio_set_value(dp_rst_l, 1); - - - gpio_set_pull(dp_hpd, GPIO_PULL_NONE); - gpio_cfg_pin(dp_hpd, GPIO_INPUT); - - /* De-assert PD (and possibly RST) to power up the bridge. */ - gpio_set_value(dp_pd_l, 1); - gpio_set_value(dp_rst_l, 1); - - /* Hang around for the bridge to come up. */ - mdelay(40); - - /* Configure the bridge chip. */ - exynos_pinmux_i2c7(); - i2c_init(7, 100000, 0x00); - - parade_ps8625_bridge_setup(7, 0x48, parade_writes, - ARRAY_SIZE(parade_writes)); - /* Spin until the display is ready. - * It's quite important to try really hard to get the display up, - * so be generous. It will typically be ready in only 5 ms. and - * we're out of here. - * If it's not ready after a second, then we're in big trouble. - */ - for(i = 0; i < 1000; i++){ - if (gpio_get_value(dp_hpd)) - break; - mdelay(1); - } -} - -/* - * This delay is T3 in the LCD timing spec (defined as >200ms). We set - * this down to 60ms since that's the approximate maximum amount of time - * it'll take a bridge to start outputting LVDS data. The delay of - * >200ms is just a conservative value to avoid turning on the backlight - * when there's random LCD data on the screen. Shaving 140ms off the - * boot is an acceptable trade-off. - */ -#define LCD_T3_DELAY_MS 60 - -#define LCD_T5_DELAY_MS 10 -#define LCD_T6_DELAY_MS 10 - -static void backlight_pwm(void) -{ - /*Configure backlight PWM as a simple output high (100% brightness) */ - gpio_direction_output(bl_pwm, 1); - udelay(LCD_T6_DELAY_MS * 1000); -} - -static void backlight_en(void) -{ - /* Configure GPIO for LCD_BL_EN */ - gpio_direction_output(bl_en, 1); -} - -static enum exynos5_gpio_pin usb_drd0_vbus = GPIO_H00; -static enum exynos5_gpio_pin usb_drd1_vbus = GPIO_H01; -/* static enum exynos5_gpio_pin hsic_reset_l = GPIO_X24; */ - -static void prepare_usb(void) -{ - /* Kick these resets off early so they get at least 100ms to settle */ - reset_usb_drd0_dwc3(); - reset_usb_drd1_dwc3(); -} - -static void setup_usb(void) -{ - /* HSIC and USB HOST port not needed in firmware on this board */ - setup_usb_drd0_phy(); - setup_usb_drd1_phy(); - - setup_usb_drd0_dwc3(); - setup_usb_drd1_dwc3(); - - gpio_direction_output(usb_drd0_vbus, 1); - gpio_direction_output(usb_drd1_vbus, 1); -} - -static struct edp_video_info dp_video_info = { - .master_mode = 0, - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, -}; - -/* FIXME: move some place more appropriate */ -#define MAX_DP_TRIES 5 - -static void setup_storage(void) -{ - /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ - if (clock_set_dwmci(PERIPH_ID_SDMMC0)) - printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); - exynos_pinmux_sdmmc0(); - - /* MMC2: Removable, 4 bit mode, no GPIO. */ - /* (Must be after romstage to avoid breaking SDMMC boot.) */ - clock_set_dwmci(PERIPH_ID_SDMMC2); - exynos_pinmux_sdmmc2(); -} - -static void gpio_init(void) -{ - /* Set up the I2C busses. */ - exynos_pinmux_i2c2(); - exynos_pinmux_i2c4(); - exynos_pinmux_i2c7(); - exynos_pinmux_i2c8(); - exynos_pinmux_i2c9(); - exynos_pinmux_i2c10(); -} - -enum { - FET_CTRL_WAIT = 3 << 2, - FET_CTRL_ADENFET = 1 << 1, - FET_CTRL_ENFET = 1 << 0 -}; - -static void tps65090_thru_ec_fet_set(int index) -{ - uint8_t value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET; - - if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { - printk(BIOS_ERR, - "Error sending i2c pass through command to EC.\n"); - return; - } -} - -static void lcd_vdd(void) -{ - /* Enable FET6, lcd panel */ - tps65090_thru_ec_fet_set(6); -} - -static void backlight_vdd(void) -{ - /* Enable FET1, backlight */ - tps65090_thru_ec_fet_set(1); -} - -static void sdmmc_vdd(void) -{ - /* Enable FET4, P3.3V_SDCARD */ - tps65090_thru_ec_fet_set(4); -} - -/* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) -{ - /* we'll stick with the crummy u-boot struct for now.*/ - /* doing this as an auto since the struct has to be writeable */ - struct edp_device_info device_info; - - void *fb_addr = (void *)(get_fb_base_kb() * KiB); - - prepare_usb(); - gpio_init(); - setup_storage(); - tmu_init(&exynos5420_tmu_info); - - /* Clock Gating all the unused IP's to save power */ - clock_gate(); - - sdmmc_vdd(); - - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); - - /* - * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 - * should be 0 according to the datasheet, but has experimentally - * been found to come up as 3. This means FIMD SYSMMU is on by - * default on Exynos5420. For now we are disabling FIMD SYSMMU. - */ - writel(0x0, (void *)0x14640000); - writel(0x0, (void *)0x14680000); - - lcd_vdd(); - - /* Start the fimd running before you do the phy and lcd setup. - * why do fimd before training etc? - * because we need a data stream from - * the fimd or the clock recovery step fails. - */ - vidinfo.screen_base = fb_addr; - exynos_fimd_lcd_init(&vidinfo); - - parade_dp_bridge_setup(); - - /* this might get more dynamic in future ... */ - memset(&device_info, 0, sizeof(device_info)); - device_info.disp_info.name = (char *)"Pit display"; - device_info.disp_info.h_total = 1366; - device_info.disp_info.v_total = 768; - device_info.video_info = dp_video_info; - device_info.raw_edid = panel_edid; - exynos_init_dp(&device_info); - - backlight_vdd(); - backlight_pwm(); - backlight_en(); - - setup_usb(); -} - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = &mainboard_init; - - /* set up caching for the DRAM */ - mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); - mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); - tlb_invalidate_all(); - - const unsigned epll_hz = 192000000; - const unsigned sample_rate = 48000; - const unsigned lr_frame_size = 256; - clock_epll_set_rate(epll_hz); - clock_select_i2s_clk_source(); - clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); - - power_enable_xclkout(); -} - -struct chip_operations mainboard_ops = { - .name = "Samsung/Google ARM Chromebook", - .enable_dev = mainboard_enable, -}; - -void lb_board(struct lb_header *header) -{ - struct lb_range *dma; - - dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; - dma->size = sizeof(*dma); - dma->range_start = (intptr_t)DMA_START; - dma->range_size = DMA_SIZE; -} diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c deleted file mode 100644 index 8a9f454..0000000 --- a/src/mainboard/google/pit/memory.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Samsung Electronics - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stddef.h> -#include <stdlib.h> -#include <console/console.h> - -#include <soc/samsung/exynos5420/gpio.h> -#include <soc/samsung/exynos5420/dmc.h> -#include <soc/samsung/exynos5420/setup.h> -#include <soc/samsung/exynos5420/clk.h> - -const struct mem_timings mem_timings = { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010046, 0x00000d70, - 0x00000c70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x6836650f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a26, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_DSREF_DISABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - /* - * For channel interleaving, the chip_base needs to be set to - * half the bus address. So for a base address of 0x2000_0000, - * the chip_base value is 0x20 without interleaving and 0x10 - * with channel interleaving. See note in section 17.14. - */ - .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB, - .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 1, - .chips_per_channel = 1, - .chips_to_configure = 1, - .send_zq_init = 1, - .gate_leveling_enable = 1, -}; diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c deleted file mode 100644 index 16dc997..0000000 --- a/src/mainboard/google/pit/romstage.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <stdlib.h> - -#include <armv7.h> -#include <cbfs.h> -#include <cbmem.h> - -#include <arch/cache.h> -#include <arch/exception.h> -#include <soc/samsung/exynos5420/i2c.h> -#include <soc/samsung/exynos5420/clk.h> -#include <soc/samsung/exynos5420/cpu.h> -#include <soc/samsung/exynos5420/dmc.h> -#include <soc/samsung/exynos5420/gpio.h> -#include <soc/samsung/exynos5420/setup.h> -#include <soc/samsung/exynos5420/periph.h> -#include <soc/samsung/exynos5420/power.h> -#include <soc/samsung/exynos5420/trustzone.h> -#include <soc/samsung/exynos5420/wakeup.h> -#include <console/console.h> -#include <arch/stages.h> - -#include <drivers/maxim/max77802/max77802.h> -#include <device/i2c.h> - -#define PMIC_I2C_BUS 4 - -struct pmic_write -{ - int or_orig; // Whether to or in the original value. - uint8_t reg; // Register to write. - uint8_t val; // Value to write. -}; - -/* - * Use read-modify-write for MAX77802 control registers and clobber the - * output voltage setting (BUCK?DVS?) registers. - */ -struct pmic_write pmic_writes[] = -{ - { 1, MAX77802_REG_PMIC_32KHZ, MAX77802_32KHCP_EN }, - { 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V }, - { 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON | - MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, - { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1_2625V }, - { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON | - MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, - { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V }, - { 1, MAX77802_REG_PMIC_BUCK3CTRL1, MAX77802_BUCK_TYPE2_ON | - MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, - { 0, MAX77802_REG_PMIC_BUCK4DVS1, MAX77802_BUCK4DVS1_1V }, - { 1, MAX77802_REG_PMIC_BUCK4CTRL1, MAX77802_BUCK_TYPE2_ON | - MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, - { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, - { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | - MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, - /* Disable Boost(bypass) OUTPUT */ - { 0, MAX77802_REG_PMIC_BOOSTCTRL, MAX77802_BOOSTCTRL_OFF}, -}; - -static int setup_power(int is_resume) -{ - int error = 0; - int i; - - power_init(); - - if (is_resume) { - return 0; - } - - /* Initialize I2C bus to configure PMIC. */ - exynos_pinmux_i2c4(); - i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ - - for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { - uint8_t data = 0; - uint8_t reg = pmic_writes[i].reg; - - if (pmic_writes[i].or_orig) - error |= i2c_read(4, MAX77802_I2C_ADDR, - reg, sizeof(reg), - &data, sizeof(data)); - data |= pmic_writes[i].val; - error |= i2c_write(4, MAX77802_I2C_ADDR, - reg, sizeof(reg), - &data, sizeof(data)); - } - - return error; -} - -static void setup_ec(void) -{ - /* SPI2 (EC) is slower and needs to work in half-duplex mode with - * single byte bus width. */ - clock_set_rate(PERIPH_ID_SPI2, 5000000); - exynos_pinmux_spi2(); -} - -static void setup_gpio(void) -{ - gpio_direction_input(GPIO_X30); // WP_GPIO - gpio_set_pull(GPIO_X30, GPIO_PULL_NONE); - - gpio_direction_input(GPIO_X07); // RECMODE_GPIO - gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); - - gpio_direction_input(GPIO_X34); // LID_GPIO - gpio_set_pull(GPIO_X34, GPIO_PULL_NONE); - - gpio_direction_input(GPIO_X12); // POWER_GPIO - gpio_set_pull(GPIO_X12, GPIO_PULL_NONE); -} - -static void setup_memory(struct mem_timings *mem, int is_resume) -{ - printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); - - if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { - die("Failed to initialize memory controller.\n"); - } -} - -#define PRIMITIVE_MEM_TEST 0 -#if PRIMITIVE_MEM_TEST -static unsigned long primitive_mem_test(void) -{ - unsigned long *l = (void *)0x40000000; - int bad = 0; - unsigned long i; - for(i = 0; i < 256*1048576; i++){ - if (! (i%1048576)) - printk(BIOS_SPEW, "%lu ...", i); - l[i] = 0xffffffff - i; - } - - for(i = 0; i < 256*1048576; i++){ - if (! (i%1048576)) - printk(BIOS_SPEW, "%lu ...", i); - if (l[i] != (0xffffffff - i)){ - printk(BIOS_SPEW, "%p: want %08lx got %08lx\n", l, l[i], 0xffffffff - i); - bad++; - } - } - - printk(BIOS_SPEW, "%d errors\n", bad); - - return bad; -} -#else -#define primitive_mem_test() -#endif - -#define SIMPLE_SPI_TEST 0 -#if SIMPLE_SPI_TEST -/* here is a simple SPI debug test, known to fid trouble */ -static void simple_spi_test(void) -{ - struct cbfs_media default_media, *media; - int i, amt = 4 * MiB, errors = 0; - //u32 *data = (void *)0x40000000; - u32 data[1024]; - u32 in; - - amt = sizeof(data); - media = &default_media; - if (init_default_cbfs_media(media) != 0) { - printk(BIOS_SPEW, "Failed to initialize default media.\n"); - return; - } - - - media->open(media); - if (media->read(media, data, (size_t) 0, amt) < amt){ - printk(BIOS_SPEW, "simple_spi_test fails\n"); - return; - } - - - for(i = 0; i < amt; i += 4){ - if (media->read(media, &in, (size_t) i, 4) < 1){ - printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); - return; - } - if (data[i/4] != in){ - errors++; - printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n", - i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); - /* reread it to see which is wrong. */ - if (media->read(media, &in, (size_t) i, 4) < 1){ - printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); - return; - } - printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n", - i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); - } - - } - printk(BIOS_SPEW, "%d errors\n", errors); -} -#else -#define simple_spi_test() -#endif - -void main(void) -{ - - extern struct mem_timings mem_timings; - void *entry; - int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); - int power_init_failed; - - exynos5420_config_smp(); - power_init_failed = setup_power(is_resume); - - /* Clock must be initialized before console_init, otherwise you may need - * to re-initialize serial console drivers again. */ - system_clock_init(); - - exynos_pinmux_uart3(); - console_init(); - exception_init(); - - if (power_init_failed) - die("Failed to intialize power.\n"); - - /* re-initialize PMIC I2C channel after (re-)setting system clocks */ - i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ - - setup_memory(&mem_timings, is_resume); - - primitive_mem_test(); - - trustzone_init(); - - if (is_resume) { - wakeup(); - } - - setup_gpio(); - setup_ec(); - - simple_spi_test(); - /* Set SPI (primary CBFS media) clock to 50MHz. */ - /* if this is uncommented SPI will not work correctly. */ - clock_set_rate(PERIPH_ID_SPI1, 50000000); - exynos_pinmux_spi1(); - simple_spi_test(); - - cbmem_initialize_empty(); - - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); - simple_spi_test(); - stage_exit(entry); -} diff --git a/src/mainboard/google/pit/wakeup.c b/src/mainboard/google/pit/wakeup.c deleted file mode 100644 index 130282c..0000000 --- a/src/mainboard/google/pit/wakeup.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <soc/samsung/exynos5420/gpio.h> -#include <soc/samsung/exynos5420/wakeup.h> - -int wakeup_need_reset(void) -{ - /* The "wake up" event is not reliable (known as "bad wakeup") and needs - * reset if the TPM reset mask GPIO value is high. */ - return gpio_get_value(GPIO_X06); -}

1 0

Patch set updated for coreboot: 1f997ff NOTFORMERGE: amdk8: Move to per-device ACPI
by Vladimir Serbinenko 23 Sep '14

23 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6948 -gerrit commit 1f997fffc6332c4b51f8f2b6ae60d020b0cd6fff Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Sep 21 14:31:19 2014 +0200 NOTFORMERGE: amdk8: Move to per-device ACPI Change-Id: I485791015aa7eaabba53813945c216f5725554b1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/amd/dbm690t/acpi_tables.c | 106 ------------- src/mainboard/amd/mahogany/acpi_tables.c | 157 ------------------- src/mainboard/amd/mahogany_fam10/acpi_tables.c | 6 - src/mainboard/amd/pistachio/acpi_tables.c | 105 ------------- src/mainboard/amd/tilapia_fam10/acpi_tables.c | 6 - src/mainboard/asrock/939a785gmh/acpi_tables.c | 157 ------------------- src/mainboard/asus/a8n_e/acpi_tables.c | 137 ----------------- src/mainboard/asus/a8v-e_deluxe/acpi_tables.c | 93 ------------ src/mainboard/asus/a8v-e_deluxe/dsdt.asl | 7 - src/mainboard/asus/a8v-e_se/acpi_tables.c | 110 -------------- src/mainboard/asus/k8v-x/acpi_tables.c | 110 -------------- src/mainboard/asus/m2v-mx_se/acpi_tables.c | 130 ---------------- src/mainboard/asus/m2v/acpi_tables.c | 131 ---------------- src/mainboard/asus/m4a78-em/acpi_tables.c | 6 - src/mainboard/asus/m4a785-m/acpi_tables.c | 8 - src/mainboard/gigabyte/m57sli/acpi_tables.c | 109 -------------- src/mainboard/gigabyte/ma785gm/acpi_tables.c | 6 - src/mainboard/gigabyte/ma785gmt/acpi_tables.c | 6 - src/mainboard/gigabyte/ma78gm/acpi_tables.c | 6 - src/mainboard/iei/kino-780am2-fam10/acpi_tables.c | 6 - src/mainboard/jetway/pa78vm5/acpi_tables.c | 6 - src/mainboard/kontron/kt690/acpi_tables.c | 105 ------------- src/mainboard/msi/ms7135/acpi_tables.c | 138 ----------------- src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 166 ++------------------- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 2 + src/mainboard/siemens/sitemp_g1p1/mainboard.h | 1 + src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 6 - src/mainboard/technexion/tim5690/acpi_tables.c | 105 ------------- src/mainboard/technexion/tim8690/acpi_tables.c | 105 ------------- src/mainboard/tyan/s2891/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2891/mainboard.c | 23 +++ src/mainboard/tyan/s2892/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2892/mainboard.c | 23 +++ src/mainboard/tyan/s2895/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2895/mainboard.c | 23 +++ src/mainboard/winent/mb6047/acpi_tables.c | 112 -------------- src/mainboard/winent/mb6047/mainboard.c | 23 +++ src/northbridge/amd/amdk8/Kconfig | 1 + src/northbridge/amd/amdk8/acpi.c | 4 +- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/amdk8/northbridge.c | 36 +++++ src/southbridge/amd/rs690/ht.c | 18 +++ src/southbridge/amd/sb600/lpc.c | 26 ++++ src/southbridge/amd/sb700/lpc.c | 33 +++- src/southbridge/nvidia/ck804/ht.c | 27 ++++ src/southbridge/nvidia/ck804/lpc.c | 4 + src/southbridge/nvidia/mcp55/lpc.c | 20 +++ src/southbridge/via/k8t890/traf_ctrl.c | 41 +++++ 49 files changed, 320 insertions(+), 2472 deletions(-) diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c index 87ff5ea..3206aaf 100644 --- a/src/mainboard/amd/dbm690t/acpi_tables.c +++ b/src/mainboard/amd/dbm690t/acpi_tables.c @@ -28,25 +28,6 @@ #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/acpi.h" #include <arch/cpu.h> -#include <cpu/amd/model_fxx_powernow.h> - -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} unsigned long acpi_fill_madt(unsigned long current) { @@ -72,90 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/mahogany/acpi_tables.c b/src/mainboard/amd/mahogany/acpi_tables.c index ef2690a..7c94e03 100644 --- a/src/mainboard/amd/mahogany/acpi_tables.c +++ b/src/mainboard/amd/mahogany/acpi_tables.c @@ -28,32 +28,8 @@ #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/acpi.h" #include <arch/cpu.h> -#include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/sb700/sb700.h> -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -78,136 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - - for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ - if ((sysconf.pci1234[i] & 1) != 1) - continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *) current; - switch (sysconf.hcid[i]) { - case 1: /* 8132 */ - p = &AmlCode_ssdt2; - break; - case 2: /* 8151 */ - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c index 01172ad..5efb0ee 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c @@ -60,12 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c index 5ef0da5..717e4b4 100644 --- a/src/mainboard/amd/pistachio/acpi_tables.c +++ b/src/mainboard/amd/pistachio/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -73,90 +55,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c index 898a955..8d7f723 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ b/src/mainboard/amd/tilapia_fam10/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/asrock/939a785gmh/acpi_tables.c b/src/mainboard/asrock/939a785gmh/acpi_tables.c index 52b45f7..e6369df 100644 --- a/src/mainboard/asrock/939a785gmh/acpi_tables.c +++ b/src/mainboard/asrock/939a785gmh/acpi_tables.c @@ -31,29 +31,6 @@ #include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/sb700/sb700.h> -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -78,137 +55,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - - for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ - if ((sysconf.pci1234[i] & 1) != 1) - continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *) current; - switch (sysconf.hcid[i]) { - case 1: /* 8132 */ - p = &AmlCode_ssdt2; - break; - case 2: /* 8151 */ - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/a8n_e/acpi_tables.c b/src/mainboard/asus/a8n_e/acpi_tables.c index ee8e81f..2e06915 100644 --- a/src/mainboard/asus/a8n_e/acpi_tables.c +++ b/src/mainboard/asus/a8n_e/acpi_tables.c @@ -21,30 +21,6 @@ #include "../../../northbridge/amd/amdk8/acpi.h" //#include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - unsigned long mcfg_base; - - dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); - if (!dev) - return current; - - mcfg_base = pci_read_config16(dev, 0x90); - if ((mcfg_base & 0x1000) == 0) - return current; - - mcfg_base = (mcfg_base & 0xf) << 28; - - printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, mcfg_base, 0x0, 0x0, 0xff); - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -86,116 +62,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - //amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - mcfg = (acpi_mcfg_t *) current; - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p\n", mcfg); - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - current += hpet->header.length; - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c b/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c index 30914e4..e2fa0f0 100644 --- a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c @@ -32,25 +32,6 @@ #include "southbridge/via/vt8237r/vt8237r.h" #include "southbridge/via/k8t890/k8t890.h" -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -80,77 +61,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl index 3afcdc3..8f1e197 100644 --- a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl +++ b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl @@ -24,13 +24,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { - /* Define the main processor.*/ - Scope (\_PR) - { - Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} - Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} - } - /* For now only define 2 power states: * - S0 which is fully on * - S5 which is soft off diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c index f5f081a..2a874db 100644 --- a/src/mainboard/asus/a8v-e_se/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c @@ -34,25 +34,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -82,94 +63,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 065db1a..da4c399 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -34,25 +34,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -82,94 +63,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 91a5da1..dab35d4 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -35,25 +35,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -83,114 +64,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/m2v/acpi_tables.c b/src/mainboard/asus/m2v/acpi_tables.c index cc1070e..7ad045c 100644 --- a/src/mainboard/asus/m2v/acpi_tables.c +++ b/src/mainboard/asus/m2v/acpi_tables.c @@ -36,25 +36,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -84,115 +65,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - - return current; -} diff --git a/src/mainboard/asus/m4a78-em/acpi_tables.c b/src/mainboard/asus/m4a78-em/acpi_tables.c index 2398c01..a132b7b 100644 --- a/src/mainboard/asus/m4a78-em/acpi_tables.c +++ b/src/mainboard/asus/m4a78-em/acpi_tables.c @@ -38,12 +38,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index a8b6365..1c0afeb 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -60,14 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } - - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c index 2e2e590..81ebd90 100644 --- a/src/mainboard/gigabyte/m57sli/acpi_tables.c +++ b/src/mainboard/gigabyte/m57sli/acpi_tables.c @@ -92,112 +92,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c index 7a5df88..e961b6e 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c index 07b174c..3b776ae 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c @@ -37,12 +37,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/ma78gm/acpi_tables.c b/src/mainboard/gigabyte/ma78gm/acpi_tables.c index 07b174c..3b776ae 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma78gm/acpi_tables.c @@ -37,12 +37,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c index 01172ad..5efb0ee 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c +++ b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c @@ -60,12 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/jetway/pa78vm5/acpi_tables.c b/src/mainboard/jetway/pa78vm5/acpi_tables.c index fc6f186..eac5619 100644 --- a/src/mainboard/jetway/pa78vm5/acpi_tables.c +++ b/src/mainboard/jetway/pa78vm5/acpi_tables.c @@ -38,12 +38,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/kontron/kt690/acpi_tables.c b/src/mainboard/kontron/kt690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/kontron/kt690/acpi_tables.c +++ b/src/mainboard/kontron/kt690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c index ee8e81f..f5ddec3 100644 --- a/src/mainboard/msi/ms7135/acpi_tables.c +++ b/src/mainboard/msi/ms7135/acpi_tables.c @@ -19,31 +19,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> #include "../../../northbridge/amd/amdk8/acpi.h" -//#include <cpu/amd/model_fxx_powernow.h> - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - unsigned long mcfg_base; - - dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); - if (!dev) - return current; - - mcfg_base = pci_read_config16(dev, 0x90); - if ((mcfg_base & 0x1000) == 0) - return current; - - mcfg_base = (mcfg_base & 0xf) << 28; - - printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, mcfg_base, 0x0, 0x0, 0xff); - return current; -} /* APIC */ unsigned long acpi_fill_madt(unsigned long current) @@ -86,116 +61,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - //amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - mcfg = (acpi_mcfg_t *) current; - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p\n", mcfg); - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - current += hpet->header.length; - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index 18e1bf9..d092308 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -33,16 +33,9 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/rs690/rs690.h> +#include "mainboard.h" +#include <cbmem.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 #define GLOBAL_VARS_SIZE 0x100 typedef struct { @@ -70,24 +63,6 @@ static void acpi_write_gvars(global_vars_t *gvars) gvars->mpen = 1; } -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - struct resource *res; - resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default - - device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); - // we report mmconf base - res = probe_resource(dev, 0x1C); - if( res ) - mmconf_base = res->base; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? - - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -116,133 +91,20 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} +unsigned long mainboard_fill_ssdt(unsigned long current, const char *oem_table_id) +{ + global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE); -#define ALIGN_CURRENT current = (ALIGN(current, 16)) + if (gnvs) { + int scopelen; + acpi_write_gvars(gnvs); -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_srat_t *srat; - acpi_xsdt_t *xsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - current = start; - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 64); - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - acpi_create_facs(facs); - current += sizeof(acpi_facs_t); - - /* HPET */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - acpi_create_hpet(hpet); - current += sizeof(acpi_hpet_t); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* MCFG */ - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - /* Pack gvars into the ACPI table area */ - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xBADEAFFE) { - printk(BIOS_DEBUG, "ACPI: Patching up globals in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); - *(u32*)(((u32)dsdt) + i) = current; - break; - } + /* Add it to SSDT. */ + scopelen = acpigen_write_scope("\\"); + scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_patch_len(scopelen - 1); } - /* And fill it */ - acpi_write_gvars((global_vars_t *)current); - current += GLOBAL_VARS_SIZE; - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* SRAT */ - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - acpi_add_table(rsdp, srat); - - printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + return (unsigned long) (acpigen_get_current()); } + diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 7890df7..e106561 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -245,7 +245,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) PWDA, 1, } - OperationRegion (GVAR, SystemMemory, 0xBADEAFFE, 0x100) + External(\NVSA) + + OperationRegion (GVAR, SystemMemory, \NVSA, 0x100) Field (GVAR, ByteAcc, NoLock, Preserve) { Offset (0x00), diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 960496f..066dfb4 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -38,6 +38,7 @@ #include <x86emu/x86emu.h> #endif #include "int15_func.h" +#include "mainboard.h" // ****LCD panel ID support: ***** // Callback Sub-Function 00h - Get LCD Panel ID @@ -846,6 +847,7 @@ static void mainboard_enable(device_t dev) update_subsystemid(dev); dev->ops->init = mainboard_init; // rest of mainboard init later + dev->ops->acpi_fill_ssdt_generator = mainboard_fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.h b/src/mainboard/siemens/sitemp_g1p1/mainboard.h new file mode 100644 index 0000000..fd70365 --- /dev/null +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.h @@ -0,0 +1 @@ +unsigned long mainboard_fill_ssdt(unsigned long current, const char *oem_table_id); diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index ae9cca9..48a396e 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { device_t dev; diff --git a/src/mainboard/technexion/tim5690/acpi_tables.c b/src/mainboard/technexion/tim5690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/technexion/tim5690/acpi_tables.c +++ b/src/mainboard/technexion/tim5690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/technexion/tim8690/acpi_tables.c +++ b/src/mainboard/technexion/tim8690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c index 42d9152..424d87e 100644 --- a/src/mainboard/tyan/s2891/acpi_tables.c +++ b/src/mainboard/tyan/s2891/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -83,108 +76,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c index 42d9152..424d87e 100644 --- a/src/mainboard/tyan/s2892/acpi_tables.c +++ b/src/mainboard/tyan/s2892/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -83,108 +76,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c index 1974171..fe8d0c3 100644 --- a/src/mainboard/tyan/s2895/acpi_tables.c +++ b/src/mainboard/tyan/s2895/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -102,108 +95,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 1b59fbb..5cf5f55 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -67,108 +60,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 3f8861e..e79b6b2 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -23,6 +23,7 @@ config NORTHBRIDGE_AMD_AMDK8 select HAVE_DEBUG_SMBUS select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT + select PER_DEVICE_ACPI_TABLES if NORTHBRIDGE_AMD_AMDK8 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index f7134f6..499f3d2 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -253,7 +253,7 @@ static int k8acpi_write_pci_data(int dlen, const char *name, int offset) { return len + lenp; } -int k8acpi_write_vars(void) +unsigned long k8acpi_write_vars(unsigned long current, const char *oem_table_id) { int lens; msr_t msr; @@ -283,7 +283,7 @@ int k8acpi_write_vars(void) lens += k8acpi_write_HT(); //minus opcode acpigen_patch_len(lens - 1); - return lens; + return (unsigned long) (acpigen_get_current()); } void update_ssdtx(void *ssdtx, int i) diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index 9d0a73a..0570716 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -21,6 +21,6 @@ #define AMDK8_ACPI_H #include <arch/acpigen.h> -int k8acpi_write_vars(void); +unsigned long k8acpi_write_vars(unsigned long current, const char *oem_table_id); #endif diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 2c19b3a..bfd2c0f 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -16,6 +16,10 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +#include <arch/acpi.h> +#include "acpi.h" +#endif #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> @@ -580,10 +584,42 @@ static void mcf0_control_init(struct device *dev) #endif } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +static unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +{ + unsigned long current; + acpi_srat_t *srat; + acpi_slit_t *slit; + + current = start; + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit); + + return current; +} +#endif + static struct device_operations northbridge_operations = { .read_resources = amdk8_read_resources, .set_resources = amdk8_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .acpi_fill_ssdt_generator = k8acpi_write_vars, + .write_acpi_tables = northbridge_write_acpi_tables, +#endif .init = mcf0_control_init, .scan_bus = amdk8_scan_chains, .enable = 0, diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index 7353f76..33fce0f 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <lib.h> +#include <arch/acpi.h> #include "rs690.h" static void ht_dev_set_resources(device_t dev) @@ -84,6 +85,23 @@ static void ht_dev_set_resources(device_t dev) pci_dev_set_resources(dev); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ +#if CONFIG_EXT_CONF_SUPPORT + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default + + device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); + // we report mmconf base + res = probe_resource(dev, 0x1C); + if( res ) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? +#endif + return current; +} + static void ht_dev_read_resources(device_t dev) { #if CONFIG_EXT_CONF_SUPPORT diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 7ef49d1..10616ce 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -24,9 +24,13 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> #include "sb600.h" static void lpc_init(device_t dev) @@ -215,6 +219,24 @@ static void sb600_lpc_enable_resources(device_t dev) sb600_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +extern u16 pm_base; + +void get_bus_conf(void); + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); + return (unsigned long) (acpigen_get_current()); +} + +static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +{ + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + return acpi_write_hpet(start, rsdp); +} +#endif + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -223,6 +245,10 @@ static struct device_operations lpc_ops = { .read_resources = sb600_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = sb600_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .init = lpc_init, .scan_bus = scan_static_bus, /* .enable = sb600_enable, */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a175210..b7c1801 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -24,12 +24,22 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cbmem.h> +#include <cpu/amd/model_fxx_powernow.h> #include "sb700.h" +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + static void lpc_init(device_t dev) { u8 byte; @@ -74,7 +84,6 @@ static void lpc_init(device_t dev) is doing the acpi init */ #if CONFIG_HAVE_ACPI_RESUME { - extern u8 acpi_slp_type; u16 tmp = inw(ACPI_PM1_CNT_BLK); acpi_slp_type = ((tmp & (7 << 10)) >> 10); printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); @@ -259,6 +268,24 @@ static void sb700_lpc_enable_resources(device_t dev) sb700_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +void get_bus_conf(void); + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); + return (unsigned long) (acpigen_get_current()); +} + +static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +{ + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + return acpi_write_hpet(start, rsdp); +} + +#endif + + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -267,6 +294,10 @@ static struct device_operations lpc_ops = { .read_resources = sb700_lpc_read_resources, .set_resources = sb700_lpc_set_resources, .enable_resources = sb700_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index a2ba295..6ef39e3 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -24,6 +24,33 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "ck804.h" +#include <arch/acpi.h> + +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + unsigned long mcfg_base; + + dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); + if (!dev) + return current; + + mcfg_base = pci_read_config16(dev, 0x90); + if ((mcfg_base & 0x1000) == 0) + return current; + + mcfg_base = (mcfg_base & 0xf) << 28; + + printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, mcfg_base, 0x0, 0x0, 0xff); + return current; +} + +#endif static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index b3a9b00..d12dffb 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -30,6 +30,7 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <assert.h> @@ -316,6 +317,9 @@ static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = ck804_lpc_set_resources, .enable_resources = ck804_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_init, .scan_bus = scan_static_bus, // .enable = ck804_enable, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 585232d..4533699 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -34,7 +34,13 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <cpu/x86/lapic.h> +#include <arch/acpi.h> #include <stdlib.h> +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +#include <arch/acpi.h> +#include <arch/acpigen.h> +#endif +#include <cpu/amd/model_fxx_powernow.h> #include "mcp55.h" #define NMI_OFF 0 @@ -275,10 +281,24 @@ static const struct pci_driver lpc_driver __pci_driver = { .devices = lpc_ids, }; +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +#endif + static struct device_operations lpc_slave_ops = { .read_resources = mcp55_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_slave_init, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index 464cb6c..0abb9af 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -21,6 +21,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/model_fxx_powernow.h> #include "k8t890.h" extern unsigned long log2(unsigned long x); @@ -122,11 +125,25 @@ static void traf_ctrl_enable_k8t890(struct device *dev) pci_write_config8(dev, 0x60, 0x80 | reg); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +#endif + static const struct device_operations traf_ctrl_ops_m = { .read_resources = apic_mmconfig_read_resources, .set_resources = mmconfig_set_resources, .enable_resources = pci_dev_enable_resources, .enable = traf_ctrl_enable_k8m890, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .ops_pci = 0, }; @@ -135,11 +152,35 @@ static const struct device_operations traf_ctrl_ops_t = { .set_resources = mmconfig_set_resources, .enable_resources = pci_dev_enable_resources, .enable = traf_ctrl_enable_k8t890, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .ops_pci = 0, }; /* K8X800 chipsets have no APIC; no 800 PCI ids here */ +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + static const struct pci_driver northbridge_driver_t __pci_driver = { .ops = &traf_ctrl_ops_t,

1 0

Patch set updated for coreboot: d43d941 arm: add missing gc-sections for ramstage
by Isaac Christensen 23 Sep '14

23 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6956 -gerrit commit d43d9410062278656fdae7d12e50d9f138d02548 Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Mon Sep 22 17:18:11 2014 -0600 arm: add missing gc-sections for ramstage This is a fix up for recent patch: c505837 arm: Have the linker garbage-collect unused functions and variables I missed adding --gc-sections to a couple of the ramstage lines. Change-Id: I81178eb99fddbd99c603c79ba506db51af975b27 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/arm/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 0c1cfc6..427e3a4 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -114,9 +114,9 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld + $(LD_ramstage) -m armelf_linux_eabi --gc-sections -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld else - $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld + $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld endif $(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage)

1 0

Patch set updated for coreboot: 62da917 big: Create a nyan_big mainboard which is a copy of nyan.
by Isaac Christensen 23 Sep '14

23 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6927 -gerrit commit 62da9179ebed1a181f9c7d4d0b00d16c9b54b0fb Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 17 22:11:35 2014 -0800 big: Create a nyan_big mainboard which is a copy of nyan. The nyan_big mainboard is very similar to nyan, but will be different in a few ways. For instance, the BCT will be different, and the GPIOs may need to be configured slightly differently. This change also adds prefixes to the kconfig variables in "choice" blocks for both boards since having multiple instances of choice blocks with the same options confuses kconfig even if all of the instances have mutually exclusive dependencies. Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/183532 Reviewed-by: Tom Warren <twarren(a)nvidia.com> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit d1a453fe1aa68b3d12936dd48cc6c94b54f81579) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/Kconfig | 3 + src/mainboard/google/nyan/Kconfig | 16 +- src/mainboard/google/nyan/bct/Makefile.inc | 8 +- src/mainboard/google/nyan_big/Kconfig | 107 ++++++++ src/mainboard/google/nyan_big/Makefile.inc | 38 +++ src/mainboard/google/nyan_big/bct/Makefile.inc | 24 ++ src/mainboard/google/nyan_big/bct/emmc.cfg | 13 + src/mainboard/google/nyan_big/bct/odmdata.cfg | 1 + src/mainboard/google/nyan_big/bct/sdram-792.cfg | 346 ++++++++++++++++++++++++ src/mainboard/google/nyan_big/bct/sdram-924.cfg | 346 ++++++++++++++++++++++++ src/mainboard/google/nyan_big/bct/spi.cfg | 16 ++ src/mainboard/google/nyan_big/boardid.c | 38 +++ src/mainboard/google/nyan_big/boardid.h | 27 ++ src/mainboard/google/nyan_big/bootblock.c | 88 ++++++ src/mainboard/google/nyan_big/chromeos.c | 99 +++++++ src/mainboard/google/nyan_big/devicetree.cb | 80 ++++++ src/mainboard/google/nyan_big/mainboard.c | 303 +++++++++++++++++++++ src/mainboard/google/nyan_big/pmic.c | 112 ++++++++ src/mainboard/google/nyan_big/pmic.h | 48 ++++ src/mainboard/google/nyan_big/romstage.c | 142 ++++++++++ 20 files changed, 1843 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 538f0d8..38588c7 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -31,6 +31,8 @@ config BOARD_GOOGLE_LINK bool "Link" config BOARD_GOOGLE_NYAN bool "Nyan" +config BOARD_GOOGLE_NYAN_BIG + bool "Nyan Big" config BOARD_GOOGLE_PANTHER bool "Panther" config BOARD_GOOGLE_PARROT @@ -57,6 +59,7 @@ source "src/mainboard/google/butterfly/Kconfig" source "src/mainboard/google/falco/Kconfig" source "src/mainboard/google/link/Kconfig" source "src/mainboard/google/nyan/Kconfig" +source "src/mainboard/google/nyan_big/Kconfig" source "src/mainboard/google/panther/Kconfig" source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/peppy/Kconfig" diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 320039f..f0cef6a 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -53,16 +53,16 @@ config DRAM_DMA_SIZE choice prompt "BCT boot media" - default BCT_CFG_SPI + default NYAN_BCT_CFG_SPI help Which boot media to configure the BCT for. -config BCT_CFG_SPI +config NYAN_BCT_CFG_SPI bool "SPI" help Configure the BCT for booting from SPI. -config BCT_CFG_EMMC +config NYAN_BCT_CFG_EMMC bool "eMMC" help Configure the BCT for booting from eMMC. @@ -72,7 +72,7 @@ endchoice config BOOT_MEDIA_SPI_BUS int "SPI bus with boot media ROM" range 1 6 - depends on BCT_CFG_SPI + depends on NYAN_BCT_CFG_SPI default 4 help Which SPI bus the boot media is connected to. @@ -80,7 +80,7 @@ config BOOT_MEDIA_SPI_BUS config BOOT_MEDIA_SPI_CHIP_SELECT int "Chip select for SPI boot media" range 0 3 - depends on BCT_CFG_SPI + depends on NYAN_BCT_CFG_SPI default 0 help Which chip select to use for boot media. @@ -91,14 +91,14 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS choice prompt "BCT sdram configuration" - default BCT_SDRAM_792 + default NYAN_BCT_SDRAM_792 help The SDRAM configuration to put in the BCT. -config BCT_SDRAM_792 +config NYAN_BCT_SDRAM_792 bool "792 MHz" -config BCT_SDRAM_924 +config NYAN_BCT_SDRAM_924 bool "924 MHz" endchoice diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc index 52251c4..aacd89f 100644 --- a/src/mainboard/google/nyan/bct/Makefile.inc +++ b/src/mainboard/google/nyan/bct/Makefile.inc @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -bct-cfg-$(CONFIG_BCT_CFG_EMMC) += emmc.cfg -bct-cfg-$(CONFIG_BCT_CFG_SPI) += spi.cfg +bct-cfg-$(CONFIG_NYAN_BCT_CFG_EMMC) += emmc.cfg +bct-cfg-$(CONFIG_NYAN_BCT_CFG_SPI) += spi.cfg bct-cfg-y += odmdata.cfg -bct-cfg-$(CONFIG_BCT_SDRAM_924) += sdram-924.cfg -bct-cfg-$(CONFIG_BCT_SDRAM_792) += sdram-792.cfg +bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_924) += sdram-924.cfg +bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_792) += sdram-792.cfg diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig new file mode 100644 index 0000000..4973667 --- /dev/null +++ b/src/mainboard/google/nyan_big/Kconfig @@ -0,0 +1,107 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_NYAN_BIG + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_NVIDIA_TEGRA124 + select MAINBOARD_HAS_CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_BOOTBLOCK_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT + select BOARD_ROMSIZE_KB_1024 + select SPI_FLASH + select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B + + +config MAINBOARD_DIR + string + default google/nyan_big + +config MAINBOARD_PART_NUMBER + string + default "Nyan Big" + +config DRAM_SIZE_MB + int + default 2048 + +config DRAM_DMA_START + hex + default 0x90000000 + +config DRAM_DMA_SIZE + hex + default 0x00100000 + +choice + prompt "BCT boot media" + default NYAN_BIG_BCT_CFG_SPI + help + Which boot media to configure the BCT for. + +config NYAN_BIG_BCT_CFG_SPI + bool "SPI" + help + Configure the BCT for booting from SPI. + +config NYAN_BIG_BCT_CFG_EMMC + bool "eMMC" + help + Configure the BCT for booting from eMMC. + +endchoice + +config BOOT_MEDIA_SPI_BUS + int "SPI bus with boot media ROM" + range 1 6 + depends on NYAN_BIG_BCT_CFG_SPI + default 4 + help + Which SPI bus the boot media is connected to. + +config BOOT_MEDIA_SPI_CHIP_SELECT + int "Chip select for SPI boot media" + range 0 3 + depends on NYAN_BIG_BCT_CFG_SPI + default 0 + help + Which chip select to use for boot media. + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 1 + +choice + prompt "BCT sdram configuration" + default NYAN_BIG_BCT_SDRAM_792 + help + The SDRAM configuration to put in the BCT. + +config NYAN_BIG_BCT_SDRAM_792 + bool "792 MHz" + +config NYAN_BIG_BCT_SDRAM_924 + bool "924 MHz" + +endchoice + +endif # BOARD_GOOGLE_NYAN_BIG diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc new file mode 100644 index 0000000..d4a8cdb --- /dev/null +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# Add a handler for BCT config files +$(call add-special-class,bct-cfg) +bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2)) + +$(obj)/generated/bct.cfg: + @printf " CAT $(subst $(obj)/,,$(@))\n" + cat $^ > $@ + +subdirs-y += bct + +bootblock-y += boardid.c +bootblock-y += bootblock.c +bootblock-y += pmic.c + +romstage-y += romstage.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += mainboard.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/nyan_big/bct/Makefile.inc b/src/mainboard/google/nyan_big/bct/Makefile.inc new file mode 100644 index 0000000..65b87f0 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_EMMC) += emmc.cfg +bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_SPI) += spi.cfg +bct-cfg-y += odmdata.cfg +bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_924) += sdram-924.cfg +bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_792) += sdram-792.cfg diff --git a/src/mainboard/google/nyan_big/bct/emmc.cfg b/src/mainboard/google/nyan_big/bct/emmc.cfg new file mode 100644 index 0000000..c93cf46 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/emmc.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. +# Distributed under the terms of the GNU General Public License v2 + +Version = 0x00350001; +BlockSize = 0x00004000; +PageSize = 0x00000200; +PartitionSize = 0x01000000; + +DevType[0] = NvBootDevType_Sdmmc; +DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009; +DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit; +DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000; +DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000; diff --git a/src/mainboard/google/nyan_big/bct/odmdata.cfg b/src/mainboard/google/nyan_big/bct/odmdata.cfg new file mode 100644 index 0000000..d0ab2bf --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/odmdata.cfg @@ -0,0 +1 @@ +OdmData = 0x80080000; diff --git a/src/mainboard/google/nyan_big/bct/sdram-792.cfg b/src/mainboard/google/nyan_big/bct/sdram-792.cfg new file mode 100644 index 0000000..d4d9660 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-792.cfg @@ -0,0 +1,346 @@ +# CFG Version 07 +# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command: +# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650 +# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg +# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz) +# bkv file: PM358/PM358_792MHz_emc_reg.txt +SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; +SDRAM[0].PllMInputDivider = 0x00000001; +SDRAM[0].PllMFeedbackDivider = 0x00000042; +SDRAM[0].PllMStableTime = 0x0000012c; +SDRAM[0].PllMSetupControl = 0x00000000; +SDRAM[0].PllMSelectDiv2 = 0x00000000; +SDRAM[0].PllMPDLshiftPh45 = 0x00000001; +SDRAM[0].PllMPDLshiftPh90 = 0x00000001; +SDRAM[0].PllMPDLshiftPh135 = 0x00000001; +SDRAM[0].PllMKCP = 0x00000000; +SDRAM[0].PllMKVCO = 0x00000000; +SDRAM[0].EmcBctSpare0 = 0x00000000; +SDRAM[0].EmcBctSpare1 = 0x00000000; +SDRAM[0].EmcBctSpare2 = 0x00000000; +SDRAM[0].EmcBctSpare3 = 0x00000000; +SDRAM[0].EmcBctSpare4 = 0x00000000; +SDRAM[0].EmcBctSpare5 = 0x00000000; +SDRAM[0].EmcBctSpare6 = 0x00000000; +SDRAM[0].EmcBctSpare7 = 0x00000000; +SDRAM[0].EmcBctSpare8 = 0x00000000; +SDRAM[0].EmcBctSpare9 = 0x00000000; +SDRAM[0].EmcBctSpare10 = 0x00000000; +SDRAM[0].EmcBctSpare11 = 0x00000000; +SDRAM[0].EmcClockSource = 0x80000000; +SDRAM[0].EmcAutoCalInterval = 0x001fffff; +SDRAM[0].EmcAutoCalConfig = 0xa1430000; +SDRAM[0].EmcAutoCalConfig2 = 0x00000000; +SDRAM[0].EmcAutoCalConfig3 = 0x00000000; +SDRAM[0].EmcAutoCalWait = 0x00000190; +SDRAM[0].EmcAdrCfg = 0x00000000; +SDRAM[0].EmcPinProgramWait = 0x00000001; +SDRAM[0].EmcPinExtraWait = 0x00000000; +SDRAM[0].EmcTimingControlWait = 0x00000000; +SDRAM[0].EmcRc = 0x00000025; +SDRAM[0].EmcRfc = 0x000000cd; +SDRAM[0].EmcRfcSlr = 0x00000000; +SDRAM[0].EmcRas = 0x00000019; +SDRAM[0].EmcRp = 0x0000000a; +SDRAM[0].EmcR2r = 0x00000000; +SDRAM[0].EmcW2w = 0x00000000; +SDRAM[0].EmcR2w = 0x00000007; +SDRAM[0].EmcW2r = 0x0000000d; +SDRAM[0].EmcR2p = 0x00000004; +SDRAM[0].EmcW2p = 0x00000013; +SDRAM[0].EmcRdRcd = 0x0000000a; +SDRAM[0].EmcWrRcd = 0x0000000a; +SDRAM[0].EmcRrd = 0x00000003; +SDRAM[0].EmcRext = 0x00000002; +SDRAM[0].EmcWext = 0x00000000; +SDRAM[0].EmcWdv = 0x00000006; +SDRAM[0].EmcWdvMask = 0x00000006; +SDRAM[0].EmcQUse = 0x0000000b; +SDRAM[0].EmcQuseWidth = 0x00000002; +SDRAM[0].EmcIbdly = 0x00000000; +SDRAM[0].EmcEInput = 0x00000003; +SDRAM[0].EmcEInputDuration = 0x0000000c; +SDRAM[0].EmcPutermExtra = 0x00090000; +SDRAM[0].EmcPutermWidth = 0x00000004; +SDRAM[0].EmcPutermAdj = 0x00000000; +SDRAM[0].EmcCdbCntl1 = 0x00000000; +SDRAM[0].EmcCdbCntl2 = 0x00000000; +SDRAM[0].EmcCdbCntl3 = 0x00000000; +SDRAM[0].EmcQRst = 0x00000002; +SDRAM[0].EmcQSafe = 0x00000011; +SDRAM[0].EmcRdv = 0x00000017; +SDRAM[0].EmcRdvMask = 0x00000019; +SDRAM[0].EmcQpop = 0x0000000f; +SDRAM[0].EmcCtt = 0x00000000; +SDRAM[0].EmcCttDuration = 0x00000004; +SDRAM[0].EmcRefresh = 0x000017eb; +SDRAM[0].EmcBurstRefreshNum = 0x00000000; +SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa; +SDRAM[0].EmcPdEx2Wr = 0x00000003; +SDRAM[0].EmcPdEx2Rd = 0x00000003; +SDRAM[0].EmcPChg2Pden = 0x00000001; +SDRAM[0].EmcAct2Pden = 0x00000000; +SDRAM[0].EmcAr2Pden = 0x000000c7; +SDRAM[0].EmcRw2Pden = 0x00000018; +SDRAM[0].EmcTxsr = 0x000000d7; +SDRAM[0].EmcTxsrDll = 0x00000200; +SDRAM[0].EmcTcke = 0x00000005; +SDRAM[0].EmcTckesr = 0x00000006; +SDRAM[0].EmcTpd = 0x00000005; +SDRAM[0].EmcTfaw = 0x0000001d; +SDRAM[0].EmcTrpab = 0x00000000; +SDRAM[0].EmcTClkStable = 0x00000008; +SDRAM[0].EmcTClkStop = 0x00000008; +SDRAM[0].EmcTRefBw = 0x0000182c; +SDRAM[0].EmcFbioCfg5 = 0x104ab898; +SDRAM[0].EmcFbioCfg6 = 0x00000002; +SDRAM[0].EmcFbioSpare = 0x00000000; +SDRAM[0].EmcCfgRsv = 0xff00ff00; +SDRAM[0].EmcMrs = 0x80001d71; +SDRAM[0].EmcEmrs = 0x80100002; +SDRAM[0].EmcEmrs2 = 0x80200018; +SDRAM[0].EmcEmrs3 = 0x80300000; +SDRAM[0].EmcMrw1 = 0x00000000; +SDRAM[0].EmcMrw2 = 0x00000000; +SDRAM[0].EmcMrw3 = 0x00000000; +SDRAM[0].EmcMrw4 = 0x00000000; +SDRAM[0].EmcMrwExtra = 0x00000000; +SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; +SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; +SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; +SDRAM[0].EmcMrwResetCommand = 0x00000000; +SDRAM[0].EmcMrwResetNInitWait = 0x00000000; +SDRAM[0].EmcMrsWaitCnt = 0x00f7000e; +SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e; +SDRAM[0].EmcCfg = 0x73300000; +SDRAM[0].EmcCfg2 = 0x0000089d; +SDRAM[0].EmcCfgPipe = 0x000040a0; +SDRAM[0].EmcDbg = 0x01000c00; +SDRAM[0].EmcCmdQ = 0x10004408; +SDRAM[0].EmcMc2EmcQ = 0x06000404; +SDRAM[0].EmcDynSelfRefControl = 0x80003025; +SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; +SDRAM[0].EmcCfgDigDll = 0xe00701b1; +SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; +SDRAM[0].EmcDevSelect = 0x00000002; +SDRAM[0].EmcSelDpdCtrl = 0x00040000; +SDRAM[0].EmcDllXformDqs0 = 0x00000008; +SDRAM[0].EmcDllXformDqs1 = 0x00000008; +SDRAM[0].EmcDllXformDqs2 = 0x00000008; +SDRAM[0].EmcDllXformDqs3 = 0x00000008; +SDRAM[0].EmcDllXformDqs4 = 0x00000008; +SDRAM[0].EmcDllXformDqs5 = 0x00000008; +SDRAM[0].EmcDllXformDqs6 = 0x00000008; +SDRAM[0].EmcDllXformDqs7 = 0x00000008; +SDRAM[0].EmcDllXformDqs8 = 0x00000008; +SDRAM[0].EmcDllXformDqs9 = 0x00000008; +SDRAM[0].EmcDllXformDqs10 = 0x00000008; +SDRAM[0].EmcDllXformDqs11 = 0x00000008; +SDRAM[0].EmcDllXformDqs12 = 0x00000008; +SDRAM[0].EmcDllXformDqs13 = 0x00000008; +SDRAM[0].EmcDllXformDqs14 = 0x00000008; +SDRAM[0].EmcDllXformDqs15 = 0x00000008; +SDRAM[0].EmcDllXformQUse0 = 0x00000000; +SDRAM[0].EmcDllXformQUse1 = 0x00000000; +SDRAM[0].EmcDllXformQUse2 = 0x00000000; +SDRAM[0].EmcDllXformQUse3 = 0x00000000; +SDRAM[0].EmcDllXformQUse4 = 0x00000000; +SDRAM[0].EmcDllXformQUse5 = 0x00000000; +SDRAM[0].EmcDllXformQUse6 = 0x00000000; +SDRAM[0].EmcDllXformQUse7 = 0x00000000; +SDRAM[0].EmcDllXformAddr0 = 0x0000000e; +SDRAM[0].EmcDllXformAddr1 = 0x0000000e; +SDRAM[0].EmcDllXformAddr2 = 0x00000000; +SDRAM[0].EmcDllXformAddr3 = 0x0000000e; +SDRAM[0].EmcDllXformAddr4 = 0x00000000; +SDRAM[0].EmcDllXformAddr5 = 0x00000000; +SDRAM[0].EmcDllXformQUse8 = 0x00000000; +SDRAM[0].EmcDllXformQUse9 = 0x00000000; +SDRAM[0].EmcDllXformQUse10 = 0x00000000; +SDRAM[0].EmcDllXformQUse11 = 0x00000000; +SDRAM[0].EmcDllXformQUse12 = 0x00000000; +SDRAM[0].EmcDllXformQUse13 = 0x00000000; +SDRAM[0].EmcDllXformQUse14 = 0x00000000; +SDRAM[0].EmcDllXformQUse15 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; +SDRAM[0].EmcDllXformDq0 = 0x0000000b; +SDRAM[0].EmcDllXformDq1 = 0x0000000b; +SDRAM[0].EmcDllXformDq2 = 0x0000000b; +SDRAM[0].EmcDllXformDq3 = 0x0000000b; +SDRAM[0].EmcDllXformDq4 = 0x0000000b; +SDRAM[0].EmcDllXformDq5 = 0x0000000b; +SDRAM[0].EmcDllXformDq6 = 0x0000000b; +SDRAM[0].EmcDllXformDq7 = 0x0000000b; +SDRAM[0].WarmBootWait = 0x00000002; +SDRAM[0].EmcCttTermCtrl = 0x00000802; +SDRAM[0].EmcOdtWrite = 0x00000000; +SDRAM[0].EmcOdtRead = 0x00000000; +SDRAM[0].EmcZcalInterval = 0x00020000; +SDRAM[0].EmcZcalWaitCnt = 0x00000042; +SDRAM[0].EmcZcalMrwCmd = 0x80000000; +SDRAM[0].EmcMrsResetDll = 0x00000000; +SDRAM[0].EmcZcalInitDev0 = 0x80000011; +SDRAM[0].EmcZcalInitDev1 = 0x00000000; +SDRAM[0].EmcZcalInitWait = 0x00000001; +SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; +SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; +SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; +SDRAM[0].EmcZcalWarmBootWait = 0x00000001; +SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; +SDRAM[0].EmcMrsResetDllWait = 0x00000000; +SDRAM[0].EmcMrsExtra = 0x80001d71; +SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; +SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; +SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; +SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; +SDRAM[0].EmcDdr2Wait = 0x00000000; +SDRAM[0].EmcClkenOverride = 0x00000000; +SDRAM[0].McDisExtraSnapLevels = 0x00000000; +SDRAM[0].EmcExtraRefreshNum = 0x00000002; +SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; +SDRAM[0].PmcVddpSel = 0x00000002; +SDRAM[0].PmcVddpSelWait = 0x00000002; +SDRAM[0].PmcDdrPwr = 0x00000003; +SDRAM[0].PmcDdrCfg = 0x00002002; +SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; +SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; +SDRAM[0].PmcRegShort = 0x00000000; +SDRAM[0].PmcNoIoPower = 0x00000000; +SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; +SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; +SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; +SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; +SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; +SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; +SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; +SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; +SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820; +SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514; +SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514; +SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800; +SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; +SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; +SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; +SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; +SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707; +SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; +SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; +SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; +SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff; +SDRAM[0].EmcAcpdControl = 0x00000000; +SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; +SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; +SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; +SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; +SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; +SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; +SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; +SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; +SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; +SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; +SDRAM[0].EmcDsrVttgenDrv = 0x0505003f; +SDRAM[0].EmcTxdsrvttgen = 0x00000000; +SDRAM[0].EmcBgbiasCtl0 = 0x00000000; +SDRAM[0].McEmemAdrCfg = 0x00000000; +SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; +SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; +SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; +SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; +SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; +SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; +SDRAM[0].McEmemCfg = 0x00000800; +SDRAM[0].McEmemArbCfg = 0x0e00000b; +SDRAM[0].McEmemArbOutstandingReq = 0x80000040; +SDRAM[0].McEmemArbTimingRcd = 0x00000004; +SDRAM[0].McEmemArbTimingRp = 0x00000005; +SDRAM[0].McEmemArbTimingRc = 0x00000013; +SDRAM[0].McEmemArbTimingRas = 0x0000000c; +SDRAM[0].McEmemArbTimingFaw = 0x0000000f; +SDRAM[0].McEmemArbTimingRrd = 0x00000002; +SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003; +SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c; +SDRAM[0].McEmemArbTimingR2R = 0x00000002; +SDRAM[0].McEmemArbTimingW2W = 0x00000002; +SDRAM[0].McEmemArbTimingR2W = 0x00000005; +SDRAM[0].McEmemArbTimingW2R = 0x00000008; +SDRAM[0].McEmemArbDaTurns = 0x08050202; +SDRAM[0].McEmemArbDaCovers = 0x00170e13; +SDRAM[0].McEmemArbMisc0 = 0x736c2414; +SDRAM[0].McEmemArbMisc1 = 0x70000f02; +SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; +SDRAM[0].McEmemArbOverride = 0x10000000; +SDRAM[0].McEmemArbOverride1 = 0x00000000; +SDRAM[0].McEmemArbRsv = 0xff00ff00; +SDRAM[0].McClkenOverride = 0x00000000; +SDRAM[0].McStatControl = 0x00000000; +SDRAM[0].McDisplaySnapRing = 0x00000003; +SDRAM[0].McVideoProtectBom = 0xfff00000; +SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; +SDRAM[0].McVideoProtectSizeMb = 0x00000000; +SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; +SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; +SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; +SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; +SDRAM[0].McSecCarveoutBom = 0xfff00000; +SDRAM[0].McSecCarveoutAdrHi = 0x00000000; +SDRAM[0].McSecCarveoutSizeMb = 0x00000000; +SDRAM[0].McVideoProtectWriteAccess = 0x00000000; +SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; +SDRAM[0].EmcCaTrainingEnable = 0x00000000; +SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; +SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; +SDRAM[0].SwizzleRankByteEncode = 0x0000006f; +SDRAM[0].BootRomPatchControl = 0x00000000; +SDRAM[0].BootRomPatchData = 0x00000000; +SDRAM[0].McMtsCarveoutBom = 0xfff00000; +SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; +SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; +SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; +#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013; +#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c; +#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038; +#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038; +#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c; +#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041; +#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041; +#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; +#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080; +#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004; +#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004; +#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; +#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081; +#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004; +#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019; +#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018; +#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024; +#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c; +#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081; +#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081; +#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081; +#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; +#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; +#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081; +#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081; +#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065; +#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c; diff --git a/src/mainboard/google/nyan_big/bct/sdram-924.cfg b/src/mainboard/google/nyan_big/bct/sdram-924.cfg new file mode 100644 index 0000000..fa3271a --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-924.cfg @@ -0,0 +1,346 @@ +# CFG Version 11 +# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command: +# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650 +# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg +# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz) +# bkv file: PM358/PM358_924MHz_emc_reg.txt +SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; +SDRAM[0].PllMInputDivider = 0x00000001; +SDRAM[0].PllMFeedbackDivider = 0x0000004d; +SDRAM[0].PllMStableTime = 0x0000012c; +SDRAM[0].PllMSetupControl = 0x00000000; +SDRAM[0].PllMSelectDiv2 = 0x00000000; +SDRAM[0].PllMPDLshiftPh45 = 0x00000001; +SDRAM[0].PllMPDLshiftPh90 = 0x00000001; +SDRAM[0].PllMPDLshiftPh135 = 0x00000001; +SDRAM[0].PllMKCP = 0x00000000; +SDRAM[0].PllMKVCO = 0x00000000; +SDRAM[0].EmcBctSpare0 = 0x00000000; +SDRAM[0].EmcBctSpare1 = 0x00000000; +SDRAM[0].EmcBctSpare2 = 0x00000000; +SDRAM[0].EmcBctSpare3 = 0x00000000; +SDRAM[0].EmcBctSpare4 = 0x00000000; +SDRAM[0].EmcBctSpare5 = 0x00000000; +SDRAM[0].EmcBctSpare6 = 0x00000000; +SDRAM[0].EmcBctSpare7 = 0x00000000; +SDRAM[0].EmcBctSpare8 = 0x00000000; +SDRAM[0].EmcBctSpare9 = 0x00000000; +SDRAM[0].EmcBctSpare10 = 0x00000000; +SDRAM[0].EmcBctSpare11 = 0x00000000; +SDRAM[0].EmcClockSource = 0x80000000; +SDRAM[0].EmcAutoCalInterval = 0x001fffff; +SDRAM[0].EmcAutoCalConfig = 0xa1430404; +SDRAM[0].EmcAutoCalConfig2 = 0x00000000; +SDRAM[0].EmcAutoCalConfig3 = 0x00000000; +SDRAM[0].EmcAutoCalWait = 0x00000190; +SDRAM[0].EmcAdrCfg = 0x00000000; +SDRAM[0].EmcPinProgramWait = 0x00000001; +SDRAM[0].EmcPinExtraWait = 0x00000000; +SDRAM[0].EmcTimingControlWait = 0x00000000; +SDRAM[0].EmcRc = 0x0000002b; +SDRAM[0].EmcRfc = 0x000000ef; +SDRAM[0].EmcRfcSlr = 0x00000000; +SDRAM[0].EmcRas = 0x0000001e; +SDRAM[0].EmcRp = 0x0000000b; +SDRAM[0].EmcR2r = 0x00000000; +SDRAM[0].EmcW2w = 0x00000000; +SDRAM[0].EmcR2w = 0x00000008; +SDRAM[0].EmcW2r = 0x0000000f; +SDRAM[0].EmcR2p = 0x00000005; +SDRAM[0].EmcW2p = 0x00000016; +SDRAM[0].EmcRdRcd = 0x0000000b; +SDRAM[0].EmcWrRcd = 0x0000000b; +SDRAM[0].EmcRrd = 0x00000004; +SDRAM[0].EmcRext = 0x00000002; +SDRAM[0].EmcWext = 0x00000000; +SDRAM[0].EmcWdv = 0x00000006; +SDRAM[0].EmcWdvMask = 0x00000006; +SDRAM[0].EmcQUse = 0x0000000c; +SDRAM[0].EmcQuseWidth = 0x00000002; +SDRAM[0].EmcIbdly = 0x00000000; +SDRAM[0].EmcEInput = 0x00000002; +SDRAM[0].EmcEInputDuration = 0x0000000e; +SDRAM[0].EmcPutermExtra = 0x000a0000; +SDRAM[0].EmcPutermWidth = 0x00000004; +SDRAM[0].EmcPutermAdj = 0x00000000; +SDRAM[0].EmcCdbCntl1 = 0x00000000; +SDRAM[0].EmcCdbCntl2 = 0x00000000; +SDRAM[0].EmcCdbCntl3 = 0x00000000; +SDRAM[0].EmcQRst = 0x00000001; +SDRAM[0].EmcQSafe = 0x00000015; +SDRAM[0].EmcRdv = 0x0000001b; +SDRAM[0].EmcRdvMask = 0x0000001d; +SDRAM[0].EmcQpop = 0x00000010; +SDRAM[0].EmcCtt = 0x00000000; +SDRAM[0].EmcCttDuration = 0x00000004; +SDRAM[0].EmcRefresh = 0x00001be9; +SDRAM[0].EmcBurstRefreshNum = 0x00000000; +SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa; +SDRAM[0].EmcPdEx2Wr = 0x00000004; +SDRAM[0].EmcPdEx2Rd = 0x00000015; +SDRAM[0].EmcPChg2Pden = 0x00000001; +SDRAM[0].EmcAct2Pden = 0x00000000; +SDRAM[0].EmcAr2Pden = 0x000000e6; +SDRAM[0].EmcRw2Pden = 0x0000001b; +SDRAM[0].EmcTxsr = 0x000000fa; +SDRAM[0].EmcTxsrDll = 0x00000200; +SDRAM[0].EmcTcke = 0x00000006; +SDRAM[0].EmcTckesr = 0x00000007; +SDRAM[0].EmcTpd = 0x00000006; +SDRAM[0].EmcTfaw = 0x00000022; +SDRAM[0].EmcTrpab = 0x00000000; +SDRAM[0].EmcTClkStable = 0x0000000a; +SDRAM[0].EmcTClkStop = 0x0000000a; +SDRAM[0].EmcTRefBw = 0x00001c29; +SDRAM[0].EmcFbioCfg5 = 0x104ab898; +SDRAM[0].EmcFbioCfg6 = 0x00000002; +SDRAM[0].EmcFbioSpare = 0x00000000; +SDRAM[0].EmcCfgRsv = 0xff00ff00; +SDRAM[0].EmcMrs = 0x80000f15; +SDRAM[0].EmcEmrs = 0x80100002; +SDRAM[0].EmcEmrs2 = 0x80200020; +SDRAM[0].EmcEmrs3 = 0x80300000; +SDRAM[0].EmcMrw1 = 0x00000000; +SDRAM[0].EmcMrw2 = 0x00000000; +SDRAM[0].EmcMrw3 = 0x00000000; +SDRAM[0].EmcMrw4 = 0x00000000; +SDRAM[0].EmcMrwExtra = 0x00000000; +SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; +SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; +SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; +SDRAM[0].EmcMrwResetCommand = 0x00000000; +SDRAM[0].EmcMrwResetNInitWait = 0x00000000; +SDRAM[0].EmcMrsWaitCnt = 0x00ce000e; +SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e; +SDRAM[0].EmcCfg = 0x73300000; +SDRAM[0].EmcCfg2 = 0x000008a5; +SDRAM[0].EmcCfgPipe = 0x00000000; +SDRAM[0].EmcDbg = 0x01000c00; +SDRAM[0].EmcCmdQ = 0x10004408; +SDRAM[0].EmcMc2EmcQ = 0x06000404; +SDRAM[0].EmcDynSelfRefControl = 0x800037ed; +SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; +SDRAM[0].EmcCfgDigDll = 0xe00401b1; +SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; +SDRAM[0].EmcDevSelect = 0x00000002; +SDRAM[0].EmcSelDpdCtrl = 0x00040000; +SDRAM[0].EmcDllXformDqs0 = 0x00000005; +SDRAM[0].EmcDllXformDqs1 = 0x00000005; +SDRAM[0].EmcDllXformDqs2 = 0x00000005; +SDRAM[0].EmcDllXformDqs3 = 0x00000005; +SDRAM[0].EmcDllXformDqs4 = 0x00000005; +SDRAM[0].EmcDllXformDqs5 = 0x00000005; +SDRAM[0].EmcDllXformDqs6 = 0x00000005; +SDRAM[0].EmcDllXformDqs7 = 0x00000005; +SDRAM[0].EmcDllXformDqs8 = 0x00000005; +SDRAM[0].EmcDllXformDqs9 = 0x00000005; +SDRAM[0].EmcDllXformDqs10 = 0x00000005; +SDRAM[0].EmcDllXformDqs11 = 0x00000005; +SDRAM[0].EmcDllXformDqs12 = 0x00000005; +SDRAM[0].EmcDllXformDqs13 = 0x00000005; +SDRAM[0].EmcDllXformDqs14 = 0x00000005; +SDRAM[0].EmcDllXformDqs15 = 0x00000005; +SDRAM[0].EmcDllXformQUse0 = 0x00000000; +SDRAM[0].EmcDllXformQUse1 = 0x00000000; +SDRAM[0].EmcDllXformQUse2 = 0x00000000; +SDRAM[0].EmcDllXformQUse3 = 0x00000000; +SDRAM[0].EmcDllXformQUse4 = 0x00000000; +SDRAM[0].EmcDllXformQUse5 = 0x00000000; +SDRAM[0].EmcDllXformQUse6 = 0x00000000; +SDRAM[0].EmcDllXformQUse7 = 0x00000000; +SDRAM[0].EmcDllXformAddr0 = 0x0000400e; +SDRAM[0].EmcDllXformAddr1 = 0x0000400e; +SDRAM[0].EmcDllXformAddr2 = 0x00000000; +SDRAM[0].EmcDllXformAddr3 = 0x0000400e; +SDRAM[0].EmcDllXformAddr4 = 0x0000400e; +SDRAM[0].EmcDllXformAddr5 = 0x00000000; +SDRAM[0].EmcDllXformQUse8 = 0x00000000; +SDRAM[0].EmcDllXformQUse9 = 0x00000000; +SDRAM[0].EmcDllXformQUse10 = 0x00000000; +SDRAM[0].EmcDllXformQUse11 = 0x00000000; +SDRAM[0].EmcDllXformQUse12 = 0x00000000; +SDRAM[0].EmcDllXformQUse13 = 0x00000000; +SDRAM[0].EmcDllXformQUse14 = 0x00000000; +SDRAM[0].EmcDllXformQUse15 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; +SDRAM[0].EmcDllXformDq0 = 0x00000006; +SDRAM[0].EmcDllXformDq1 = 0x00000006; +SDRAM[0].EmcDllXformDq2 = 0x00000006; +SDRAM[0].EmcDllXformDq3 = 0x00000006; +SDRAM[0].EmcDllXformDq4 = 0x00000006; +SDRAM[0].EmcDllXformDq5 = 0x00000006; +SDRAM[0].EmcDllXformDq6 = 0x00000006; +SDRAM[0].EmcDllXformDq7 = 0x00000006; +SDRAM[0].WarmBootWait = 0x00000002; +SDRAM[0].EmcCttTermCtrl = 0x00000802; +SDRAM[0].EmcOdtWrite = 0x00000000; +SDRAM[0].EmcOdtRead = 0x00000000; +SDRAM[0].EmcZcalInterval = 0x00020000; +SDRAM[0].EmcZcalWaitCnt = 0x0000004c; +SDRAM[0].EmcZcalMrwCmd = 0x80000000; +SDRAM[0].EmcMrsResetDll = 0x00000000; +SDRAM[0].EmcZcalInitDev0 = 0x80000011; +SDRAM[0].EmcZcalInitDev1 = 0x00000000; +SDRAM[0].EmcZcalInitWait = 0x00000001; +SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; +SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; +SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; +SDRAM[0].EmcZcalWarmBootWait = 0x00000001; +SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; +SDRAM[0].EmcMrsResetDllWait = 0x00000000; +SDRAM[0].EmcMrsExtra = 0x80000f15; +SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; +SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; +SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; +SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; +SDRAM[0].EmcDdr2Wait = 0x00000000; +SDRAM[0].EmcClkenOverride = 0x00000000; +SDRAM[0].McDisExtraSnapLevels = 0x00000000; +SDRAM[0].EmcExtraRefreshNum = 0x00000002; +SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; +SDRAM[0].PmcVddpSel = 0x00000002; +SDRAM[0].PmcVddpSelWait = 0x00000002; +SDRAM[0].PmcDdrPwr = 0x00000003; +SDRAM[0].PmcDdrCfg = 0x00002002; +SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; +SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; +SDRAM[0].PmcRegShort = 0x00000000; +SDRAM[0].PmcNoIoPower = 0x00000000; +SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; +SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; +SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; +SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; +SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; +SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; +SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; +SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; +SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520; +SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf; +SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf; +SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500; +SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; +SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; +SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; +SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; +SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303; +SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; +SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; +SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; +SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee; +SDRAM[0].EmcAcpdControl = 0x00000000; +SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; +SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; +SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; +SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; +SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; +SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; +SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; +SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; +SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; +SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; +SDRAM[0].EmcDsrVttgenDrv = 0x0606003f; +SDRAM[0].EmcTxdsrvttgen = 0x00000000; +SDRAM[0].EmcBgbiasCtl0 = 0x00000000; +SDRAM[0].McEmemAdrCfg = 0x00000000; +SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; +SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; +SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; +SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; +SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; +SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; +SDRAM[0].McEmemCfg = 0x00000800; +SDRAM[0].McEmemArbCfg = 0x0e00000d; +SDRAM[0].McEmemArbOutstandingReq = 0x80000040; +SDRAM[0].McEmemArbTimingRcd = 0x00000005; +SDRAM[0].McEmemArbTimingRp = 0x00000006; +SDRAM[0].McEmemArbTimingRc = 0x00000016; +SDRAM[0].McEmemArbTimingRas = 0x0000000e; +SDRAM[0].McEmemArbTimingFaw = 0x00000011; +SDRAM[0].McEmemArbTimingRrd = 0x00000002; +SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004; +SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e; +SDRAM[0].McEmemArbTimingR2R = 0x00000002; +SDRAM[0].McEmemArbTimingW2W = 0x00000002; +SDRAM[0].McEmemArbTimingR2W = 0x00000006; +SDRAM[0].McEmemArbTimingW2R = 0x00000009; +SDRAM[0].McEmemArbDaTurns = 0x09060202; +SDRAM[0].McEmemArbDaCovers = 0x001a1016; +SDRAM[0].McEmemArbMisc0 = 0x734e2a17; +SDRAM[0].McEmemArbMisc1 = 0x70000f02; +SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; +SDRAM[0].McEmemArbOverride = 0x10000000; +SDRAM[0].McEmemArbOverride1 = 0x00000000; +SDRAM[0].McEmemArbRsv = 0xff00ff00; +SDRAM[0].McClkenOverride = 0x00000000; +SDRAM[0].McStatControl = 0x00000000; +SDRAM[0].McDisplaySnapRing = 0x00000003; +SDRAM[0].McVideoProtectBom = 0xfff00000; +SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; +SDRAM[0].McVideoProtectSizeMb = 0x00000000; +SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; +SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; +SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; +SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; +SDRAM[0].McSecCarveoutBom = 0xfff00000; +SDRAM[0].McSecCarveoutAdrHi = 0x00000000; +SDRAM[0].McSecCarveoutSizeMb = 0x00000000; +SDRAM[0].McVideoProtectWriteAccess = 0x00000000; +SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; +SDRAM[0].EmcCaTrainingEnable = 0x00000000; +SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; +SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; +SDRAM[0].SwizzleRankByteEncode = 0x0000006f; +SDRAM[0].BootRomPatchControl = 0x00000000; +SDRAM[0].BootRomPatchData = 0x00000000; +SDRAM[0].McMtsCarveoutBom = 0xfff00000; +SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; +SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; +SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; +#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; +#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; +#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; +#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; +#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; +#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; +#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; +#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; +#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; +#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; +#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; +#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; +#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; +#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; +#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; +#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; +#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; +#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; +#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; +#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; +#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; +#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; +#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; +#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; +#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; +#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; +#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; diff --git a/src/mainboard/google/nyan_big/bct/spi.cfg b/src/mainboard/google/nyan_big/bct/spi.cfg new file mode 100644 index 0000000..aef7e82 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/spi.cfg @@ -0,0 +1,16 @@ +# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. +# Distributed under the terms of the GNU General Public License v2 + +Version = 0x00350001; +BlockSize = 32768; +PageSize = 2048; +PartitionSize = 4194304; + +Bctcopy = 1; + +DevType[0] = NvBootDevType_Spi; +DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; + diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c new file mode 100644 index 0000000..f43e532 --- /dev/null +++ b/src/mainboard/google/nyan_big/boardid.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <soc/nvidia/tegra124/gpio.h> + +#include "boardid.h" + +uint8_t board_id(void) +{ + static int id = -1; + + if (id < 0) { + id = gpio_get_in_value(GPIO(Q3)) << 0 | + gpio_get_in_value(GPIO(T1)) << 1 | + gpio_get_in_value(GPIO(X1)) << 2 | + gpio_get_in_value(GPIO(X4)) << 3; + printk(BIOS_SPEW, "Board ID: %#x.\n", id); + } + + return id; +} diff --git a/src/mainboard/google/nyan_big/boardid.h b/src/mainboard/google/nyan_big/boardid.h new file mode 100644 index 0000000..8b20032 --- /dev/null +++ b/src/mainboard/google/nyan_big/boardid.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_BIG_BOARDID_H__ +#define __MAINBOARD_GOOGLE_NYAN_BIG_BOARDID_H__ + +#include <stdint.h> + +uint8_t board_id(void); + +#endif /* __MAINBOARD_GOOGLE_NYAN_BIG_BOARDID_H__ */ diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c new file mode 100644 index 0000000..f07951a --- /dev/null +++ b/src/mainboard/google/nyan_big/bootblock.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <device/i2c.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra124/clk_rst.h> +#include <soc/nvidia/tegra124/gpio.h> +#include <soc/nvidia/tegra124/pinmux.h> +#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */ + +#include "pmic.h" + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void set_clock_sources(void) +{ + /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ + writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); + + clock_configure_source(mselect, PLLP, 102000); + + /* TODO: is the 1.333MHz correct? This may have always been bogus... */ + clock_configure_source(i2c5, CLK_M, 1333); + + /* TODO: We should be able to set this to 50MHz, but that did not seem + * reliable. */ + clock_configure_source(sbc4, PLLP, 33333); +} + +void bootblock_mainboard_init(void) +{ + set_clock_sources(); + + clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR, + CLK_H_I2C5 | CLK_H_APBDMA, + 0, CLK_V_MSELECT, 0, 0); + + // Board ID GPIOs, bits 0-3. + gpio_input(GPIO(Q3)); + gpio_input(GPIO(T1)); + gpio_input(GPIO(X1)); + gpio_input(GPIO(X4)); + + // I2C5 (PMU) clock. + pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, + PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); + // I2C5 (PMU) data. + pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX, + PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); + i2c_init(4); + pmic_init(4); + + /* SPI4 data out (MOSI) */ + pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, + PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 data in (MISO) */ + pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, + PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 clock */ + pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, + PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 chip select 0 */ + pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, + PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + + tegra_spi_init(4); +} diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c new file mode 100644 index 0000000..298fd6a --- /dev/null +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> +#include <soc/nvidia/tegra124/gpio.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_R1_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Lid: active high */ + gpios->gpios[count].port = GPIO_R4_INDEX; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = gpio_get_in_value(GPIO(R4)); + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; + + /* Power: active low */ + gpios->gpios[count].port = GPIO_Q0_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO(Q0)); + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + uint32_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_in_value(GPIO(R1)); +} diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb new file mode 100644 index 0000000..cb55b72 --- /dev/null +++ b/src/mainboard/google/nyan_big/devicetree.cb @@ -0,0 +1,80 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/nvidia/tegra124 + device cpu_cluster 0 on end +# N.B. We ae not using the device tree in an effective way. +# We need to change this in future such that the on-soc +# devices are 'chips', which will allow us to go at them +# in parallel. This is even easier on the ARM SOCs since there +# are no single-access resources such as the infamous +# cf8/cfc registers found on PCs. + register "display_controller" = "TEGRA_ARM_DISPLAYA" + register "xres" = "1366" + register "yres" = "768" + # this setting is what nvidia does; it makes no sense + # and does not agree with hardware. Why'd they do it? + register "framebuffer_bits_per_pixel" = "18" + register "cache_policy" = "DCACHE_WRITETHROUGH" + + # With some help from the mainbaord designer + register "backlight_en_gpio" = "GPIO(H2)" + register "lvds_shutdown_gpio" = "0" + register "backlight_vdd_gpio" = "GPIO(P2)" + register "panel_vdd_gpio" = "0" + register "pwm" = "GPIO(H1)" + +# taken from u-boot; these look wrong however. + register "vdd_delay" = "400" + register "vdd_data_delay" = "4" + register "data_backlight_delay" = "203" + register "backlight_pwm_delay" = "17" + register "pwm_backlight_en_delay" = "15" + +# How to compute these: xrandr --verbose will give you this: +#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm +# 2560 2608 2640 2720 hborder 0 +# 1700 1703 1713 1749 vborder 0 +#Then you can compute your values: +#H front porch = 2608 - 2560 = 48 +#H sync = 2640 - 2608 = 32 +#H back porch = 2720 - 2640 = 80 +#V front porch = 1703 - 1700 = 3 +#V sync = 1713 - 1703 = 10 +#V back porch = 1749 - 1713 = 36 +#href_to_sync and vref_to_sync are from the vendor +#this is just an example for a Pixel panel; other panels differ. +# Here is a peppy panel: +# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred +# h: width 1366 start 1502 end 1532 total 1592 +# v: height 768 start 776 end 788 total 800 +# These numbers were provided by Nvidia. + register "href_to_sync" = "1" + register "hfront_porch" = "44" + register "hsync_width" = "46" + register "hback_porch" = "44" + + register "vref_to_sync" = "1" + register "vfront_porch" = "6" + register "vsync_width" = "8" + register "vback_porch" = "6" + + # we *know* the pixel clock for this system. + register "pixel_clock" = "71" +end diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c new file mode 100644 index 0000000..4a05991 --- /dev/null +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -0,0 +1,303 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <boot/coreboot_tables.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra124/clk_rst.h> +#include <soc/nvidia/tegra124/gpio.h> +#include <soc/nvidia/tegra124/mc.h> +#include <soc/nvidia/tegra124/pmc.h> +#include <soc/nvidia/tegra124/spi.h> +#include <soc/nvidia/tegra124/usb.h> + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void set_clock_sources(void) +{ + clock_configure_source(i2c1, CLK_M, 1333); + clock_configure_source(i2c2, CLK_M, 1333); + clock_configure_source(i2c3, CLK_M, 1333); + clock_configure_source(i2c4, CLK_M, 1333); + + clock_configure_source(sbc1, PLLP, 5000); + + /* + * MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's + * maximum speed (48MHz) so we can change SDCLK by second stage divisor + * in payloads, without touching base clock. + */ + clock_configure_source(sdmmc3, PLLP, 48000); + clock_configure_source(sdmmc4, PLLP, 48000); + + /* External peripheral 1: audio codec (max98090) using 12MHz CLK1. + * Note the source id of CLK_M for EXTPERIPH1 is 3. */ + clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3); + + /* + * I2S1 can use either PLLP or PLLA. Using PLLP is sufficient now since + * we only need 4.8MHz. Note the source id of PLLP for I2S is 4. + */ + clock_configure_irregular_source(i2s1, PLLP, 4800, 4); + + /* Note source id of PLLP for HOST1x is 4. */ + clock_configure_irregular_source(host1x, PLLP, 408000, 4); + + /* Use PLLD_OUT0 as clock source for disp1 */ + clrsetbits_le32(&clk_rst->clk_src_disp1, + CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + 2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT); + +} + +static void setup_pinmux(void) +{ + // Write protect. + gpio_input_pullup(GPIO(R1)); + // Recovery mode. + gpio_input_pullup(GPIO(Q7)); + // Lid switch. + gpio_input_pullup(GPIO(R4)); + // Power switch. + gpio_input_pullup(GPIO(Q0)); + // Developer mode. + gpio_input_pullup(GPIO(Q6)); + // EC in RW. + gpio_input_pullup(GPIO(U4)); + + // SOC and TPM reset GPIO, active low. + gpio_output(GPIO(I5), 1); + + // SPI1 MOSI + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 MISO + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 SCLK + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 CS0 + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + // I2C1 clock. + pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX, + PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C1 data. + pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX, + PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C2 clock. + pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, + PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C2 data. + pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, + PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) clock. + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) data. + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C4 (DDC) clock. + pinmux_set_config(PINMUX_DDC_SCL_INDEX, + PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE); + // I2C4 (DDC) data. + pinmux_set_config(PINMUX_DDC_SDA_INDEX, + PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE); + + // TODO(hungte) Revice pinmux setup, make nice little SoC functions for + // every single logical thing instead of dumping a wall of code below. + uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, + pin_up3 = (PINMUX_PULL_UP | PINMUX_INPUT_ENABLE | + PINMUX_TRISTATE), + pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE, + pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE; + + // MMC3 + pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX, + PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none); + pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX, + PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX, + PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX, + PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX, + PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX, + PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX, + PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up3); + pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX, + PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down); + + // MMC3 Card Detect pin. + gpio_input_pullup(GPIO(V2)); + // Enable MMC power. + gpio_output(GPIO(R0), 1); + + // MMC4 + pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX, + PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none); + pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX, + PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX, + PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX, + PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX, + PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX, + PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX, + PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX, + PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX, + PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX, + PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up); + + /* We pull the USB VBUS signals up but keep them as inputs since the + * voltage source likes to drive them low on overcurrent conditions */ + gpio_input_pullup(GPIO(N4)); /* USB VBUS EN0 */ + gpio_input_pullup(GPIO(N5)); /* USB VBUS EN1 */ + + /* Clock output 1 (for external peripheral) */ + pinmux_set_config(PINMUX_DAP_MCLK1_INDEX, + PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE); + + /* I2S1 */ + pinmux_set_config(PINMUX_DAP2_DIN_INDEX, + PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_TRISTATE | + PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_DAP2_DOUT_INDEX, + PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_DAP2_FS_INDEX, + PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_DAP2_SCLK_INDEX, + PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE); +} + +static void setup_kernel_info(void) +{ + // Setup required information for Linux kernel. + + // pmc.odmdata: [18:19]: console type, [15:17]: UART id. + // TODO(hungte) This should be done by filling BCT values, or derived + // from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the + // value defined in BCT. + struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE; + writel(0x80080000, &pmc->odmdata); + + // Not strictly info, but kernel graphics driver needs this region locked down + struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE; + writel(0, &mc->video_protect_bom); + writel(0, &mc->video_protect_size_mb); + writel(1, &mc->video_protect_reg_ctrl); +} + +static void setup_ec_spi(void) +{ + struct tegra_spi_channel *spi; + + spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + + /* Set frame header for use by CrOS EC */ + spi->frame_header = 0xec; + spi->rx_frame_header_enable = 1; +} + +static void mainboard_init(device_t dev) +{ + set_clock_sources(); + + clock_external_output(1); /* For external MAX98090 audio codec. */ + + /* + * Confirmed by NVIDIA hardware team, we need to take ALL audio devices + * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out + * of reset and clock-enabled, otherwise reading AHUB devices (In our + * case, I2S/APBIF/AUDIO<XBAR>) will hang. + */ + clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 | + CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 | + CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 | + CLK_L_HOST1X, + + CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 | + CLK_H_PMC | CLK_H_MEM | CLK_H_USB3, + + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3, + + CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF | + CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 | + CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2, + + CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0, + + CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 | + CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 | + CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 | + CLK_X_AFC5); + + usb_setup_utmip1(); + /* USB2 is the camera, we don't need it in firmware */ + usb_setup_utmip3(); + + setup_pinmux(); + + i2c_init(0); + i2c_init(1); + i2c_init(2); + i2c_init(3); + + setup_kernel_info(); + clock_init_arm_generic_timer(); + setup_ec_spi(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "nyan_big", + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = CONFIG_DRAM_DMA_START; + dma->range_size = CONFIG_DRAM_DMA_SIZE; +} diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c new file mode 100644 index 0000000..f64b59c --- /dev/null +++ b/src/mainboard/google/nyan_big/pmic.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <device/i2c.h> +#include <stdint.h> +#include <stdlib.h> + +#include "boardid.h" +#include "pmic.h" + +enum { + AS3722_I2C_ADDR = 0x40 +}; + +struct as3722_init_reg { + u8 reg; + u8 val; +}; + +static struct as3722_init_reg init_list[] = { + {AS3722_SDO0, 0x3C}, + {AS3722_SDO1, 0x32}, + {AS3722_SDO2, 0x3C}, + {AS3722_SDO3, 0x00}, + {AS3722_SDO4, 0x00}, + {AS3722_SDO5, 0x50}, + {AS3722_SDO6, 0x28}, + {AS3722_LDO0, 0x8A}, + {AS3722_LDO1, 0x00}, + {AS3722_LDO2, 0x10}, + {AS3722_LDO3, 0x59}, + {AS3722_LDO4, 0x00}, + {AS3722_LDO5, 0x00}, + {AS3722_LDO6, 0x3F}, + {AS3722_LDO7, 0x00}, + {AS3722_LDO9, 0x00}, + {AS3722_LDO10, 0x00}, + {AS3722_LDO11, 0x00}, +}; +#define AS3722_INIT_REG_LEN ARRAY_SIZE(init_list) + +static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val) +{ + i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1); + udelay(10 * 1000); +} + +static void pmic_slam_defaults(unsigned bus) +{ + int i; + + for (i = 0; i < AS3722_INIT_REG_LEN; i++) + pmic_write_reg(bus, init_list[i].reg, init_list[i].val); +} + +void pmic_init(unsigned bus) +{ + /* + * Don't need to set up VDD_CORE - already done - by OTP + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + */ + + /* Restore PMIC POR defaults, in case kernel changed 'em */ + pmic_slam_defaults(bus); + + /* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */ + if (board_id() == 0) + pmic_write_reg(bus, 0x00, 0x3c); + else + pmic_write_reg(bus, 0x00, 0x50); + + /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */ + pmic_write_reg(bus, 0x06, 0x28); + + /* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */ + pmic_write_reg(bus, 0x12, 0x10); + + /* + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. + * First set it to bypass 3.3V straight thru, then enable the regulator + * + * NOTE: We do this early because doing it later seems to hose the CPU + * power rail/partition startup. Need to debug. + */ + pmic_write_reg(bus, 0x16, 0x3f); + + /* + * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set + * the value (register 0x20 bit 4) + */ + pmic_write_reg(bus, 0x0c, 0x07); + pmic_write_reg(bus, 0x20, 0x10); +} diff --git a/src/mainboard/google/nyan_big/pmic.h b/src/mainboard/google/nyan_big/pmic.h new file mode 100644 index 0000000..a641599 --- /dev/null +++ b/src/mainboard/google/nyan_big/pmic.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__ +#define __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__ + +enum { + AS3722_SDO0 = 0, + AS3722_SDO1, + AS3722_SDO2, + AS3722_SDO3, + AS3722_SDO4, + AS3722_SDO5, + AS3722_SDO6, + + AS3722_LDO0 = 0x10, + AS3722_LDO1, + AS3722_LDO2, + AS3722_LDO3, + AS3722_LDO4, + AS3722_LDO5, + AS3722_LDO6, + AS3722_LDO7, + + AS3722_LDO9 = 0x19, + AS3722_LDO10, + AS3722_LDO11, +}; + +void pmic_init(unsigned bus); + +#endif /* __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__ */ diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c new file mode 100644 index 0000000..0e71020 --- /dev/null +++ b/src/mainboard/google/nyan_big/romstage.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/cpu.h> +#include <arch/exception.h> +#include <arch/stages.h> +#include <device/device.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include "soc/nvidia/tegra124/chip.h" +#include <soc/display.h> +#include <timestamp.h> + +// Convenient shorthand (in MB) +#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) +#define DRAM_SIZE CONFIG_DRAM_SIZE_MB +#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ + +enum { + L2CTLR_ECC_PARITY = 0x1 << 21, + L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, + L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, + L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, + L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 +}; + +enum { + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, + L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 +}; + +/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ +static void configure_l2ctlr(void) +{ + uint32_t val; + + val = read_l2ctlr(); + val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); + val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | + L2CTLR_ECC_PARITY); + write_l2ctlr(val); +} + +/* Configures L2 Auxiliary Control Register for Cortex A15. */ +static void configure_l2actlr(void) +{ + uint32_t val; + + val = read_l2actlr(); + val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); + write_l2actlr(val); +} + +void main(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + uint64_t romstage_start_time = timestamp_get(); +#endif + + // Globally disable MMU, caches and branch prediction (these should + // already be disabled by default on reset). + uint32_t sctlr = read_sctlr(); + sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); + write_sctlr(sctlr); + + arm_invalidate_caches(); + + // Renable icache and branch prediction. + sctlr = read_sctlr(); + sctlr |= SCTLR_Z | SCTLR_I; + write_sctlr(sctlr); + + configure_l2ctlr(); + configure_l2actlr(); + + console_init(); + exception_init(); + + mmu_init(); + mmu_config_range(0, DRAM_START, DCACHE_OFF); + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(CONFIG_DRAM_DMA_START >> 20, + CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + mmu_disable_range(0, 1); + dcache_invalidate_all(); + dcache_mmu_enable(); + + /* For quality of the user experience, it's important to get + * the video going ASAP. Because there are long delays in some + * of the powerup steps, we do some very early setup here in + * romstage. The only thing setup_display does is manage + * 4 GPIOs, under control of the config struct members. + * In general, it is safe to enable panel power, and disable + * anything related to the backlight. If we get something wrong, + * we can easily fix it in ramstage by further GPIO manipulation, + * so we feel it is ok to do some setting at this point. + */ + + const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); + printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); + if (soc && soc->chip_info) { + const struct soc_nvidia_tegra124_config *config = + soc->chip_info; + setup_display((struct soc_nvidia_tegra124_config *)config); + } + + cbmem_initialize_empty(); + +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(0); + timestamp_add(TS_START_ROMSTAGE, romstage_start_time); + timestamp_add(TS_START_COPYRAM, timestamp_get()); +#endif + void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + "fallback/coreboot_ram"); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add(TS_END_COPYRAM, timestamp_get()); +#endif + stage_exit(entry); +}

1 0

Patch set updated for coreboot: dd328b9 tegra/nyan*: sdram updates
by Isaac Christensen 23 Sep '14

23 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6949 -gerrit commit dd328b962c69a3fffb71c7aaf1fd986a5159fbb1 Author: Tom Warren <twarren(a)nvidia.com> Date: Thu Jan 23 13:37:50 2014 -0700 tegra/nyan*: sdram updates nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/Kconfig | 18 - src/mainboard/google/nyan/Makefile.inc | 1 + src/mainboard/google/nyan/bct/Makefile.inc | 6 +- src/mainboard/google/nyan/bct/cfg2inc.sh | 34 ++ src/mainboard/google/nyan/bct/sdram-792.cfg | 346 ----------- src/mainboard/google/nyan/bct/sdram-924.cfg | 346 ----------- .../google/nyan/bct/sdram-hynix-2GB-792.inc | 311 ++++++++++ .../google/nyan/bct/sdram-hynix-2GB-924.inc | 311 ++++++++++ src/mainboard/google/nyan/bct/sdram-unused.inc | 4 + src/mainboard/google/nyan/bootblock.c | 18 +- src/mainboard/google/nyan/romstage.c | 22 +- src/mainboard/google/nyan/sdram_configs.c | 58 ++ src/mainboard/google/nyan/sdram_configs.h | 28 + src/mainboard/google/nyan_big/Kconfig | 18 - src/mainboard/google/nyan_big/Makefile.inc | 1 + src/mainboard/google/nyan_big/bct/Makefile.inc | 6 +- src/mainboard/google/nyan_big/bct/sdram-792.cfg | 346 ----------- src/mainboard/google/nyan_big/bct/sdram-924.cfg | 346 ----------- .../google/nyan_big/bct/sdram-hynix-2GB-204.inc | 311 ++++++++++ .../google/nyan_big/bct/sdram-hynix-2GB-792.inc | 311 ++++++++++ .../google/nyan_big/bct/sdram-hynix-2GB-924.inc | 311 ++++++++++ .../google/nyan_big/bct/sdram-hynix-4GB-204.inc | 311 ++++++++++ .../google/nyan_big/bct/sdram-hynix-4GB-792.inc | 311 ++++++++++ src/mainboard/google/nyan_big/bct/sdram-unused.inc | 4 + src/mainboard/google/nyan_big/bct/spi.cfg | 18 + src/mainboard/google/nyan_big/boardid.c | 17 +- src/mainboard/google/nyan_big/bootblock.c | 18 +- src/mainboard/google/nyan_big/pmic.c | 5 +- src/mainboard/google/nyan_big/romstage.c | 22 +- src/mainboard/google/nyan_big/sdram_configs.c | 62 ++ src/mainboard/google/nyan_big/sdram_configs.h | 28 + src/soc/nvidia/tegra/dc.h | 3 + src/soc/nvidia/tegra/gpio.c | 53 ++ src/soc/nvidia/tegra/gpio.h | 1 + src/soc/nvidia/tegra124/Kconfig | 33 +- src/soc/nvidia/tegra124/Makefile.inc | 2 + src/soc/nvidia/tegra124/cbmem.c | 5 +- src/soc/nvidia/tegra124/display.c | 8 +- src/soc/nvidia/tegra124/include/soc/addressmap.h | 5 - src/soc/nvidia/tegra124/include/soc/display.h | 4 + src/soc/nvidia/tegra124/mc.h | 3 + src/soc/nvidia/tegra124/sdram.c | 30 + src/soc/nvidia/tegra124/sdram.h | 4 + src/soc/nvidia/tegra124/sdram_lp0.c | 633 +++++++++++++++++++++ src/soc/nvidia/tegra124/sdram_param.h | 20 +- src/soc/nvidia/tegra124/soc.c | 8 +- 46 files changed, 3259 insertions(+), 1502 deletions(-) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index f0cef6a..61a17b4 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -39,10 +39,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan" -config DRAM_SIZE_MB - int - default 2048 - config DRAM_DMA_START hex default 0x90000000 @@ -89,18 +85,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 -choice - prompt "BCT sdram configuration" - default NYAN_BCT_SDRAM_792 - help - The SDRAM configuration to put in the BCT. - -config NYAN_BCT_SDRAM_792 - bool "792 MHz" - -config NYAN_BCT_SDRAM_924 - bool "924 MHz" - -endchoice - endif # BOARD_GOOGLE_NYAN diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index e612af3..825b33e 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -32,6 +32,7 @@ bootblock-y += bootblock.c bootblock-y += pmic.c romstage-y += romstage.c +romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc index aacd89f..32490eb 100644 --- a/src/mainboard/google/nyan/bct/Makefile.inc +++ b/src/mainboard/google/nyan/bct/Makefile.inc @@ -20,5 +20,7 @@ bct-cfg-$(CONFIG_NYAN_BCT_CFG_EMMC) += emmc.cfg bct-cfg-$(CONFIG_NYAN_BCT_CFG_SPI) += spi.cfg bct-cfg-y += odmdata.cfg -bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_924) += sdram-924.cfg -bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_792) += sdram-792.cfg + +# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate +# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg". +# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage. diff --git a/src/mainboard/google/nyan/bct/cfg2inc.sh b/src/mainboard/google/nyan/bct/cfg2inc.sh new file mode 100755 index 0000000..6d0c7a8 --- /dev/null +++ b/src/mainboard/google/nyan/bct/cfg2inc.sh @@ -0,0 +1,34 @@ +#!/bin/sh +# +# This file is part of the coreboot project. +# +# Copyright 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +bct_cfg2inc() { + local in_file="$1" + local out_file="$2" + echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}" + # Note currently we can only handle DDR3 type memory, even in C + # implementation. + sed "/^#.*$/d; s/^SDRAM.0./ /; s/;$/,/;" \ + "${in_file}" >> "${out_file}" + echo "}," >>"${out_file}" +} + +for file in $@; do + echo "Generating $file => ${file%cfg}inc..." + bct_cfg2inc "${file}" "${file%cfg}inc" +done diff --git a/src/mainboard/google/nyan/bct/sdram-792.cfg b/src/mainboard/google/nyan/bct/sdram-792.cfg deleted file mode 100644 index d4d9660..0000000 --- a/src/mainboard/google/nyan/bct/sdram-792.cfg +++ /dev/null @@ -1,346 +0,0 @@ -# CFG Version 07 -# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command: -# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650 -# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg -# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz) -# bkv file: PM358/PM358_792MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x00000042; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430000; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000000; -SDRAM[0].EmcPinProgramWait = 0x00000001; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x00000025; -SDRAM[0].EmcRfc = 0x000000cd; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x00000019; -SDRAM[0].EmcRp = 0x0000000a; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000007; -SDRAM[0].EmcW2r = 0x0000000d; -SDRAM[0].EmcR2p = 0x00000004; -SDRAM[0].EmcW2p = 0x00000013; -SDRAM[0].EmcRdRcd = 0x0000000a; -SDRAM[0].EmcWrRcd = 0x0000000a; -SDRAM[0].EmcRrd = 0x00000003; -SDRAM[0].EmcRext = 0x00000002; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000006; -SDRAM[0].EmcWdvMask = 0x00000006; -SDRAM[0].EmcQUse = 0x0000000b; -SDRAM[0].EmcQuseWidth = 0x00000002; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000003; -SDRAM[0].EmcEInputDuration = 0x0000000c; -SDRAM[0].EmcPutermExtra = 0x00090000; -SDRAM[0].EmcPutermWidth = 0x00000004; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000002; -SDRAM[0].EmcQSafe = 0x00000011; -SDRAM[0].EmcRdv = 0x00000017; -SDRAM[0].EmcRdvMask = 0x00000019; -SDRAM[0].EmcQpop = 0x0000000f; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000004; -SDRAM[0].EmcRefresh = 0x000017eb; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa; -SDRAM[0].EmcPdEx2Wr = 0x00000003; -SDRAM[0].EmcPdEx2Rd = 0x00000003; -SDRAM[0].EmcPChg2Pden = 0x00000001; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x000000c7; -SDRAM[0].EmcRw2Pden = 0x00000018; -SDRAM[0].EmcTxsr = 0x000000d7; -SDRAM[0].EmcTxsrDll = 0x00000200; -SDRAM[0].EmcTcke = 0x00000005; -SDRAM[0].EmcTckesr = 0x00000006; -SDRAM[0].EmcTpd = 0x00000005; -SDRAM[0].EmcTfaw = 0x0000001d; -SDRAM[0].EmcTrpab = 0x00000000; -SDRAM[0].EmcTClkStable = 0x00000008; -SDRAM[0].EmcTClkStop = 0x00000008; -SDRAM[0].EmcTRefBw = 0x0000182c; -SDRAM[0].EmcFbioCfg5 = 0x104ab898; -SDRAM[0].EmcFbioCfg6 = 0x00000002; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x80001d71; -SDRAM[0].EmcEmrs = 0x80100002; -SDRAM[0].EmcEmrs2 = 0x80200018; -SDRAM[0].EmcEmrs3 = 0x80300000; -SDRAM[0].EmcMrw1 = 0x00000000; -SDRAM[0].EmcMrw2 = 0x00000000; -SDRAM[0].EmcMrw3 = 0x00000000; -SDRAM[0].EmcMrw4 = 0x00000000; -SDRAM[0].EmcMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x00000000; -SDRAM[0].EmcMrwResetNInitWait = 0x00000000; -SDRAM[0].EmcMrsWaitCnt = 0x00f7000e; -SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e; -SDRAM[0].EmcCfg = 0x73300000; -SDRAM[0].EmcCfg2 = 0x0000089d; -SDRAM[0].EmcCfgPipe = 0x000040a0; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x80003025; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00701b1; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000002; -SDRAM[0].EmcSelDpdCtrl = 0x00040000; -SDRAM[0].EmcDllXformDqs0 = 0x00000008; -SDRAM[0].EmcDllXformDqs1 = 0x00000008; -SDRAM[0].EmcDllXformDqs2 = 0x00000008; -SDRAM[0].EmcDllXformDqs3 = 0x00000008; -SDRAM[0].EmcDllXformDqs4 = 0x00000008; -SDRAM[0].EmcDllXformDqs5 = 0x00000008; -SDRAM[0].EmcDllXformDqs6 = 0x00000008; -SDRAM[0].EmcDllXformDqs7 = 0x00000008; -SDRAM[0].EmcDllXformDqs8 = 0x00000008; -SDRAM[0].EmcDllXformDqs9 = 0x00000008; -SDRAM[0].EmcDllXformDqs10 = 0x00000008; -SDRAM[0].EmcDllXformDqs11 = 0x00000008; -SDRAM[0].EmcDllXformDqs12 = 0x00000008; -SDRAM[0].EmcDllXformDqs13 = 0x00000008; -SDRAM[0].EmcDllXformDqs14 = 0x00000008; -SDRAM[0].EmcDllXformDqs15 = 0x00000008; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x0000000e; -SDRAM[0].EmcDllXformAddr1 = 0x0000000e; -SDRAM[0].EmcDllXformAddr2 = 0x00000000; -SDRAM[0].EmcDllXformAddr3 = 0x0000000e; -SDRAM[0].EmcDllXformAddr4 = 0x00000000; -SDRAM[0].EmcDllXformAddr5 = 0x00000000; -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; -SDRAM[0].EmcDllXformDq0 = 0x0000000b; -SDRAM[0].EmcDllXformDq1 = 0x0000000b; -SDRAM[0].EmcDllXformDq2 = 0x0000000b; -SDRAM[0].EmcDllXformDq3 = 0x0000000b; -SDRAM[0].EmcDllXformDq4 = 0x0000000b; -SDRAM[0].EmcDllXformDq5 = 0x0000000b; -SDRAM[0].EmcDllXformDq6 = 0x0000000b; -SDRAM[0].EmcDllXformDq7 = 0x0000000b; -SDRAM[0].WarmBootWait = 0x00000002; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00020000; -SDRAM[0].EmcZcalWaitCnt = 0x00000042; -SDRAM[0].EmcZcalMrwCmd = 0x80000000; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x80000011; -SDRAM[0].EmcZcalInitDev1 = 0x00000000; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x80001d71; -SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000002; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00002002; -SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x00000000; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; -SDRAM[0].EmcDsrVttgenDrv = 0x0505003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000000; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00000800; -SDRAM[0].McEmemArbCfg = 0x0e00000b; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000004; -SDRAM[0].McEmemArbTimingRp = 0x00000005; -SDRAM[0].McEmemArbTimingRc = 0x00000013; -SDRAM[0].McEmemArbTimingRas = 0x0000000c; -SDRAM[0].McEmemArbTimingFaw = 0x0000000f; -SDRAM[0].McEmemArbTimingRrd = 0x00000002; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c; -SDRAM[0].McEmemArbTimingR2R = 0x00000002; -SDRAM[0].McEmemArbTimingW2W = 0x00000002; -SDRAM[0].McEmemArbTimingR2W = 0x00000005; -SDRAM[0].McEmemArbTimingW2R = 0x00000008; -SDRAM[0].McEmemArbDaTurns = 0x08050202; -SDRAM[0].McEmemArbDaCovers = 0x00170e13; -SDRAM[0].McEmemArbMisc0 = 0x736c2414; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000000; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; -SDRAM[0].SwizzleRankByteEncode = 0x0000006f; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0xfff00000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c; diff --git a/src/mainboard/google/nyan/bct/sdram-924.cfg b/src/mainboard/google/nyan/bct/sdram-924.cfg deleted file mode 100644 index fa3271a..0000000 --- a/src/mainboard/google/nyan/bct/sdram-924.cfg +++ /dev/null @@ -1,346 +0,0 @@ -# CFG Version 11 -# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command: -# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650 -# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg -# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz) -# bkv file: PM358/PM358_924MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x0000004d; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430404; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000000; -SDRAM[0].EmcPinProgramWait = 0x00000001; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x0000002b; -SDRAM[0].EmcRfc = 0x000000ef; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x0000001e; -SDRAM[0].EmcRp = 0x0000000b; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000008; -SDRAM[0].EmcW2r = 0x0000000f; -SDRAM[0].EmcR2p = 0x00000005; -SDRAM[0].EmcW2p = 0x00000016; -SDRAM[0].EmcRdRcd = 0x0000000b; -SDRAM[0].EmcWrRcd = 0x0000000b; -SDRAM[0].EmcRrd = 0x00000004; -SDRAM[0].EmcRext = 0x00000002; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000006; -SDRAM[0].EmcWdvMask = 0x00000006; -SDRAM[0].EmcQUse = 0x0000000c; -SDRAM[0].EmcQuseWidth = 0x00000002; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000002; -SDRAM[0].EmcEInputDuration = 0x0000000e; -SDRAM[0].EmcPutermExtra = 0x000a0000; -SDRAM[0].EmcPutermWidth = 0x00000004; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000001; -SDRAM[0].EmcQSafe = 0x00000015; -SDRAM[0].EmcRdv = 0x0000001b; -SDRAM[0].EmcRdvMask = 0x0000001d; -SDRAM[0].EmcQpop = 0x00000010; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000004; -SDRAM[0].EmcRefresh = 0x00001be9; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa; -SDRAM[0].EmcPdEx2Wr = 0x00000004; -SDRAM[0].EmcPdEx2Rd = 0x00000015; -SDRAM[0].EmcPChg2Pden = 0x00000001; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x000000e6; -SDRAM[0].EmcRw2Pden = 0x0000001b; -SDRAM[0].EmcTxsr = 0x000000fa; -SDRAM[0].EmcTxsrDll = 0x00000200; -SDRAM[0].EmcTcke = 0x00000006; -SDRAM[0].EmcTckesr = 0x00000007; -SDRAM[0].EmcTpd = 0x00000006; -SDRAM[0].EmcTfaw = 0x00000022; -SDRAM[0].EmcTrpab = 0x00000000; -SDRAM[0].EmcTClkStable = 0x0000000a; -SDRAM[0].EmcTClkStop = 0x0000000a; -SDRAM[0].EmcTRefBw = 0x00001c29; -SDRAM[0].EmcFbioCfg5 = 0x104ab898; -SDRAM[0].EmcFbioCfg6 = 0x00000002; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x80000f15; -SDRAM[0].EmcEmrs = 0x80100002; -SDRAM[0].EmcEmrs2 = 0x80200020; -SDRAM[0].EmcEmrs3 = 0x80300000; -SDRAM[0].EmcMrw1 = 0x00000000; -SDRAM[0].EmcMrw2 = 0x00000000; -SDRAM[0].EmcMrw3 = 0x00000000; -SDRAM[0].EmcMrw4 = 0x00000000; -SDRAM[0].EmcMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x00000000; -SDRAM[0].EmcMrwResetNInitWait = 0x00000000; -SDRAM[0].EmcMrsWaitCnt = 0x00ce000e; -SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e; -SDRAM[0].EmcCfg = 0x73300000; -SDRAM[0].EmcCfg2 = 0x000008a5; -SDRAM[0].EmcCfgPipe = 0x00000000; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x800037ed; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00401b1; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000002; -SDRAM[0].EmcSelDpdCtrl = 0x00040000; -SDRAM[0].EmcDllXformDqs0 = 0x00000005; -SDRAM[0].EmcDllXformDqs1 = 0x00000005; -SDRAM[0].EmcDllXformDqs2 = 0x00000005; -SDRAM[0].EmcDllXformDqs3 = 0x00000005; -SDRAM[0].EmcDllXformDqs4 = 0x00000005; -SDRAM[0].EmcDllXformDqs5 = 0x00000005; -SDRAM[0].EmcDllXformDqs6 = 0x00000005; -SDRAM[0].EmcDllXformDqs7 = 0x00000005; -SDRAM[0].EmcDllXformDqs8 = 0x00000005; -SDRAM[0].EmcDllXformDqs9 = 0x00000005; -SDRAM[0].EmcDllXformDqs10 = 0x00000005; -SDRAM[0].EmcDllXformDqs11 = 0x00000005; -SDRAM[0].EmcDllXformDqs12 = 0x00000005; -SDRAM[0].EmcDllXformDqs13 = 0x00000005; -SDRAM[0].EmcDllXformDqs14 = 0x00000005; -SDRAM[0].EmcDllXformDqs15 = 0x00000005; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x0000400e; -SDRAM[0].EmcDllXformAddr1 = 0x0000400e; -SDRAM[0].EmcDllXformAddr2 = 0x00000000; -SDRAM[0].EmcDllXformAddr3 = 0x0000400e; -SDRAM[0].EmcDllXformAddr4 = 0x0000400e; -SDRAM[0].EmcDllXformAddr5 = 0x00000000; -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; -SDRAM[0].EmcDllXformDq0 = 0x00000006; -SDRAM[0].EmcDllXformDq1 = 0x00000006; -SDRAM[0].EmcDllXformDq2 = 0x00000006; -SDRAM[0].EmcDllXformDq3 = 0x00000006; -SDRAM[0].EmcDllXformDq4 = 0x00000006; -SDRAM[0].EmcDllXformDq5 = 0x00000006; -SDRAM[0].EmcDllXformDq6 = 0x00000006; -SDRAM[0].EmcDllXformDq7 = 0x00000006; -SDRAM[0].WarmBootWait = 0x00000002; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00020000; -SDRAM[0].EmcZcalWaitCnt = 0x0000004c; -SDRAM[0].EmcZcalMrwCmd = 0x80000000; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x80000011; -SDRAM[0].EmcZcalInitDev1 = 0x00000000; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x80000f15; -SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000002; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00002002; -SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x00000000; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; -SDRAM[0].EmcDsrVttgenDrv = 0x0606003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000000; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00000800; -SDRAM[0].McEmemArbCfg = 0x0e00000d; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000005; -SDRAM[0].McEmemArbTimingRp = 0x00000006; -SDRAM[0].McEmemArbTimingRc = 0x00000016; -SDRAM[0].McEmemArbTimingRas = 0x0000000e; -SDRAM[0].McEmemArbTimingFaw = 0x00000011; -SDRAM[0].McEmemArbTimingRrd = 0x00000002; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e; -SDRAM[0].McEmemArbTimingR2R = 0x00000002; -SDRAM[0].McEmemArbTimingW2W = 0x00000002; -SDRAM[0].McEmemArbTimingR2W = 0x00000006; -SDRAM[0].McEmemArbTimingW2R = 0x00000009; -SDRAM[0].McEmemArbDaTurns = 0x09060202; -SDRAM[0].McEmemArbDaCovers = 0x001a1016; -SDRAM[0].McEmemArbMisc0 = 0x734e2a17; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000000; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; -SDRAM[0].SwizzleRankByteEncode = 0x0000006f; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0xfff00000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; diff --git a/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc new file mode 100644 index 0000000..d175e7b --- /dev/null +++ b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x000000cd, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000019, + .EmcRp = 0x0000000a, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000007, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x0000000a, + .EmcWrRcd = 0x0000000a, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000003, + .EmcEInputDuration = 0x0000000c, + .EmcPutermExtra = 0x00090000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000002, + .EmcQSafe = 0x00000011, + .EmcRdv = 0x00000017, + .EmcRdvMask = 0x00000019, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017eb, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005fa, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000003, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000c7, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x000000d7, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x0000182c, + .EmcFbioCfg5 = 0x104ab898, + .EmcFbioCfg6 = 0x00000002, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80001d71, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200018, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00f7000e, + .EmcMrsWaitCnt2 = 0x00f7000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x000040a0, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003025, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00701b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0000000e, + .EmcDllXformAddr1 = 0x0000000e, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0000000e, + .EmcDllXformAddr4 = 0x00000000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x0000000b, + .EmcDllXformDq1 = 0x0000000b, + .EmcDllXformDq2 = 0x0000000b, + .EmcDllXformDq3 = 0x0000000b, + .EmcDllXformDq4 = 0x0000000b, + .EmcDllXformDq5 = 0x0000000b, + .EmcDllXformDq6 = 0x0000000b, + .EmcDllXformDq7 = 0x0000000b, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80001d71, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0020013d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000707, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x017fffff, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0505003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000005, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08050202, + .McEmemArbDaCovers = 0x00170e13, + .McEmemArbMisc0 = 0x736c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc new file mode 100644 index 0000000..e4d4faf --- /dev/null +++ b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x0000004d, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430404, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x0000002b, + .EmcRfc = 0x000000ef, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001e, + .EmcRp = 0x0000000b, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000f, + .EmcR2p = 0x00000005, + .EmcW2p = 0x00000016, + .EmcRdRcd = 0x0000000b, + .EmcWrRcd = 0x0000000b, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000c, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000e, + .EmcPutermExtra = 0x000a0000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000015, + .EmcRdv = 0x0000001b, + .EmcRdvMask = 0x0000001d, + .EmcQpop = 0x00000010, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x00001be9, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000006fa, + .EmcPdEx2Wr = 0x00000004, + .EmcPdEx2Rd = 0x00000015, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000e6, + .EmcRw2Pden = 0x0000001b, + .EmcTxsr = 0x000000fa, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000006, + .EmcTckesr = 0x00000007, + .EmcTpd = 0x00000006, + .EmcTfaw = 0x00000022, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x0000000a, + .EmcTClkStop = 0x0000000a, + .EmcTRefBw = 0x00001c29, + .EmcFbioCfg5 = 0x104ab898, + .EmcFbioCfg6 = 0x00000002, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80000f15, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200020, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00ce000e, + .EmcMrsWaitCnt2 = 0x00ce000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x000008a5, + .EmcCfgPipe = 0x00000000, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x800037ed, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00401b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000005, + .EmcDllXformDqs1 = 0x00000005, + .EmcDllXformDqs2 = 0x00000005, + .EmcDllXformDqs3 = 0x00000005, + .EmcDllXformDqs4 = 0x00000005, + .EmcDllXformDqs5 = 0x00000005, + .EmcDllXformDqs6 = 0x00000005, + .EmcDllXformDqs7 = 0x00000005, + .EmcDllXformDqs8 = 0x00000005, + .EmcDllXformDqs9 = 0x00000005, + .EmcDllXformDqs10 = 0x00000005, + .EmcDllXformDqs11 = 0x00000005, + .EmcDllXformDqs12 = 0x00000005, + .EmcDllXformDqs13 = 0x00000005, + .EmcDllXformDqs14 = 0x00000005, + .EmcDllXformDqs15 = 0x00000005, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0000400e, + .EmcDllXformAddr1 = 0x0000400e, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0000400e, + .EmcDllXformAddr4 = 0x0000400e, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00000006, + .EmcDllXformDq1 = 0x00000006, + .EmcDllXformDq2 = 0x00000006, + .EmcDllXformDq3 = 0x00000006, + .EmcDllXformDq4 = 0x00000006, + .EmcDllXformDq5 = 0x00000006, + .EmcDllXformDq6 = 0x00000006, + .EmcDllXformDq7 = 0x00000006, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x0000004c, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80000f15, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0020013d, + .EmcXm2DqsPadCtrl3 = 0x55555520, + .EmcXm2DqsPadCtrl4 = 0x003cf3cf, + .EmcXm2DqsPadCtrl5 = 0x003cf3cf, + .EmcXm2DqsPadCtrl6 = 0x55555500, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000303, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000d, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000005, + .McEmemArbTimingRp = 0x00000006, + .McEmemArbTimingRc = 0x00000016, + .McEmemArbTimingRas = 0x0000000e, + .McEmemArbTimingFaw = 0x00000011, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000004, + .McEmemArbTimingWap2Pre = 0x0000000e, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000009, + .McEmemArbDaTurns = 0x09060202, + .McEmemArbDaCovers = 0x001a1016, + .McEmemArbMisc0 = 0x734e2a17, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan/bct/sdram-unused.inc b/src/mainboard/google/nyan/bct/sdram-unused.inc new file mode 100644 index 0000000..bef63dc --- /dev/null +++ b/src/mainboard/google/nyan/bct/sdram-unused.inc @@ -0,0 +1,4 @@ +{ /* dummy. */ + .MemoryType = NvBootMemoryType_Unused, + 0, +}, diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index 0761aed..c168550 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -72,17 +72,19 @@ void bootblock_mainboard_init(void) pmic_init(4); /* SPI4 data out (MOSI) */ - pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, - PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG6_INDEX, + PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE | + PINMUX_PULL_UP); /* SPI4 data in (MISO) */ - pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, - PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG7_INDEX, + PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE | + PINMUX_PULL_UP); /* SPI4 clock */ - pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, - PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG5_INDEX, + PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE); /* SPI4 chip select 0 */ - pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, - PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PI3_INDEX, + PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); tegra_spi_init(4); } diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index ea40388..3eaf38c 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -25,15 +25,12 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include "sdram_configs.h" #include "soc/nvidia/tegra124/chip.h" +#include "soc/nvidia/tegra124/sdram.h" #include <soc/display.h> #include <timestamp.h> -// Convenient shorthand (in MB) -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ - enum { L2CTLR_ECC_PARITY = 0x1 << 21, L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, @@ -74,6 +71,7 @@ static void configure_l2actlr(void) void main(void) { + int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -97,12 +95,20 @@ void main(void) console_init(); exception_init(); + sdram_init(get_sdram_config()); + + /* used for MMU and CBMEM setup */ + dram_size_mb = sdram_size_mb(); + + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); - mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start, DCACHE_OFF); + mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); dcache_invalidate_all(); dcache_mmu_enable(); diff --git a/src/mainboard/google/nyan/sdram_configs.c b/src/mainboard/google/nyan/sdram_configs.c new file mode 100644 index 0000000..89e3361 --- /dev/null +++ b/src/mainboard/google/nyan/sdram_configs.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <soc/nvidia/tegra124/sdram.h> +#include "sdram_configs.h" + +static struct sdram_params sdram_configs[] = { +#include "bct/sdram-hynix-2GB-792.inc" /* ram_code = 0000 */ +#include "bct/sdram-unused.inc" /* ram_code = 0001 */ +#include "bct/sdram-unused.inc" /* ram_code = 0010 */ +#include "bct/sdram-unused.inc" /* ram_code = 0011 */ +#include "bct/sdram-unused.inc" /* ram_code = 0100 */ +#include "bct/sdram-unused.inc" /* ram_code = 0101 */ +#include "bct/sdram-unused.inc" /* ram_code = 0110 */ +#include "bct/sdram-unused.inc" /* ram_code = 0111 */ +#include "bct/sdram-unused.inc" /* ram_code = 1000 */ +#include "bct/sdram-unused.inc" /* ram_code = 1001 */ +#include "bct/sdram-unused.inc" /* ram_code = 1010 */ +#include "bct/sdram-unused.inc" /* ram_code = 1011 */ +#include "bct/sdram-unused.inc" /* ram_code = 1100 */ +#include "bct/sdram-unused.inc" /* ram_code = 1101 */ +#include "bct/sdram-unused.inc" /* ram_code = 1110 */ +#include "bct/sdram-unused.inc" /* ram_code = 1111 */ +}; + +const struct sdram_params *get_sdram_config() +{ + uint32_t ramcode = sdram_get_ram_code(); + /* + * If we need to apply some special hacks to RAMCODE mapping (ex, by + * board_id), do that now. + */ + + printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); + if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { + die("Invalid RAMCODE."); + } + + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/nyan/sdram_configs.h b/src/mainboard/google/nyan/sdram_configs.h new file mode 100644 index 0000000..e0ea1e2 --- /dev/null +++ b/src/mainboard/google/nyan/sdram_configs.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ +#define __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ + +#include <soc/nvidia/tegra124/sdram_param.h> + +/* Loads SDRAM configurations for current system. */ +const struct sdram_params *get_sdram_config(void); + +#endif /* __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ */ diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 4973667..6e24926 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan Big" -config DRAM_SIZE_MB - int - default 2048 - config DRAM_DMA_START hex default 0x90000000 @@ -90,18 +86,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 -choice - prompt "BCT sdram configuration" - default NYAN_BIG_BCT_SDRAM_792 - help - The SDRAM configuration to put in the BCT. - -config NYAN_BIG_BCT_SDRAM_792 - bool "792 MHz" - -config NYAN_BIG_BCT_SDRAM_924 - bool "924 MHz" - -endchoice - endif # BOARD_GOOGLE_NYAN_BIG diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index d4a8cdb..9cdff3b 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -32,6 +32,7 @@ bootblock-y += bootblock.c bootblock-y += pmic.c romstage-y += romstage.c +romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan_big/bct/Makefile.inc b/src/mainboard/google/nyan_big/bct/Makefile.inc index 65b87f0..09af378 100644 --- a/src/mainboard/google/nyan_big/bct/Makefile.inc +++ b/src/mainboard/google/nyan_big/bct/Makefile.inc @@ -20,5 +20,7 @@ bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_EMMC) += emmc.cfg bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_SPI) += spi.cfg bct-cfg-y += odmdata.cfg -bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_924) += sdram-924.cfg -bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_792) += sdram-792.cfg + +# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate +# the include files (sdram-*.inc). See ../../nyan/bct/Makefile.inc for more +# information. diff --git a/src/mainboard/google/nyan_big/bct/sdram-792.cfg b/src/mainboard/google/nyan_big/bct/sdram-792.cfg deleted file mode 100644 index d4d9660..0000000 --- a/src/mainboard/google/nyan_big/bct/sdram-792.cfg +++ /dev/null @@ -1,346 +0,0 @@ -# CFG Version 07 -# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command: -# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650 -# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg -# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz) -# bkv file: PM358/PM358_792MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x00000042; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430000; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000000; -SDRAM[0].EmcPinProgramWait = 0x00000001; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x00000025; -SDRAM[0].EmcRfc = 0x000000cd; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x00000019; -SDRAM[0].EmcRp = 0x0000000a; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000007; -SDRAM[0].EmcW2r = 0x0000000d; -SDRAM[0].EmcR2p = 0x00000004; -SDRAM[0].EmcW2p = 0x00000013; -SDRAM[0].EmcRdRcd = 0x0000000a; -SDRAM[0].EmcWrRcd = 0x0000000a; -SDRAM[0].EmcRrd = 0x00000003; -SDRAM[0].EmcRext = 0x00000002; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000006; -SDRAM[0].EmcWdvMask = 0x00000006; -SDRAM[0].EmcQUse = 0x0000000b; -SDRAM[0].EmcQuseWidth = 0x00000002; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000003; -SDRAM[0].EmcEInputDuration = 0x0000000c; -SDRAM[0].EmcPutermExtra = 0x00090000; -SDRAM[0].EmcPutermWidth = 0x00000004; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000002; -SDRAM[0].EmcQSafe = 0x00000011; -SDRAM[0].EmcRdv = 0x00000017; -SDRAM[0].EmcRdvMask = 0x00000019; -SDRAM[0].EmcQpop = 0x0000000f; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000004; -SDRAM[0].EmcRefresh = 0x000017eb; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa; -SDRAM[0].EmcPdEx2Wr = 0x00000003; -SDRAM[0].EmcPdEx2Rd = 0x00000003; -SDRAM[0].EmcPChg2Pden = 0x00000001; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x000000c7; -SDRAM[0].EmcRw2Pden = 0x00000018; -SDRAM[0].EmcTxsr = 0x000000d7; -SDRAM[0].EmcTxsrDll = 0x00000200; -SDRAM[0].EmcTcke = 0x00000005; -SDRAM[0].EmcTckesr = 0x00000006; -SDRAM[0].EmcTpd = 0x00000005; -SDRAM[0].EmcTfaw = 0x0000001d; -SDRAM[0].EmcTrpab = 0x00000000; -SDRAM[0].EmcTClkStable = 0x00000008; -SDRAM[0].EmcTClkStop = 0x00000008; -SDRAM[0].EmcTRefBw = 0x0000182c; -SDRAM[0].EmcFbioCfg5 = 0x104ab898; -SDRAM[0].EmcFbioCfg6 = 0x00000002; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x80001d71; -SDRAM[0].EmcEmrs = 0x80100002; -SDRAM[0].EmcEmrs2 = 0x80200018; -SDRAM[0].EmcEmrs3 = 0x80300000; -SDRAM[0].EmcMrw1 = 0x00000000; -SDRAM[0].EmcMrw2 = 0x00000000; -SDRAM[0].EmcMrw3 = 0x00000000; -SDRAM[0].EmcMrw4 = 0x00000000; -SDRAM[0].EmcMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x00000000; -SDRAM[0].EmcMrwResetNInitWait = 0x00000000; -SDRAM[0].EmcMrsWaitCnt = 0x00f7000e; -SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e; -SDRAM[0].EmcCfg = 0x73300000; -SDRAM[0].EmcCfg2 = 0x0000089d; -SDRAM[0].EmcCfgPipe = 0x000040a0; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x80003025; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00701b1; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000002; -SDRAM[0].EmcSelDpdCtrl = 0x00040000; -SDRAM[0].EmcDllXformDqs0 = 0x00000008; -SDRAM[0].EmcDllXformDqs1 = 0x00000008; -SDRAM[0].EmcDllXformDqs2 = 0x00000008; -SDRAM[0].EmcDllXformDqs3 = 0x00000008; -SDRAM[0].EmcDllXformDqs4 = 0x00000008; -SDRAM[0].EmcDllXformDqs5 = 0x00000008; -SDRAM[0].EmcDllXformDqs6 = 0x00000008; -SDRAM[0].EmcDllXformDqs7 = 0x00000008; -SDRAM[0].EmcDllXformDqs8 = 0x00000008; -SDRAM[0].EmcDllXformDqs9 = 0x00000008; -SDRAM[0].EmcDllXformDqs10 = 0x00000008; -SDRAM[0].EmcDllXformDqs11 = 0x00000008; -SDRAM[0].EmcDllXformDqs12 = 0x00000008; -SDRAM[0].EmcDllXformDqs13 = 0x00000008; -SDRAM[0].EmcDllXformDqs14 = 0x00000008; -SDRAM[0].EmcDllXformDqs15 = 0x00000008; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x0000000e; -SDRAM[0].EmcDllXformAddr1 = 0x0000000e; -SDRAM[0].EmcDllXformAddr2 = 0x00000000; -SDRAM[0].EmcDllXformAddr3 = 0x0000000e; -SDRAM[0].EmcDllXformAddr4 = 0x00000000; -SDRAM[0].EmcDllXformAddr5 = 0x00000000; -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; -SDRAM[0].EmcDllXformDq0 = 0x0000000b; -SDRAM[0].EmcDllXformDq1 = 0x0000000b; -SDRAM[0].EmcDllXformDq2 = 0x0000000b; -SDRAM[0].EmcDllXformDq3 = 0x0000000b; -SDRAM[0].EmcDllXformDq4 = 0x0000000b; -SDRAM[0].EmcDllXformDq5 = 0x0000000b; -SDRAM[0].EmcDllXformDq6 = 0x0000000b; -SDRAM[0].EmcDllXformDq7 = 0x0000000b; -SDRAM[0].WarmBootWait = 0x00000002; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00020000; -SDRAM[0].EmcZcalWaitCnt = 0x00000042; -SDRAM[0].EmcZcalMrwCmd = 0x80000000; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x80000011; -SDRAM[0].EmcZcalInitDev1 = 0x00000000; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x80001d71; -SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000002; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00002002; -SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x00000000; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; -SDRAM[0].EmcDsrVttgenDrv = 0x0505003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000000; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00000800; -SDRAM[0].McEmemArbCfg = 0x0e00000b; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000004; -SDRAM[0].McEmemArbTimingRp = 0x00000005; -SDRAM[0].McEmemArbTimingRc = 0x00000013; -SDRAM[0].McEmemArbTimingRas = 0x0000000c; -SDRAM[0].McEmemArbTimingFaw = 0x0000000f; -SDRAM[0].McEmemArbTimingRrd = 0x00000002; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c; -SDRAM[0].McEmemArbTimingR2R = 0x00000002; -SDRAM[0].McEmemArbTimingW2W = 0x00000002; -SDRAM[0].McEmemArbTimingR2W = 0x00000005; -SDRAM[0].McEmemArbTimingW2R = 0x00000008; -SDRAM[0].McEmemArbDaTurns = 0x08050202; -SDRAM[0].McEmemArbDaCovers = 0x00170e13; -SDRAM[0].McEmemArbMisc0 = 0x736c2414; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000000; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; -SDRAM[0].SwizzleRankByteEncode = 0x0000006f; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0xfff00000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c; diff --git a/src/mainboard/google/nyan_big/bct/sdram-924.cfg b/src/mainboard/google/nyan_big/bct/sdram-924.cfg deleted file mode 100644 index fa3271a..0000000 --- a/src/mainboard/google/nyan_big/bct/sdram-924.cfg +++ /dev/null @@ -1,346 +0,0 @@ -# CFG Version 11 -# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command: -# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650 -# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg -# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz) -# bkv file: PM358/PM358_924MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x0000004d; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430404; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000000; -SDRAM[0].EmcPinProgramWait = 0x00000001; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x0000002b; -SDRAM[0].EmcRfc = 0x000000ef; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x0000001e; -SDRAM[0].EmcRp = 0x0000000b; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000008; -SDRAM[0].EmcW2r = 0x0000000f; -SDRAM[0].EmcR2p = 0x00000005; -SDRAM[0].EmcW2p = 0x00000016; -SDRAM[0].EmcRdRcd = 0x0000000b; -SDRAM[0].EmcWrRcd = 0x0000000b; -SDRAM[0].EmcRrd = 0x00000004; -SDRAM[0].EmcRext = 0x00000002; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000006; -SDRAM[0].EmcWdvMask = 0x00000006; -SDRAM[0].EmcQUse = 0x0000000c; -SDRAM[0].EmcQuseWidth = 0x00000002; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000002; -SDRAM[0].EmcEInputDuration = 0x0000000e; -SDRAM[0].EmcPutermExtra = 0x000a0000; -SDRAM[0].EmcPutermWidth = 0x00000004; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000001; -SDRAM[0].EmcQSafe = 0x00000015; -SDRAM[0].EmcRdv = 0x0000001b; -SDRAM[0].EmcRdvMask = 0x0000001d; -SDRAM[0].EmcQpop = 0x00000010; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000004; -SDRAM[0].EmcRefresh = 0x00001be9; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa; -SDRAM[0].EmcPdEx2Wr = 0x00000004; -SDRAM[0].EmcPdEx2Rd = 0x00000015; -SDRAM[0].EmcPChg2Pden = 0x00000001; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x000000e6; -SDRAM[0].EmcRw2Pden = 0x0000001b; -SDRAM[0].EmcTxsr = 0x000000fa; -SDRAM[0].EmcTxsrDll = 0x00000200; -SDRAM[0].EmcTcke = 0x00000006; -SDRAM[0].EmcTckesr = 0x00000007; -SDRAM[0].EmcTpd = 0x00000006; -SDRAM[0].EmcTfaw = 0x00000022; -SDRAM[0].EmcTrpab = 0x00000000; -SDRAM[0].EmcTClkStable = 0x0000000a; -SDRAM[0].EmcTClkStop = 0x0000000a; -SDRAM[0].EmcTRefBw = 0x00001c29; -SDRAM[0].EmcFbioCfg5 = 0x104ab898; -SDRAM[0].EmcFbioCfg6 = 0x00000002; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x80000f15; -SDRAM[0].EmcEmrs = 0x80100002; -SDRAM[0].EmcEmrs2 = 0x80200020; -SDRAM[0].EmcEmrs3 = 0x80300000; -SDRAM[0].EmcMrw1 = 0x00000000; -SDRAM[0].EmcMrw2 = 0x00000000; -SDRAM[0].EmcMrw3 = 0x00000000; -SDRAM[0].EmcMrw4 = 0x00000000; -SDRAM[0].EmcMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x00000000; -SDRAM[0].EmcMrwResetNInitWait = 0x00000000; -SDRAM[0].EmcMrsWaitCnt = 0x00ce000e; -SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e; -SDRAM[0].EmcCfg = 0x73300000; -SDRAM[0].EmcCfg2 = 0x000008a5; -SDRAM[0].EmcCfgPipe = 0x00000000; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x800037ed; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00401b1; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000002; -SDRAM[0].EmcSelDpdCtrl = 0x00040000; -SDRAM[0].EmcDllXformDqs0 = 0x00000005; -SDRAM[0].EmcDllXformDqs1 = 0x00000005; -SDRAM[0].EmcDllXformDqs2 = 0x00000005; -SDRAM[0].EmcDllXformDqs3 = 0x00000005; -SDRAM[0].EmcDllXformDqs4 = 0x00000005; -SDRAM[0].EmcDllXformDqs5 = 0x00000005; -SDRAM[0].EmcDllXformDqs6 = 0x00000005; -SDRAM[0].EmcDllXformDqs7 = 0x00000005; -SDRAM[0].EmcDllXformDqs8 = 0x00000005; -SDRAM[0].EmcDllXformDqs9 = 0x00000005; -SDRAM[0].EmcDllXformDqs10 = 0x00000005; -SDRAM[0].EmcDllXformDqs11 = 0x00000005; -SDRAM[0].EmcDllXformDqs12 = 0x00000005; -SDRAM[0].EmcDllXformDqs13 = 0x00000005; -SDRAM[0].EmcDllXformDqs14 = 0x00000005; -SDRAM[0].EmcDllXformDqs15 = 0x00000005; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x0000400e; -SDRAM[0].EmcDllXformAddr1 = 0x0000400e; -SDRAM[0].EmcDllXformAddr2 = 0x00000000; -SDRAM[0].EmcDllXformAddr3 = 0x0000400e; -SDRAM[0].EmcDllXformAddr4 = 0x0000400e; -SDRAM[0].EmcDllXformAddr5 = 0x00000000; -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; -SDRAM[0].EmcDllXformDq0 = 0x00000006; -SDRAM[0].EmcDllXformDq1 = 0x00000006; -SDRAM[0].EmcDllXformDq2 = 0x00000006; -SDRAM[0].EmcDllXformDq3 = 0x00000006; -SDRAM[0].EmcDllXformDq4 = 0x00000006; -SDRAM[0].EmcDllXformDq5 = 0x00000006; -SDRAM[0].EmcDllXformDq6 = 0x00000006; -SDRAM[0].EmcDllXformDq7 = 0x00000006; -SDRAM[0].WarmBootWait = 0x00000002; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00020000; -SDRAM[0].EmcZcalWaitCnt = 0x0000004c; -SDRAM[0].EmcZcalMrwCmd = 0x80000000; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x80000011; -SDRAM[0].EmcZcalInitDev1 = 0x00000000; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x80000f15; -SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000002; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00002002; -SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x00000000; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; -SDRAM[0].EmcDsrVttgenDrv = 0x0606003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000000; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00000800; -SDRAM[0].McEmemArbCfg = 0x0e00000d; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000005; -SDRAM[0].McEmemArbTimingRp = 0x00000006; -SDRAM[0].McEmemArbTimingRc = 0x00000016; -SDRAM[0].McEmemArbTimingRas = 0x0000000e; -SDRAM[0].McEmemArbTimingFaw = 0x00000011; -SDRAM[0].McEmemArbTimingRrd = 0x00000002; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e; -SDRAM[0].McEmemArbTimingR2R = 0x00000002; -SDRAM[0].McEmemArbTimingW2W = 0x00000002; -SDRAM[0].McEmemArbTimingR2W = 0x00000006; -SDRAM[0].McEmemArbTimingW2R = 0x00000009; -SDRAM[0].McEmemArbDaTurns = 0x09060202; -SDRAM[0].McEmemArbDaCovers = 0x001a1016; -SDRAM[0].McEmemArbMisc0 = 0x734e2a17; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000000; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; -SDRAM[0].SwizzleRankByteEncode = 0x0000006f; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0xfff00000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-204.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-204.inc new file mode 100644 index 0000000..d75e0b5 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-204.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-204-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000022, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x40000002, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000009, + .EmcRfc = 0x00000035, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000007, + .EmcRp = 0x00000002, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000005, + .EmcW2r = 0x0000000a, + .EmcR2p = 0x00000003, + .EmcW2p = 0x0000000b, + .EmcRdRcd = 0x00000002, + .EmcWrRcd = 0x00000002, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000003, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000005, + .EmcWdvMask = 0x00000005, + .EmcQUse = 0x00000006, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000004, + .EmcEInputDuration = 0x00000006, + .EmcPutermExtra = 0x00010000, + .EmcPutermWidth = 0x00000003, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000003, + .EmcQSafe = 0x0000000d, + .EmcRdv = 0x0000000f, + .EmcRdvMask = 0x00000011, + .EmcQpop = 0x0000000a, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000003, + .EmcRefresh = 0x00000607, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x00000181, + .EmcPdEx2Wr = 0x00000002, + .EmcPdEx2Rd = 0x00000002, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x00000032, + .EmcRw2Pden = 0x0000000f, + .EmcTxsr = 0x00000038, + .EmcTxsrDll = 0x00000038, + .EmcTcke = 0x00000004, + .EmcTckesr = 0x00000005, + .EmcTpd = 0x00000004, + .EmcTfaw = 0x00000007, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000005, + .EmcTClkStop = 0x00000005, + .EmcTRefBw = 0x00000638, + .EmcFbioCfg5 = 0x106aa298, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80001221, + .EmcEmrs = 0x80100003, + .EmcEmrs2 = 0x80200008, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x000c000c, + .EmcMrsWaitCnt2 = 0x000c000c, + .EmcCfg = 0x73240000, + .EmcCfg2 = 0x0000088d, + .EmcCfgPipe = 0x0000d2b3, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80000d22, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0x002c00a0, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040008, + .EmcDllXformDqs0 = 0x00064000, + .EmcDllXformDqs1 = 0x00064000, + .EmcDllXformDqs2 = 0x00064000, + .EmcDllXformDqs3 = 0x00064000, + .EmcDllXformDqs4 = 0x00064000, + .EmcDllXformDqs5 = 0x00064000, + .EmcDllXformDqs6 = 0x00064000, + .EmcDllXformDqs7 = 0x00064000, + .EmcDllXformDqs8 = 0x00064000, + .EmcDllXformDqs9 = 0x00064000, + .EmcDllXformDqs10 = 0x00064000, + .EmcDllXformDqs11 = 0x00064000, + .EmcDllXformDqs12 = 0x00064000, + .EmcDllXformDqs13 = 0x00064000, + .EmcDllXformDqs14 = 0x00064000, + .EmcDllXformDqs15 = 0x00064000, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00000000, + .EmcDllXformAddr1 = 0x00000000, + .EmcDllXformAddr2 = 0x00004000, + .EmcDllXformAddr3 = 0x00000000, + .EmcDllXformAddr4 = 0x00000000, + .EmcDllXformAddr5 = 0x00004000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00090000, + .EmcDllXformDq1 = 0x00090000, + .EmcDllXformDq2 = 0x00094000, + .EmcDllXformDq3 = 0x00094000, + .EmcDllXformDq4 = 0x00009400, + .EmcDllXformDq5 = 0x00009000, + .EmcDllXformDq6 = 0x00009000, + .EmcDllXformDq7 = 0x00009000, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000003, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000002, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80001221, + .EmcWarmBootMrsExtra = 0x80100003, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x10000280, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0130b118, + .EmcXm2DqsPadCtrl3 = 0x51451400, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x51451400, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc081, + .EmcXm2ClkPadCtrl2 = 0x00000303, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x0000003f, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0000003f, + .EmcTxdsrvttgen = 0x00000066, + .EmcBgbiasCtl0 = 0x00000008, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x01000003, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000001, + .McEmemArbTimingRp = 0x00000001, + .McEmemArbTimingRc = 0x00000005, + .McEmemArbTimingRas = 0x00000002, + .McEmemArbTimingFaw = 0x00000004, + .McEmemArbTimingRrd = 0x00000001, + .McEmemArbTimingRap2Pre = 0x00000002, + .McEmemArbTimingWap2Pre = 0x00000008, + .McEmemArbTimingR2R = 0x00000003, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000004, + .McEmemArbTimingW2R = 0x00000006, + .McEmemArbDaTurns = 0x06040203, + .McEmemArbDaCovers = 0x000a0405, + .McEmemArbMisc0 = 0x73840a06, + .McEmemArbMisc1 = 0x70000f03, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc new file mode 100644 index 0000000..3020002 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x000000cc, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000009, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000c6, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x000000d6, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80000d71, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200018, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00f8000c, + .EmcMrsWaitCnt2 = 0x00f8000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00034000, + .EmcDllXformAddr1 = 0x00034000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x00034000, + .EmcDllXformAddr4 = 0x00034000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000009, + .EmcDliTrimTxDqs4 = 0x00000009, + .EmcDliTrimTxDqs5 = 0x00000007, + .EmcDliTrimTxDqs6 = 0x00000009, + .EmcDliTrimTxDqs7 = 0x00000008, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000009, + .EmcDliTrimTxDqs12 = 0x00000009, + .EmcDliTrimTxDqs13 = 0x00000007, + .EmcDliTrimTxDqs14 = 0x00000009, + .EmcDliTrimTxDqs15 = 0x00000008, + .EmcDllXformDq0 = 0x0000000e, + .EmcDllXformDq1 = 0x0000000e, + .EmcDllXformDq2 = 0x0000000e, + .EmcDllXformDq3 = 0x0000000e, + .EmcDllXformDq4 = 0x0000000e, + .EmcDllXformDq5 = 0x0000000e, + .EmcDllXformDq6 = 0x0000000e, + .EmcDllXformDq7 = 0x0000000e, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80000d71, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000101, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00160d13, + .McEmemArbMisc0 = 0x734c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-924.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-924.inc new file mode 100644 index 0000000..e4d4faf --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-924.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x0000004d, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430404, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x0000002b, + .EmcRfc = 0x000000ef, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001e, + .EmcRp = 0x0000000b, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000f, + .EmcR2p = 0x00000005, + .EmcW2p = 0x00000016, + .EmcRdRcd = 0x0000000b, + .EmcWrRcd = 0x0000000b, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000c, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000e, + .EmcPutermExtra = 0x000a0000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000015, + .EmcRdv = 0x0000001b, + .EmcRdvMask = 0x0000001d, + .EmcQpop = 0x00000010, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x00001be9, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000006fa, + .EmcPdEx2Wr = 0x00000004, + .EmcPdEx2Rd = 0x00000015, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000e6, + .EmcRw2Pden = 0x0000001b, + .EmcTxsr = 0x000000fa, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000006, + .EmcTckesr = 0x00000007, + .EmcTpd = 0x00000006, + .EmcTfaw = 0x00000022, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x0000000a, + .EmcTClkStop = 0x0000000a, + .EmcTRefBw = 0x00001c29, + .EmcFbioCfg5 = 0x104ab898, + .EmcFbioCfg6 = 0x00000002, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80000f15, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200020, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00ce000e, + .EmcMrsWaitCnt2 = 0x00ce000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x000008a5, + .EmcCfgPipe = 0x00000000, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x800037ed, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00401b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000005, + .EmcDllXformDqs1 = 0x00000005, + .EmcDllXformDqs2 = 0x00000005, + .EmcDllXformDqs3 = 0x00000005, + .EmcDllXformDqs4 = 0x00000005, + .EmcDllXformDqs5 = 0x00000005, + .EmcDllXformDqs6 = 0x00000005, + .EmcDllXformDqs7 = 0x00000005, + .EmcDllXformDqs8 = 0x00000005, + .EmcDllXformDqs9 = 0x00000005, + .EmcDllXformDqs10 = 0x00000005, + .EmcDllXformDqs11 = 0x00000005, + .EmcDllXformDqs12 = 0x00000005, + .EmcDllXformDqs13 = 0x00000005, + .EmcDllXformDqs14 = 0x00000005, + .EmcDllXformDqs15 = 0x00000005, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0000400e, + .EmcDllXformAddr1 = 0x0000400e, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0000400e, + .EmcDllXformAddr4 = 0x0000400e, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00000006, + .EmcDllXformDq1 = 0x00000006, + .EmcDllXformDq2 = 0x00000006, + .EmcDllXformDq3 = 0x00000006, + .EmcDllXformDq4 = 0x00000006, + .EmcDllXformDq5 = 0x00000006, + .EmcDllXformDq6 = 0x00000006, + .EmcDllXformDq7 = 0x00000006, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x0000004c, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80000f15, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0020013d, + .EmcXm2DqsPadCtrl3 = 0x55555520, + .EmcXm2DqsPadCtrl4 = 0x003cf3cf, + .EmcXm2DqsPadCtrl5 = 0x003cf3cf, + .EmcXm2DqsPadCtrl6 = 0x55555500, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000303, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000d, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000005, + .McEmemArbTimingRp = 0x00000006, + .McEmemArbTimingRc = 0x00000016, + .McEmemArbTimingRas = 0x0000000e, + .McEmemArbTimingFaw = 0x00000011, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000004, + .McEmemArbTimingWap2Pre = 0x0000000e, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000009, + .McEmemArbDaTurns = 0x09060202, + .McEmemArbDaCovers = 0x001a1016, + .McEmemArbMisc0 = 0x734e2a17, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-204.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-204.inc new file mode 100644 index 0000000..2feede7 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-204.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0100-204-4GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000022, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x40000002, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000009, + .EmcRfc = 0x00000047, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000007, + .EmcRp = 0x00000002, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000005, + .EmcW2r = 0x0000000a, + .EmcR2p = 0x00000003, + .EmcW2p = 0x0000000b, + .EmcRdRcd = 0x00000002, + .EmcWrRcd = 0x00000002, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000003, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000005, + .EmcWdvMask = 0x00000005, + .EmcQUse = 0x00000006, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000004, + .EmcEInputDuration = 0x00000006, + .EmcPutermExtra = 0x00010000, + .EmcPutermWidth = 0x00000003, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000003, + .EmcQSafe = 0x0000000d, + .EmcRdv = 0x0000000f, + .EmcRdvMask = 0x00000011, + .EmcQpop = 0x0000000a, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000003, + .EmcRefresh = 0x00000607, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x00000181, + .EmcPdEx2Wr = 0x00000002, + .EmcPdEx2Rd = 0x00000002, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x00000044, + .EmcRw2Pden = 0x0000000f, + .EmcTxsr = 0x0000004a, + .EmcTxsrDll = 0x0000004a, + .EmcTcke = 0x00000004, + .EmcTckesr = 0x00000005, + .EmcTpd = 0x00000004, + .EmcTfaw = 0x00000007, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000005, + .EmcTClkStop = 0x00000005, + .EmcTRefBw = 0x00000638, + .EmcFbioCfg5 = 0x106aa298, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00001221, + .EmcEmrs = 0x00100003, + .EmcEmrs2 = 0x00200008, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x000c000c, + .EmcMrsWaitCnt2 = 0x000c000c, + .EmcCfg = 0x73240000, + .EmcCfg2 = 0x0000088d, + .EmcCfgPipe = 0x0000d2b3, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80000d22, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0x002c00a0, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040008, + .EmcDllXformDqs0 = 0x00064000, + .EmcDllXformDqs1 = 0x00064000, + .EmcDllXformDqs2 = 0x00064000, + .EmcDllXformDqs3 = 0x00064000, + .EmcDllXformDqs4 = 0x00064000, + .EmcDllXformDqs5 = 0x00064000, + .EmcDllXformDqs6 = 0x00064000, + .EmcDllXformDqs7 = 0x00064000, + .EmcDllXformDqs8 = 0x00064000, + .EmcDllXformDqs9 = 0x00064000, + .EmcDllXformDqs10 = 0x00064000, + .EmcDllXformDqs11 = 0x00064000, + .EmcDllXformDqs12 = 0x00064000, + .EmcDllXformDqs13 = 0x00064000, + .EmcDllXformDqs14 = 0x00064000, + .EmcDllXformDqs15 = 0x00064000, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00000000, + .EmcDllXformAddr1 = 0x00000000, + .EmcDllXformAddr2 = 0x00004000, + .EmcDllXformAddr3 = 0x00000000, + .EmcDllXformAddr4 = 0x00000000, + .EmcDllXformAddr5 = 0x00004000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00090000, + .EmcDllXformDq1 = 0x00090000, + .EmcDllXformDq2 = 0x00094000, + .EmcDllXformDq3 = 0x00094000, + .EmcDllXformDq4 = 0x00009400, + .EmcDllXformDq5 = 0x00009000, + .EmcDllXformDq6 = 0x00009000, + .EmcDllXformDq7 = 0x00009000, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000003, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000002, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00001221, + .EmcWarmBootMrsExtra = 0x00100003, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x10000280, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0130b118, + .EmcXm2DqsPadCtrl3 = 0x51451400, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x51451400, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc081, + .EmcXm2ClkPadCtrl2 = 0x00000303, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x0000003f, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0000003f, + .EmcTxdsrvttgen = 0x00000066, + .EmcBgbiasCtl0 = 0x00000008, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x01000003, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000001, + .McEmemArbTimingRp = 0x00000001, + .McEmemArbTimingRc = 0x00000005, + .McEmemArbTimingRas = 0x00000002, + .McEmemArbTimingFaw = 0x00000004, + .McEmemArbTimingRrd = 0x00000001, + .McEmemArbTimingRap2Pre = 0x00000002, + .McEmemArbTimingWap2Pre = 0x00000008, + .McEmemArbTimingR2R = 0x00000003, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000004, + .McEmemArbTimingW2R = 0x00000006, + .McEmemArbDaTurns = 0x06040203, + .McEmemArbDaCovers = 0x000a0405, + .McEmemArbMisc0 = 0x74a40a06, + .McEmemArbMisc1 = 0x70000f03, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc new file mode 100644 index 0000000..5c8d09c --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0100-792-4GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x00000114, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000007, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x0000010d, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x0000011e, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00000d71, + .EmcEmrs = 0x00100002, + .EmcEmrs2 = 0x00200018, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x006f000c, + .EmcMrsWaitCnt2 = 0x006f000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00034000, + .EmcDllXformAddr1 = 0x00034000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x00034000, + .EmcDllXformAddr4 = 0x00034000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000009, + .EmcDliTrimTxDqs4 = 0x00000009, + .EmcDliTrimTxDqs5 = 0x00000007, + .EmcDliTrimTxDqs6 = 0x00000009, + .EmcDliTrimTxDqs7 = 0x00000008, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000009, + .EmcDliTrimTxDqs12 = 0x00000009, + .EmcDliTrimTxDqs13 = 0x00000007, + .EmcDliTrimTxDqs14 = 0x00000009, + .EmcDliTrimTxDqs15 = 0x00000008, + .EmcDllXformDq0 = 0x0000000e, + .EmcDllXformDq1 = 0x0000000e, + .EmcDllXformDq2 = 0x0000000e, + .EmcDllXformDq3 = 0x0000000e, + .EmcDllXformDq4 = 0x0000000e, + .EmcDllXformDq5 = 0x0000000e, + .EmcDllXformDq6 = 0x0000000e, + .EmcDllXformDq7 = 0x0000000e, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00000d71, + .EmcWarmBootMrsExtra = 0x00100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000101, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000004, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00150c13, + .McEmemArbMisc0 = 0x746c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-unused.inc b/src/mainboard/google/nyan_big/bct/sdram-unused.inc new file mode 100644 index 0000000..bef63dc --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-unused.inc @@ -0,0 +1,4 @@ +{ /* dummy. */ + .MemoryType = NvBootMemoryType_Unused, + 0, +}, diff --git a/src/mainboard/google/nyan_big/bct/spi.cfg b/src/mainboard/google/nyan_big/bct/spi.cfg index aef7e82..e9f85d5 100644 --- a/src/mainboard/google/nyan_big/bct/spi.cfg +++ b/src/mainboard/google/nyan_big/bct/spi.cfg @@ -14,3 +14,21 @@ DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; +DevType[1] = NvBootDevType_Spi; +DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[1].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0; + +DevType[2] = NvBootDevType_Spi; +DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[2].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0; + +DevType[3] = NvBootDevType_Spi; +DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0; + diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index f43e532..23b1c6a 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <soc/nvidia/tegra124/gpio.h> +#include <stdlib.h> #include "boardid.h" @@ -27,11 +28,17 @@ uint8_t board_id(void) static int id = -1; if (id < 0) { - id = gpio_get_in_value(GPIO(Q3)) << 0 | - gpio_get_in_value(GPIO(T1)) << 1 | - gpio_get_in_value(GPIO(X1)) << 2 | - gpio_get_in_value(GPIO(X4)) << 3; - printk(BIOS_SPEW, "Board ID: %#x.\n", id); + gpio_t gpio[] = {GPIO(Q3), GPIO(T1), GPIO(X1), GPIO(X4)}; + int value[ARRAY_SIZE(gpio)]; + + gpio_get_in_tristate_values(gpio, ARRAY_SIZE(gpio), value); + + /* A gpio state is encoded in every two-bit */ + id = value[0] << 0 | + value[1] << 2 | + value[2] << 4 | + value[3] << 6; + printk(BIOS_SPEW, "Board TRISTATE ID: %#x.\n", id); } return id; diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c index f07951a..e88765f 100644 --- a/src/mainboard/google/nyan_big/bootblock.c +++ b/src/mainboard/google/nyan_big/bootblock.c @@ -72,17 +72,19 @@ void bootblock_mainboard_init(void) pmic_init(4); /* SPI4 data out (MOSI) */ - pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, - PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG6_INDEX, + PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE | + PINMUX_PULL_UP); /* SPI4 data in (MISO) */ - pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, - PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG7_INDEX, + PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE | + PINMUX_PULL_UP); /* SPI4 clock */ - pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, - PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG5_INDEX, + PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE); /* SPI4 chip select 0 */ - pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, - PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PI3_INDEX, + PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); tegra_spi_init(4); } diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index f64b59c..89e1f87 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -83,10 +83,7 @@ void pmic_init(unsigned bus) pmic_slam_defaults(bus); /* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */ - if (board_id() == 0) - pmic_write_reg(bus, 0x00, 0x3c); - else - pmic_write_reg(bus, 0x00, 0x50); + pmic_write_reg(bus, 0x00, 0x50); /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */ pmic_write_reg(bus, 0x06, 0x28); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 0e71020..80eea77 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -25,15 +25,12 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include "sdram_configs.h" #include "soc/nvidia/tegra124/chip.h" +#include "soc/nvidia/tegra124/sdram.h" #include <soc/display.h> #include <timestamp.h> -// Convenient shorthand (in MB) -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ - enum { L2CTLR_ECC_PARITY = 0x1 << 21, L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, @@ -74,6 +71,7 @@ static void configure_l2actlr(void) void main(void) { + int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -97,12 +95,20 @@ void main(void) console_init(); exception_init(); + sdram_init(get_sdram_config()); + + /* used for MMU and CBMEM setup */ + dram_size_mb = sdram_size_mb(); + + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); - mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start, DCACHE_OFF); + mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); dcache_invalidate_all(); dcache_mmu_enable(); diff --git a/src/mainboard/google/nyan_big/sdram_configs.c b/src/mainboard/google/nyan_big/sdram_configs.c new file mode 100644 index 0000000..2aaace4 --- /dev/null +++ b/src/mainboard/google/nyan_big/sdram_configs.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <soc/nvidia/tegra124/sdram.h> +#include "sdram_configs.h" + +/* + * Note for board bring up, we've temporarily filled SDRAM table with + * hynix-2GB-204 configuration (except the hynix-4GB-204 entry for 0100). + */ +static struct sdram_params sdram_configs[] = { +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0000 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0001 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0010 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0011 */ +#include "bct/sdram-hynix-4GB-204.inc" /* ram_code = 0100 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0101 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0110 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0111 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1000 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1001 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1010 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1011 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1100 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1101 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1110 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1111 */ +}; + +const struct sdram_params *get_sdram_config() +{ + uint32_t ramcode = sdram_get_ram_code(); + /* + * If we need to apply some special hacks to RAMCODE mapping (ex, by + * board_id), do that now. + */ + + printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); + if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { + die("Invalid RAMCODE."); + } + + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/nyan_big/sdram_configs.h b/src/mainboard/google/nyan_big/sdram_configs.h new file mode 100644 index 0000000..4bf376c --- /dev/null +++ b/src/mainboard/google/nyan_big/sdram_configs.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ +#define __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ + +#include <soc/nvidia/tegra124/sdram_param.h> + +/* Loads SDRAM configurations for current system. */ +const struct sdram_params *get_sdram_config(void); + +#endif /* __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ */ diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 7a38adf..48ffbda 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -569,4 +569,7 @@ struct disp_ctl_win { void display_startup(device_t dev); void dp_bringup(u32 winb_addr); + +unsigned int fb_base_mb(void); + #endif /* __SOC_NVIDIA_TEGRA_DC_H */ diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 4cf6d5f..ac0fc3f 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -22,6 +22,7 @@ #include <soc/addressmap.h> #include <stddef.h> #include <stdint.h> +#include <delay.h> #include "gpio.h" #include "pinmux.h" @@ -174,6 +175,58 @@ int gpio_get_in_value(gpio_t gpio) return (port & (1 << bit)) != 0; } +int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int value[]) +{ + /* + * GPIOs which are tied to stronger external pull up or pull down + * will stay there regardless of the internal pull up or pull + * down setting. + * + * GPIOs which are floating will go to whatever level they're + * internally pulled to. + */ + + int temp; + int index; + + /* Enable internal pull up */ + for (index = 0; index < num_gpio; ++index) + gpio_input_pullup(gpio[index]); + + /* Wait until signals become stable */ + udelay(10); + + /* Get gpio values at internal pull up */ + for (index = 0; index < num_gpio; ++index) + value[index] = gpio_get_in_value(gpio[index]); + + /* Enable internal pull down */ + for (index = 0; index < num_gpio; ++index) + gpio_input_pulldown(gpio[index]); + + /* Wait until signals become stable */ + udelay(10); + + /* + * Get gpio values at internal pull down. + * Compare with gpio pull up value and then + * determine a gpio final value/state: + * 0: pull down + * 1: pull up + * 2: floating + */ + for (index = 0; index < num_gpio; ++index) { + temp = gpio_get_in_value(gpio[index]); + value[index] = ((value[index] ^ temp) << 1) | temp; + } + + /* Disable pull up / pull down to conserve power */ + for (index = 0; index < num_gpio; ++index) + gpio_input(gpio[index]); + + return 0; +} + int gpio_get_int_status(gpio_t gpio) { int bit = gpio % GPIO_GPIOS_PER_PORT; diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index 70c1026..5f6833a 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -81,6 +81,7 @@ void gpio_set_out_value(gpio_t gpio, int value); int gpio_get_out_value(gpio_t gpio); int gpio_get_in_value(gpio_t gpio); +int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int value[]); int gpio_get_int_status(gpio_t gpio); diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index ec6ee92..3876a9e 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -26,17 +26,15 @@ config BOOTBLOCK_CPU_INIT # 0x18080 Free for CBFS data. # # iRAM (256k) layout. -# 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM. -# +0000 (BootROM) Boot Information Table. -# +0100 (BootROM) BCT. -# --------------------------------------------------------------------- -# +0000 (Coreboot) TTB 16KB. -# +4000 (Coreboot) Stack. -# 0x4000_E000 Valid for anything to be executed after BootROM (effective entry -# point address specified in BCT). -# +0000 (Coreboot) Bootblock (max 36k). -# +9000 (Coreboot) ROM stage (max 36k). -# 0x4002_0000 (Coreboot) Cache of CBFS. +# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, +# so the bootblock loading address must be placed after that. After the +# handoff that area may be reclaimed for other uses, e.g. CBFS cache.) +# +# 0x4000_0000 TTB (16KB). +# 0x4000_4000 CBFS mapping cache (96KB). +# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!). +# 0x4002_0000 Bootblock (max 48KB). +# 0x4002_C000 ROM stage (max 80KB). # 0x4003_FFFF End of iRAM. config BOOTBLOCK_ROM_OFFSET @@ -57,11 +55,11 @@ config SYS_SDRAM_BASE config BOOTBLOCK_BASE hex - default 0x4000e000 + default 0x40020000 config ROMSTAGE_BASE hex - default 0x40017000 + default 0x4002c000 config RAMSTAGE_BASE hex @@ -69,12 +67,13 @@ config RAMSTAGE_BASE config STACK_TOP hex - default 0x4000c000 + default 0x40020000 config STACK_BOTTOM hex - default 0x40004000 + default 0x4001c000 +# This is the ramstage thread stack, *not* the same as above! Currently unused. config STACK_SIZE hex default 0x800 @@ -86,10 +85,10 @@ config TTB_BUFFER config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" - default 0x40020000 + default 0x40004000 config CBFS_CACHE_SIZE hex "size of CBFS cache data" - default 0x00020000 + default 0x00018000 endif diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 7a6bced..4ba2342 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += dma.c romstage-y += i2c.c romstage-y += monotonic_timer.c romstage-y += sdram.c +romstage-y += sdram_lp0.c romstage-y += spi.c romstage-y += ../tegra/gpio.c romstage-y += ../tegra/i2c.c @@ -41,6 +42,7 @@ ramstage-y += dma.c ramstage-y += i2c.c ramstage-y += maincpu.S ramstage-y += monotonic_timer.c +ramstage-y += sdram.c ramstage-y += soc.c ramstage-y += sor.c ramstage-y += spi.c diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index d80b3a0..7f20702 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -18,10 +18,11 @@ */ #include <cbmem.h> -#include <soc/addressmap.h> +#include <soc/display.h> +#include <soc/nvidia/tegra124/sdram.h> void *cbmem_top(void) { return (void *)(CONFIG_SYS_SDRAM_BASE + - ((CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)<< 20UL)); + ((sdram_size_mb() - FB_SIZE_MB)<< 20UL)); } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index ba357fd..00dfbb6 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -33,6 +33,7 @@ #include <edid.h> #include <soc/clock.h> #include <soc/nvidia/tegra/dc.h> +#include <soc/nvidia/tegra124/sdram.h> #include "chip.h" #include <soc/display.h> @@ -225,6 +226,11 @@ static void update_window(struct display_controller *dc, WRITEL(val, &dc->cmd.state_ctrl); } +uint32_t fb_base_mb(void) +{ + return CONFIG_SYS_SDRAM_BASE/MiB + (sdram_size_mb() - FB_SIZE_MB); +} + /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ @@ -279,7 +285,7 @@ void display_startup(device_t dev) } if (! framebuffer_base_mb) - framebuffer_base_mb = FB_BASE_MB; + framebuffer_base_mb = fb_base_mb(); mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, config->cache_policy); diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index 5e55ee5..063e369 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -80,9 +80,4 @@ enum { TEGRA_I2C_BASE_COUNT = 6, }; -enum { - FB_SIZE_MB = (32), - FB_BASE_MB = (CONFIG_SYS_SDRAM_BASE/MiB + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)), -}; - #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h index b764671..36348ff 100644 --- a/src/soc/nvidia/tegra124/include/soc/display.h +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -188,6 +188,7 @@ #define COLORDEPTH 0x6 #define COLOR_WHITE 0xFFFFFF +struct soc_nvidia_tegra124_config; /* forward declaration */ void setup_display(struct soc_nvidia_tegra124_config *config); void init_dca_regs(void); void dp_io_powerup(void); @@ -195,4 +196,7 @@ u32 dp_setup_timing(u32 width, u32 height); void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 lane_count, u32 enhanced_framing, u32 panel_edp, u32 pclkfreq, u32 linkfreq); + +#define FB_SIZE_MB (32) + #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra124/mc.h b/src/soc/nvidia/tegra124/mc.h index 0fc3738..567b32a 100644 --- a/src/soc/nvidia/tegra124/mc.h +++ b/src/soc/nvidia/tegra124/mc.h @@ -115,6 +115,9 @@ struct tegra_mc_regs { }; enum { + MC_EMEM_CFG_SIZE_MB_SHIFT = 0, + MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff, + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 283cbf4..dcab810 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -568,6 +568,13 @@ void sdram_init(const struct sdram_params *param) struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE; struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE; + printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n", + param->MemoryType, clock_get_osc_khz() * + param->PllMFeedbackDivider / param->PllMInputDivider / + (1 + param->PllMSelectDiv2)); + if (param->MemoryType != NvBootMemoryType_Ddr3) + die("Unsupported memory type!\n"); + sdram_configure_pmc(param, pmc); sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1); @@ -600,6 +607,8 @@ void sdram_init(const struct sdram_params *param) sdram_set_refresh(param, emc); sdram_enable_arbiter(param); sdram_lock_carveouts(param, mc); + + sdram_lp0_save_params(param); } uint32_t sdram_get_ram_code(void) @@ -609,3 +618,24 @@ uint32_t sdram_get_ram_code(void) PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); } + +/* returns total amount of DRAM (in MB) from memory controller registers */ +int sdram_size_mb(void) +{ + struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE; + static int total_size = 0; + + if (total_size) + return total_size; + + /* + * This obtains memory size from the External Memory Aperture + * Configuration register. Nvidia confirmed that it is safe to assume + * this value represents the total physical DRAM size. + */ + total_size = (read32(&mc->emem_cfg) >> + MC_EMEM_CFG_SIZE_MB_SHIFT) & MC_EMEM_CFG_SIZE_MB_MASK; + + printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size); + return total_size; +} diff --git a/src/soc/nvidia/tegra124/sdram.h b/src/soc/nvidia/tegra124/sdram.h index cf5761c..66dbaa1 100644 --- a/src/soc/nvidia/tegra124/sdram.h +++ b/src/soc/nvidia/tegra124/sdram.h @@ -24,5 +24,9 @@ uint32_t sdram_get_ram_code(void); void sdram_init(const struct sdram_params *param); +int sdram_size_mb(void); + +/* Save params to PMC scratch registers for use by BootROM on LP0 resume. */ +void sdram_lp0_save_params(const struct sdram_params *sdram); #endif /* __SOC_NVIDIA_TEGRA124_SDRAM_H__ */ diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c new file mode 100644 index 0000000..0cd814e --- /dev/null +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <arch/cache.h> +#include <console/console.h> +#include <stdlib.h> +#include <soc/addressmap.h> + +#include "clk_rst.h" +#include "pmc.h" +#include "sdram.h" + +/* + * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from + * the common BCT format and writes them into PMC scratch registers (where the + * BootROM expects them on LP0 resume). Since those store the same values in a + * different format, we follow a "translation table" taken from Nvidia's U-Boot + * implementation to shift bits into the right position. + * + * Contrary to U-Boot, we transform the same macros directly into hardcoded + * assignments (without any pesky function calls or volatile qualifiers) to give + * the compiler as much room for optimization as possible. For that reason, we + * also intentionally avoid <arch/io.h> read/write macros, under the assumption + * that PMC scratch register accesses should not have side effects and can be + * arbitrarily reordered. For the few accesses that do have side-effects, the + * code must contain explicit memory barriers. + */ +void sdram_lp0_save_params(const struct sdram_params *sdram) +{ + struct tegra_pmc_regs * pmc = (void *)TEGRA_PMC_BASE; + struct clk_rst_ctlr * clk_rst = (void *)TEGRA_CLK_RST_BASE; + +#define pack(src, src_bits, dst, dst_bits) { \ + _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ + (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \ + _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \ + (0 ? dst_bits), "src and dst byte range lengths differ" ); \ + u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ + dst &= ~(mask << (0 ? dst_bits)); \ + dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ +} + +#define s(param, src_bits, pmcreg, dst_bits) \ + pack(sdram->param, src_bits, pmc->pmcreg, dst_bits) + +#define m(clkreg, src_bits, pmcreg, dst_bits) \ + pack(clk_rst->clkreg, src_bits, pmc->pmcreg, dst_bits) + +#define c(value, pmcreg, dst_bits) \ + pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) + + s(EmcClockSource, 7:0, scratch6, 15:8); + s(EmcClockSource, 31:29, scratch6, 18:16); + s(EmcClockSource, 26:26, scratch6, 19:19); + s(EmcOdtWrite, 5:0, scratch6, 25:20); + s(EmcOdtWrite, 11:8, scratch6, 29:26); + s(EmcOdtWrite, 30:30, scratch6, 30:30); + s(EmcOdtWrite, 31:31, scratch6, 31:31); + s(EmcXm2DqPadCtrl2, 18:16, scratch7, 22:20); + s(EmcXm2DqPadCtrl2, 22:20, scratch7, 25:23); + s(EmcXm2DqPadCtrl2, 26:24, scratch7, 28:26); + s(EmcXm2DqPadCtrl2, 30:28, scratch7, 31:29); + s(EmcXm2DqPadCtrl3, 18:16, scratch8, 22:20); + s(EmcXm2DqPadCtrl3, 22:20, scratch8, 25:23); + s(EmcXm2DqPadCtrl3, 26:24, scratch8, 28:26); + s(EmcXm2DqPadCtrl3, 30:28, scratch8, 31:29); + s(EmcTxsrDll, 11:0, scratch9, 31:20); + c(0, scratch10, 31:0); + s(EmcDsrVttgenDrv, 5:0, scratch10, 25:20); + s(EmcDsrVttgenDrv, 18:16, scratch10, 28:26); + s(EmcDsrVttgenDrv, 26:24, scratch10, 31:29); + s(EmcFbioSpare, 31:24, scratch11, 7:0); + s(EmcFbioSpare, 23:16, scratch11, 15:8); + s(EmcFbioSpare, 15:8, scratch11, 23:16); + s(EmcFbioSpare, 7:0, scratch11, 31:24); + s(EmcCfgRsv, 31:0, scratch12, 31:0); + s(EmcCdbCntl2, 31:0, scratch13, 31:0); + s(McEmemArbDaTurns, 31:0, scratch14, 31:0); + s(EmcCfgDigDll, 0:0, scratch17, 0:0); + s(EmcCfgDigDll, 25:2, scratch17, 24:1); + s(EmcCfgDigDll, 31:27, scratch17, 29:25); + s(EmcCdbCntl1, 29:0, scratch18, 29:0); + s(McEmemArbMisc0, 14:0, scratch19, 14:0); + s(McEmemArbMisc0, 30:16, scratch19, 29:15); + s(EmcXm2DqsPadCtrl, 4:0, scratch22, 4:0); + s(EmcXm2DqsPadCtrl, 12:8, scratch22, 9:5); + s(EmcXm2DqsPadCtrl, 31:14, scratch22, 27:10); + s(EmcRrd, 3:0, scratch22, 31:28); + s(EmcXm2DqPadCtrl, 31:4, scratch23, 27:0); + s(EmcRext, 3:0, scratch23, 31:28); + s(EmcXm2CompPadCtrl, 16:0, scratch24, 16:0); + s(EmcXm2CompPadCtrl, 24:20, scratch24, 21:17); + s(EmcXm2CompPadCtrl, 27:27, scratch24, 22:22); + s(EmcXm2CompPadCtrl, 31:28, scratch24, 26:23); + s(EmcR2w, 4:0, scratch24, 31:27); + s(EmcCfg, 9:1, scratch25, 8:0); + s(EmcCfg, 26:16, scratch25, 19:9); + s(EmcCfg, 31:28, scratch25, 23:20); + s(EmcXm2VttGenPadCtrl, 0:0, scratch25, 24:24); + s(EmcXm2VttGenPadCtrl, 2:2, scratch25, 25:25); + s(EmcXm2VttGenPadCtrl, 18:16, scratch25, 28:26); + s(EmcXm2VttGenPadCtrl, 26:24, scratch25, 31:29); + s(EmcZcalInterval, 23:10, scratch26, 13:0); + s(EmcZcalInterval, 9:0, scratch26, 23:14); + s(EmcSelDpdCtrl, 5:2, scratch26, 27:24); + s(EmcSelDpdCtrl, 8:8, scratch26, 28:28); + s(EmcSelDpdCtrl, 18:16, scratch26, 31:29); + s(EmcXm2VttGenPadCtrl3, 22:0, scratch27, 22:0); + s(EmcXm2VttGenPadCtrl3, 24:24, scratch27, 23:23); + s(EmcSwizzleRank0ByteCfg, 1:0, scratch27, 25:24); + s(EmcSwizzleRank0ByteCfg, 5:4, scratch27, 27:26); + s(EmcSwizzleRank0ByteCfg, 9:8, scratch27, 29:28); + s(EmcSwizzleRank0ByteCfg, 13:12, scratch27, 31:30); + s(EmcXm2ClkPadCtrl2, 5:0, scratch28, 5:0); + s(EmcXm2ClkPadCtrl2, 13:8, scratch28, 11:6); + s(EmcXm2ClkPadCtrl2, 20:16, scratch28, 16:12); + s(EmcXm2ClkPadCtrl2, 23:23, scratch28, 17:17); + s(EmcXm2ClkPadCtrl2, 28:24, scratch28, 22:18); + s(EmcXm2ClkPadCtrl2, 31:31, scratch28, 23:23); + s(EmcSwizzleRank1ByteCfg, 1:0, scratch28, 25:24); + s(EmcSwizzleRank1ByteCfg, 5:4, scratch28, 27:26); + s(EmcSwizzleRank1ByteCfg, 9:8, scratch28, 29:28); + s(EmcSwizzleRank1ByteCfg, 13:12, scratch28, 31:30); + s(McEmemArbDaCovers, 23:0, scratch29, 23:0); + s(McEmemArbRsv, 7:0, scratch29, 31:24); + s(EmcAutoCalConfig, 4:0, scratch30, 4:0); + s(EmcAutoCalConfig, 12:8, scratch30, 9:5); + s(EmcAutoCalConfig, 18:16, scratch30, 12:10); + s(EmcAutoCalConfig, 25:20, scratch30, 18:13); + s(EmcAutoCalConfig, 31:28, scratch30, 22:19); + s(EmcRfc, 8:0, scratch30, 31:23); + s(EmcXm2DqsPadCtrl2, 21:0, scratch31, 21:0); + s(EmcXm2DqsPadCtrl2, 24:24, scratch31, 22:22); + s(EmcAr2Pden, 8:0, scratch31, 31:23); + s(EmcXm2ClkPadCtrl, 0:0, scratch32, 0:0); + s(EmcXm2ClkPadCtrl, 4:2, scratch32, 3:1); + s(EmcXm2ClkPadCtrl, 7:7, scratch32, 4:4); + s(EmcXm2ClkPadCtrl, 31:14, scratch32, 22:5); + s(EmcRfcSlr, 8:0, scratch32, 31:23); + s(EmcXm2DqsPadCtrl3, 0:0, scratch33, 0:0); + s(EmcXm2DqsPadCtrl3, 5:5, scratch33, 1:1); + s(EmcXm2DqsPadCtrl3, 12:8, scratch33, 6:2); + s(EmcXm2DqsPadCtrl3, 18:14, scratch33, 11:7); + s(EmcXm2DqsPadCtrl3, 24:20, scratch33, 16:12); + s(EmcXm2DqsPadCtrl3, 30:26, scratch33, 21:17); + s(EmcTxsr, 9:0, scratch33, 31:22); + s(McEmemArbCfg, 8:0, scratch40, 8:0); + s(McEmemArbCfg, 20:16, scratch40, 13:9); + s(McEmemArbCfg, 27:24, scratch40, 17:14); + s(McEmemArbCfg, 31:28, scratch40, 21:18); + s(EmcMc2EmcQ, 2:0, scratch40, 24:22); + s(EmcMc2EmcQ, 10:8, scratch40, 27:25); + s(EmcMc2EmcQ, 27:24, scratch40, 31:28); + s(EmcAutoCalInterval, 20:0, scratch42, 20:0); + s(McEmemArbOutstandingReq, 8:0, scratch42, 29:21); + s(McEmemArbOutstandingReq, 31:30, scratch42, 31:30); + s(EmcMrsWaitCnt2, 9:0, scratch44, 9:0); + s(EmcMrsWaitCnt2, 25:16, scratch44, 19:10); + s(EmcTxdsrvttgen, 11:0, scratch44, 31:20); + s(EmcMrsWaitCnt, 9:0, scratch45, 9:0); + s(EmcMrsWaitCnt, 25:16, scratch45, 19:10); + s(EmcCfgPipe, 1:0, scratch45, 21:20); + s(EmcCfgPipe, 9:4, scratch45, 27:22); + s(EmcCfgPipe, 15:12, scratch45, 31:28); + s(EmcXm2DqsPadCtrl4, 22:18, scratch46, 4:0); + s(EmcXm2DqsPadCtrl4, 16:12, scratch46, 9:5); + s(EmcXm2DqsPadCtrl4, 10:6, scratch46, 14:10); + s(EmcXm2DqsPadCtrl4, 4:0, scratch46, 19:15); + s(EmcZcalWaitCnt, 9:0, scratch46, 29:20); + s(EmcXm2DqsPadCtrl5, 22:18, scratch47, 4:0); + s(EmcXm2DqsPadCtrl5, 16:12, scratch47, 9:5); + s(EmcXm2DqsPadCtrl5, 10:6, scratch47, 14:10); + s(EmcXm2DqsPadCtrl5, 4:0, scratch47, 19:15); + s(EmcXm2VttGenPadCtrl2, 5:0, scratch47, 25:20); + s(EmcXm2VttGenPadCtrl2, 31:28, scratch47, 29:26); + s(EmcXm2DqsPadCtrl6, 12:8, scratch48, 4:0); + s(EmcXm2DqsPadCtrl6, 18:14, scratch48, 9:5); + s(EmcXm2DqsPadCtrl6, 24:20, scratch48, 14:10); + s(EmcXm2DqsPadCtrl6, 30:26, scratch48, 19:15); + s(EmcAutoCalConfig3, 4:0, scratch48, 24:20); + s(EmcAutoCalConfig3, 12:8, scratch48, 29:25); + s(EmcFbioCfg5, 1:0, scratch48, 31:30); + s(EmcDllXformQUse8, 4:0, scratch50, 4:0); + s(EmcDllXformQUse8, 22:8, scratch50, 19:5); + s(McEmemArbRing1Throttle, 4:0, scratch50, 24:20); + s(McEmemArbRing1Throttle, 20:16, scratch50, 29:25); + s(EmcFbioCfg5, 3:2, scratch50, 31:30); + s(EmcDllXformQUse9, 4:0, scratch51, 4:0); + s(EmcDllXformQUse9, 22:8, scratch51, 19:5); + s(EmcCttTermCtrl, 2:0, scratch51, 22:20); + s(EmcCttTermCtrl, 12:8, scratch51, 27:23); + s(EmcCttTermCtrl, 31:31, scratch51, 28:28); + s(EmcFbioCfg6, 2:0, scratch51, 31:29); + s(EmcDllXformQUse10, 4:0, scratch56, 4:0); + s(EmcDllXformQUse10, 22:8, scratch56, 19:5); + s(EmcXm2CmdPadCtrl, 10:3, scratch56, 27:20); + s(EmcXm2CmdPadCtrl, 28:28, scratch56, 28:28); + s(EmcPutermAdj, 1:0, scratch56, 30:29); + s(EmcPutermAdj, 7:7, scratch56, 31:31); + s(EmcDllXformQUse11, 4:0, scratch57, 4:0); + s(EmcDllXformQUse11, 22:8, scratch57, 19:5); + s(EmcWdv, 3:0, scratch57, 31:28); + s(EmcDllXformQUse12, 4:0, scratch58, 4:0); + s(EmcDllXformQUse12, 22:8, scratch58, 19:5); + s(EmcBurstRefreshNum, 3:0, scratch58, 31:28); + s(EmcDllXformQUse13, 4:0, scratch59, 4:0); + s(EmcDllXformQUse13, 22:8, scratch59, 19:5); + s(EmcWext, 3:0, scratch59, 31:28); + s(EmcDllXformQUse14, 4:0, scratch60, 4:0); + s(EmcDllXformQUse14, 22:8, scratch60, 19:5); + s(EmcClkenOverride, 3:1, scratch60, 30:28); + s(EmcClkenOverride, 6:6, scratch60, 31:31); + s(EmcDllXformQUse15, 4:0, scratch61, 4:0); + s(EmcDllXformQUse15, 22:8, scratch61, 19:5); + s(EmcR2r, 3:0, scratch61, 31:28); + s(EmcDllXformDq4, 4:0, scratch62, 4:0); + s(EmcDllXformDq4, 22:8, scratch62, 19:5); + s(EmcRc, 6:0, scratch62, 26:20); + s(EmcW2r, 4:0, scratch62, 31:27); + s(EmcDllXformDq5, 4:0, scratch63, 4:0); + s(EmcDllXformDq5, 22:8, scratch63, 19:5); + s(EmcTfaw, 6:0, scratch63, 26:20); + s(EmcR2p, 4:0, scratch63, 31:27); + s(EmcDllXformDq6, 4:0, scratch64, 4:0); + s(EmcDllXformDq6, 22:8, scratch64, 19:5); + s(EmcDliTrimTxDqs0, 6:0, scratch64, 26:20); + s(EmcQSafe, 4:0, scratch64, 31:27); + s(EmcDllXformDq7, 4:0, scratch65, 4:0); + s(EmcDllXformDq7, 22:8, scratch65, 19:5); + s(EmcDliTrimTxDqs1, 6:0, scratch65, 26:20); + s(EmcTClkStable, 4:0, scratch65, 31:27); + s(EmcAutoCalConfig2, 4:0, scratch66, 4:0); + s(EmcAutoCalConfig2, 12:8, scratch66, 9:5); + s(EmcAutoCalConfig2, 20:16, scratch66, 14:10); + s(EmcAutoCalConfig2, 28:24, scratch66, 19:15); + s(EmcDliTrimTxDqs2, 6:0, scratch66, 26:20); + s(EmcTClkStop, 4:0, scratch66, 31:27); + s(McEmemArbMisc1, 1:0, scratch67, 1:0); + s(McEmemArbMisc1, 12:4, scratch67, 10:2); + s(McEmemArbMisc1, 25:21, scratch67, 15:11); + s(McEmemArbMisc1, 31:28, scratch67, 19:16); + s(EmcDliTrimTxDqs3, 6:0, scratch67, 26:20); + s(EmcEInputDuration, 4:0, scratch67, 31:27); + s(EmcZcalMrwCmd, 7:0, scratch68, 7:0); + s(EmcZcalMrwCmd, 23:16, scratch68, 15:8); + s(EmcZcalMrwCmd, 31:30, scratch68, 17:16); + s(EmcTRefBw, 13:0, scratch68, 31:18); + s(EmcXm2CmdPadCtrl2, 31:14, scratch69, 17:0); + s(EmcDliTrimTxDqs4, 6:0, scratch69, 24:18); + s(EmcDliTrimTxDqs5, 6:0, scratch69, 31:25); + s(EmcXm2CmdPadCtrl3, 31:14, scratch70, 17:0); + s(EmcDliTrimTxDqs6, 6:0, scratch70, 24:18); + s(EmcDliTrimTxDqs7, 6:0, scratch70, 31:25); + s(EmcXm2CmdPadCtrl5, 2:0, scratch71, 2:0); + s(EmcXm2CmdPadCtrl5, 6:4, scratch71, 5:3); + s(EmcXm2CmdPadCtrl5, 10:8, scratch71, 8:6); + s(EmcXm2CmdPadCtrl5, 14:12, scratch71, 11:9); + s(EmcXm2CmdPadCtrl5, 18:16, scratch71, 14:12); + s(EmcXm2CmdPadCtrl5, 22:20, scratch71, 17:15); + s(EmcDliTrimTxDqs8, 6:0, scratch71, 24:18); + s(EmcDliTrimTxDqs9, 6:0, scratch71, 31:25); + s(EmcCdbCntl3, 17:0, scratch72, 17:0); + s(EmcDliTrimTxDqs10, 6:0, scratch72, 24:18); + s(EmcDliTrimTxDqs11, 6:0, scratch72, 31:25); + s(EmcSwizzleRank0Byte0, 2:0, scratch73, 2:0); + s(EmcSwizzleRank0Byte0, 6:4, scratch73, 5:3); + s(EmcSwizzleRank0Byte0, 10:8, scratch73, 8:6); + s(EmcSwizzleRank0Byte0, 14:12, scratch73, 11:9); + s(EmcSwizzleRank0Byte0, 18:16, scratch73, 14:12); + s(EmcSwizzleRank0Byte0, 22:20, scratch73, 17:15); + s(EmcDliTrimTxDqs12, 6:0, scratch73, 24:18); + s(EmcDliTrimTxDqs13, 6:0, scratch73, 31:25); + s(EmcSwizzleRank0Byte1, 2:0, scratch74, 2:0); + s(EmcSwizzleRank0Byte1, 6:4, scratch74, 5:3); + s(EmcSwizzleRank0Byte1, 10:8, scratch74, 8:6); + s(EmcSwizzleRank0Byte1, 14:12, scratch74, 11:9); + s(EmcSwizzleRank0Byte1, 18:16, scratch74, 14:12); + s(EmcSwizzleRank0Byte1, 22:20, scratch74, 17:15); + s(EmcDliTrimTxDqs14, 6:0, scratch74, 24:18); + s(EmcDliTrimTxDqs15, 6:0, scratch74, 31:25); + s(EmcSwizzleRank0Byte2, 2:0, scratch75, 2:0); + s(EmcSwizzleRank0Byte2, 6:4, scratch75, 5:3); + s(EmcSwizzleRank0Byte2, 10:8, scratch75, 8:6); + s(EmcSwizzleRank0Byte2, 14:12, scratch75, 11:9); + s(EmcSwizzleRank0Byte2, 18:16, scratch75, 14:12); + s(EmcSwizzleRank0Byte2, 22:20, scratch75, 17:15); + s(McEmemArbTimingRp, 6:0, scratch75, 24:18); + s(McEmemArbTimingRc, 6:0, scratch75, 31:25); + s(EmcSwizzleRank0Byte3, 2:0, scratch76, 2:0); + s(EmcSwizzleRank0Byte3, 6:4, scratch76, 5:3); + s(EmcSwizzleRank0Byte3, 10:8, scratch76, 8:6); + s(EmcSwizzleRank0Byte3, 14:12, scratch76, 11:9); + s(EmcSwizzleRank0Byte3, 18:16, scratch76, 14:12); + s(EmcSwizzleRank0Byte3, 22:20, scratch76, 17:15); + s(McEmemArbTimingFaw, 6:0, scratch76, 24:18); + s(McEmemArbTimingWap2Pre, 6:0, scratch76, 31:25); + s(EmcSwizzleRank1Byte0, 2:0, scratch77, 2:0); + s(EmcSwizzleRank1Byte0, 6:4, scratch77, 5:3); + s(EmcSwizzleRank1Byte0, 10:8, scratch77, 8:6); + s(EmcSwizzleRank1Byte0, 14:12, scratch77, 11:9); + s(EmcSwizzleRank1Byte0, 18:16, scratch77, 14:12); + s(EmcSwizzleRank1Byte0, 22:20, scratch77, 17:15); + s(EmcRas, 5:0, scratch77, 23:18); + s(EmcRp, 5:0, scratch77, 29:24); + s(EmcCfg2, 9:8, scratch77, 31:30); + s(EmcSwizzleRank1Byte1, 2:0, scratch78, 2:0); + s(EmcSwizzleRank1Byte1, 6:4, scratch78, 5:3); + s(EmcSwizzleRank1Byte1, 10:8, scratch78, 8:6); + s(EmcSwizzleRank1Byte1, 14:12, scratch78, 11:9); + s(EmcSwizzleRank1Byte1, 18:16, scratch78, 14:12); + s(EmcSwizzleRank1Byte1, 22:20, scratch78, 17:15); + s(EmcW2p, 5:0, scratch78, 23:18); + s(EmcRdRcd, 5:0, scratch78, 29:24); + s(EmcCfg2, 27:26, scratch78, 31:30); + s(EmcSwizzleRank1Byte2, 2:0, scratch79, 2:0); + s(EmcSwizzleRank1Byte2, 6:4, scratch79, 5:3); + s(EmcSwizzleRank1Byte2, 10:8, scratch79, 8:6); + s(EmcSwizzleRank1Byte2, 14:12, scratch79, 11:9); + s(EmcSwizzleRank1Byte2, 18:16, scratch79, 14:12); + s(EmcSwizzleRank1Byte2, 22:20, scratch79, 17:15); + s(EmcWrRcd, 5:0, scratch79, 23:18); + s(EmcQUse, 5:0, scratch79, 29:24); + s(EmcFbioCfg5, 4:4, scratch79, 31:31); + s(EmcSwizzleRank1Byte3, 2:0, scratch80, 2:0); + s(EmcSwizzleRank1Byte3, 6:4, scratch80, 5:3); + s(EmcSwizzleRank1Byte3, 10:8, scratch80, 8:6); + s(EmcSwizzleRank1Byte3, 14:12, scratch80, 11:9); + s(EmcSwizzleRank1Byte3, 18:16, scratch80, 14:12); + s(EmcSwizzleRank1Byte3, 22:20, scratch80, 17:15); + s(EmcQRst, 5:0, scratch80, 23:18); + s(EmcRdv, 5:0, scratch80, 29:24); + s(EmcFbioCfg5, 6:5, scratch80, 31:30); + s(EmcDynSelfRefControl, 15:0, scratch81, 15:0); + s(EmcDynSelfRefControl, 31:31, scratch81, 16:16); + s(EmcPdEx2Wr, 5:0, scratch81, 22:17); + s(EmcPdEx2Rd, 5:0, scratch81, 28:23); + s(EmcRefresh, 5:0, scratch82, 5:0); + s(EmcRefresh, 15:6, scratch82, 15:6); + s(EmcCmdQ, 4:0, scratch82, 20:16); + s(EmcCmdQ, 10:8, scratch82, 23:21); + s(EmcCmdQ, 14:12, scratch82, 26:24); + s(EmcCmdQ, 28:24, scratch82, 31:27); + s(EmcAcpdControl, 15:0, scratch83, 15:0); + s(EmcCfgDigDllPeriod, 15:0, scratch83, 31:16); + s(EmcDllXformDqs0, 4:0, scratch84, 4:0); + s(EmcDllXformDqs0, 22:12, scratch84, 15:5); + s(EmcDllXformDqs1, 4:0, scratch84, 20:16); + s(EmcDllXformDqs1, 22:12, scratch84, 31:21); + s(EmcDllXformDqs2, 4:0, scratch85, 4:0); + s(EmcDllXformDqs2, 22:12, scratch85, 15:5); + s(EmcDllXformDqs3, 4:0, scratch85, 20:16); + s(EmcDllXformDqs3, 22:12, scratch85, 31:21); + s(EmcDllXformDqs4, 4:0, scratch86, 4:0); + s(EmcDllXformDqs4, 22:12, scratch86, 15:5); + s(EmcDllXformDqs5, 4:0, scratch86, 20:16); + s(EmcDllXformDqs5, 22:12, scratch86, 31:21); + s(EmcDllXformDqs6, 4:0, scratch87, 4:0); + s(EmcDllXformDqs6, 22:12, scratch87, 15:5); + s(EmcDllXformDqs7, 4:0, scratch87, 20:16); + s(EmcDllXformDqs7, 22:12, scratch87, 31:21); + s(EmcDllXformDqs8, 4:0, scratch88, 4:0); + s(EmcDllXformDqs8, 22:12, scratch88, 15:5); + s(EmcDllXformDqs9, 4:0, scratch88, 20:16); + s(EmcDllXformDqs9, 22:12, scratch88, 31:21); + s(EmcDllXformDqs10, 4:0, scratch89, 4:0); + s(EmcDllXformDqs10, 22:12, scratch89, 15:5); + s(EmcDllXformDqs11, 4:0, scratch89, 20:16); + s(EmcDllXformDqs11, 22:12, scratch89, 31:21); + s(EmcDllXformDqs12, 4:0, scratch90, 4:0); + s(EmcDllXformDqs12, 22:12, scratch90, 15:5); + s(EmcDllXformDqs13, 4:0, scratch90, 20:16); + s(EmcDllXformDqs13, 22:12, scratch90, 31:21); + s(EmcDllXformDqs14, 4:0, scratch91, 4:0); + s(EmcDllXformDqs14, 22:12, scratch91, 15:5); + s(EmcDllXformDqs15, 4:0, scratch91, 20:16); + s(EmcDllXformDqs15, 22:12, scratch91, 31:21); + s(EmcDllXformQUse0, 4:0, scratch92, 4:0); + s(EmcDllXformQUse0, 22:12, scratch92, 15:5); + s(EmcDllXformQUse1, 4:0, scratch92, 20:16); + s(EmcDllXformQUse1, 22:12, scratch92, 31:21); + s(EmcDllXformQUse2, 4:0, scratch93, 4:0); + s(EmcDllXformQUse2, 22:12, scratch93, 15:5); + s(EmcDllXformQUse3, 4:0, scratch93, 20:16); + s(EmcDllXformQUse3, 22:12, scratch93, 31:21); + s(EmcDllXformQUse4, 4:0, scratch94, 4:0); + s(EmcDllXformQUse4, 22:12, scratch94, 15:5); + s(EmcDllXformQUse5, 4:0, scratch94, 20:16); + s(EmcDllXformQUse5, 22:12, scratch94, 31:21); + s(EmcDllXformQUse6, 4:0, scratch95, 4:0); + s(EmcDllXformQUse6, 22:12, scratch95, 15:5); + s(EmcDllXformQUse7, 4:0, scratch95, 20:16); + s(EmcDllXformQUse7, 22:12, scratch95, 31:21); + s(EmcDllXformDq0, 4:0, scratch96, 4:0); + s(EmcDllXformDq0, 22:12, scratch96, 15:5); + s(EmcDllXformDq1, 4:0, scratch96, 20:16); + s(EmcDllXformDq1, 22:12, scratch96, 31:21); + s(EmcDllXformDq2, 4:0, scratch97, 4:0); + s(EmcDllXformDq2, 22:12, scratch97, 15:5); + s(EmcDllXformDq3, 4:0, scratch97, 20:16); + s(EmcDllXformDq3, 22:12, scratch97, 31:21); + s(EmcPreRefreshReqCnt, 15:0, scratch98, 15:0); + s(EmcDllXformAddr0, 4:0, scratch98, 20:16); + s(EmcDllXformAddr0, 22:12, scratch98, 31:21); + s(EmcDllXformAddr1, 4:0, scratch99, 4:0); + s(EmcDllXformAddr1, 22:12, scratch99, 15:5); + s(EmcDllXformAddr2, 4:0, scratch99, 20:16); + s(EmcDllXformAddr2, 22:12, scratch99, 31:21); + s(EmcDllXformAddr3, 4:0, scratch100, 4:0); + s(EmcDllXformAddr3, 22:12, scratch100, 15:5); + s(EmcDllXformAddr4, 4:0, scratch100, 20:16); + s(EmcDllXformAddr4, 22:12, scratch100, 31:21); + s(EmcDllXformAddr5, 4:0, scratch101, 4:0); + s(EmcDllXformAddr5, 22:12, scratch101, 15:5); + s(EmcPChg2Pden, 5:0, scratch102, 5:0); + s(EmcAct2Pden, 5:0, scratch102, 11:6); + s(EmcRw2Pden, 5:0, scratch102, 17:12); + s(EmcTcke, 5:0, scratch102, 23:18); + s(EmcTrpab, 5:0, scratch102, 29:24); + s(EmcFbioCfg5, 8:7, scratch102, 31:30); + s(EmcCtt, 5:0, scratch103, 5:0); + s(EmcEInput, 5:0, scratch103, 11:6); + s(EmcPutermExtra, 21:16, scratch103, 17:12); + s(EmcTckesr, 5:0, scratch103, 23:18); + s(EmcTpd, 5:0, scratch103, 29:24); + s(EmcFbioCfg5, 10:9, scratch103, 31:30); + s(EmcRdvMask, 5:0, scratch104, 5:0); + s(EmcXm2CmdPadCtrl4, 0:0, scratch104, 6:6); + s(EmcXm2CmdPadCtrl4, 2:2, scratch104, 7:7); + s(EmcXm2CmdPadCtrl4, 4:4, scratch104, 8:8); + s(EmcXm2CmdPadCtrl4, 6:6, scratch104, 9:9); + s(EmcXm2CmdPadCtrl4, 8:8, scratch104, 10:10); + s(EmcXm2CmdPadCtrl4, 10:10, scratch104, 11:11); + s(EmcQpop, 5:0, scratch104, 17:12); + s(McEmemArbTimingRcd, 5:0, scratch104, 23:18); + s(McEmemArbTimingRas, 5:0, scratch104, 29:24); + s(EmcFbioCfg5, 12:11, scratch104, 31:30); + s(McEmemArbTimingRap2Pre, 5:0, scratch105, 5:0); + s(McEmemArbTimingR2W, 5:0, scratch105, 11:6); + s(McEmemArbTimingW2R, 5:0, scratch105, 17:12); + s(EmcIbdly, 4:0, scratch105, 22:18); + s(McEmemArbTimingR2R, 4:0, scratch105, 27:23); + s(EmcW2w, 3:0, scratch105, 31:28); + s(McEmemArbTimingW2W, 4:0, scratch106, 4:0); + s(McEmemArbOverride, 27:27, scratch106, 5:5); + s(McEmemArbOverride, 26:26, scratch106, 6:6); + s(McEmemArbOverride, 16:16, scratch106, 7:7); + s(McEmemArbOverride, 10:10, scratch106, 8:8); + s(McEmemArbOverride, 4:4, scratch106, 9:9); + s(EmcWdvMask, 3:0, scratch106, 13:10); + s(EmcCttDuration, 3:0, scratch106, 17:14); + s(EmcQuseWidth, 3:0, scratch106, 21:18); + s(EmcPutermWidth, 3:0, scratch106, 25:22); + s(EmcBgbiasCtl0, 3:0, scratch106, 29:26); + s(EmcFbioCfg5, 25:24, scratch106, 31:30); + s(McEmemArbTimingRrd, 3:0, scratch107, 3:0); + s(EmcFbioCfg5, 23:20, scratch107, 10:7); + s(EmcFbioCfg5, 15:13, scratch107, 13:11); + s(EmcCfg2, 5:3, scratch107, 16:14); + s(EmcFbioCfg5, 26:26, scratch107, 17:17); + s(EmcFbioCfg5, 28:28, scratch107, 18:18); + s(EmcCfg2, 2:0, scratch107, 21:19); + s(EmcCfg2, 7:6, scratch107, 23:22); + s(EmcCfg2, 15:10, scratch107, 29:24); + s(EmcCfg2, 23:22, scratch107, 31:30); + s(EmcCfg2, 25:24, scratch108, 1:0); + s(EmcCfg2, 31:28, scratch108, 5:2); + s(BootRomPatchData, 31:0, scratch15, 31:0); + s(BootRomPatchControl, 31:0, scratch16, 31:0); + s(EmcDevSelect, 1:0, scratch17, 31:30); + s(EmcZcalWarmColdBootEnables, 1:0, scratch18, 31:30); + s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch19, 31:30); + s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch46, 30:30); + s(McClkenOverrideAllWarmBoot, 0:0, scratch46, 31:31); + s(EmcClkenOverrideAllWarmBoot, 0:0, scratch47, 30:30); + s(EmcMrsWarmBootEnable, 0:0, scratch47, 31:31); + s(EmcTimingControlWait, 7:0, scratch57, 27:20); + s(EmcZcalWarmBootWait, 7:0, scratch58, 27:20); + s(EmcAutoCalWait, 7:0, scratch59, 27:20); + s(WarmBootWait, 7:0, scratch60, 27:20); + s(EmcPinProgramWait, 7:0, scratch61, 27:20); + s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch79, 30:30); + s(EmcExtraRefreshNum, 2:0, scratch81, 31:29); + s(SwizzleRankByteEncode, 15:0, scratch101, 31:16); + s(MemoryType, 2:0, scratch107, 6:4); + + switch (sdram->MemoryType) { + case NvBootMemoryType_LpDdr2: + s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); + s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); + s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); + s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); + s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); + s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); + s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); + s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); + s(EmcMrw1, 7:0, scratch7, 7:0); + s(EmcMrw1, 23:16, scratch7, 15:8); + s(EmcMrw1, 27:26, scratch7, 17:16); + s(EmcMrw1, 31:30, scratch7, 19:18); + s(EmcMrw2, 7:0, scratch8, 7:0); + s(EmcMrw2, 23:16, scratch8, 15:8); + s(EmcMrw2, 27:26, scratch8, 17:16); + s(EmcMrw2, 31:30, scratch8, 19:18); + s(EmcMrw3, 7:0, scratch9, 7:0); + s(EmcMrw3, 23:16, scratch9, 15:8); + s(EmcMrw3, 27:26, scratch9, 17:16); + s(EmcMrw3, 31:30, scratch9, 19:18); + s(EmcMrw4, 7:0, scratch10, 7:0); + s(EmcMrw4, 23:16, scratch10, 15:8); + s(EmcMrw4, 27:26, scratch10, 17:16); + s(EmcMrw4, 31:30, scratch10, 19:18); + break; + case NvBootMemoryType_Ddr3: + s(EmcMrs, 13:0, scratch5, 13:0); + s(EmcEmrs, 13:0, scratch5, 27:14); + s(EmcMrs, 21:20, scratch5, 29:28); + s(EmcMrs, 31:30, scratch5, 31:30); + s(EmcEmrs2, 13:0, scratch7, 13:0); + s(EmcEmrs, 21:20, scratch7, 15:14); + s(EmcEmrs, 31:30, scratch7, 17:16); + s(EmcEmrs2, 21:20, scratch7, 19:18); + s(EmcEmrs3, 13:0, scratch8, 13:0); + s(EmcEmrs2, 31:30, scratch8, 15:14); + s(EmcEmrs3, 21:20, scratch8, 17:16); + s(EmcEmrs3, 31:30, scratch8, 19:18); + s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); + s(EmcWarmBootMrsExtra, 31:30, scratch9, 15:14); + s(EmcWarmBootMrsExtra, 21:20, scratch9, 17:16); + s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 19:18); + s(EmcMrs, 27:26, scratch10, 1:0); + s(EmcEmrs, 27:26, scratch10, 3:2); + s(EmcEmrs2, 27:26, scratch10, 5:4); + s(EmcEmrs3, 27:26, scratch10, 7:6); + s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); + s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); + s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); + s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); + c(0, scratch116, 31:0); + c(0, scratch117, 31:0); + break; + default: + printk(BIOS_CRIT, "ERROR: %s() unrecognized MemoryType %d!\n", + __func__, sdram->MemoryType); + } + + s(McVideoProtectGpuOverride0, 31:0, secure_scratch8, 31:0); + s(McVideoProtectVprOverride, 3:0, secure_scratch9, 3:0); + s(McVideoProtectVprOverride, 11:6, secure_scratch9, 9:4); + s(McVideoProtectVprOverride, 23:14, secure_scratch9, 19:10); + s(McVideoProtectVprOverride, 26:26, secure_scratch9, 20:20); + s(McVideoProtectVprOverride, 31:29, secure_scratch9, 23:21); + s(EmcFbioCfg5, 19:16, secure_scratch9, 27:24); + s(McDisplaySnapRing, 1:0, secure_scratch9, 29:28); + s(McDisplaySnapRing, 31:31, secure_scratch9, 30:30); + s(EmcAdrCfg, 0:0, secure_scratch9, 31:31); + s(McVideoProtectGpuOverride1, 15:0, secure_scratch10, 15:0); + s(McEmemAdrCfgBankMask0, 15:0, secure_scratch10, 31:16); + s(McEmemAdrCfgBankMask1, 15:0, secure_scratch11, 15:0); + s(McEmemAdrCfgBankMask2, 15:0, secure_scratch11, 31:16); + s(McEmemCfg, 13:0, secure_scratch12, 13:0); + s(McEmemCfg, 31:31, secure_scratch12, 14:14); + s(McVideoProtectBom, 31:20, secure_scratch12, 26:15); + s(McVideoProtectVprOverride1, 1:0, secure_scratch12, 28:27); + s(McVideoProtectVprOverride1, 4:4, secure_scratch12, 29:29); + s(McVideoProtectBomAdrHi, 1:0, secure_scratch12, 31:30); + s(McVideoProtectSizeMb, 11:0, secure_scratch13, 11:0); + s(McSecCarveoutBom, 31:20, secure_scratch13, 23:12); + s(McEmemAdrCfgBankSwizzle3, 2:0, secure_scratch13, 26:24); + s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 28:27); + s(McSecCarveoutAdrHi, 1:0, secure_scratch13, 30:29); + s(McEmemAdrCfg, 0:0, secure_scratch13, 31:31); + s(McSecCarveoutSizeMb, 11:0, secure_scratch14, 11:0); + s(McMtsCarveoutBom, 31:20, secure_scratch14, 23:12); + s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 25:24); + s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch14, 26:26); + s(McMtsCarveoutRegCtrl, 0:0, secure_scratch14, 27:27); + s(McMtsCarveoutSizeMb, 11:0, secure_scratch15, 11:0); + s(McEmemAdrCfgDev0, 2:0, secure_scratch15, 14:12); + s(McEmemAdrCfgDev0, 9:8, secure_scratch15, 16:15); + s(McEmemAdrCfgDev0, 19:16, secure_scratch15, 20:17); + s(McEmemAdrCfgDev1, 2:0, secure_scratch15, 23:21); + s(McEmemAdrCfgDev1, 9:8, secure_scratch15, 25:24); + s(McEmemAdrCfgDev1, 19:16, secure_scratch15, 29:26); + + /* Make sure all writes complete before we lock the secure_scratchs. */ + dmb(); + c(0x1555555, sec_disable2, 25:0); + c(0xff, sec_disable, 19:12); + + c(0, scratch2, 31:0); + m(pllm_base, 15:0, scratch2, 15:0); + m(pllm_base, 20:20, scratch2, 16:16); + m(pllm_misc2, 2:0, scratch2, 19:17); + c(0, scratch35, 31:0); + m(pllm_misc1, 23:0, scratch35, 23:0); + m(pllm_misc1, 30:28, scratch35, 30:28); + c(0, scratch3, 31:0); + s(PllMInputDivider, 7:0, scratch3, 7:0); + c(0x3e, scratch3, 15:8); + c(0, scratch3, 19:16); + s(PllMKVCO, 0:0, scratch3, 20:20); + s(PllMKCP, 1:0, scratch3, 22:21); + c(0, scratch36, 31:0); + s(PllMSetupControl, 23:0, scratch36, 23:0); + c(0, scratch4, 31:0); + s(PllMStableTime, 9:0, scratch4, 9:0); + s(PllMStableTime, 9:0, scratch4, 19:10); + + s(PllMSelectDiv2, 0:0, pllm_wb0_override2, 27:27); + s(PllMKVCO, 0:0, pllm_wb0_override2, 26:26); + s(PllMKCP, 1:0, pllm_wb0_override2, 25:24); + s(PllMSetupControl, 23:0, pllm_wb0_override2, 23:0); + s(PllMFeedbackDivider, 7:0, pllm_wb0_override_freq, 15:8); + s(PllMInputDivider, 7:0, pllm_wb0_override_freq, 7:0); + + /* Need to ensure override params are written before we activate it. */ + dmb(); + c(3, pllp_wb0_override, 12:11); +} diff --git a/src/soc/nvidia/tegra124/sdram_param.h b/src/soc/nvidia/tegra124/sdram_param.h index 1f05566..c845611 100644 --- a/src/soc/nvidia/tegra124/sdram_param.h +++ b/src/soc/nvidia/tegra124/sdram_param.h @@ -33,25 +33,27 @@ enum { /* Specifies the memory type to be undefined */ - MEMORY_TYPE_NONE = 0, + NvBootMemoryType_None = 0, /* Specifies the memory type to be DDR SDRAM */ - MEMORY_TYPE_DDR = 0, + NvBootMemoryType_Ddr = 0, /* Specifies the memory type to be LPDDR SDRAM */ - MEMORY_TYPE_LPDDR = 0, + NvBootMemoryType_LpDdr = 0, /* Specifies the memory type to be DDR2 SDRAM */ - MEMORY_TYPE_DDR2 = 0, + NvBootMemoryType_Ddr2 = 0, /* Specifies the memory type to be LPDDR2 SDRAM */ - MEMORY_TYPE_LPDDR2, + NvBootMemoryType_LpDdr2, /* Specifies the memory type to be DDR3 SDRAM */ - MEMORY_TYPE_DDR3, + NvBootMemoryType_Ddr3, - MEMORY_TYPE_NUM, - MEMORY_TYPE_FORCE32 = 0X7FFFFFF + NvBootMemoryType_Num, + + /* Specifies an entry in the ram_code table that's not in use */ + NvBootMemoryType_Unused = 0X7FFFFFF, }; enum { @@ -69,7 +71,7 @@ enum { struct sdram_params { /* Specifies the type of memory device */ - uint32_t memory_type; + uint32_t MemoryType; /* MC/EMC clock source configuration */ diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index e996c11..11a52c4 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -22,7 +22,8 @@ #include <console/console.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> -#include <soc/addressmap.h> +#include <soc/nvidia/tegra124/sdram.h> +#include <soc/display.h> /* this sucks, but for now, fb size/location are hardcoded. * Will break if we get 2. Sigh. @@ -30,10 +31,11 @@ */ static void soc_enable(device_t dev) { + u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; - u32 lcdbase = FB_BASE_MB; + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, - (CONFIG_DRAM_SIZE_MB - fb_size)*KiB); + (sdram_size_mb() - fb_size)*KiB); mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); }

1 0

New patch to review for coreboot: 4fb0077 arm: add missing gc-sections for ramstage
by Isaac Christensen 23 Sep '14

23 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6956 -gerrit commit 4fb007704a59bcce1a7d342afceb3cb80f213e4e Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Mon Sep 22 17:18:11 2014 -0600 arm: add missing gc-sections for ramstage This is a fix up for recent patch: c505837 arm: Have the linker garbage-collect unused functions and variables I missed adding --gc-sections to a couple of the ramstage lines. Change-Id: I81178eb99fddbd99c603c79ba506db51af975b27 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/arm/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 0c1cfc6..427e3a4 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -114,9 +114,9 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld + $(LD_ramstage) -m armelf_linux_eabi --gc-sections -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld else - $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld + $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld endif $(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage)

1 0

Patch set updated for coreboot: e781ae6 tegra/nyan*: sdram updates
by Isaac Christensen 23 Sep '14

23 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6949 -gerrit commit e781ae621bc50263f1342d0cbec152542831fa46 Author: Tom Warren <twarren(a)nvidia.com> Date: Thu Jan 23 13:37:50 2014 -0700 tegra/nyan*: sdram updates nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/Kconfig | 18 - src/mainboard/google/nyan/Makefile.inc | 1 + src/mainboard/google/nyan/bct/Makefile.inc | 6 +- src/mainboard/google/nyan/bct/cfg2inc.sh | 34 ++ src/mainboard/google/nyan/bct/sdram-792.cfg | 346 ----------- src/mainboard/google/nyan/bct/sdram-924.cfg | 346 ----------- .../google/nyan/bct/sdram-hynix-2GB-792.inc | 311 ++++++++++ .../google/nyan/bct/sdram-hynix-2GB-924.inc | 311 ++++++++++ src/mainboard/google/nyan/bct/sdram-unused.inc | 4 + src/mainboard/google/nyan/bootblock.c | 18 +- src/mainboard/google/nyan/romstage.c | 22 +- src/mainboard/google/nyan/sdram_configs.c | 58 ++ src/mainboard/google/nyan/sdram_configs.h | 28 + src/mainboard/google/nyan_big/Kconfig | 18 - src/mainboard/google/nyan_big/Makefile.inc | 1 + src/mainboard/google/nyan_big/bct/Makefile.inc | 6 +- src/mainboard/google/nyan_big/bct/sdram-792.cfg | 346 ----------- src/mainboard/google/nyan_big/bct/sdram-924.cfg | 346 ----------- .../google/nyan_big/bct/sdram-hynix-2GB-204.inc | 311 ++++++++++ .../google/nyan_big/bct/sdram-hynix-2GB-792.inc | 311 ++++++++++ .../google/nyan_big/bct/sdram-hynix-2GB-924.inc | 311 ++++++++++ .../google/nyan_big/bct/sdram-hynix-4GB-204.inc | 311 ++++++++++ .../google/nyan_big/bct/sdram-hynix-4GB-792.inc | 311 ++++++++++ src/mainboard/google/nyan_big/bct/sdram-unused.inc | 4 + src/mainboard/google/nyan_big/bct/spi.cfg | 18 + src/mainboard/google/nyan_big/boardid.c | 17 +- src/mainboard/google/nyan_big/bootblock.c | 18 +- src/mainboard/google/nyan_big/pmic.c | 5 +- src/mainboard/google/nyan_big/romstage.c | 22 +- src/mainboard/google/nyan_big/sdram_configs.c | 62 ++ src/mainboard/google/nyan_big/sdram_configs.h | 28 + src/soc/nvidia/tegra/dc.h | 3 + src/soc/nvidia/tegra/gpio.c | 53 ++ src/soc/nvidia/tegra/gpio.h | 1 + src/soc/nvidia/tegra124/Kconfig | 33 +- src/soc/nvidia/tegra124/Makefile.inc | 2 + src/soc/nvidia/tegra124/cbmem.c | 5 +- src/soc/nvidia/tegra124/display.c | 8 +- src/soc/nvidia/tegra124/include/soc/addressmap.h | 5 - src/soc/nvidia/tegra124/include/soc/display.h | 4 + src/soc/nvidia/tegra124/mc.h | 3 + src/soc/nvidia/tegra124/sdram.c | 30 + src/soc/nvidia/tegra124/sdram.h | 4 + src/soc/nvidia/tegra124/sdram_lp0.c | 633 +++++++++++++++++++++ src/soc/nvidia/tegra124/sdram_param.h | 20 +- src/soc/nvidia/tegra124/soc.c | 8 +- 46 files changed, 3259 insertions(+), 1502 deletions(-) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index f0cef6a..61a17b4 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -39,10 +39,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan" -config DRAM_SIZE_MB - int - default 2048 - config DRAM_DMA_START hex default 0x90000000 @@ -89,18 +85,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 -choice - prompt "BCT sdram configuration" - default NYAN_BCT_SDRAM_792 - help - The SDRAM configuration to put in the BCT. - -config NYAN_BCT_SDRAM_792 - bool "792 MHz" - -config NYAN_BCT_SDRAM_924 - bool "924 MHz" - -endchoice - endif # BOARD_GOOGLE_NYAN diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index e612af3..825b33e 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -32,6 +32,7 @@ bootblock-y += bootblock.c bootblock-y += pmic.c romstage-y += romstage.c +romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc index aacd89f..32490eb 100644 --- a/src/mainboard/google/nyan/bct/Makefile.inc +++ b/src/mainboard/google/nyan/bct/Makefile.inc @@ -20,5 +20,7 @@ bct-cfg-$(CONFIG_NYAN_BCT_CFG_EMMC) += emmc.cfg bct-cfg-$(CONFIG_NYAN_BCT_CFG_SPI) += spi.cfg bct-cfg-y += odmdata.cfg -bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_924) += sdram-924.cfg -bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_792) += sdram-792.cfg + +# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate +# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg". +# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage. diff --git a/src/mainboard/google/nyan/bct/cfg2inc.sh b/src/mainboard/google/nyan/bct/cfg2inc.sh new file mode 100755 index 0000000..6d0c7a8 --- /dev/null +++ b/src/mainboard/google/nyan/bct/cfg2inc.sh @@ -0,0 +1,34 @@ +#!/bin/sh +# +# This file is part of the coreboot project. +# +# Copyright 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +bct_cfg2inc() { + local in_file="$1" + local out_file="$2" + echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}" + # Note currently we can only handle DDR3 type memory, even in C + # implementation. + sed "/^#.*$/d; s/^SDRAM.0./ /; s/;$/,/;" \ + "${in_file}" >> "${out_file}" + echo "}," >>"${out_file}" +} + +for file in $@; do + echo "Generating $file => ${file%cfg}inc..." + bct_cfg2inc "${file}" "${file%cfg}inc" +done diff --git a/src/mainboard/google/nyan/bct/sdram-792.cfg b/src/mainboard/google/nyan/bct/sdram-792.cfg deleted file mode 100644 index d4d9660..0000000 --- a/src/mainboard/google/nyan/bct/sdram-792.cfg +++ /dev/null @@ -1,346 +0,0 @@ -# CFG Version 07 -# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command: -# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650 -# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg -# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz) -# bkv file: PM358/PM358_792MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x00000042; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430000; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000000; -SDRAM[0].EmcPinProgramWait = 0x00000001; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x00000025; -SDRAM[0].EmcRfc = 0x000000cd; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x00000019; -SDRAM[0].EmcRp = 0x0000000a; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000007; -SDRAM[0].EmcW2r = 0x0000000d; -SDRAM[0].EmcR2p = 0x00000004; -SDRAM[0].EmcW2p = 0x00000013; -SDRAM[0].EmcRdRcd = 0x0000000a; -SDRAM[0].EmcWrRcd = 0x0000000a; -SDRAM[0].EmcRrd = 0x00000003; -SDRAM[0].EmcRext = 0x00000002; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000006; -SDRAM[0].EmcWdvMask = 0x00000006; -SDRAM[0].EmcQUse = 0x0000000b; -SDRAM[0].EmcQuseWidth = 0x00000002; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000003; -SDRAM[0].EmcEInputDuration = 0x0000000c; -SDRAM[0].EmcPutermExtra = 0x00090000; -SDRAM[0].EmcPutermWidth = 0x00000004; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000002; -SDRAM[0].EmcQSafe = 0x00000011; -SDRAM[0].EmcRdv = 0x00000017; -SDRAM[0].EmcRdvMask = 0x00000019; -SDRAM[0].EmcQpop = 0x0000000f; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000004; -SDRAM[0].EmcRefresh = 0x000017eb; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa; -SDRAM[0].EmcPdEx2Wr = 0x00000003; -SDRAM[0].EmcPdEx2Rd = 0x00000003; -SDRAM[0].EmcPChg2Pden = 0x00000001; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x000000c7; -SDRAM[0].EmcRw2Pden = 0x00000018; -SDRAM[0].EmcTxsr = 0x000000d7; -SDRAM[0].EmcTxsrDll = 0x00000200; -SDRAM[0].EmcTcke = 0x00000005; -SDRAM[0].EmcTckesr = 0x00000006; -SDRAM[0].EmcTpd = 0x00000005; -SDRAM[0].EmcTfaw = 0x0000001d; -SDRAM[0].EmcTrpab = 0x00000000; -SDRAM[0].EmcTClkStable = 0x00000008; -SDRAM[0].EmcTClkStop = 0x00000008; -SDRAM[0].EmcTRefBw = 0x0000182c; -SDRAM[0].EmcFbioCfg5 = 0x104ab898; -SDRAM[0].EmcFbioCfg6 = 0x00000002; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x80001d71; -SDRAM[0].EmcEmrs = 0x80100002; -SDRAM[0].EmcEmrs2 = 0x80200018; -SDRAM[0].EmcEmrs3 = 0x80300000; -SDRAM[0].EmcMrw1 = 0x00000000; -SDRAM[0].EmcMrw2 = 0x00000000; -SDRAM[0].EmcMrw3 = 0x00000000; -SDRAM[0].EmcMrw4 = 0x00000000; -SDRAM[0].EmcMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x00000000; -SDRAM[0].EmcMrwResetNInitWait = 0x00000000; -SDRAM[0].EmcMrsWaitCnt = 0x00f7000e; -SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e; -SDRAM[0].EmcCfg = 0x73300000; -SDRAM[0].EmcCfg2 = 0x0000089d; -SDRAM[0].EmcCfgPipe = 0x000040a0; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x80003025; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00701b1; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000002; -SDRAM[0].EmcSelDpdCtrl = 0x00040000; -SDRAM[0].EmcDllXformDqs0 = 0x00000008; -SDRAM[0].EmcDllXformDqs1 = 0x00000008; -SDRAM[0].EmcDllXformDqs2 = 0x00000008; -SDRAM[0].EmcDllXformDqs3 = 0x00000008; -SDRAM[0].EmcDllXformDqs4 = 0x00000008; -SDRAM[0].EmcDllXformDqs5 = 0x00000008; -SDRAM[0].EmcDllXformDqs6 = 0x00000008; -SDRAM[0].EmcDllXformDqs7 = 0x00000008; -SDRAM[0].EmcDllXformDqs8 = 0x00000008; -SDRAM[0].EmcDllXformDqs9 = 0x00000008; -SDRAM[0].EmcDllXformDqs10 = 0x00000008; -SDRAM[0].EmcDllXformDqs11 = 0x00000008; -SDRAM[0].EmcDllXformDqs12 = 0x00000008; -SDRAM[0].EmcDllXformDqs13 = 0x00000008; -SDRAM[0].EmcDllXformDqs14 = 0x00000008; -SDRAM[0].EmcDllXformDqs15 = 0x00000008; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x0000000e; -SDRAM[0].EmcDllXformAddr1 = 0x0000000e; -SDRAM[0].EmcDllXformAddr2 = 0x00000000; -SDRAM[0].EmcDllXformAddr3 = 0x0000000e; -SDRAM[0].EmcDllXformAddr4 = 0x00000000; -SDRAM[0].EmcDllXformAddr5 = 0x00000000; -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; -SDRAM[0].EmcDllXformDq0 = 0x0000000b; -SDRAM[0].EmcDllXformDq1 = 0x0000000b; -SDRAM[0].EmcDllXformDq2 = 0x0000000b; -SDRAM[0].EmcDllXformDq3 = 0x0000000b; -SDRAM[0].EmcDllXformDq4 = 0x0000000b; -SDRAM[0].EmcDllXformDq5 = 0x0000000b; -SDRAM[0].EmcDllXformDq6 = 0x0000000b; -SDRAM[0].EmcDllXformDq7 = 0x0000000b; -SDRAM[0].WarmBootWait = 0x00000002; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00020000; -SDRAM[0].EmcZcalWaitCnt = 0x00000042; -SDRAM[0].EmcZcalMrwCmd = 0x80000000; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x80000011; -SDRAM[0].EmcZcalInitDev1 = 0x00000000; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x80001d71; -SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000002; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00002002; -SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x00000000; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; -SDRAM[0].EmcDsrVttgenDrv = 0x0505003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000000; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00000800; -SDRAM[0].McEmemArbCfg = 0x0e00000b; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000004; -SDRAM[0].McEmemArbTimingRp = 0x00000005; -SDRAM[0].McEmemArbTimingRc = 0x00000013; -SDRAM[0].McEmemArbTimingRas = 0x0000000c; -SDRAM[0].McEmemArbTimingFaw = 0x0000000f; -SDRAM[0].McEmemArbTimingRrd = 0x00000002; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c; -SDRAM[0].McEmemArbTimingR2R = 0x00000002; -SDRAM[0].McEmemArbTimingW2W = 0x00000002; -SDRAM[0].McEmemArbTimingR2W = 0x00000005; -SDRAM[0].McEmemArbTimingW2R = 0x00000008; -SDRAM[0].McEmemArbDaTurns = 0x08050202; -SDRAM[0].McEmemArbDaCovers = 0x00170e13; -SDRAM[0].McEmemArbMisc0 = 0x736c2414; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000000; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; -SDRAM[0].SwizzleRankByteEncode = 0x0000006f; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0xfff00000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c; diff --git a/src/mainboard/google/nyan/bct/sdram-924.cfg b/src/mainboard/google/nyan/bct/sdram-924.cfg deleted file mode 100644 index fa3271a..0000000 --- a/src/mainboard/google/nyan/bct/sdram-924.cfg +++ /dev/null @@ -1,346 +0,0 @@ -# CFG Version 11 -# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command: -# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650 -# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg -# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz) -# bkv file: PM358/PM358_924MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x0000004d; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430404; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000000; -SDRAM[0].EmcPinProgramWait = 0x00000001; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x0000002b; -SDRAM[0].EmcRfc = 0x000000ef; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x0000001e; -SDRAM[0].EmcRp = 0x0000000b; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000008; -SDRAM[0].EmcW2r = 0x0000000f; -SDRAM[0].EmcR2p = 0x00000005; -SDRAM[0].EmcW2p = 0x00000016; -SDRAM[0].EmcRdRcd = 0x0000000b; -SDRAM[0].EmcWrRcd = 0x0000000b; -SDRAM[0].EmcRrd = 0x00000004; -SDRAM[0].EmcRext = 0x00000002; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000006; -SDRAM[0].EmcWdvMask = 0x00000006; -SDRAM[0].EmcQUse = 0x0000000c; -SDRAM[0].EmcQuseWidth = 0x00000002; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000002; -SDRAM[0].EmcEInputDuration = 0x0000000e; -SDRAM[0].EmcPutermExtra = 0x000a0000; -SDRAM[0].EmcPutermWidth = 0x00000004; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000001; -SDRAM[0].EmcQSafe = 0x00000015; -SDRAM[0].EmcRdv = 0x0000001b; -SDRAM[0].EmcRdvMask = 0x0000001d; -SDRAM[0].EmcQpop = 0x00000010; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000004; -SDRAM[0].EmcRefresh = 0x00001be9; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa; -SDRAM[0].EmcPdEx2Wr = 0x00000004; -SDRAM[0].EmcPdEx2Rd = 0x00000015; -SDRAM[0].EmcPChg2Pden = 0x00000001; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x000000e6; -SDRAM[0].EmcRw2Pden = 0x0000001b; -SDRAM[0].EmcTxsr = 0x000000fa; -SDRAM[0].EmcTxsrDll = 0x00000200; -SDRAM[0].EmcTcke = 0x00000006; -SDRAM[0].EmcTckesr = 0x00000007; -SDRAM[0].EmcTpd = 0x00000006; -SDRAM[0].EmcTfaw = 0x00000022; -SDRAM[0].EmcTrpab = 0x00000000; -SDRAM[0].EmcTClkStable = 0x0000000a; -SDRAM[0].EmcTClkStop = 0x0000000a; -SDRAM[0].EmcTRefBw = 0x00001c29; -SDRAM[0].EmcFbioCfg5 = 0x104ab898; -SDRAM[0].EmcFbioCfg6 = 0x00000002; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x80000f15; -SDRAM[0].EmcEmrs = 0x80100002; -SDRAM[0].EmcEmrs2 = 0x80200020; -SDRAM[0].EmcEmrs3 = 0x80300000; -SDRAM[0].EmcMrw1 = 0x00000000; -SDRAM[0].EmcMrw2 = 0x00000000; -SDRAM[0].EmcMrw3 = 0x00000000; -SDRAM[0].EmcMrw4 = 0x00000000; -SDRAM[0].EmcMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x00000000; -SDRAM[0].EmcMrwResetNInitWait = 0x00000000; -SDRAM[0].EmcMrsWaitCnt = 0x00ce000e; -SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e; -SDRAM[0].EmcCfg = 0x73300000; -SDRAM[0].EmcCfg2 = 0x000008a5; -SDRAM[0].EmcCfgPipe = 0x00000000; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x800037ed; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00401b1; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000002; -SDRAM[0].EmcSelDpdCtrl = 0x00040000; -SDRAM[0].EmcDllXformDqs0 = 0x00000005; -SDRAM[0].EmcDllXformDqs1 = 0x00000005; -SDRAM[0].EmcDllXformDqs2 = 0x00000005; -SDRAM[0].EmcDllXformDqs3 = 0x00000005; -SDRAM[0].EmcDllXformDqs4 = 0x00000005; -SDRAM[0].EmcDllXformDqs5 = 0x00000005; -SDRAM[0].EmcDllXformDqs6 = 0x00000005; -SDRAM[0].EmcDllXformDqs7 = 0x00000005; -SDRAM[0].EmcDllXformDqs8 = 0x00000005; -SDRAM[0].EmcDllXformDqs9 = 0x00000005; -SDRAM[0].EmcDllXformDqs10 = 0x00000005; -SDRAM[0].EmcDllXformDqs11 = 0x00000005; -SDRAM[0].EmcDllXformDqs12 = 0x00000005; -SDRAM[0].EmcDllXformDqs13 = 0x00000005; -SDRAM[0].EmcDllXformDqs14 = 0x00000005; -SDRAM[0].EmcDllXformDqs15 = 0x00000005; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x0000400e; -SDRAM[0].EmcDllXformAddr1 = 0x0000400e; -SDRAM[0].EmcDllXformAddr2 = 0x00000000; -SDRAM[0].EmcDllXformAddr3 = 0x0000400e; -SDRAM[0].EmcDllXformAddr4 = 0x0000400e; -SDRAM[0].EmcDllXformAddr5 = 0x00000000; -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; -SDRAM[0].EmcDllXformDq0 = 0x00000006; -SDRAM[0].EmcDllXformDq1 = 0x00000006; -SDRAM[0].EmcDllXformDq2 = 0x00000006; -SDRAM[0].EmcDllXformDq3 = 0x00000006; -SDRAM[0].EmcDllXformDq4 = 0x00000006; -SDRAM[0].EmcDllXformDq5 = 0x00000006; -SDRAM[0].EmcDllXformDq6 = 0x00000006; -SDRAM[0].EmcDllXformDq7 = 0x00000006; -SDRAM[0].WarmBootWait = 0x00000002; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00020000; -SDRAM[0].EmcZcalWaitCnt = 0x0000004c; -SDRAM[0].EmcZcalMrwCmd = 0x80000000; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x80000011; -SDRAM[0].EmcZcalInitDev1 = 0x00000000; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x80000f15; -SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000002; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00002002; -SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x00000000; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; -SDRAM[0].EmcDsrVttgenDrv = 0x0606003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000000; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00000800; -SDRAM[0].McEmemArbCfg = 0x0e00000d; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000005; -SDRAM[0].McEmemArbTimingRp = 0x00000006; -SDRAM[0].McEmemArbTimingRc = 0x00000016; -SDRAM[0].McEmemArbTimingRas = 0x0000000e; -SDRAM[0].McEmemArbTimingFaw = 0x00000011; -SDRAM[0].McEmemArbTimingRrd = 0x00000002; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e; -SDRAM[0].McEmemArbTimingR2R = 0x00000002; -SDRAM[0].McEmemArbTimingW2W = 0x00000002; -SDRAM[0].McEmemArbTimingR2W = 0x00000006; -SDRAM[0].McEmemArbTimingW2R = 0x00000009; -SDRAM[0].McEmemArbDaTurns = 0x09060202; -SDRAM[0].McEmemArbDaCovers = 0x001a1016; -SDRAM[0].McEmemArbMisc0 = 0x734e2a17; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000000; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; -SDRAM[0].SwizzleRankByteEncode = 0x0000006f; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0xfff00000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; diff --git a/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc new file mode 100644 index 0000000..d175e7b --- /dev/null +++ b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x000000cd, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000019, + .EmcRp = 0x0000000a, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000007, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x0000000a, + .EmcWrRcd = 0x0000000a, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000003, + .EmcEInputDuration = 0x0000000c, + .EmcPutermExtra = 0x00090000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000002, + .EmcQSafe = 0x00000011, + .EmcRdv = 0x00000017, + .EmcRdvMask = 0x00000019, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017eb, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005fa, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000003, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000c7, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x000000d7, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x0000182c, + .EmcFbioCfg5 = 0x104ab898, + .EmcFbioCfg6 = 0x00000002, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80001d71, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200018, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00f7000e, + .EmcMrsWaitCnt2 = 0x00f7000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x000040a0, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003025, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00701b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0000000e, + .EmcDllXformAddr1 = 0x0000000e, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0000000e, + .EmcDllXformAddr4 = 0x00000000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x0000000b, + .EmcDllXformDq1 = 0x0000000b, + .EmcDllXformDq2 = 0x0000000b, + .EmcDllXformDq3 = 0x0000000b, + .EmcDllXformDq4 = 0x0000000b, + .EmcDllXformDq5 = 0x0000000b, + .EmcDllXformDq6 = 0x0000000b, + .EmcDllXformDq7 = 0x0000000b, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80001d71, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0020013d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000707, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x017fffff, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0505003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000005, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08050202, + .McEmemArbDaCovers = 0x00170e13, + .McEmemArbMisc0 = 0x736c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc new file mode 100644 index 0000000..e4d4faf --- /dev/null +++ b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x0000004d, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430404, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x0000002b, + .EmcRfc = 0x000000ef, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001e, + .EmcRp = 0x0000000b, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000f, + .EmcR2p = 0x00000005, + .EmcW2p = 0x00000016, + .EmcRdRcd = 0x0000000b, + .EmcWrRcd = 0x0000000b, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000c, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000e, + .EmcPutermExtra = 0x000a0000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000015, + .EmcRdv = 0x0000001b, + .EmcRdvMask = 0x0000001d, + .EmcQpop = 0x00000010, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x00001be9, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000006fa, + .EmcPdEx2Wr = 0x00000004, + .EmcPdEx2Rd = 0x00000015, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000e6, + .EmcRw2Pden = 0x0000001b, + .EmcTxsr = 0x000000fa, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000006, + .EmcTckesr = 0x00000007, + .EmcTpd = 0x00000006, + .EmcTfaw = 0x00000022, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x0000000a, + .EmcTClkStop = 0x0000000a, + .EmcTRefBw = 0x00001c29, + .EmcFbioCfg5 = 0x104ab898, + .EmcFbioCfg6 = 0x00000002, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80000f15, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200020, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00ce000e, + .EmcMrsWaitCnt2 = 0x00ce000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x000008a5, + .EmcCfgPipe = 0x00000000, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x800037ed, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00401b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000005, + .EmcDllXformDqs1 = 0x00000005, + .EmcDllXformDqs2 = 0x00000005, + .EmcDllXformDqs3 = 0x00000005, + .EmcDllXformDqs4 = 0x00000005, + .EmcDllXformDqs5 = 0x00000005, + .EmcDllXformDqs6 = 0x00000005, + .EmcDllXformDqs7 = 0x00000005, + .EmcDllXformDqs8 = 0x00000005, + .EmcDllXformDqs9 = 0x00000005, + .EmcDllXformDqs10 = 0x00000005, + .EmcDllXformDqs11 = 0x00000005, + .EmcDllXformDqs12 = 0x00000005, + .EmcDllXformDqs13 = 0x00000005, + .EmcDllXformDqs14 = 0x00000005, + .EmcDllXformDqs15 = 0x00000005, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0000400e, + .EmcDllXformAddr1 = 0x0000400e, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0000400e, + .EmcDllXformAddr4 = 0x0000400e, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00000006, + .EmcDllXformDq1 = 0x00000006, + .EmcDllXformDq2 = 0x00000006, + .EmcDllXformDq3 = 0x00000006, + .EmcDllXformDq4 = 0x00000006, + .EmcDllXformDq5 = 0x00000006, + .EmcDllXformDq6 = 0x00000006, + .EmcDllXformDq7 = 0x00000006, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x0000004c, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80000f15, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0020013d, + .EmcXm2DqsPadCtrl3 = 0x55555520, + .EmcXm2DqsPadCtrl4 = 0x003cf3cf, + .EmcXm2DqsPadCtrl5 = 0x003cf3cf, + .EmcXm2DqsPadCtrl6 = 0x55555500, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000303, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000d, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000005, + .McEmemArbTimingRp = 0x00000006, + .McEmemArbTimingRc = 0x00000016, + .McEmemArbTimingRas = 0x0000000e, + .McEmemArbTimingFaw = 0x00000011, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000004, + .McEmemArbTimingWap2Pre = 0x0000000e, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000009, + .McEmemArbDaTurns = 0x09060202, + .McEmemArbDaCovers = 0x001a1016, + .McEmemArbMisc0 = 0x734e2a17, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan/bct/sdram-unused.inc b/src/mainboard/google/nyan/bct/sdram-unused.inc new file mode 100644 index 0000000..bef63dc --- /dev/null +++ b/src/mainboard/google/nyan/bct/sdram-unused.inc @@ -0,0 +1,4 @@ +{ /* dummy. */ + .MemoryType = NvBootMemoryType_Unused, + 0, +}, diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index 0761aed..c168550 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -72,17 +72,19 @@ void bootblock_mainboard_init(void) pmic_init(4); /* SPI4 data out (MOSI) */ - pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, - PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG6_INDEX, + PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE | + PINMUX_PULL_UP); /* SPI4 data in (MISO) */ - pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, - PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG7_INDEX, + PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE | + PINMUX_PULL_UP); /* SPI4 clock */ - pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, - PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG5_INDEX, + PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE); /* SPI4 chip select 0 */ - pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, - PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PI3_INDEX, + PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); tegra_spi_init(4); } diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index ea40388..3eaf38c 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -25,15 +25,12 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include "sdram_configs.h" #include "soc/nvidia/tegra124/chip.h" +#include "soc/nvidia/tegra124/sdram.h" #include <soc/display.h> #include <timestamp.h> -// Convenient shorthand (in MB) -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ - enum { L2CTLR_ECC_PARITY = 0x1 << 21, L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, @@ -74,6 +71,7 @@ static void configure_l2actlr(void) void main(void) { + int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -97,12 +95,20 @@ void main(void) console_init(); exception_init(); + sdram_init(get_sdram_config()); + + /* used for MMU and CBMEM setup */ + dram_size_mb = sdram_size_mb(); + + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); - mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start, DCACHE_OFF); + mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); dcache_invalidate_all(); dcache_mmu_enable(); diff --git a/src/mainboard/google/nyan/sdram_configs.c b/src/mainboard/google/nyan/sdram_configs.c new file mode 100644 index 0000000..89e3361 --- /dev/null +++ b/src/mainboard/google/nyan/sdram_configs.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <soc/nvidia/tegra124/sdram.h> +#include "sdram_configs.h" + +static struct sdram_params sdram_configs[] = { +#include "bct/sdram-hynix-2GB-792.inc" /* ram_code = 0000 */ +#include "bct/sdram-unused.inc" /* ram_code = 0001 */ +#include "bct/sdram-unused.inc" /* ram_code = 0010 */ +#include "bct/sdram-unused.inc" /* ram_code = 0011 */ +#include "bct/sdram-unused.inc" /* ram_code = 0100 */ +#include "bct/sdram-unused.inc" /* ram_code = 0101 */ +#include "bct/sdram-unused.inc" /* ram_code = 0110 */ +#include "bct/sdram-unused.inc" /* ram_code = 0111 */ +#include "bct/sdram-unused.inc" /* ram_code = 1000 */ +#include "bct/sdram-unused.inc" /* ram_code = 1001 */ +#include "bct/sdram-unused.inc" /* ram_code = 1010 */ +#include "bct/sdram-unused.inc" /* ram_code = 1011 */ +#include "bct/sdram-unused.inc" /* ram_code = 1100 */ +#include "bct/sdram-unused.inc" /* ram_code = 1101 */ +#include "bct/sdram-unused.inc" /* ram_code = 1110 */ +#include "bct/sdram-unused.inc" /* ram_code = 1111 */ +}; + +const struct sdram_params *get_sdram_config() +{ + uint32_t ramcode = sdram_get_ram_code(); + /* + * If we need to apply some special hacks to RAMCODE mapping (ex, by + * board_id), do that now. + */ + + printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); + if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { + die("Invalid RAMCODE."); + } + + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/nyan/sdram_configs.h b/src/mainboard/google/nyan/sdram_configs.h new file mode 100644 index 0000000..e0ea1e2 --- /dev/null +++ b/src/mainboard/google/nyan/sdram_configs.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ +#define __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ + +#include <soc/nvidia/tegra124/sdram_param.h> + +/* Loads SDRAM configurations for current system. */ +const struct sdram_params *get_sdram_config(void); + +#endif /* __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ */ diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 4973667..6e24926 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan Big" -config DRAM_SIZE_MB - int - default 2048 - config DRAM_DMA_START hex default 0x90000000 @@ -90,18 +86,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 -choice - prompt "BCT sdram configuration" - default NYAN_BIG_BCT_SDRAM_792 - help - The SDRAM configuration to put in the BCT. - -config NYAN_BIG_BCT_SDRAM_792 - bool "792 MHz" - -config NYAN_BIG_BCT_SDRAM_924 - bool "924 MHz" - -endchoice - endif # BOARD_GOOGLE_NYAN_BIG diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index d4a8cdb..9cdff3b 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -32,6 +32,7 @@ bootblock-y += bootblock.c bootblock-y += pmic.c romstage-y += romstage.c +romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan_big/bct/Makefile.inc b/src/mainboard/google/nyan_big/bct/Makefile.inc index 65b87f0..09af378 100644 --- a/src/mainboard/google/nyan_big/bct/Makefile.inc +++ b/src/mainboard/google/nyan_big/bct/Makefile.inc @@ -20,5 +20,7 @@ bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_EMMC) += emmc.cfg bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_SPI) += spi.cfg bct-cfg-y += odmdata.cfg -bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_924) += sdram-924.cfg -bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_792) += sdram-792.cfg + +# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate +# the include files (sdram-*.inc). See ../../nyan/bct/Makefile.inc for more +# information. diff --git a/src/mainboard/google/nyan_big/bct/sdram-792.cfg b/src/mainboard/google/nyan_big/bct/sdram-792.cfg deleted file mode 100644 index d4d9660..0000000 --- a/src/mainboard/google/nyan_big/bct/sdram-792.cfg +++ /dev/null @@ -1,346 +0,0 @@ -# CFG Version 07 -# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command: -# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650 -# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg -# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz) -# bkv file: PM358/PM358_792MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x00000042; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430000; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000000; -SDRAM[0].EmcPinProgramWait = 0x00000001; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x00000025; -SDRAM[0].EmcRfc = 0x000000cd; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x00000019; -SDRAM[0].EmcRp = 0x0000000a; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000007; -SDRAM[0].EmcW2r = 0x0000000d; -SDRAM[0].EmcR2p = 0x00000004; -SDRAM[0].EmcW2p = 0x00000013; -SDRAM[0].EmcRdRcd = 0x0000000a; -SDRAM[0].EmcWrRcd = 0x0000000a; -SDRAM[0].EmcRrd = 0x00000003; -SDRAM[0].EmcRext = 0x00000002; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000006; -SDRAM[0].EmcWdvMask = 0x00000006; -SDRAM[0].EmcQUse = 0x0000000b; -SDRAM[0].EmcQuseWidth = 0x00000002; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000003; -SDRAM[0].EmcEInputDuration = 0x0000000c; -SDRAM[0].EmcPutermExtra = 0x00090000; -SDRAM[0].EmcPutermWidth = 0x00000004; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000002; -SDRAM[0].EmcQSafe = 0x00000011; -SDRAM[0].EmcRdv = 0x00000017; -SDRAM[0].EmcRdvMask = 0x00000019; -SDRAM[0].EmcQpop = 0x0000000f; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000004; -SDRAM[0].EmcRefresh = 0x000017eb; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa; -SDRAM[0].EmcPdEx2Wr = 0x00000003; -SDRAM[0].EmcPdEx2Rd = 0x00000003; -SDRAM[0].EmcPChg2Pden = 0x00000001; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x000000c7; -SDRAM[0].EmcRw2Pden = 0x00000018; -SDRAM[0].EmcTxsr = 0x000000d7; -SDRAM[0].EmcTxsrDll = 0x00000200; -SDRAM[0].EmcTcke = 0x00000005; -SDRAM[0].EmcTckesr = 0x00000006; -SDRAM[0].EmcTpd = 0x00000005; -SDRAM[0].EmcTfaw = 0x0000001d; -SDRAM[0].EmcTrpab = 0x00000000; -SDRAM[0].EmcTClkStable = 0x00000008; -SDRAM[0].EmcTClkStop = 0x00000008; -SDRAM[0].EmcTRefBw = 0x0000182c; -SDRAM[0].EmcFbioCfg5 = 0x104ab898; -SDRAM[0].EmcFbioCfg6 = 0x00000002; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x80001d71; -SDRAM[0].EmcEmrs = 0x80100002; -SDRAM[0].EmcEmrs2 = 0x80200018; -SDRAM[0].EmcEmrs3 = 0x80300000; -SDRAM[0].EmcMrw1 = 0x00000000; -SDRAM[0].EmcMrw2 = 0x00000000; -SDRAM[0].EmcMrw3 = 0x00000000; -SDRAM[0].EmcMrw4 = 0x00000000; -SDRAM[0].EmcMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x00000000; -SDRAM[0].EmcMrwResetNInitWait = 0x00000000; -SDRAM[0].EmcMrsWaitCnt = 0x00f7000e; -SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e; -SDRAM[0].EmcCfg = 0x73300000; -SDRAM[0].EmcCfg2 = 0x0000089d; -SDRAM[0].EmcCfgPipe = 0x000040a0; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x80003025; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00701b1; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000002; -SDRAM[0].EmcSelDpdCtrl = 0x00040000; -SDRAM[0].EmcDllXformDqs0 = 0x00000008; -SDRAM[0].EmcDllXformDqs1 = 0x00000008; -SDRAM[0].EmcDllXformDqs2 = 0x00000008; -SDRAM[0].EmcDllXformDqs3 = 0x00000008; -SDRAM[0].EmcDllXformDqs4 = 0x00000008; -SDRAM[0].EmcDllXformDqs5 = 0x00000008; -SDRAM[0].EmcDllXformDqs6 = 0x00000008; -SDRAM[0].EmcDllXformDqs7 = 0x00000008; -SDRAM[0].EmcDllXformDqs8 = 0x00000008; -SDRAM[0].EmcDllXformDqs9 = 0x00000008; -SDRAM[0].EmcDllXformDqs10 = 0x00000008; -SDRAM[0].EmcDllXformDqs11 = 0x00000008; -SDRAM[0].EmcDllXformDqs12 = 0x00000008; -SDRAM[0].EmcDllXformDqs13 = 0x00000008; -SDRAM[0].EmcDllXformDqs14 = 0x00000008; -SDRAM[0].EmcDllXformDqs15 = 0x00000008; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x0000000e; -SDRAM[0].EmcDllXformAddr1 = 0x0000000e; -SDRAM[0].EmcDllXformAddr2 = 0x00000000; -SDRAM[0].EmcDllXformAddr3 = 0x0000000e; -SDRAM[0].EmcDllXformAddr4 = 0x00000000; -SDRAM[0].EmcDllXformAddr5 = 0x00000000; -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; -SDRAM[0].EmcDllXformDq0 = 0x0000000b; -SDRAM[0].EmcDllXformDq1 = 0x0000000b; -SDRAM[0].EmcDllXformDq2 = 0x0000000b; -SDRAM[0].EmcDllXformDq3 = 0x0000000b; -SDRAM[0].EmcDllXformDq4 = 0x0000000b; -SDRAM[0].EmcDllXformDq5 = 0x0000000b; -SDRAM[0].EmcDllXformDq6 = 0x0000000b; -SDRAM[0].EmcDllXformDq7 = 0x0000000b; -SDRAM[0].WarmBootWait = 0x00000002; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00020000; -SDRAM[0].EmcZcalWaitCnt = 0x00000042; -SDRAM[0].EmcZcalMrwCmd = 0x80000000; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x80000011; -SDRAM[0].EmcZcalInitDev1 = 0x00000000; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x80001d71; -SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000002; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00002002; -SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x00000000; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; -SDRAM[0].EmcDsrVttgenDrv = 0x0505003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000000; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00000800; -SDRAM[0].McEmemArbCfg = 0x0e00000b; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000004; -SDRAM[0].McEmemArbTimingRp = 0x00000005; -SDRAM[0].McEmemArbTimingRc = 0x00000013; -SDRAM[0].McEmemArbTimingRas = 0x0000000c; -SDRAM[0].McEmemArbTimingFaw = 0x0000000f; -SDRAM[0].McEmemArbTimingRrd = 0x00000002; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c; -SDRAM[0].McEmemArbTimingR2R = 0x00000002; -SDRAM[0].McEmemArbTimingW2W = 0x00000002; -SDRAM[0].McEmemArbTimingR2W = 0x00000005; -SDRAM[0].McEmemArbTimingW2R = 0x00000008; -SDRAM[0].McEmemArbDaTurns = 0x08050202; -SDRAM[0].McEmemArbDaCovers = 0x00170e13; -SDRAM[0].McEmemArbMisc0 = 0x736c2414; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000000; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; -SDRAM[0].SwizzleRankByteEncode = 0x0000006f; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0xfff00000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c; diff --git a/src/mainboard/google/nyan_big/bct/sdram-924.cfg b/src/mainboard/google/nyan_big/bct/sdram-924.cfg deleted file mode 100644 index fa3271a..0000000 --- a/src/mainboard/google/nyan_big/bct/sdram-924.cfg +++ /dev/null @@ -1,346 +0,0 @@ -# CFG Version 11 -# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command: -# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650 -# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg -# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz) -# bkv file: PM358/PM358_924MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x0000004d; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430404; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000000; -SDRAM[0].EmcPinProgramWait = 0x00000001; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x0000002b; -SDRAM[0].EmcRfc = 0x000000ef; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x0000001e; -SDRAM[0].EmcRp = 0x0000000b; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000008; -SDRAM[0].EmcW2r = 0x0000000f; -SDRAM[0].EmcR2p = 0x00000005; -SDRAM[0].EmcW2p = 0x00000016; -SDRAM[0].EmcRdRcd = 0x0000000b; -SDRAM[0].EmcWrRcd = 0x0000000b; -SDRAM[0].EmcRrd = 0x00000004; -SDRAM[0].EmcRext = 0x00000002; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000006; -SDRAM[0].EmcWdvMask = 0x00000006; -SDRAM[0].EmcQUse = 0x0000000c; -SDRAM[0].EmcQuseWidth = 0x00000002; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000002; -SDRAM[0].EmcEInputDuration = 0x0000000e; -SDRAM[0].EmcPutermExtra = 0x000a0000; -SDRAM[0].EmcPutermWidth = 0x00000004; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000001; -SDRAM[0].EmcQSafe = 0x00000015; -SDRAM[0].EmcRdv = 0x0000001b; -SDRAM[0].EmcRdvMask = 0x0000001d; -SDRAM[0].EmcQpop = 0x00000010; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000004; -SDRAM[0].EmcRefresh = 0x00001be9; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa; -SDRAM[0].EmcPdEx2Wr = 0x00000004; -SDRAM[0].EmcPdEx2Rd = 0x00000015; -SDRAM[0].EmcPChg2Pden = 0x00000001; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x000000e6; -SDRAM[0].EmcRw2Pden = 0x0000001b; -SDRAM[0].EmcTxsr = 0x000000fa; -SDRAM[0].EmcTxsrDll = 0x00000200; -SDRAM[0].EmcTcke = 0x00000006; -SDRAM[0].EmcTckesr = 0x00000007; -SDRAM[0].EmcTpd = 0x00000006; -SDRAM[0].EmcTfaw = 0x00000022; -SDRAM[0].EmcTrpab = 0x00000000; -SDRAM[0].EmcTClkStable = 0x0000000a; -SDRAM[0].EmcTClkStop = 0x0000000a; -SDRAM[0].EmcTRefBw = 0x00001c29; -SDRAM[0].EmcFbioCfg5 = 0x104ab898; -SDRAM[0].EmcFbioCfg6 = 0x00000002; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x80000f15; -SDRAM[0].EmcEmrs = 0x80100002; -SDRAM[0].EmcEmrs2 = 0x80200020; -SDRAM[0].EmcEmrs3 = 0x80300000; -SDRAM[0].EmcMrw1 = 0x00000000; -SDRAM[0].EmcMrw2 = 0x00000000; -SDRAM[0].EmcMrw3 = 0x00000000; -SDRAM[0].EmcMrw4 = 0x00000000; -SDRAM[0].EmcMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x00000000; -SDRAM[0].EmcMrwResetNInitWait = 0x00000000; -SDRAM[0].EmcMrsWaitCnt = 0x00ce000e; -SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e; -SDRAM[0].EmcCfg = 0x73300000; -SDRAM[0].EmcCfg2 = 0x000008a5; -SDRAM[0].EmcCfgPipe = 0x00000000; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x800037ed; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00401b1; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000002; -SDRAM[0].EmcSelDpdCtrl = 0x00040000; -SDRAM[0].EmcDllXformDqs0 = 0x00000005; -SDRAM[0].EmcDllXformDqs1 = 0x00000005; -SDRAM[0].EmcDllXformDqs2 = 0x00000005; -SDRAM[0].EmcDllXformDqs3 = 0x00000005; -SDRAM[0].EmcDllXformDqs4 = 0x00000005; -SDRAM[0].EmcDllXformDqs5 = 0x00000005; -SDRAM[0].EmcDllXformDqs6 = 0x00000005; -SDRAM[0].EmcDllXformDqs7 = 0x00000005; -SDRAM[0].EmcDllXformDqs8 = 0x00000005; -SDRAM[0].EmcDllXformDqs9 = 0x00000005; -SDRAM[0].EmcDllXformDqs10 = 0x00000005; -SDRAM[0].EmcDllXformDqs11 = 0x00000005; -SDRAM[0].EmcDllXformDqs12 = 0x00000005; -SDRAM[0].EmcDllXformDqs13 = 0x00000005; -SDRAM[0].EmcDllXformDqs14 = 0x00000005; -SDRAM[0].EmcDllXformDqs15 = 0x00000005; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x0000400e; -SDRAM[0].EmcDllXformAddr1 = 0x0000400e; -SDRAM[0].EmcDllXformAddr2 = 0x00000000; -SDRAM[0].EmcDllXformAddr3 = 0x0000400e; -SDRAM[0].EmcDllXformAddr4 = 0x0000400e; -SDRAM[0].EmcDllXformAddr5 = 0x00000000; -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; -SDRAM[0].EmcDllXformDq0 = 0x00000006; -SDRAM[0].EmcDllXformDq1 = 0x00000006; -SDRAM[0].EmcDllXformDq2 = 0x00000006; -SDRAM[0].EmcDllXformDq3 = 0x00000006; -SDRAM[0].EmcDllXformDq4 = 0x00000006; -SDRAM[0].EmcDllXformDq5 = 0x00000006; -SDRAM[0].EmcDllXformDq6 = 0x00000006; -SDRAM[0].EmcDllXformDq7 = 0x00000006; -SDRAM[0].WarmBootWait = 0x00000002; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00020000; -SDRAM[0].EmcZcalWaitCnt = 0x0000004c; -SDRAM[0].EmcZcalMrwCmd = 0x80000000; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x80000011; -SDRAM[0].EmcZcalInitDev1 = 0x00000000; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x80000f15; -SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000002; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00002002; -SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x00000000; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; -SDRAM[0].EmcDsrVttgenDrv = 0x0606003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000000; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00000800; -SDRAM[0].McEmemArbCfg = 0x0e00000d; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000005; -SDRAM[0].McEmemArbTimingRp = 0x00000006; -SDRAM[0].McEmemArbTimingRc = 0x00000016; -SDRAM[0].McEmemArbTimingRas = 0x0000000e; -SDRAM[0].McEmemArbTimingFaw = 0x00000011; -SDRAM[0].McEmemArbTimingRrd = 0x00000002; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e; -SDRAM[0].McEmemArbTimingR2R = 0x00000002; -SDRAM[0].McEmemArbTimingW2W = 0x00000002; -SDRAM[0].McEmemArbTimingR2W = 0x00000006; -SDRAM[0].McEmemArbTimingW2R = 0x00000009; -SDRAM[0].McEmemArbDaTurns = 0x09060202; -SDRAM[0].McEmemArbDaCovers = 0x001a1016; -SDRAM[0].McEmemArbMisc0 = 0x734e2a17; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000000; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; -SDRAM[0].SwizzleRankByteEncode = 0x0000006f; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0xfff00000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-204.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-204.inc new file mode 100644 index 0000000..d75e0b5 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-204.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-204-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000022, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x40000002, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000009, + .EmcRfc = 0x00000035, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000007, + .EmcRp = 0x00000002, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000005, + .EmcW2r = 0x0000000a, + .EmcR2p = 0x00000003, + .EmcW2p = 0x0000000b, + .EmcRdRcd = 0x00000002, + .EmcWrRcd = 0x00000002, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000003, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000005, + .EmcWdvMask = 0x00000005, + .EmcQUse = 0x00000006, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000004, + .EmcEInputDuration = 0x00000006, + .EmcPutermExtra = 0x00010000, + .EmcPutermWidth = 0x00000003, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000003, + .EmcQSafe = 0x0000000d, + .EmcRdv = 0x0000000f, + .EmcRdvMask = 0x00000011, + .EmcQpop = 0x0000000a, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000003, + .EmcRefresh = 0x00000607, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x00000181, + .EmcPdEx2Wr = 0x00000002, + .EmcPdEx2Rd = 0x00000002, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x00000032, + .EmcRw2Pden = 0x0000000f, + .EmcTxsr = 0x00000038, + .EmcTxsrDll = 0x00000038, + .EmcTcke = 0x00000004, + .EmcTckesr = 0x00000005, + .EmcTpd = 0x00000004, + .EmcTfaw = 0x00000007, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000005, + .EmcTClkStop = 0x00000005, + .EmcTRefBw = 0x00000638, + .EmcFbioCfg5 = 0x106aa298, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80001221, + .EmcEmrs = 0x80100003, + .EmcEmrs2 = 0x80200008, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x000c000c, + .EmcMrsWaitCnt2 = 0x000c000c, + .EmcCfg = 0x73240000, + .EmcCfg2 = 0x0000088d, + .EmcCfgPipe = 0x0000d2b3, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80000d22, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0x002c00a0, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040008, + .EmcDllXformDqs0 = 0x00064000, + .EmcDllXformDqs1 = 0x00064000, + .EmcDllXformDqs2 = 0x00064000, + .EmcDllXformDqs3 = 0x00064000, + .EmcDllXformDqs4 = 0x00064000, + .EmcDllXformDqs5 = 0x00064000, + .EmcDllXformDqs6 = 0x00064000, + .EmcDllXformDqs7 = 0x00064000, + .EmcDllXformDqs8 = 0x00064000, + .EmcDllXformDqs9 = 0x00064000, + .EmcDllXformDqs10 = 0x00064000, + .EmcDllXformDqs11 = 0x00064000, + .EmcDllXformDqs12 = 0x00064000, + .EmcDllXformDqs13 = 0x00064000, + .EmcDllXformDqs14 = 0x00064000, + .EmcDllXformDqs15 = 0x00064000, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00000000, + .EmcDllXformAddr1 = 0x00000000, + .EmcDllXformAddr2 = 0x00004000, + .EmcDllXformAddr3 = 0x00000000, + .EmcDllXformAddr4 = 0x00000000, + .EmcDllXformAddr5 = 0x00004000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00090000, + .EmcDllXformDq1 = 0x00090000, + .EmcDllXformDq2 = 0x00094000, + .EmcDllXformDq3 = 0x00094000, + .EmcDllXformDq4 = 0x00009400, + .EmcDllXformDq5 = 0x00009000, + .EmcDllXformDq6 = 0x00009000, + .EmcDllXformDq7 = 0x00009000, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000003, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000002, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80001221, + .EmcWarmBootMrsExtra = 0x80100003, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x10000280, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0130b118, + .EmcXm2DqsPadCtrl3 = 0x51451400, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x51451400, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc081, + .EmcXm2ClkPadCtrl2 = 0x00000303, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x0000003f, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0000003f, + .EmcTxdsrvttgen = 0x00000066, + .EmcBgbiasCtl0 = 0x00000008, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x01000003, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000001, + .McEmemArbTimingRp = 0x00000001, + .McEmemArbTimingRc = 0x00000005, + .McEmemArbTimingRas = 0x00000002, + .McEmemArbTimingFaw = 0x00000004, + .McEmemArbTimingRrd = 0x00000001, + .McEmemArbTimingRap2Pre = 0x00000002, + .McEmemArbTimingWap2Pre = 0x00000008, + .McEmemArbTimingR2R = 0x00000003, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000004, + .McEmemArbTimingW2R = 0x00000006, + .McEmemArbDaTurns = 0x06040203, + .McEmemArbDaCovers = 0x000a0405, + .McEmemArbMisc0 = 0x73840a06, + .McEmemArbMisc1 = 0x70000f03, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc new file mode 100644 index 0000000..3020002 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x000000cc, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000009, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000c6, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x000000d6, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80000d71, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200018, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00f8000c, + .EmcMrsWaitCnt2 = 0x00f8000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00034000, + .EmcDllXformAddr1 = 0x00034000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x00034000, + .EmcDllXformAddr4 = 0x00034000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000009, + .EmcDliTrimTxDqs4 = 0x00000009, + .EmcDliTrimTxDqs5 = 0x00000007, + .EmcDliTrimTxDqs6 = 0x00000009, + .EmcDliTrimTxDqs7 = 0x00000008, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000009, + .EmcDliTrimTxDqs12 = 0x00000009, + .EmcDliTrimTxDqs13 = 0x00000007, + .EmcDliTrimTxDqs14 = 0x00000009, + .EmcDliTrimTxDqs15 = 0x00000008, + .EmcDllXformDq0 = 0x0000000e, + .EmcDllXformDq1 = 0x0000000e, + .EmcDllXformDq2 = 0x0000000e, + .EmcDllXformDq3 = 0x0000000e, + .EmcDllXformDq4 = 0x0000000e, + .EmcDllXformDq5 = 0x0000000e, + .EmcDllXformDq6 = 0x0000000e, + .EmcDllXformDq7 = 0x0000000e, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80000d71, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000101, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00160d13, + .McEmemArbMisc0 = 0x734c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-924.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-924.inc new file mode 100644 index 0000000..e4d4faf --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-924.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x0000004d, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430404, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x0000002b, + .EmcRfc = 0x000000ef, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001e, + .EmcRp = 0x0000000b, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000f, + .EmcR2p = 0x00000005, + .EmcW2p = 0x00000016, + .EmcRdRcd = 0x0000000b, + .EmcWrRcd = 0x0000000b, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000c, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000e, + .EmcPutermExtra = 0x000a0000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000015, + .EmcRdv = 0x0000001b, + .EmcRdvMask = 0x0000001d, + .EmcQpop = 0x00000010, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x00001be9, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000006fa, + .EmcPdEx2Wr = 0x00000004, + .EmcPdEx2Rd = 0x00000015, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000e6, + .EmcRw2Pden = 0x0000001b, + .EmcTxsr = 0x000000fa, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000006, + .EmcTckesr = 0x00000007, + .EmcTpd = 0x00000006, + .EmcTfaw = 0x00000022, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x0000000a, + .EmcTClkStop = 0x0000000a, + .EmcTRefBw = 0x00001c29, + .EmcFbioCfg5 = 0x104ab898, + .EmcFbioCfg6 = 0x00000002, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80000f15, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200020, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00ce000e, + .EmcMrsWaitCnt2 = 0x00ce000e, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x000008a5, + .EmcCfgPipe = 0x00000000, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x800037ed, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00401b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000005, + .EmcDllXformDqs1 = 0x00000005, + .EmcDllXformDqs2 = 0x00000005, + .EmcDllXformDqs3 = 0x00000005, + .EmcDllXformDqs4 = 0x00000005, + .EmcDllXformDqs5 = 0x00000005, + .EmcDllXformDqs6 = 0x00000005, + .EmcDllXformDqs7 = 0x00000005, + .EmcDllXformDqs8 = 0x00000005, + .EmcDllXformDqs9 = 0x00000005, + .EmcDllXformDqs10 = 0x00000005, + .EmcDllXformDqs11 = 0x00000005, + .EmcDllXformDqs12 = 0x00000005, + .EmcDllXformDqs13 = 0x00000005, + .EmcDllXformDqs14 = 0x00000005, + .EmcDllXformDqs15 = 0x00000005, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0000400e, + .EmcDllXformAddr1 = 0x0000400e, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0000400e, + .EmcDllXformAddr4 = 0x0000400e, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00000006, + .EmcDllXformDq1 = 0x00000006, + .EmcDllXformDq2 = 0x00000006, + .EmcDllXformDq3 = 0x00000006, + .EmcDllXformDq4 = 0x00000006, + .EmcDllXformDq5 = 0x00000006, + .EmcDllXformDq6 = 0x00000006, + .EmcDllXformDq7 = 0x00000006, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x0000004c, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80000f15, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0020013d, + .EmcXm2DqsPadCtrl3 = 0x55555520, + .EmcXm2DqsPadCtrl4 = 0x003cf3cf, + .EmcXm2DqsPadCtrl5 = 0x003cf3cf, + .EmcXm2DqsPadCtrl6 = 0x55555500, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000303, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000d, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000005, + .McEmemArbTimingRp = 0x00000006, + .McEmemArbTimingRc = 0x00000016, + .McEmemArbTimingRas = 0x0000000e, + .McEmemArbTimingFaw = 0x00000011, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000004, + .McEmemArbTimingWap2Pre = 0x0000000e, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000009, + .McEmemArbDaTurns = 0x09060202, + .McEmemArbDaCovers = 0x001a1016, + .McEmemArbMisc0 = 0x734e2a17, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-204.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-204.inc new file mode 100644 index 0000000..2feede7 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-204.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0100-204-4GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000022, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x40000002, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000009, + .EmcRfc = 0x00000047, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x00000007, + .EmcRp = 0x00000002, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000005, + .EmcW2r = 0x0000000a, + .EmcR2p = 0x00000003, + .EmcW2p = 0x0000000b, + .EmcRdRcd = 0x00000002, + .EmcWrRcd = 0x00000002, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000003, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000005, + .EmcWdvMask = 0x00000005, + .EmcQUse = 0x00000006, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000004, + .EmcEInputDuration = 0x00000006, + .EmcPutermExtra = 0x00010000, + .EmcPutermWidth = 0x00000003, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000003, + .EmcQSafe = 0x0000000d, + .EmcRdv = 0x0000000f, + .EmcRdvMask = 0x00000011, + .EmcQpop = 0x0000000a, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000003, + .EmcRefresh = 0x00000607, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x00000181, + .EmcPdEx2Wr = 0x00000002, + .EmcPdEx2Rd = 0x00000002, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x00000044, + .EmcRw2Pden = 0x0000000f, + .EmcTxsr = 0x0000004a, + .EmcTxsrDll = 0x0000004a, + .EmcTcke = 0x00000004, + .EmcTckesr = 0x00000005, + .EmcTpd = 0x00000004, + .EmcTfaw = 0x00000007, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000005, + .EmcTClkStop = 0x00000005, + .EmcTRefBw = 0x00000638, + .EmcFbioCfg5 = 0x106aa298, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00001221, + .EmcEmrs = 0x00100003, + .EmcEmrs2 = 0x00200008, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x000c000c, + .EmcMrsWaitCnt2 = 0x000c000c, + .EmcCfg = 0x73240000, + .EmcCfg2 = 0x0000088d, + .EmcCfgPipe = 0x0000d2b3, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80000d22, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0x002c00a0, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040008, + .EmcDllXformDqs0 = 0x00064000, + .EmcDllXformDqs1 = 0x00064000, + .EmcDllXformDqs2 = 0x00064000, + .EmcDllXformDqs3 = 0x00064000, + .EmcDllXformDqs4 = 0x00064000, + .EmcDllXformDqs5 = 0x00064000, + .EmcDllXformDqs6 = 0x00064000, + .EmcDllXformDqs7 = 0x00064000, + .EmcDllXformDqs8 = 0x00064000, + .EmcDllXformDqs9 = 0x00064000, + .EmcDllXformDqs10 = 0x00064000, + .EmcDllXformDqs11 = 0x00064000, + .EmcDllXformDqs12 = 0x00064000, + .EmcDllXformDqs13 = 0x00064000, + .EmcDllXformDqs14 = 0x00064000, + .EmcDllXformDqs15 = 0x00064000, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00000000, + .EmcDllXformAddr1 = 0x00000000, + .EmcDllXformAddr2 = 0x00004000, + .EmcDllXformAddr3 = 0x00000000, + .EmcDllXformAddr4 = 0x00000000, + .EmcDllXformAddr5 = 0x00004000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000000, + .EmcDliTrimTxDqs1 = 0x00000000, + .EmcDliTrimTxDqs2 = 0x00000000, + .EmcDliTrimTxDqs3 = 0x00000000, + .EmcDliTrimTxDqs4 = 0x00000000, + .EmcDliTrimTxDqs5 = 0x00000000, + .EmcDliTrimTxDqs6 = 0x00000000, + .EmcDliTrimTxDqs7 = 0x00000000, + .EmcDliTrimTxDqs8 = 0x00000000, + .EmcDliTrimTxDqs9 = 0x00000000, + .EmcDliTrimTxDqs10 = 0x00000000, + .EmcDliTrimTxDqs11 = 0x00000000, + .EmcDliTrimTxDqs12 = 0x00000000, + .EmcDliTrimTxDqs13 = 0x00000000, + .EmcDliTrimTxDqs14 = 0x00000000, + .EmcDliTrimTxDqs15 = 0x00000000, + .EmcDllXformDq0 = 0x00090000, + .EmcDllXformDq1 = 0x00090000, + .EmcDllXformDq2 = 0x00094000, + .EmcDllXformDq3 = 0x00094000, + .EmcDllXformDq4 = 0x00009400, + .EmcDllXformDq5 = 0x00009000, + .EmcDllXformDq6 = 0x00009000, + .EmcDllXformDq7 = 0x00009000, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000003, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000002, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00001221, + .EmcWarmBootMrsExtra = 0x00100003, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x10000280, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0130b118, + .EmcXm2DqsPadCtrl3 = 0x51451400, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x51451400, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc081, + .EmcXm2ClkPadCtrl2 = 0x00000303, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x0000003f, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0000003f, + .EmcTxdsrvttgen = 0x00000066, + .EmcBgbiasCtl0 = 0x00000008, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x01000003, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000001, + .McEmemArbTimingRp = 0x00000001, + .McEmemArbTimingRc = 0x00000005, + .McEmemArbTimingRas = 0x00000002, + .McEmemArbTimingFaw = 0x00000004, + .McEmemArbTimingRrd = 0x00000001, + .McEmemArbTimingRap2Pre = 0x00000002, + .McEmemArbTimingWap2Pre = 0x00000008, + .McEmemArbTimingR2R = 0x00000003, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000004, + .McEmemArbTimingW2R = 0x00000006, + .McEmemArbDaTurns = 0x06040203, + .McEmemArbDaCovers = 0x000a0405, + .McEmemArbMisc0 = 0x74a40a06, + .McEmemArbMisc1 = 0x70000f03, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc new file mode 100644 index 0000000..5c8d09c --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from sdram-0100-792-4GB.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x00000114, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000007, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000003, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x0000010d, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x0000011e, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00000d71, + .EmcEmrs = 0x00100002, + .EmcEmrs2 = 0x00200018, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x006f000c, + .EmcMrsWaitCnt2 = 0x006f000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00034000, + .EmcDllXformAddr1 = 0x00034000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x00034000, + .EmcDllXformAddr4 = 0x00034000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000009, + .EmcDliTrimTxDqs4 = 0x00000009, + .EmcDliTrimTxDqs5 = 0x00000007, + .EmcDliTrimTxDqs6 = 0x00000009, + .EmcDliTrimTxDqs7 = 0x00000008, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000009, + .EmcDliTrimTxDqs12 = 0x00000009, + .EmcDliTrimTxDqs13 = 0x00000007, + .EmcDliTrimTxDqs14 = 0x00000009, + .EmcDliTrimTxDqs15 = 0x00000008, + .EmcDllXformDq0 = 0x0000000e, + .EmcDllXformDq1 = 0x0000000e, + .EmcDllXformDq2 = 0x0000000e, + .EmcDllXformDq3 = 0x0000000e, + .EmcDllXformDq4 = 0x0000000e, + .EmcDllXformDq5 = 0x0000000e, + .EmcDllXformDq6 = 0x0000000e, + .EmcDllXformDq7 = 0x0000000e, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00000d71, + .EmcWarmBootMrsExtra = 0x00100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000101, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000004, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00150c13, + .McEmemArbMisc0 = 0x746c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/bct/sdram-unused.inc b/src/mainboard/google/nyan_big/bct/sdram-unused.inc new file mode 100644 index 0000000..bef63dc --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-unused.inc @@ -0,0 +1,4 @@ +{ /* dummy. */ + .MemoryType = NvBootMemoryType_Unused, + 0, +}, diff --git a/src/mainboard/google/nyan_big/bct/spi.cfg b/src/mainboard/google/nyan_big/bct/spi.cfg index aef7e82..e9f85d5 100644 --- a/src/mainboard/google/nyan_big/bct/spi.cfg +++ b/src/mainboard/google/nyan_big/bct/spi.cfg @@ -14,3 +14,21 @@ DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; +DevType[1] = NvBootDevType_Spi; +DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[1].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0; + +DevType[2] = NvBootDevType_Spi; +DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[2].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0; + +DevType[3] = NvBootDevType_Spi; +DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0; + diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index f43e532..23b1c6a 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <soc/nvidia/tegra124/gpio.h> +#include <stdlib.h> #include "boardid.h" @@ -27,11 +28,17 @@ uint8_t board_id(void) static int id = -1; if (id < 0) { - id = gpio_get_in_value(GPIO(Q3)) << 0 | - gpio_get_in_value(GPIO(T1)) << 1 | - gpio_get_in_value(GPIO(X1)) << 2 | - gpio_get_in_value(GPIO(X4)) << 3; - printk(BIOS_SPEW, "Board ID: %#x.\n", id); + gpio_t gpio[] = {GPIO(Q3), GPIO(T1), GPIO(X1), GPIO(X4)}; + int value[ARRAY_SIZE(gpio)]; + + gpio_get_in_tristate_values(gpio, ARRAY_SIZE(gpio), value); + + /* A gpio state is encoded in every two-bit */ + id = value[0] << 0 | + value[1] << 2 | + value[2] << 4 | + value[3] << 6; + printk(BIOS_SPEW, "Board TRISTATE ID: %#x.\n", id); } return id; diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c index f07951a..e88765f 100644 --- a/src/mainboard/google/nyan_big/bootblock.c +++ b/src/mainboard/google/nyan_big/bootblock.c @@ -72,17 +72,19 @@ void bootblock_mainboard_init(void) pmic_init(4); /* SPI4 data out (MOSI) */ - pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, - PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG6_INDEX, + PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE | + PINMUX_PULL_UP); /* SPI4 data in (MISO) */ - pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, - PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG7_INDEX, + PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE | + PINMUX_PULL_UP); /* SPI4 clock */ - pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, - PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PG5_INDEX, + PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE); /* SPI4 chip select 0 */ - pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, - PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + pinmux_set_config(PINMUX_GPIO_PI3_INDEX, + PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); tegra_spi_init(4); } diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index f64b59c..89e1f87 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -83,10 +83,7 @@ void pmic_init(unsigned bus) pmic_slam_defaults(bus); /* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */ - if (board_id() == 0) - pmic_write_reg(bus, 0x00, 0x3c); - else - pmic_write_reg(bus, 0x00, 0x50); + pmic_write_reg(bus, 0x00, 0x50); /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */ pmic_write_reg(bus, 0x06, 0x28); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 0e71020..80eea77 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -25,15 +25,12 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include "sdram_configs.h" #include "soc/nvidia/tegra124/chip.h" +#include "soc/nvidia/tegra124/sdram.h" #include <soc/display.h> #include <timestamp.h> -// Convenient shorthand (in MB) -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ - enum { L2CTLR_ECC_PARITY = 0x1 << 21, L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, @@ -74,6 +71,7 @@ static void configure_l2actlr(void) void main(void) { + int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -97,12 +95,20 @@ void main(void) console_init(); exception_init(); + sdram_init(get_sdram_config()); + + /* used for MMU and CBMEM setup */ + dram_size_mb = sdram_size_mb(); + + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); - mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start, DCACHE_OFF); + mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); dcache_invalidate_all(); dcache_mmu_enable(); diff --git a/src/mainboard/google/nyan_big/sdram_configs.c b/src/mainboard/google/nyan_big/sdram_configs.c new file mode 100644 index 0000000..2aaace4 --- /dev/null +++ b/src/mainboard/google/nyan_big/sdram_configs.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <soc/nvidia/tegra124/sdram.h> +#include "sdram_configs.h" + +/* + * Note for board bring up, we've temporarily filled SDRAM table with + * hynix-2GB-204 configuration (except the hynix-4GB-204 entry for 0100). + */ +static struct sdram_params sdram_configs[] = { +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0000 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0001 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0010 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0011 */ +#include "bct/sdram-hynix-4GB-204.inc" /* ram_code = 0100 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0101 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0110 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0111 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1000 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1001 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1010 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1011 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1100 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1101 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1110 */ +#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1111 */ +}; + +const struct sdram_params *get_sdram_config() +{ + uint32_t ramcode = sdram_get_ram_code(); + /* + * If we need to apply some special hacks to RAMCODE mapping (ex, by + * board_id), do that now. + */ + + printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); + if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { + die("Invalid RAMCODE."); + } + + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/nyan_big/sdram_configs.h b/src/mainboard/google/nyan_big/sdram_configs.h new file mode 100644 index 0000000..4bf376c --- /dev/null +++ b/src/mainboard/google/nyan_big/sdram_configs.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ +#define __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ + +#include <soc/nvidia/tegra124/sdram_param.h> + +/* Loads SDRAM configurations for current system. */ +const struct sdram_params *get_sdram_config(void); + +#endif /* __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ */ diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 7a38adf..48ffbda 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -569,4 +569,7 @@ struct disp_ctl_win { void display_startup(device_t dev); void dp_bringup(u32 winb_addr); + +unsigned int fb_base_mb(void); + #endif /* __SOC_NVIDIA_TEGRA_DC_H */ diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 4cf6d5f..ac0fc3f 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -22,6 +22,7 @@ #include <soc/addressmap.h> #include <stddef.h> #include <stdint.h> +#include <delay.h> #include "gpio.h" #include "pinmux.h" @@ -174,6 +175,58 @@ int gpio_get_in_value(gpio_t gpio) return (port & (1 << bit)) != 0; } +int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int value[]) +{ + /* + * GPIOs which are tied to stronger external pull up or pull down + * will stay there regardless of the internal pull up or pull + * down setting. + * + * GPIOs which are floating will go to whatever level they're + * internally pulled to. + */ + + int temp; + int index; + + /* Enable internal pull up */ + for (index = 0; index < num_gpio; ++index) + gpio_input_pullup(gpio[index]); + + /* Wait until signals become stable */ + udelay(10); + + /* Get gpio values at internal pull up */ + for (index = 0; index < num_gpio; ++index) + value[index] = gpio_get_in_value(gpio[index]); + + /* Enable internal pull down */ + for (index = 0; index < num_gpio; ++index) + gpio_input_pulldown(gpio[index]); + + /* Wait until signals become stable */ + udelay(10); + + /* + * Get gpio values at internal pull down. + * Compare with gpio pull up value and then + * determine a gpio final value/state: + * 0: pull down + * 1: pull up + * 2: floating + */ + for (index = 0; index < num_gpio; ++index) { + temp = gpio_get_in_value(gpio[index]); + value[index] = ((value[index] ^ temp) << 1) | temp; + } + + /* Disable pull up / pull down to conserve power */ + for (index = 0; index < num_gpio; ++index) + gpio_input(gpio[index]); + + return 0; +} + int gpio_get_int_status(gpio_t gpio) { int bit = gpio % GPIO_GPIOS_PER_PORT; diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index 70c1026..5f6833a 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -81,6 +81,7 @@ void gpio_set_out_value(gpio_t gpio, int value); int gpio_get_out_value(gpio_t gpio); int gpio_get_in_value(gpio_t gpio); +int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int value[]); int gpio_get_int_status(gpio_t gpio); diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index ec6ee92..3876a9e 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -26,17 +26,15 @@ config BOOTBLOCK_CPU_INIT # 0x18080 Free for CBFS data. # # iRAM (256k) layout. -# 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM. -# +0000 (BootROM) Boot Information Table. -# +0100 (BootROM) BCT. -# --------------------------------------------------------------------- -# +0000 (Coreboot) TTB 16KB. -# +4000 (Coreboot) Stack. -# 0x4000_E000 Valid for anything to be executed after BootROM (effective entry -# point address specified in BCT). -# +0000 (Coreboot) Bootblock (max 36k). -# +9000 (Coreboot) ROM stage (max 36k). -# 0x4002_0000 (Coreboot) Cache of CBFS. +# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, +# so the bootblock loading address must be placed after that. After the +# handoff that area may be reclaimed for other uses, e.g. CBFS cache.) +# +# 0x4000_0000 TTB (16KB). +# 0x4000_4000 CBFS mapping cache (96KB). +# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!). +# 0x4002_0000 Bootblock (max 48KB). +# 0x4002_C000 ROM stage (max 80KB). # 0x4003_FFFF End of iRAM. config BOOTBLOCK_ROM_OFFSET @@ -57,11 +55,11 @@ config SYS_SDRAM_BASE config BOOTBLOCK_BASE hex - default 0x4000e000 + default 0x40020000 config ROMSTAGE_BASE hex - default 0x40017000 + default 0x4002c000 config RAMSTAGE_BASE hex @@ -69,12 +67,13 @@ config RAMSTAGE_BASE config STACK_TOP hex - default 0x4000c000 + default 0x40020000 config STACK_BOTTOM hex - default 0x40004000 + default 0x4001c000 +# This is the ramstage thread stack, *not* the same as above! Currently unused. config STACK_SIZE hex default 0x800 @@ -86,10 +85,10 @@ config TTB_BUFFER config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" - default 0x40020000 + default 0x40004000 config CBFS_CACHE_SIZE hex "size of CBFS cache data" - default 0x00020000 + default 0x00018000 endif diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 7a6bced..4ba2342 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += dma.c romstage-y += i2c.c romstage-y += monotonic_timer.c romstage-y += sdram.c +romstage-y += sdram_lp0.c romstage-y += spi.c romstage-y += ../tegra/gpio.c romstage-y += ../tegra/i2c.c @@ -41,6 +42,7 @@ ramstage-y += dma.c ramstage-y += i2c.c ramstage-y += maincpu.S ramstage-y += monotonic_timer.c +ramstage-y += sdram.c ramstage-y += soc.c ramstage-y += sor.c ramstage-y += spi.c diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index d80b3a0..7f20702 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -18,10 +18,11 @@ */ #include <cbmem.h> -#include <soc/addressmap.h> +#include <soc/display.h> +#include <soc/nvidia/tegra124/sdram.h> void *cbmem_top(void) { return (void *)(CONFIG_SYS_SDRAM_BASE + - ((CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)<< 20UL)); + ((sdram_size_mb() - FB_SIZE_MB)<< 20UL)); } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index ba357fd..00dfbb6 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -33,6 +33,7 @@ #include <edid.h> #include <soc/clock.h> #include <soc/nvidia/tegra/dc.h> +#include <soc/nvidia/tegra124/sdram.h> #include "chip.h" #include <soc/display.h> @@ -225,6 +226,11 @@ static void update_window(struct display_controller *dc, WRITEL(val, &dc->cmd.state_ctrl); } +uint32_t fb_base_mb(void) +{ + return CONFIG_SYS_SDRAM_BASE/MiB + (sdram_size_mb() - FB_SIZE_MB); +} + /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ @@ -279,7 +285,7 @@ void display_startup(device_t dev) } if (! framebuffer_base_mb) - framebuffer_base_mb = FB_BASE_MB; + framebuffer_base_mb = fb_base_mb(); mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, config->cache_policy); diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index 5e55ee5..063e369 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -80,9 +80,4 @@ enum { TEGRA_I2C_BASE_COUNT = 6, }; -enum { - FB_SIZE_MB = (32), - FB_BASE_MB = (CONFIG_SYS_SDRAM_BASE/MiB + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)), -}; - #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h index b764671..36348ff 100644 --- a/src/soc/nvidia/tegra124/include/soc/display.h +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -188,6 +188,7 @@ #define COLORDEPTH 0x6 #define COLOR_WHITE 0xFFFFFF +struct soc_nvidia_tegra124_config; /* forward declaration */ void setup_display(struct soc_nvidia_tegra124_config *config); void init_dca_regs(void); void dp_io_powerup(void); @@ -195,4 +196,7 @@ u32 dp_setup_timing(u32 width, u32 height); void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 lane_count, u32 enhanced_framing, u32 panel_edp, u32 pclkfreq, u32 linkfreq); + +#define FB_SIZE_MB (32) + #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra124/mc.h b/src/soc/nvidia/tegra124/mc.h index 0fc3738..567b32a 100644 --- a/src/soc/nvidia/tegra124/mc.h +++ b/src/soc/nvidia/tegra124/mc.h @@ -115,6 +115,9 @@ struct tegra_mc_regs { }; enum { + MC_EMEM_CFG_SIZE_MB_SHIFT = 0, + MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff, + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 283cbf4..dcab810 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -568,6 +568,13 @@ void sdram_init(const struct sdram_params *param) struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE; struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE; + printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n", + param->MemoryType, clock_get_osc_khz() * + param->PllMFeedbackDivider / param->PllMInputDivider / + (1 + param->PllMSelectDiv2)); + if (param->MemoryType != NvBootMemoryType_Ddr3) + die("Unsupported memory type!\n"); + sdram_configure_pmc(param, pmc); sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1); @@ -600,6 +607,8 @@ void sdram_init(const struct sdram_params *param) sdram_set_refresh(param, emc); sdram_enable_arbiter(param); sdram_lock_carveouts(param, mc); + + sdram_lp0_save_params(param); } uint32_t sdram_get_ram_code(void) @@ -609,3 +618,24 @@ uint32_t sdram_get_ram_code(void) PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); } + +/* returns total amount of DRAM (in MB) from memory controller registers */ +int sdram_size_mb(void) +{ + struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE; + static int total_size = 0; + + if (total_size) + return total_size; + + /* + * This obtains memory size from the External Memory Aperture + * Configuration register. Nvidia confirmed that it is safe to assume + * this value represents the total physical DRAM size. + */ + total_size = (read32(&mc->emem_cfg) >> + MC_EMEM_CFG_SIZE_MB_SHIFT) & MC_EMEM_CFG_SIZE_MB_MASK; + + printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size); + return total_size; +} diff --git a/src/soc/nvidia/tegra124/sdram.h b/src/soc/nvidia/tegra124/sdram.h index cf5761c..66dbaa1 100644 --- a/src/soc/nvidia/tegra124/sdram.h +++ b/src/soc/nvidia/tegra124/sdram.h @@ -24,5 +24,9 @@ uint32_t sdram_get_ram_code(void); void sdram_init(const struct sdram_params *param); +int sdram_size_mb(void); + +/* Save params to PMC scratch registers for use by BootROM on LP0 resume. */ +void sdram_lp0_save_params(const struct sdram_params *sdram); #endif /* __SOC_NVIDIA_TEGRA124_SDRAM_H__ */ diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c new file mode 100644 index 0000000..0cd814e --- /dev/null +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <arch/cache.h> +#include <console/console.h> +#include <stdlib.h> +#include <soc/addressmap.h> + +#include "clk_rst.h" +#include "pmc.h" +#include "sdram.h" + +/* + * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from + * the common BCT format and writes them into PMC scratch registers (where the + * BootROM expects them on LP0 resume). Since those store the same values in a + * different format, we follow a "translation table" taken from Nvidia's U-Boot + * implementation to shift bits into the right position. + * + * Contrary to U-Boot, we transform the same macros directly into hardcoded + * assignments (without any pesky function calls or volatile qualifiers) to give + * the compiler as much room for optimization as possible. For that reason, we + * also intentionally avoid <arch/io.h> read/write macros, under the assumption + * that PMC scratch register accesses should not have side effects and can be + * arbitrarily reordered. For the few accesses that do have side-effects, the + * code must contain explicit memory barriers. + */ +void sdram_lp0_save_params(const struct sdram_params *sdram) +{ + struct tegra_pmc_regs * pmc = (void *)TEGRA_PMC_BASE; + struct clk_rst_ctlr * clk_rst = (void *)TEGRA_CLK_RST_BASE; + +#define pack(src, src_bits, dst, dst_bits) { \ + _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ + (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \ + _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \ + (0 ? dst_bits), "src and dst byte range lengths differ" ); \ + u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ + dst &= ~(mask << (0 ? dst_bits)); \ + dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ +} + +#define s(param, src_bits, pmcreg, dst_bits) \ + pack(sdram->param, src_bits, pmc->pmcreg, dst_bits) + +#define m(clkreg, src_bits, pmcreg, dst_bits) \ + pack(clk_rst->clkreg, src_bits, pmc->pmcreg, dst_bits) + +#define c(value, pmcreg, dst_bits) \ + pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) + + s(EmcClockSource, 7:0, scratch6, 15:8); + s(EmcClockSource, 31:29, scratch6, 18:16); + s(EmcClockSource, 26:26, scratch6, 19:19); + s(EmcOdtWrite, 5:0, scratch6, 25:20); + s(EmcOdtWrite, 11:8, scratch6, 29:26); + s(EmcOdtWrite, 30:30, scratch6, 30:30); + s(EmcOdtWrite, 31:31, scratch6, 31:31); + s(EmcXm2DqPadCtrl2, 18:16, scratch7, 22:20); + s(EmcXm2DqPadCtrl2, 22:20, scratch7, 25:23); + s(EmcXm2DqPadCtrl2, 26:24, scratch7, 28:26); + s(EmcXm2DqPadCtrl2, 30:28, scratch7, 31:29); + s(EmcXm2DqPadCtrl3, 18:16, scratch8, 22:20); + s(EmcXm2DqPadCtrl3, 22:20, scratch8, 25:23); + s(EmcXm2DqPadCtrl3, 26:24, scratch8, 28:26); + s(EmcXm2DqPadCtrl3, 30:28, scratch8, 31:29); + s(EmcTxsrDll, 11:0, scratch9, 31:20); + c(0, scratch10, 31:0); + s(EmcDsrVttgenDrv, 5:0, scratch10, 25:20); + s(EmcDsrVttgenDrv, 18:16, scratch10, 28:26); + s(EmcDsrVttgenDrv, 26:24, scratch10, 31:29); + s(EmcFbioSpare, 31:24, scratch11, 7:0); + s(EmcFbioSpare, 23:16, scratch11, 15:8); + s(EmcFbioSpare, 15:8, scratch11, 23:16); + s(EmcFbioSpare, 7:0, scratch11, 31:24); + s(EmcCfgRsv, 31:0, scratch12, 31:0); + s(EmcCdbCntl2, 31:0, scratch13, 31:0); + s(McEmemArbDaTurns, 31:0, scratch14, 31:0); + s(EmcCfgDigDll, 0:0, scratch17, 0:0); + s(EmcCfgDigDll, 25:2, scratch17, 24:1); + s(EmcCfgDigDll, 31:27, scratch17, 29:25); + s(EmcCdbCntl1, 29:0, scratch18, 29:0); + s(McEmemArbMisc0, 14:0, scratch19, 14:0); + s(McEmemArbMisc0, 30:16, scratch19, 29:15); + s(EmcXm2DqsPadCtrl, 4:0, scratch22, 4:0); + s(EmcXm2DqsPadCtrl, 12:8, scratch22, 9:5); + s(EmcXm2DqsPadCtrl, 31:14, scratch22, 27:10); + s(EmcRrd, 3:0, scratch22, 31:28); + s(EmcXm2DqPadCtrl, 31:4, scratch23, 27:0); + s(EmcRext, 3:0, scratch23, 31:28); + s(EmcXm2CompPadCtrl, 16:0, scratch24, 16:0); + s(EmcXm2CompPadCtrl, 24:20, scratch24, 21:17); + s(EmcXm2CompPadCtrl, 27:27, scratch24, 22:22); + s(EmcXm2CompPadCtrl, 31:28, scratch24, 26:23); + s(EmcR2w, 4:0, scratch24, 31:27); + s(EmcCfg, 9:1, scratch25, 8:0); + s(EmcCfg, 26:16, scratch25, 19:9); + s(EmcCfg, 31:28, scratch25, 23:20); + s(EmcXm2VttGenPadCtrl, 0:0, scratch25, 24:24); + s(EmcXm2VttGenPadCtrl, 2:2, scratch25, 25:25); + s(EmcXm2VttGenPadCtrl, 18:16, scratch25, 28:26); + s(EmcXm2VttGenPadCtrl, 26:24, scratch25, 31:29); + s(EmcZcalInterval, 23:10, scratch26, 13:0); + s(EmcZcalInterval, 9:0, scratch26, 23:14); + s(EmcSelDpdCtrl, 5:2, scratch26, 27:24); + s(EmcSelDpdCtrl, 8:8, scratch26, 28:28); + s(EmcSelDpdCtrl, 18:16, scratch26, 31:29); + s(EmcXm2VttGenPadCtrl3, 22:0, scratch27, 22:0); + s(EmcXm2VttGenPadCtrl3, 24:24, scratch27, 23:23); + s(EmcSwizzleRank0ByteCfg, 1:0, scratch27, 25:24); + s(EmcSwizzleRank0ByteCfg, 5:4, scratch27, 27:26); + s(EmcSwizzleRank0ByteCfg, 9:8, scratch27, 29:28); + s(EmcSwizzleRank0ByteCfg, 13:12, scratch27, 31:30); + s(EmcXm2ClkPadCtrl2, 5:0, scratch28, 5:0); + s(EmcXm2ClkPadCtrl2, 13:8, scratch28, 11:6); + s(EmcXm2ClkPadCtrl2, 20:16, scratch28, 16:12); + s(EmcXm2ClkPadCtrl2, 23:23, scratch28, 17:17); + s(EmcXm2ClkPadCtrl2, 28:24, scratch28, 22:18); + s(EmcXm2ClkPadCtrl2, 31:31, scratch28, 23:23); + s(EmcSwizzleRank1ByteCfg, 1:0, scratch28, 25:24); + s(EmcSwizzleRank1ByteCfg, 5:4, scratch28, 27:26); + s(EmcSwizzleRank1ByteCfg, 9:8, scratch28, 29:28); + s(EmcSwizzleRank1ByteCfg, 13:12, scratch28, 31:30); + s(McEmemArbDaCovers, 23:0, scratch29, 23:0); + s(McEmemArbRsv, 7:0, scratch29, 31:24); + s(EmcAutoCalConfig, 4:0, scratch30, 4:0); + s(EmcAutoCalConfig, 12:8, scratch30, 9:5); + s(EmcAutoCalConfig, 18:16, scratch30, 12:10); + s(EmcAutoCalConfig, 25:20, scratch30, 18:13); + s(EmcAutoCalConfig, 31:28, scratch30, 22:19); + s(EmcRfc, 8:0, scratch30, 31:23); + s(EmcXm2DqsPadCtrl2, 21:0, scratch31, 21:0); + s(EmcXm2DqsPadCtrl2, 24:24, scratch31, 22:22); + s(EmcAr2Pden, 8:0, scratch31, 31:23); + s(EmcXm2ClkPadCtrl, 0:0, scratch32, 0:0); + s(EmcXm2ClkPadCtrl, 4:2, scratch32, 3:1); + s(EmcXm2ClkPadCtrl, 7:7, scratch32, 4:4); + s(EmcXm2ClkPadCtrl, 31:14, scratch32, 22:5); + s(EmcRfcSlr, 8:0, scratch32, 31:23); + s(EmcXm2DqsPadCtrl3, 0:0, scratch33, 0:0); + s(EmcXm2DqsPadCtrl3, 5:5, scratch33, 1:1); + s(EmcXm2DqsPadCtrl3, 12:8, scratch33, 6:2); + s(EmcXm2DqsPadCtrl3, 18:14, scratch33, 11:7); + s(EmcXm2DqsPadCtrl3, 24:20, scratch33, 16:12); + s(EmcXm2DqsPadCtrl3, 30:26, scratch33, 21:17); + s(EmcTxsr, 9:0, scratch33, 31:22); + s(McEmemArbCfg, 8:0, scratch40, 8:0); + s(McEmemArbCfg, 20:16, scratch40, 13:9); + s(McEmemArbCfg, 27:24, scratch40, 17:14); + s(McEmemArbCfg, 31:28, scratch40, 21:18); + s(EmcMc2EmcQ, 2:0, scratch40, 24:22); + s(EmcMc2EmcQ, 10:8, scratch40, 27:25); + s(EmcMc2EmcQ, 27:24, scratch40, 31:28); + s(EmcAutoCalInterval, 20:0, scratch42, 20:0); + s(McEmemArbOutstandingReq, 8:0, scratch42, 29:21); + s(McEmemArbOutstandingReq, 31:30, scratch42, 31:30); + s(EmcMrsWaitCnt2, 9:0, scratch44, 9:0); + s(EmcMrsWaitCnt2, 25:16, scratch44, 19:10); + s(EmcTxdsrvttgen, 11:0, scratch44, 31:20); + s(EmcMrsWaitCnt, 9:0, scratch45, 9:0); + s(EmcMrsWaitCnt, 25:16, scratch45, 19:10); + s(EmcCfgPipe, 1:0, scratch45, 21:20); + s(EmcCfgPipe, 9:4, scratch45, 27:22); + s(EmcCfgPipe, 15:12, scratch45, 31:28); + s(EmcXm2DqsPadCtrl4, 22:18, scratch46, 4:0); + s(EmcXm2DqsPadCtrl4, 16:12, scratch46, 9:5); + s(EmcXm2DqsPadCtrl4, 10:6, scratch46, 14:10); + s(EmcXm2DqsPadCtrl4, 4:0, scratch46, 19:15); + s(EmcZcalWaitCnt, 9:0, scratch46, 29:20); + s(EmcXm2DqsPadCtrl5, 22:18, scratch47, 4:0); + s(EmcXm2DqsPadCtrl5, 16:12, scratch47, 9:5); + s(EmcXm2DqsPadCtrl5, 10:6, scratch47, 14:10); + s(EmcXm2DqsPadCtrl5, 4:0, scratch47, 19:15); + s(EmcXm2VttGenPadCtrl2, 5:0, scratch47, 25:20); + s(EmcXm2VttGenPadCtrl2, 31:28, scratch47, 29:26); + s(EmcXm2DqsPadCtrl6, 12:8, scratch48, 4:0); + s(EmcXm2DqsPadCtrl6, 18:14, scratch48, 9:5); + s(EmcXm2DqsPadCtrl6, 24:20, scratch48, 14:10); + s(EmcXm2DqsPadCtrl6, 30:26, scratch48, 19:15); + s(EmcAutoCalConfig3, 4:0, scratch48, 24:20); + s(EmcAutoCalConfig3, 12:8, scratch48, 29:25); + s(EmcFbioCfg5, 1:0, scratch48, 31:30); + s(EmcDllXformQUse8, 4:0, scratch50, 4:0); + s(EmcDllXformQUse8, 22:8, scratch50, 19:5); + s(McEmemArbRing1Throttle, 4:0, scratch50, 24:20); + s(McEmemArbRing1Throttle, 20:16, scratch50, 29:25); + s(EmcFbioCfg5, 3:2, scratch50, 31:30); + s(EmcDllXformQUse9, 4:0, scratch51, 4:0); + s(EmcDllXformQUse9, 22:8, scratch51, 19:5); + s(EmcCttTermCtrl, 2:0, scratch51, 22:20); + s(EmcCttTermCtrl, 12:8, scratch51, 27:23); + s(EmcCttTermCtrl, 31:31, scratch51, 28:28); + s(EmcFbioCfg6, 2:0, scratch51, 31:29); + s(EmcDllXformQUse10, 4:0, scratch56, 4:0); + s(EmcDllXformQUse10, 22:8, scratch56, 19:5); + s(EmcXm2CmdPadCtrl, 10:3, scratch56, 27:20); + s(EmcXm2CmdPadCtrl, 28:28, scratch56, 28:28); + s(EmcPutermAdj, 1:0, scratch56, 30:29); + s(EmcPutermAdj, 7:7, scratch56, 31:31); + s(EmcDllXformQUse11, 4:0, scratch57, 4:0); + s(EmcDllXformQUse11, 22:8, scratch57, 19:5); + s(EmcWdv, 3:0, scratch57, 31:28); + s(EmcDllXformQUse12, 4:0, scratch58, 4:0); + s(EmcDllXformQUse12, 22:8, scratch58, 19:5); + s(EmcBurstRefreshNum, 3:0, scratch58, 31:28); + s(EmcDllXformQUse13, 4:0, scratch59, 4:0); + s(EmcDllXformQUse13, 22:8, scratch59, 19:5); + s(EmcWext, 3:0, scratch59, 31:28); + s(EmcDllXformQUse14, 4:0, scratch60, 4:0); + s(EmcDllXformQUse14, 22:8, scratch60, 19:5); + s(EmcClkenOverride, 3:1, scratch60, 30:28); + s(EmcClkenOverride, 6:6, scratch60, 31:31); + s(EmcDllXformQUse15, 4:0, scratch61, 4:0); + s(EmcDllXformQUse15, 22:8, scratch61, 19:5); + s(EmcR2r, 3:0, scratch61, 31:28); + s(EmcDllXformDq4, 4:0, scratch62, 4:0); + s(EmcDllXformDq4, 22:8, scratch62, 19:5); + s(EmcRc, 6:0, scratch62, 26:20); + s(EmcW2r, 4:0, scratch62, 31:27); + s(EmcDllXformDq5, 4:0, scratch63, 4:0); + s(EmcDllXformDq5, 22:8, scratch63, 19:5); + s(EmcTfaw, 6:0, scratch63, 26:20); + s(EmcR2p, 4:0, scratch63, 31:27); + s(EmcDllXformDq6, 4:0, scratch64, 4:0); + s(EmcDllXformDq6, 22:8, scratch64, 19:5); + s(EmcDliTrimTxDqs0, 6:0, scratch64, 26:20); + s(EmcQSafe, 4:0, scratch64, 31:27); + s(EmcDllXformDq7, 4:0, scratch65, 4:0); + s(EmcDllXformDq7, 22:8, scratch65, 19:5); + s(EmcDliTrimTxDqs1, 6:0, scratch65, 26:20); + s(EmcTClkStable, 4:0, scratch65, 31:27); + s(EmcAutoCalConfig2, 4:0, scratch66, 4:0); + s(EmcAutoCalConfig2, 12:8, scratch66, 9:5); + s(EmcAutoCalConfig2, 20:16, scratch66, 14:10); + s(EmcAutoCalConfig2, 28:24, scratch66, 19:15); + s(EmcDliTrimTxDqs2, 6:0, scratch66, 26:20); + s(EmcTClkStop, 4:0, scratch66, 31:27); + s(McEmemArbMisc1, 1:0, scratch67, 1:0); + s(McEmemArbMisc1, 12:4, scratch67, 10:2); + s(McEmemArbMisc1, 25:21, scratch67, 15:11); + s(McEmemArbMisc1, 31:28, scratch67, 19:16); + s(EmcDliTrimTxDqs3, 6:0, scratch67, 26:20); + s(EmcEInputDuration, 4:0, scratch67, 31:27); + s(EmcZcalMrwCmd, 7:0, scratch68, 7:0); + s(EmcZcalMrwCmd, 23:16, scratch68, 15:8); + s(EmcZcalMrwCmd, 31:30, scratch68, 17:16); + s(EmcTRefBw, 13:0, scratch68, 31:18); + s(EmcXm2CmdPadCtrl2, 31:14, scratch69, 17:0); + s(EmcDliTrimTxDqs4, 6:0, scratch69, 24:18); + s(EmcDliTrimTxDqs5, 6:0, scratch69, 31:25); + s(EmcXm2CmdPadCtrl3, 31:14, scratch70, 17:0); + s(EmcDliTrimTxDqs6, 6:0, scratch70, 24:18); + s(EmcDliTrimTxDqs7, 6:0, scratch70, 31:25); + s(EmcXm2CmdPadCtrl5, 2:0, scratch71, 2:0); + s(EmcXm2CmdPadCtrl5, 6:4, scratch71, 5:3); + s(EmcXm2CmdPadCtrl5, 10:8, scratch71, 8:6); + s(EmcXm2CmdPadCtrl5, 14:12, scratch71, 11:9); + s(EmcXm2CmdPadCtrl5, 18:16, scratch71, 14:12); + s(EmcXm2CmdPadCtrl5, 22:20, scratch71, 17:15); + s(EmcDliTrimTxDqs8, 6:0, scratch71, 24:18); + s(EmcDliTrimTxDqs9, 6:0, scratch71, 31:25); + s(EmcCdbCntl3, 17:0, scratch72, 17:0); + s(EmcDliTrimTxDqs10, 6:0, scratch72, 24:18); + s(EmcDliTrimTxDqs11, 6:0, scratch72, 31:25); + s(EmcSwizzleRank0Byte0, 2:0, scratch73, 2:0); + s(EmcSwizzleRank0Byte0, 6:4, scratch73, 5:3); + s(EmcSwizzleRank0Byte0, 10:8, scratch73, 8:6); + s(EmcSwizzleRank0Byte0, 14:12, scratch73, 11:9); + s(EmcSwizzleRank0Byte0, 18:16, scratch73, 14:12); + s(EmcSwizzleRank0Byte0, 22:20, scratch73, 17:15); + s(EmcDliTrimTxDqs12, 6:0, scratch73, 24:18); + s(EmcDliTrimTxDqs13, 6:0, scratch73, 31:25); + s(EmcSwizzleRank0Byte1, 2:0, scratch74, 2:0); + s(EmcSwizzleRank0Byte1, 6:4, scratch74, 5:3); + s(EmcSwizzleRank0Byte1, 10:8, scratch74, 8:6); + s(EmcSwizzleRank0Byte1, 14:12, scratch74, 11:9); + s(EmcSwizzleRank0Byte1, 18:16, scratch74, 14:12); + s(EmcSwizzleRank0Byte1, 22:20, scratch74, 17:15); + s(EmcDliTrimTxDqs14, 6:0, scratch74, 24:18); + s(EmcDliTrimTxDqs15, 6:0, scratch74, 31:25); + s(EmcSwizzleRank0Byte2, 2:0, scratch75, 2:0); + s(EmcSwizzleRank0Byte2, 6:4, scratch75, 5:3); + s(EmcSwizzleRank0Byte2, 10:8, scratch75, 8:6); + s(EmcSwizzleRank0Byte2, 14:12, scratch75, 11:9); + s(EmcSwizzleRank0Byte2, 18:16, scratch75, 14:12); + s(EmcSwizzleRank0Byte2, 22:20, scratch75, 17:15); + s(McEmemArbTimingRp, 6:0, scratch75, 24:18); + s(McEmemArbTimingRc, 6:0, scratch75, 31:25); + s(EmcSwizzleRank0Byte3, 2:0, scratch76, 2:0); + s(EmcSwizzleRank0Byte3, 6:4, scratch76, 5:3); + s(EmcSwizzleRank0Byte3, 10:8, scratch76, 8:6); + s(EmcSwizzleRank0Byte3, 14:12, scratch76, 11:9); + s(EmcSwizzleRank0Byte3, 18:16, scratch76, 14:12); + s(EmcSwizzleRank0Byte3, 22:20, scratch76, 17:15); + s(McEmemArbTimingFaw, 6:0, scratch76, 24:18); + s(McEmemArbTimingWap2Pre, 6:0, scratch76, 31:25); + s(EmcSwizzleRank1Byte0, 2:0, scratch77, 2:0); + s(EmcSwizzleRank1Byte0, 6:4, scratch77, 5:3); + s(EmcSwizzleRank1Byte0, 10:8, scratch77, 8:6); + s(EmcSwizzleRank1Byte0, 14:12, scratch77, 11:9); + s(EmcSwizzleRank1Byte0, 18:16, scratch77, 14:12); + s(EmcSwizzleRank1Byte0, 22:20, scratch77, 17:15); + s(EmcRas, 5:0, scratch77, 23:18); + s(EmcRp, 5:0, scratch77, 29:24); + s(EmcCfg2, 9:8, scratch77, 31:30); + s(EmcSwizzleRank1Byte1, 2:0, scratch78, 2:0); + s(EmcSwizzleRank1Byte1, 6:4, scratch78, 5:3); + s(EmcSwizzleRank1Byte1, 10:8, scratch78, 8:6); + s(EmcSwizzleRank1Byte1, 14:12, scratch78, 11:9); + s(EmcSwizzleRank1Byte1, 18:16, scratch78, 14:12); + s(EmcSwizzleRank1Byte1, 22:20, scratch78, 17:15); + s(EmcW2p, 5:0, scratch78, 23:18); + s(EmcRdRcd, 5:0, scratch78, 29:24); + s(EmcCfg2, 27:26, scratch78, 31:30); + s(EmcSwizzleRank1Byte2, 2:0, scratch79, 2:0); + s(EmcSwizzleRank1Byte2, 6:4, scratch79, 5:3); + s(EmcSwizzleRank1Byte2, 10:8, scratch79, 8:6); + s(EmcSwizzleRank1Byte2, 14:12, scratch79, 11:9); + s(EmcSwizzleRank1Byte2, 18:16, scratch79, 14:12); + s(EmcSwizzleRank1Byte2, 22:20, scratch79, 17:15); + s(EmcWrRcd, 5:0, scratch79, 23:18); + s(EmcQUse, 5:0, scratch79, 29:24); + s(EmcFbioCfg5, 4:4, scratch79, 31:31); + s(EmcSwizzleRank1Byte3, 2:0, scratch80, 2:0); + s(EmcSwizzleRank1Byte3, 6:4, scratch80, 5:3); + s(EmcSwizzleRank1Byte3, 10:8, scratch80, 8:6); + s(EmcSwizzleRank1Byte3, 14:12, scratch80, 11:9); + s(EmcSwizzleRank1Byte3, 18:16, scratch80, 14:12); + s(EmcSwizzleRank1Byte3, 22:20, scratch80, 17:15); + s(EmcQRst, 5:0, scratch80, 23:18); + s(EmcRdv, 5:0, scratch80, 29:24); + s(EmcFbioCfg5, 6:5, scratch80, 31:30); + s(EmcDynSelfRefControl, 15:0, scratch81, 15:0); + s(EmcDynSelfRefControl, 31:31, scratch81, 16:16); + s(EmcPdEx2Wr, 5:0, scratch81, 22:17); + s(EmcPdEx2Rd, 5:0, scratch81, 28:23); + s(EmcRefresh, 5:0, scratch82, 5:0); + s(EmcRefresh, 15:6, scratch82, 15:6); + s(EmcCmdQ, 4:0, scratch82, 20:16); + s(EmcCmdQ, 10:8, scratch82, 23:21); + s(EmcCmdQ, 14:12, scratch82, 26:24); + s(EmcCmdQ, 28:24, scratch82, 31:27); + s(EmcAcpdControl, 15:0, scratch83, 15:0); + s(EmcCfgDigDllPeriod, 15:0, scratch83, 31:16); + s(EmcDllXformDqs0, 4:0, scratch84, 4:0); + s(EmcDllXformDqs0, 22:12, scratch84, 15:5); + s(EmcDllXformDqs1, 4:0, scratch84, 20:16); + s(EmcDllXformDqs1, 22:12, scratch84, 31:21); + s(EmcDllXformDqs2, 4:0, scratch85, 4:0); + s(EmcDllXformDqs2, 22:12, scratch85, 15:5); + s(EmcDllXformDqs3, 4:0, scratch85, 20:16); + s(EmcDllXformDqs3, 22:12, scratch85, 31:21); + s(EmcDllXformDqs4, 4:0, scratch86, 4:0); + s(EmcDllXformDqs4, 22:12, scratch86, 15:5); + s(EmcDllXformDqs5, 4:0, scratch86, 20:16); + s(EmcDllXformDqs5, 22:12, scratch86, 31:21); + s(EmcDllXformDqs6, 4:0, scratch87, 4:0); + s(EmcDllXformDqs6, 22:12, scratch87, 15:5); + s(EmcDllXformDqs7, 4:0, scratch87, 20:16); + s(EmcDllXformDqs7, 22:12, scratch87, 31:21); + s(EmcDllXformDqs8, 4:0, scratch88, 4:0); + s(EmcDllXformDqs8, 22:12, scratch88, 15:5); + s(EmcDllXformDqs9, 4:0, scratch88, 20:16); + s(EmcDllXformDqs9, 22:12, scratch88, 31:21); + s(EmcDllXformDqs10, 4:0, scratch89, 4:0); + s(EmcDllXformDqs10, 22:12, scratch89, 15:5); + s(EmcDllXformDqs11, 4:0, scratch89, 20:16); + s(EmcDllXformDqs11, 22:12, scratch89, 31:21); + s(EmcDllXformDqs12, 4:0, scratch90, 4:0); + s(EmcDllXformDqs12, 22:12, scratch90, 15:5); + s(EmcDllXformDqs13, 4:0, scratch90, 20:16); + s(EmcDllXformDqs13, 22:12, scratch90, 31:21); + s(EmcDllXformDqs14, 4:0, scratch91, 4:0); + s(EmcDllXformDqs14, 22:12, scratch91, 15:5); + s(EmcDllXformDqs15, 4:0, scratch91, 20:16); + s(EmcDllXformDqs15, 22:12, scratch91, 31:21); + s(EmcDllXformQUse0, 4:0, scratch92, 4:0); + s(EmcDllXformQUse0, 22:12, scratch92, 15:5); + s(EmcDllXformQUse1, 4:0, scratch92, 20:16); + s(EmcDllXformQUse1, 22:12, scratch92, 31:21); + s(EmcDllXformQUse2, 4:0, scratch93, 4:0); + s(EmcDllXformQUse2, 22:12, scratch93, 15:5); + s(EmcDllXformQUse3, 4:0, scratch93, 20:16); + s(EmcDllXformQUse3, 22:12, scratch93, 31:21); + s(EmcDllXformQUse4, 4:0, scratch94, 4:0); + s(EmcDllXformQUse4, 22:12, scratch94, 15:5); + s(EmcDllXformQUse5, 4:0, scratch94, 20:16); + s(EmcDllXformQUse5, 22:12, scratch94, 31:21); + s(EmcDllXformQUse6, 4:0, scratch95, 4:0); + s(EmcDllXformQUse6, 22:12, scratch95, 15:5); + s(EmcDllXformQUse7, 4:0, scratch95, 20:16); + s(EmcDllXformQUse7, 22:12, scratch95, 31:21); + s(EmcDllXformDq0, 4:0, scratch96, 4:0); + s(EmcDllXformDq0, 22:12, scratch96, 15:5); + s(EmcDllXformDq1, 4:0, scratch96, 20:16); + s(EmcDllXformDq1, 22:12, scratch96, 31:21); + s(EmcDllXformDq2, 4:0, scratch97, 4:0); + s(EmcDllXformDq2, 22:12, scratch97, 15:5); + s(EmcDllXformDq3, 4:0, scratch97, 20:16); + s(EmcDllXformDq3, 22:12, scratch97, 31:21); + s(EmcPreRefreshReqCnt, 15:0, scratch98, 15:0); + s(EmcDllXformAddr0, 4:0, scratch98, 20:16); + s(EmcDllXformAddr0, 22:12, scratch98, 31:21); + s(EmcDllXformAddr1, 4:0, scratch99, 4:0); + s(EmcDllXformAddr1, 22:12, scratch99, 15:5); + s(EmcDllXformAddr2, 4:0, scratch99, 20:16); + s(EmcDllXformAddr2, 22:12, scratch99, 31:21); + s(EmcDllXformAddr3, 4:0, scratch100, 4:0); + s(EmcDllXformAddr3, 22:12, scratch100, 15:5); + s(EmcDllXformAddr4, 4:0, scratch100, 20:16); + s(EmcDllXformAddr4, 22:12, scratch100, 31:21); + s(EmcDllXformAddr5, 4:0, scratch101, 4:0); + s(EmcDllXformAddr5, 22:12, scratch101, 15:5); + s(EmcPChg2Pden, 5:0, scratch102, 5:0); + s(EmcAct2Pden, 5:0, scratch102, 11:6); + s(EmcRw2Pden, 5:0, scratch102, 17:12); + s(EmcTcke, 5:0, scratch102, 23:18); + s(EmcTrpab, 5:0, scratch102, 29:24); + s(EmcFbioCfg5, 8:7, scratch102, 31:30); + s(EmcCtt, 5:0, scratch103, 5:0); + s(EmcEInput, 5:0, scratch103, 11:6); + s(EmcPutermExtra, 21:16, scratch103, 17:12); + s(EmcTckesr, 5:0, scratch103, 23:18); + s(EmcTpd, 5:0, scratch103, 29:24); + s(EmcFbioCfg5, 10:9, scratch103, 31:30); + s(EmcRdvMask, 5:0, scratch104, 5:0); + s(EmcXm2CmdPadCtrl4, 0:0, scratch104, 6:6); + s(EmcXm2CmdPadCtrl4, 2:2, scratch104, 7:7); + s(EmcXm2CmdPadCtrl4, 4:4, scratch104, 8:8); + s(EmcXm2CmdPadCtrl4, 6:6, scratch104, 9:9); + s(EmcXm2CmdPadCtrl4, 8:8, scratch104, 10:10); + s(EmcXm2CmdPadCtrl4, 10:10, scratch104, 11:11); + s(EmcQpop, 5:0, scratch104, 17:12); + s(McEmemArbTimingRcd, 5:0, scratch104, 23:18); + s(McEmemArbTimingRas, 5:0, scratch104, 29:24); + s(EmcFbioCfg5, 12:11, scratch104, 31:30); + s(McEmemArbTimingRap2Pre, 5:0, scratch105, 5:0); + s(McEmemArbTimingR2W, 5:0, scratch105, 11:6); + s(McEmemArbTimingW2R, 5:0, scratch105, 17:12); + s(EmcIbdly, 4:0, scratch105, 22:18); + s(McEmemArbTimingR2R, 4:0, scratch105, 27:23); + s(EmcW2w, 3:0, scratch105, 31:28); + s(McEmemArbTimingW2W, 4:0, scratch106, 4:0); + s(McEmemArbOverride, 27:27, scratch106, 5:5); + s(McEmemArbOverride, 26:26, scratch106, 6:6); + s(McEmemArbOverride, 16:16, scratch106, 7:7); + s(McEmemArbOverride, 10:10, scratch106, 8:8); + s(McEmemArbOverride, 4:4, scratch106, 9:9); + s(EmcWdvMask, 3:0, scratch106, 13:10); + s(EmcCttDuration, 3:0, scratch106, 17:14); + s(EmcQuseWidth, 3:0, scratch106, 21:18); + s(EmcPutermWidth, 3:0, scratch106, 25:22); + s(EmcBgbiasCtl0, 3:0, scratch106, 29:26); + s(EmcFbioCfg5, 25:24, scratch106, 31:30); + s(McEmemArbTimingRrd, 3:0, scratch107, 3:0); + s(EmcFbioCfg5, 23:20, scratch107, 10:7); + s(EmcFbioCfg5, 15:13, scratch107, 13:11); + s(EmcCfg2, 5:3, scratch107, 16:14); + s(EmcFbioCfg5, 26:26, scratch107, 17:17); + s(EmcFbioCfg5, 28:28, scratch107, 18:18); + s(EmcCfg2, 2:0, scratch107, 21:19); + s(EmcCfg2, 7:6, scratch107, 23:22); + s(EmcCfg2, 15:10, scratch107, 29:24); + s(EmcCfg2, 23:22, scratch107, 31:30); + s(EmcCfg2, 25:24, scratch108, 1:0); + s(EmcCfg2, 31:28, scratch108, 5:2); + s(BootRomPatchData, 31:0, scratch15, 31:0); + s(BootRomPatchControl, 31:0, scratch16, 31:0); + s(EmcDevSelect, 1:0, scratch17, 31:30); + s(EmcZcalWarmColdBootEnables, 1:0, scratch18, 31:30); + s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch19, 31:30); + s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch46, 30:30); + s(McClkenOverrideAllWarmBoot, 0:0, scratch46, 31:31); + s(EmcClkenOverrideAllWarmBoot, 0:0, scratch47, 30:30); + s(EmcMrsWarmBootEnable, 0:0, scratch47, 31:31); + s(EmcTimingControlWait, 7:0, scratch57, 27:20); + s(EmcZcalWarmBootWait, 7:0, scratch58, 27:20); + s(EmcAutoCalWait, 7:0, scratch59, 27:20); + s(WarmBootWait, 7:0, scratch60, 27:20); + s(EmcPinProgramWait, 7:0, scratch61, 27:20); + s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch79, 30:30); + s(EmcExtraRefreshNum, 2:0, scratch81, 31:29); + s(SwizzleRankByteEncode, 15:0, scratch101, 31:16); + s(MemoryType, 2:0, scratch107, 6:4); + + switch (sdram->MemoryType) { + case NvBootMemoryType_LpDdr2: + s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); + s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); + s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); + s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); + s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); + s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); + s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); + s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); + s(EmcMrw1, 7:0, scratch7, 7:0); + s(EmcMrw1, 23:16, scratch7, 15:8); + s(EmcMrw1, 27:26, scratch7, 17:16); + s(EmcMrw1, 31:30, scratch7, 19:18); + s(EmcMrw2, 7:0, scratch8, 7:0); + s(EmcMrw2, 23:16, scratch8, 15:8); + s(EmcMrw2, 27:26, scratch8, 17:16); + s(EmcMrw2, 31:30, scratch8, 19:18); + s(EmcMrw3, 7:0, scratch9, 7:0); + s(EmcMrw3, 23:16, scratch9, 15:8); + s(EmcMrw3, 27:26, scratch9, 17:16); + s(EmcMrw3, 31:30, scratch9, 19:18); + s(EmcMrw4, 7:0, scratch10, 7:0); + s(EmcMrw4, 23:16, scratch10, 15:8); + s(EmcMrw4, 27:26, scratch10, 17:16); + s(EmcMrw4, 31:30, scratch10, 19:18); + break; + case NvBootMemoryType_Ddr3: + s(EmcMrs, 13:0, scratch5, 13:0); + s(EmcEmrs, 13:0, scratch5, 27:14); + s(EmcMrs, 21:20, scratch5, 29:28); + s(EmcMrs, 31:30, scratch5, 31:30); + s(EmcEmrs2, 13:0, scratch7, 13:0); + s(EmcEmrs, 21:20, scratch7, 15:14); + s(EmcEmrs, 31:30, scratch7, 17:16); + s(EmcEmrs2, 21:20, scratch7, 19:18); + s(EmcEmrs3, 13:0, scratch8, 13:0); + s(EmcEmrs2, 31:30, scratch8, 15:14); + s(EmcEmrs3, 21:20, scratch8, 17:16); + s(EmcEmrs3, 31:30, scratch8, 19:18); + s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); + s(EmcWarmBootMrsExtra, 31:30, scratch9, 15:14); + s(EmcWarmBootMrsExtra, 21:20, scratch9, 17:16); + s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 19:18); + s(EmcMrs, 27:26, scratch10, 1:0); + s(EmcEmrs, 27:26, scratch10, 3:2); + s(EmcEmrs2, 27:26, scratch10, 5:4); + s(EmcEmrs3, 27:26, scratch10, 7:6); + s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); + s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); + s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); + s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); + c(0, scratch116, 31:0); + c(0, scratch117, 31:0); + break; + default: + printk(BIOS_CRIT, "ERROR: %s() unrecognized MemoryType %d!\n", + __func__, sdram->MemoryType); + } + + s(McVideoProtectGpuOverride0, 31:0, secure_scratch8, 31:0); + s(McVideoProtectVprOverride, 3:0, secure_scratch9, 3:0); + s(McVideoProtectVprOverride, 11:6, secure_scratch9, 9:4); + s(McVideoProtectVprOverride, 23:14, secure_scratch9, 19:10); + s(McVideoProtectVprOverride, 26:26, secure_scratch9, 20:20); + s(McVideoProtectVprOverride, 31:29, secure_scratch9, 23:21); + s(EmcFbioCfg5, 19:16, secure_scratch9, 27:24); + s(McDisplaySnapRing, 1:0, secure_scratch9, 29:28); + s(McDisplaySnapRing, 31:31, secure_scratch9, 30:30); + s(EmcAdrCfg, 0:0, secure_scratch9, 31:31); + s(McVideoProtectGpuOverride1, 15:0, secure_scratch10, 15:0); + s(McEmemAdrCfgBankMask0, 15:0, secure_scratch10, 31:16); + s(McEmemAdrCfgBankMask1, 15:0, secure_scratch11, 15:0); + s(McEmemAdrCfgBankMask2, 15:0, secure_scratch11, 31:16); + s(McEmemCfg, 13:0, secure_scratch12, 13:0); + s(McEmemCfg, 31:31, secure_scratch12, 14:14); + s(McVideoProtectBom, 31:20, secure_scratch12, 26:15); + s(McVideoProtectVprOverride1, 1:0, secure_scratch12, 28:27); + s(McVideoProtectVprOverride1, 4:4, secure_scratch12, 29:29); + s(McVideoProtectBomAdrHi, 1:0, secure_scratch12, 31:30); + s(McVideoProtectSizeMb, 11:0, secure_scratch13, 11:0); + s(McSecCarveoutBom, 31:20, secure_scratch13, 23:12); + s(McEmemAdrCfgBankSwizzle3, 2:0, secure_scratch13, 26:24); + s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 28:27); + s(McSecCarveoutAdrHi, 1:0, secure_scratch13, 30:29); + s(McEmemAdrCfg, 0:0, secure_scratch13, 31:31); + s(McSecCarveoutSizeMb, 11:0, secure_scratch14, 11:0); + s(McMtsCarveoutBom, 31:20, secure_scratch14, 23:12); + s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 25:24); + s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch14, 26:26); + s(McMtsCarveoutRegCtrl, 0:0, secure_scratch14, 27:27); + s(McMtsCarveoutSizeMb, 11:0, secure_scratch15, 11:0); + s(McEmemAdrCfgDev0, 2:0, secure_scratch15, 14:12); + s(McEmemAdrCfgDev0, 9:8, secure_scratch15, 16:15); + s(McEmemAdrCfgDev0, 19:16, secure_scratch15, 20:17); + s(McEmemAdrCfgDev1, 2:0, secure_scratch15, 23:21); + s(McEmemAdrCfgDev1, 9:8, secure_scratch15, 25:24); + s(McEmemAdrCfgDev1, 19:16, secure_scratch15, 29:26); + + /* Make sure all writes complete before we lock the secure_scratchs. */ + dmb(); + c(0x1555555, sec_disable2, 25:0); + c(0xff, sec_disable, 19:12); + + c(0, scratch2, 31:0); + m(pllm_base, 15:0, scratch2, 15:0); + m(pllm_base, 20:20, scratch2, 16:16); + m(pllm_misc2, 2:0, scratch2, 19:17); + c(0, scratch35, 31:0); + m(pllm_misc1, 23:0, scratch35, 23:0); + m(pllm_misc1, 30:28, scratch35, 30:28); + c(0, scratch3, 31:0); + s(PllMInputDivider, 7:0, scratch3, 7:0); + c(0x3e, scratch3, 15:8); + c(0, scratch3, 19:16); + s(PllMKVCO, 0:0, scratch3, 20:20); + s(PllMKCP, 1:0, scratch3, 22:21); + c(0, scratch36, 31:0); + s(PllMSetupControl, 23:0, scratch36, 23:0); + c(0, scratch4, 31:0); + s(PllMStableTime, 9:0, scratch4, 9:0); + s(PllMStableTime, 9:0, scratch4, 19:10); + + s(PllMSelectDiv2, 0:0, pllm_wb0_override2, 27:27); + s(PllMKVCO, 0:0, pllm_wb0_override2, 26:26); + s(PllMKCP, 1:0, pllm_wb0_override2, 25:24); + s(PllMSetupControl, 23:0, pllm_wb0_override2, 23:0); + s(PllMFeedbackDivider, 7:0, pllm_wb0_override_freq, 15:8); + s(PllMInputDivider, 7:0, pllm_wb0_override_freq, 7:0); + + /* Need to ensure override params are written before we activate it. */ + dmb(); + c(3, pllp_wb0_override, 12:11); +} diff --git a/src/soc/nvidia/tegra124/sdram_param.h b/src/soc/nvidia/tegra124/sdram_param.h index 1f05566..c845611 100644 --- a/src/soc/nvidia/tegra124/sdram_param.h +++ b/src/soc/nvidia/tegra124/sdram_param.h @@ -33,25 +33,27 @@ enum { /* Specifies the memory type to be undefined */ - MEMORY_TYPE_NONE = 0, + NvBootMemoryType_None = 0, /* Specifies the memory type to be DDR SDRAM */ - MEMORY_TYPE_DDR = 0, + NvBootMemoryType_Ddr = 0, /* Specifies the memory type to be LPDDR SDRAM */ - MEMORY_TYPE_LPDDR = 0, + NvBootMemoryType_LpDdr = 0, /* Specifies the memory type to be DDR2 SDRAM */ - MEMORY_TYPE_DDR2 = 0, + NvBootMemoryType_Ddr2 = 0, /* Specifies the memory type to be LPDDR2 SDRAM */ - MEMORY_TYPE_LPDDR2, + NvBootMemoryType_LpDdr2, /* Specifies the memory type to be DDR3 SDRAM */ - MEMORY_TYPE_DDR3, + NvBootMemoryType_Ddr3, - MEMORY_TYPE_NUM, - MEMORY_TYPE_FORCE32 = 0X7FFFFFF + NvBootMemoryType_Num, + + /* Specifies an entry in the ram_code table that's not in use */ + NvBootMemoryType_Unused = 0X7FFFFFF, }; enum { @@ -69,7 +71,7 @@ enum { struct sdram_params { /* Specifies the type of memory device */ - uint32_t memory_type; + uint32_t MemoryType; /* MC/EMC clock source configuration */ diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index e996c11..11a52c4 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -22,7 +22,8 @@ #include <console/console.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> -#include <soc/addressmap.h> +#include <soc/nvidia/tegra124/sdram.h> +#include <soc/display.h> /* this sucks, but for now, fb size/location are hardcoded. * Will break if we get 2. Sigh. @@ -30,10 +31,11 @@ */ static void soc_enable(device_t dev) { + u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; - u32 lcdbase = FB_BASE_MB; + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, - (CONFIG_DRAM_SIZE_MB - fb_size)*KiB); + (sdram_size_mb() - fb_size)*KiB); mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); }

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Patch set updated for coreboot: c385ceb NOTFORMERGE: amdk8: Move to per-device ACPI
by Vladimir Serbinenko 23 Sep '14

23 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6948 -gerrit commit c385ceb2aa35b5cff5c961cda7a62c563a9b240f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Sep 21 14:31:19 2014 +0200 NOTFORMERGE: amdk8: Move to per-device ACPI Change-Id: I485791015aa7eaabba53813945c216f5725554b1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/amd/dbm690t/acpi_tables.c | 106 ------------- src/mainboard/amd/mahogany/acpi_tables.c | 157 ------------------- src/mainboard/amd/mahogany_fam10/acpi_tables.c | 6 - src/mainboard/amd/pistachio/acpi_tables.c | 105 ------------- src/mainboard/amd/tilapia_fam10/acpi_tables.c | 6 - src/mainboard/asrock/939a785gmh/acpi_tables.c | 157 ------------------- src/mainboard/asus/a8n_e/acpi_tables.c | 137 ----------------- src/mainboard/asus/a8v-e_deluxe/acpi_tables.c | 93 ------------ src/mainboard/asus/a8v-e_deluxe/dsdt.asl | 7 - src/mainboard/asus/a8v-e_se/acpi_tables.c | 110 -------------- src/mainboard/asus/k8v-x/acpi_tables.c | 110 -------------- src/mainboard/asus/m2v-mx_se/acpi_tables.c | 130 ---------------- src/mainboard/asus/m2v/acpi_tables.c | 131 ---------------- src/mainboard/asus/m4a78-em/acpi_tables.c | 6 - src/mainboard/asus/m4a785-m/acpi_tables.c | 8 - src/mainboard/gigabyte/m57sli/acpi_tables.c | 109 -------------- src/mainboard/gigabyte/ma785gm/acpi_tables.c | 6 - src/mainboard/gigabyte/ma785gmt/acpi_tables.c | 6 - src/mainboard/gigabyte/ma78gm/acpi_tables.c | 6 - src/mainboard/iei/kino-780am2-fam10/acpi_tables.c | 6 - src/mainboard/jetway/pa78vm5/acpi_tables.c | 6 - src/mainboard/kontron/kt690/acpi_tables.c | 105 ------------- src/mainboard/msi/ms7135/acpi_tables.c | 138 ----------------- src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 166 ++------------------- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 2 + src/mainboard/siemens/sitemp_g1p1/mainboard.h | 1 + src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 6 - src/mainboard/technexion/tim5690/acpi_tables.c | 105 ------------- src/mainboard/technexion/tim8690/acpi_tables.c | 105 ------------- src/mainboard/tyan/s2891/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2891/mainboard.c | 23 +++ src/mainboard/tyan/s2892/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2892/mainboard.c | 23 +++ src/mainboard/tyan/s2895/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2895/mainboard.c | 23 +++ src/mainboard/winent/mb6047/acpi_tables.c | 112 -------------- src/mainboard/winent/mb6047/mainboard.c | 23 +++ src/northbridge/amd/amdk8/Kconfig | 1 + src/northbridge/amd/amdk8/acpi.c | 4 +- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/amdk8/northbridge.c | 36 +++++ src/southbridge/amd/rs690/ht.c | 18 +++ src/southbridge/amd/sb600/lpc.c | 26 ++++ src/southbridge/amd/sb700/lpc.c | 33 +++- src/southbridge/nvidia/ck804/ht.c | 27 ++++ src/southbridge/nvidia/ck804/lpc.c | 4 + src/southbridge/nvidia/mcp55/lpc.c | 18 +++ src/southbridge/via/k8t890/traf_ctrl.c | 41 +++++ 49 files changed, 318 insertions(+), 2472 deletions(-) diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c index 87ff5ea..3206aaf 100644 --- a/src/mainboard/amd/dbm690t/acpi_tables.c +++ b/src/mainboard/amd/dbm690t/acpi_tables.c @@ -28,25 +28,6 @@ #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/acpi.h" #include <arch/cpu.h> -#include <cpu/amd/model_fxx_powernow.h> - -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} unsigned long acpi_fill_madt(unsigned long current) { @@ -72,90 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/mahogany/acpi_tables.c b/src/mainboard/amd/mahogany/acpi_tables.c index ef2690a..7c94e03 100644 --- a/src/mainboard/amd/mahogany/acpi_tables.c +++ b/src/mainboard/amd/mahogany/acpi_tables.c @@ -28,32 +28,8 @@ #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/acpi.h" #include <arch/cpu.h> -#include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/sb700/sb700.h> -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -78,136 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - - for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ - if ((sysconf.pci1234[i] & 1) != 1) - continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *) current; - switch (sysconf.hcid[i]) { - case 1: /* 8132 */ - p = &AmlCode_ssdt2; - break; - case 2: /* 8151 */ - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c index 01172ad..5efb0ee 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c @@ -60,12 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c index 5ef0da5..717e4b4 100644 --- a/src/mainboard/amd/pistachio/acpi_tables.c +++ b/src/mainboard/amd/pistachio/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -73,90 +55,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c index 898a955..8d7f723 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ b/src/mainboard/amd/tilapia_fam10/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/asrock/939a785gmh/acpi_tables.c b/src/mainboard/asrock/939a785gmh/acpi_tables.c index 52b45f7..e6369df 100644 --- a/src/mainboard/asrock/939a785gmh/acpi_tables.c +++ b/src/mainboard/asrock/939a785gmh/acpi_tables.c @@ -31,29 +31,6 @@ #include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/sb700/sb700.h> -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -78,137 +55,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - - for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ - if ((sysconf.pci1234[i] & 1) != 1) - continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *) current; - switch (sysconf.hcid[i]) { - case 1: /* 8132 */ - p = &AmlCode_ssdt2; - break; - case 2: /* 8151 */ - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/a8n_e/acpi_tables.c b/src/mainboard/asus/a8n_e/acpi_tables.c index ee8e81f..2e06915 100644 --- a/src/mainboard/asus/a8n_e/acpi_tables.c +++ b/src/mainboard/asus/a8n_e/acpi_tables.c @@ -21,30 +21,6 @@ #include "../../../northbridge/amd/amdk8/acpi.h" //#include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - unsigned long mcfg_base; - - dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); - if (!dev) - return current; - - mcfg_base = pci_read_config16(dev, 0x90); - if ((mcfg_base & 0x1000) == 0) - return current; - - mcfg_base = (mcfg_base & 0xf) << 28; - - printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, mcfg_base, 0x0, 0x0, 0xff); - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -86,116 +62,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - //amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - mcfg = (acpi_mcfg_t *) current; - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p\n", mcfg); - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - current += hpet->header.length; - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c b/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c index 30914e4..e2fa0f0 100644 --- a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c @@ -32,25 +32,6 @@ #include "southbridge/via/vt8237r/vt8237r.h" #include "southbridge/via/k8t890/k8t890.h" -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -80,77 +61,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl index 3afcdc3..8f1e197 100644 --- a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl +++ b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl @@ -24,13 +24,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { - /* Define the main processor.*/ - Scope (\_PR) - { - Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} - Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} - } - /* For now only define 2 power states: * - S0 which is fully on * - S5 which is soft off diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c index f5f081a..2a874db 100644 --- a/src/mainboard/asus/a8v-e_se/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c @@ -34,25 +34,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -82,94 +63,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 065db1a..da4c399 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -34,25 +34,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -82,94 +63,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 91a5da1..dab35d4 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -35,25 +35,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -83,114 +64,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/m2v/acpi_tables.c b/src/mainboard/asus/m2v/acpi_tables.c index cc1070e..7ad045c 100644 --- a/src/mainboard/asus/m2v/acpi_tables.c +++ b/src/mainboard/asus/m2v/acpi_tables.c @@ -36,25 +36,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -84,115 +65,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - - return current; -} diff --git a/src/mainboard/asus/m4a78-em/acpi_tables.c b/src/mainboard/asus/m4a78-em/acpi_tables.c index 2398c01..a132b7b 100644 --- a/src/mainboard/asus/m4a78-em/acpi_tables.c +++ b/src/mainboard/asus/m4a78-em/acpi_tables.c @@ -38,12 +38,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index a8b6365..1c0afeb 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -60,14 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } - - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c index 2e2e590..81ebd90 100644 --- a/src/mainboard/gigabyte/m57sli/acpi_tables.c +++ b/src/mainboard/gigabyte/m57sli/acpi_tables.c @@ -92,112 +92,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c index 7a5df88..e961b6e 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c index 07b174c..3b776ae 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c @@ -37,12 +37,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/ma78gm/acpi_tables.c b/src/mainboard/gigabyte/ma78gm/acpi_tables.c index 07b174c..3b776ae 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma78gm/acpi_tables.c @@ -37,12 +37,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c index 01172ad..5efb0ee 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c +++ b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c @@ -60,12 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/jetway/pa78vm5/acpi_tables.c b/src/mainboard/jetway/pa78vm5/acpi_tables.c index fc6f186..eac5619 100644 --- a/src/mainboard/jetway/pa78vm5/acpi_tables.c +++ b/src/mainboard/jetway/pa78vm5/acpi_tables.c @@ -38,12 +38,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/kontron/kt690/acpi_tables.c b/src/mainboard/kontron/kt690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/kontron/kt690/acpi_tables.c +++ b/src/mainboard/kontron/kt690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c index ee8e81f..f5ddec3 100644 --- a/src/mainboard/msi/ms7135/acpi_tables.c +++ b/src/mainboard/msi/ms7135/acpi_tables.c @@ -19,31 +19,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> #include "../../../northbridge/amd/amdk8/acpi.h" -//#include <cpu/amd/model_fxx_powernow.h> - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - unsigned long mcfg_base; - - dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); - if (!dev) - return current; - - mcfg_base = pci_read_config16(dev, 0x90); - if ((mcfg_base & 0x1000) == 0) - return current; - - mcfg_base = (mcfg_base & 0xf) << 28; - - printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, mcfg_base, 0x0, 0x0, 0xff); - return current; -} /* APIC */ unsigned long acpi_fill_madt(unsigned long current) @@ -86,116 +61,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - //amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - mcfg = (acpi_mcfg_t *) current; - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p\n", mcfg); - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - current += hpet->header.length; - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index 18e1bf9..d092308 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -33,16 +33,9 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/rs690/rs690.h> +#include "mainboard.h" +#include <cbmem.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 #define GLOBAL_VARS_SIZE 0x100 typedef struct { @@ -70,24 +63,6 @@ static void acpi_write_gvars(global_vars_t *gvars) gvars->mpen = 1; } -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - struct resource *res; - resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default - - device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); - // we report mmconf base - res = probe_resource(dev, 0x1C); - if( res ) - mmconf_base = res->base; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? - - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -116,133 +91,20 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} +unsigned long mainboard_fill_ssdt(unsigned long current, const char *oem_table_id) +{ + global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE); -#define ALIGN_CURRENT current = (ALIGN(current, 16)) + if (gnvs) { + int scopelen; + acpi_write_gvars(gnvs); -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_srat_t *srat; - acpi_xsdt_t *xsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - current = start; - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 64); - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - acpi_create_facs(facs); - current += sizeof(acpi_facs_t); - - /* HPET */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - acpi_create_hpet(hpet); - current += sizeof(acpi_hpet_t); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* MCFG */ - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - /* Pack gvars into the ACPI table area */ - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xBADEAFFE) { - printk(BIOS_DEBUG, "ACPI: Patching up globals in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); - *(u32*)(((u32)dsdt) + i) = current; - break; - } + /* Add it to SSDT. */ + scopelen = acpigen_write_scope("\\"); + scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_patch_len(scopelen - 1); } - /* And fill it */ - acpi_write_gvars((global_vars_t *)current); - current += GLOBAL_VARS_SIZE; - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* SRAT */ - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - acpi_add_table(rsdp, srat); - - printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + return (unsigned long) (acpigen_get_current()); } + diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 7890df7..e106561 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -245,7 +245,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) PWDA, 1, } - OperationRegion (GVAR, SystemMemory, 0xBADEAFFE, 0x100) + External(\NVSA) + + OperationRegion (GVAR, SystemMemory, \NVSA, 0x100) Field (GVAR, ByteAcc, NoLock, Preserve) { Offset (0x00), diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 960496f..066dfb4 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -38,6 +38,7 @@ #include <x86emu/x86emu.h> #endif #include "int15_func.h" +#include "mainboard.h" // ****LCD panel ID support: ***** // Callback Sub-Function 00h - Get LCD Panel ID @@ -846,6 +847,7 @@ static void mainboard_enable(device_t dev) update_subsystemid(dev); dev->ops->init = mainboard_init; // rest of mainboard init later + dev->ops->acpi_fill_ssdt_generator = mainboard_fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.h b/src/mainboard/siemens/sitemp_g1p1/mainboard.h new file mode 100644 index 0000000..fd70365 --- /dev/null +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.h @@ -0,0 +1 @@ +unsigned long mainboard_fill_ssdt(unsigned long current, const char *oem_table_id); diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index ae9cca9..48a396e 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { device_t dev; diff --git a/src/mainboard/technexion/tim5690/acpi_tables.c b/src/mainboard/technexion/tim5690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/technexion/tim5690/acpi_tables.c +++ b/src/mainboard/technexion/tim5690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/technexion/tim8690/acpi_tables.c +++ b/src/mainboard/technexion/tim8690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c index 42d9152..424d87e 100644 --- a/src/mainboard/tyan/s2891/acpi_tables.c +++ b/src/mainboard/tyan/s2891/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -83,108 +76,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c index 42d9152..424d87e 100644 --- a/src/mainboard/tyan/s2892/acpi_tables.c +++ b/src/mainboard/tyan/s2892/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -83,108 +76,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c index 1974171..fe8d0c3 100644 --- a/src/mainboard/tyan/s2895/acpi_tables.c +++ b/src/mainboard/tyan/s2895/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -102,108 +95,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 1b59fbb..5cf5f55 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -67,108 +60,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 3f8861e..e79b6b2 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -23,6 +23,7 @@ config NORTHBRIDGE_AMD_AMDK8 select HAVE_DEBUG_SMBUS select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT + select PER_DEVICE_ACPI_TABLES if NORTHBRIDGE_AMD_AMDK8 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index f7134f6..499f3d2 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -253,7 +253,7 @@ static int k8acpi_write_pci_data(int dlen, const char *name, int offset) { return len + lenp; } -int k8acpi_write_vars(void) +unsigned long k8acpi_write_vars(unsigned long current, const char *oem_table_id) { int lens; msr_t msr; @@ -283,7 +283,7 @@ int k8acpi_write_vars(void) lens += k8acpi_write_HT(); //minus opcode acpigen_patch_len(lens - 1); - return lens; + return (unsigned long) (acpigen_get_current()); } void update_ssdtx(void *ssdtx, int i) diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index 9d0a73a..0570716 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -21,6 +21,6 @@ #define AMDK8_ACPI_H #include <arch/acpigen.h> -int k8acpi_write_vars(void); +unsigned long k8acpi_write_vars(unsigned long current, const char *oem_table_id); #endif diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 2c19b3a..bfd2c0f 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -16,6 +16,10 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +#include <arch/acpi.h> +#include "acpi.h" +#endif #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> @@ -580,10 +584,42 @@ static void mcf0_control_init(struct device *dev) #endif } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +static unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +{ + unsigned long current; + acpi_srat_t *srat; + acpi_slit_t *slit; + + current = start; + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit); + + return current; +} +#endif + static struct device_operations northbridge_operations = { .read_resources = amdk8_read_resources, .set_resources = amdk8_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .acpi_fill_ssdt_generator = k8acpi_write_vars, + .write_acpi_tables = northbridge_write_acpi_tables, +#endif .init = mcf0_control_init, .scan_bus = amdk8_scan_chains, .enable = 0, diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index 7353f76..33fce0f 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <lib.h> +#include <arch/acpi.h> #include "rs690.h" static void ht_dev_set_resources(device_t dev) @@ -84,6 +85,23 @@ static void ht_dev_set_resources(device_t dev) pci_dev_set_resources(dev); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ +#if CONFIG_EXT_CONF_SUPPORT + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default + + device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); + // we report mmconf base + res = probe_resource(dev, 0x1C); + if( res ) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? +#endif + return current; +} + static void ht_dev_read_resources(device_t dev) { #if CONFIG_EXT_CONF_SUPPORT diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 7ef49d1..10616ce 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -24,9 +24,13 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> #include "sb600.h" static void lpc_init(device_t dev) @@ -215,6 +219,24 @@ static void sb600_lpc_enable_resources(device_t dev) sb600_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +extern u16 pm_base; + +void get_bus_conf(void); + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); + return (unsigned long) (acpigen_get_current()); +} + +static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +{ + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + return acpi_write_hpet(start, rsdp); +} +#endif + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -223,6 +245,10 @@ static struct device_operations lpc_ops = { .read_resources = sb600_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = sb600_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .init = lpc_init, .scan_bus = scan_static_bus, /* .enable = sb600_enable, */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a175210..b7c1801 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -24,12 +24,22 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cbmem.h> +#include <cpu/amd/model_fxx_powernow.h> #include "sb700.h" +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + static void lpc_init(device_t dev) { u8 byte; @@ -74,7 +84,6 @@ static void lpc_init(device_t dev) is doing the acpi init */ #if CONFIG_HAVE_ACPI_RESUME { - extern u8 acpi_slp_type; u16 tmp = inw(ACPI_PM1_CNT_BLK); acpi_slp_type = ((tmp & (7 << 10)) >> 10); printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); @@ -259,6 +268,24 @@ static void sb700_lpc_enable_resources(device_t dev) sb700_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +void get_bus_conf(void); + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); + return (unsigned long) (acpigen_get_current()); +} + +static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +{ + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + return acpi_write_hpet(start, rsdp); +} + +#endif + + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -267,6 +294,10 @@ static struct device_operations lpc_ops = { .read_resources = sb700_lpc_read_resources, .set_resources = sb700_lpc_set_resources, .enable_resources = sb700_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index a2ba295..6ef39e3 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -24,6 +24,33 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "ck804.h" +#include <arch/acpi.h> + +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + unsigned long mcfg_base; + + dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); + if (!dev) + return current; + + mcfg_base = pci_read_config16(dev, 0x90); + if ((mcfg_base & 0x1000) == 0) + return current; + + mcfg_base = (mcfg_base & 0xf) << 28; + + printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, mcfg_base, 0x0, 0x0, 0xff); + return current; +} + +#endif static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index b3a9b00..d12dffb 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -30,6 +30,7 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <assert.h> @@ -316,6 +317,9 @@ static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = ck804_lpc_set_resources, .enable_resources = ck804_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_init, .scan_bus = scan_static_bus, // .enable = ck804_enable, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 585232d..6baafea 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -34,7 +34,11 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <cpu/x86/lapic.h> +#include <arch/acpi.h> #include <stdlib.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/model_fxx_powernow.h> #include "mcp55.h" #define NMI_OFF 0 @@ -275,10 +279,24 @@ static const struct pci_driver lpc_driver __pci_driver = { .devices = lpc_ids, }; +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +#endif + static struct device_operations lpc_slave_ops = { .read_resources = mcp55_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_slave_init, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index 464cb6c..0abb9af 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -21,6 +21,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/model_fxx_powernow.h> #include "k8t890.h" extern unsigned long log2(unsigned long x); @@ -122,11 +125,25 @@ static void traf_ctrl_enable_k8t890(struct device *dev) pci_write_config8(dev, 0x60, 0x80 | reg); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +#endif + static const struct device_operations traf_ctrl_ops_m = { .read_resources = apic_mmconfig_read_resources, .set_resources = mmconfig_set_resources, .enable_resources = pci_dev_enable_resources, .enable = traf_ctrl_enable_k8m890, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .ops_pci = 0, }; @@ -135,11 +152,35 @@ static const struct device_operations traf_ctrl_ops_t = { .set_resources = mmconfig_set_resources, .enable_resources = pci_dev_enable_resources, .enable = traf_ctrl_enable_k8t890, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .ops_pci = 0, }; /* K8X800 chipsets have no APIC; no 800 PCI ids here */ +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + static const struct pci_driver northbridge_driver_t __pci_driver = { .ops = &traf_ctrl_ops_t,

1 0

Patch set updated for coreboot: 447af0f NOTFORMERGE: amdk8: Move to per-device ACPI
by Vladimir Serbinenko 23 Sep '14

23 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6948 -gerrit commit 447af0f560926a8ce7be4137cf956e0ca3f62b61 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Sep 21 14:31:19 2014 +0200 NOTFORMERGE: amdk8: Move to per-device ACPI Change-Id: I485791015aa7eaabba53813945c216f5725554b1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/amd/dbm690t/acpi_tables.c | 106 ------------- src/mainboard/amd/mahogany/acpi_tables.c | 157 ------------------- src/mainboard/amd/mahogany_fam10/acpi_tables.c | 6 - src/mainboard/amd/pistachio/acpi_tables.c | 105 ------------- src/mainboard/amd/tilapia_fam10/acpi_tables.c | 6 - src/mainboard/asrock/939a785gmh/acpi_tables.c | 157 ------------------- src/mainboard/asus/a8n_e/acpi_tables.c | 137 ----------------- src/mainboard/asus/a8v-e_deluxe/acpi_tables.c | 93 ------------ src/mainboard/asus/a8v-e_deluxe/dsdt.asl | 7 - src/mainboard/asus/a8v-e_se/acpi_tables.c | 110 -------------- src/mainboard/asus/k8v-x/acpi_tables.c | 110 -------------- src/mainboard/asus/m2v-mx_se/acpi_tables.c | 130 ---------------- src/mainboard/asus/m2v/acpi_tables.c | 131 ---------------- src/mainboard/asus/m4a78-em/acpi_tables.c | 6 - src/mainboard/asus/m4a785-m/acpi_tables.c | 8 - src/mainboard/gigabyte/m57sli/acpi_tables.c | 109 -------------- src/mainboard/gigabyte/ma785gm/acpi_tables.c | 6 - src/mainboard/gigabyte/ma785gmt/acpi_tables.c | 6 - src/mainboard/gigabyte/ma78gm/acpi_tables.c | 6 - src/mainboard/iei/kino-780am2-fam10/acpi_tables.c | 6 - src/mainboard/jetway/pa78vm5/acpi_tables.c | 6 - src/mainboard/kontron/kt690/acpi_tables.c | 105 ------------- src/mainboard/msi/ms7135/acpi_tables.c | 138 ----------------- src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 166 ++------------------- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 4 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 2 + src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 6 - src/mainboard/technexion/tim5690/acpi_tables.c | 105 ------------- src/mainboard/technexion/tim8690/acpi_tables.c | 105 ------------- src/mainboard/tyan/s2891/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2891/mainboard.c | 23 +++ src/mainboard/tyan/s2892/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2892/mainboard.c | 23 +++ src/mainboard/tyan/s2895/acpi_tables.c | 112 -------------- src/mainboard/tyan/s2895/mainboard.c | 23 +++ src/mainboard/winent/mb6047/acpi_tables.c | 112 -------------- src/mainboard/winent/mb6047/mainboard.c | 23 +++ src/northbridge/amd/amdk8/Kconfig | 1 + src/northbridge/amd/amdk8/acpi.c | 4 +- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/amdk8/northbridge.c | 36 +++++ src/southbridge/amd/rs690/ht.c | 18 +++ src/southbridge/amd/sb600/lpc.c | 26 ++++ src/southbridge/amd/sb700/lpc.c | 33 +++- src/southbridge/nvidia/ck804/ht.c | 27 ++++ src/southbridge/nvidia/ck804/lpc.c | 4 + src/southbridge/nvidia/mcp55/lpc.c | 17 +++ src/southbridge/via/k8t890/traf_ctrl.c | 41 +++++ 48 files changed, 316 insertions(+), 2472 deletions(-) diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c index 87ff5ea..3206aaf 100644 --- a/src/mainboard/amd/dbm690t/acpi_tables.c +++ b/src/mainboard/amd/dbm690t/acpi_tables.c @@ -28,25 +28,6 @@ #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/acpi.h" #include <arch/cpu.h> -#include <cpu/amd/model_fxx_powernow.h> - -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} unsigned long acpi_fill_madt(unsigned long current) { @@ -72,90 +53,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/mahogany/acpi_tables.c b/src/mainboard/amd/mahogany/acpi_tables.c index ef2690a..7c94e03 100644 --- a/src/mainboard/amd/mahogany/acpi_tables.c +++ b/src/mainboard/amd/mahogany/acpi_tables.c @@ -28,32 +28,8 @@ #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/acpi.h" #include <arch/cpu.h> -#include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/sb700/sb700.h> -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -78,136 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - - for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ - if ((sysconf.pci1234[i] & 1) != 1) - continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *) current; - switch (sysconf.hcid[i]) { - case 1: /* 8132 */ - p = &AmlCode_ssdt2; - break; - case 2: /* 8151 */ - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c index 01172ad..5efb0ee 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c @@ -60,12 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c index 5ef0da5..717e4b4 100644 --- a/src/mainboard/amd/pistachio/acpi_tables.c +++ b/src/mainboard/amd/pistachio/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -73,90 +55,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c index 898a955..8d7f723 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ b/src/mainboard/amd/tilapia_fam10/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/asrock/939a785gmh/acpi_tables.c b/src/mainboard/asrock/939a785gmh/acpi_tables.c index 52b45f7..e6369df 100644 --- a/src/mainboard/asrock/939a785gmh/acpi_tables.c +++ b/src/mainboard/asrock/939a785gmh/acpi_tables.c @@ -31,29 +31,6 @@ #include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/sb700/sb700.h> -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -78,137 +55,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ - - for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ - if ((sysconf.pci1234[i] & 1) != 1) - continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *) current; - switch (sysconf.hcid[i]) { - case 1: /* 8132 */ - p = &AmlCode_ssdt2; - break; - case 2: /* 8151 */ - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/a8n_e/acpi_tables.c b/src/mainboard/asus/a8n_e/acpi_tables.c index ee8e81f..2e06915 100644 --- a/src/mainboard/asus/a8n_e/acpi_tables.c +++ b/src/mainboard/asus/a8n_e/acpi_tables.c @@ -21,30 +21,6 @@ #include "../../../northbridge/amd/amdk8/acpi.h" //#include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - unsigned long mcfg_base; - - dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); - if (!dev) - return current; - - mcfg_base = pci_read_config16(dev, 0x90); - if ((mcfg_base & 0x1000) == 0) - return current; - - mcfg_base = (mcfg_base & 0xf) << 28; - - printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, mcfg_base, 0x0, 0x0, 0xff); - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -86,116 +62,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - //amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - mcfg = (acpi_mcfg_t *) current; - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p\n", mcfg); - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - current += hpet->header.length; - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c b/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c index 30914e4..e2fa0f0 100644 --- a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c @@ -32,25 +32,6 @@ #include "southbridge/via/vt8237r/vt8237r.h" #include "southbridge/via/k8t890/k8t890.h" -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -80,77 +61,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl index 3afcdc3..8f1e197 100644 --- a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl +++ b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl @@ -24,13 +24,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { - /* Define the main processor.*/ - Scope (\_PR) - { - Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} - Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} - } - /* For now only define 2 power states: * - S0 which is fully on * - S5 which is soft off diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c index f5f081a..2a874db 100644 --- a/src/mainboard/asus/a8v-e_se/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c @@ -34,25 +34,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -82,94 +63,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 065db1a..da4c399 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -34,25 +34,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -82,94 +63,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* If we want to use HPET timers Linux wants it in MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 91a5da1..dab35d4 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -35,25 +35,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -83,114 +64,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/asus/m2v/acpi_tables.c b/src/mainboard/asus/m2v/acpi_tables.c index cc1070e..7ad045c 100644 --- a/src/mainboard/asus/m2v/acpi_tables.c +++ b/src/mainboard/asus/m2v/acpi_tables.c @@ -36,25 +36,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - struct resource *res; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); - if (!dev) - return current; - - res = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, res->base, 0x0, 0x0, 0xff); - } - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; @@ -84,115 +65,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - - return current; -} diff --git a/src/mainboard/asus/m4a78-em/acpi_tables.c b/src/mainboard/asus/m4a78-em/acpi_tables.c index 2398c01..a132b7b 100644 --- a/src/mainboard/asus/m4a78-em/acpi_tables.c +++ b/src/mainboard/asus/m4a78-em/acpi_tables.c @@ -38,12 +38,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index a8b6365..1c0afeb 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -60,14 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } - - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c index 2e2e590..81ebd90 100644 --- a/src/mainboard/gigabyte/m57sli/acpi_tables.c +++ b/src/mainboard/gigabyte/m57sli/acpi_tables.c @@ -92,112 +92,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) -{ - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT table. */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - - /* we should align FACS to 64B as per ACPI specs */ - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - dsdt->checksum = 0; /* Don't trust iasl to get this right. */ - dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET timers Linux wants an MADT. */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp, slit); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c index 7a5df88..e961b6e 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c index 07b174c..3b776ae 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c @@ -37,12 +37,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/gigabyte/ma78gm/acpi_tables.c b/src/mainboard/gigabyte/ma78gm/acpi_tables.c index 07b174c..3b776ae 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma78gm/acpi_tables.c @@ -37,12 +37,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c index 01172ad..5efb0ee 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c +++ b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c @@ -60,12 +60,6 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta return (unsigned long) (acpigen_get_current()); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/jetway/pa78vm5/acpi_tables.c b/src/mainboard/jetway/pa78vm5/acpi_tables.c index fc6f186..eac5619 100644 --- a/src/mainboard/jetway/pa78vm5/acpi_tables.c +++ b/src/mainboard/jetway/pa78vm5/acpi_tables.c @@ -38,12 +38,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/mainboard/kontron/kt690/acpi_tables.c b/src/mainboard/kontron/kt690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/kontron/kt690/acpi_tables.c +++ b/src/mainboard/kontron/kt690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c index ee8e81f..f5ddec3 100644 --- a/src/mainboard/msi/ms7135/acpi_tables.c +++ b/src/mainboard/msi/ms7135/acpi_tables.c @@ -19,31 +19,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> #include "../../../northbridge/amd/amdk8/acpi.h" -//#include <cpu/amd/model_fxx_powernow.h> - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - unsigned long mcfg_base; - - dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); - if (!dev) - return current; - - mcfg_base = pci_read_config16(dev, 0x90); - if ((mcfg_base & 0x1000) == 0) - return current; - - mcfg_base = (mcfg_base & 0xf) << 28; - - printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) - current, mcfg_base, 0x0, 0x0, 0xff); - return current; -} /* APIC */ unsigned long acpi_fill_madt(unsigned long current) @@ -86,116 +61,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - //amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - mcfg = (acpi_mcfg_t *) current; - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p\n", mcfg); - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - current += hpet->header.length; - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index 18e1bf9..d092308 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -33,16 +33,9 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> #include <southbridge/amd/rs690/rs690.h> +#include "mainboard.h" +#include <cbmem.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 #define GLOBAL_VARS_SIZE 0x100 typedef struct { @@ -70,24 +63,6 @@ static void acpi_write_gvars(global_vars_t *gvars) gvars->mpen = 1; } -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - struct resource *res; - resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default - - device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); - // we report mmconf base - res = probe_resource(dev, 0x1C); - if( res ) - mmconf_base = res->base; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? - - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -116,133 +91,20 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} +unsigned long mainboard_fill_ssdt(unsigned long current, const char *oem_table_id) +{ + global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE); -#define ALIGN_CURRENT current = (ALIGN(current, 16)) + if (gnvs) { + int scopelen; + acpi_write_gvars(gnvs); -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_srat_t *srat; - acpi_xsdt_t *xsdt; - acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - current = start; - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - /* - * We explicitly add these tables later on: - */ - current = ALIGN(current, 64); - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - acpi_create_facs(facs); - current += sizeof(acpi_facs_t); - - /* HPET */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - acpi_create_hpet(hpet); - current += sizeof(acpi_hpet_t); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* MCFG */ - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - /* Pack gvars into the ACPI table area */ - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xBADEAFFE) { - printk(BIOS_DEBUG, "ACPI: Patching up globals in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); - *(u32*)(((u32)dsdt) + i) = current; - break; - } + /* Add it to SSDT. */ + scopelen = acpigen_write_scope("\\"); + scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_patch_len(scopelen - 1); } - /* And fill it */ - acpi_write_gvars((global_vars_t *)current); - current += GLOBAL_VARS_SIZE; - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* SRAT */ - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - acpi_add_table(rsdp, srat); - - printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + return (unsigned long) (acpigen_get_current()); } + diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 7890df7..e106561 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -245,7 +245,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) PWDA, 1, } - OperationRegion (GVAR, SystemMemory, 0xBADEAFFE, 0x100) + External(\NVSA) + + OperationRegion (GVAR, SystemMemory, \NVSA, 0x100) Field (GVAR, ByteAcc, NoLock, Preserve) { Offset (0x00), diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 960496f..066dfb4 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -38,6 +38,7 @@ #include <x86emu/x86emu.h> #endif #include "int15_func.h" +#include "mainboard.h" // ****LCD panel ID support: ***** // Callback Sub-Function 00h - Get LCD Panel ID @@ -846,6 +847,7 @@ static void mainboard_enable(device_t dev) update_subsystemid(dev); dev->ops->init = mainboard_init; // rest of mainboard init later + dev->ops->acpi_fill_ssdt_generator = mainboard_fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index ae9cca9..48a396e 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -39,12 +39,6 @@ extern const unsigned char AmlCode_ssdt4[]; extern const unsigned char AmlCode_ssdt5[]; #endif -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { device_t dev; diff --git a/src/mainboard/technexion/tim5690/acpi_tables.c b/src/mainboard/technexion/tim5690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/technexion/tim5690/acpi_tables.c +++ b/src/mainboard/technexion/tim5690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c index 520dc6c..4429370 100644 --- a/src/mainboard/technexion/tim8690/acpi_tables.c +++ b/src/mainboard/technexion/tim8690/acpi_tables.c @@ -30,24 +30,6 @@ #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> -extern u16 pm_base; - -/* -* Assume the max pstate number is 8 -* 0x21(33 bytes) is one package length of _PSS package -*/ - -#define Maxpstate 8 -#define Defpkglength 0x21 - -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ @@ -72,90 +54,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SSDT */ - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); - /* FADT */ - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c index 42d9152..424d87e 100644 --- a/src/mainboard/tyan/s2891/acpi_tables.c +++ b/src/mainboard/tyan/s2891/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -83,108 +76,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c index 42d9152..424d87e 100644 --- a/src/mainboard/tyan/s2892/acpi_tables.c +++ b/src/mainboard/tyan/s2892/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -83,108 +76,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c index 1974171..fe8d0c3 100644 --- a/src/mainboard/tyan/s2895/acpi_tables.c +++ b/src/mainboard/tyan/s2895/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -102,108 +95,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 1b59fbb..5cf5f55 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -20,13 +20,6 @@ #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> -extern const unsigned char AmlCode[]; - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - /* APIC */ unsigned long acpi_fill_madt(unsigned long current) { @@ -67,108 +60,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { - k8acpi_write_vars(); - amd_model_fxx_generate_powernow(0, 0, 0); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_srat_t *srat; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16 byte. */ - start = ALIGN(start, 16); - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - - current = ALIGN(current, 16); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* Clear all table memory. */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - current = ALIGN(current, 64); - facs = (acpi_facs_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs); - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* DSDT */ - current = ALIGN(current, 16); - dsdt = (acpi_header_t *) current; - printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt); - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - current = ALIGN(current, 16); - fadt = (acpi_fadt_t *) current; - printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt); - current += sizeof(acpi_fadt_t); - - /* Add FADT now that we have facs and dsdt. */ - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - current = ALIGN(current, 16); - hpet = (acpi_hpet_t *) current; - printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet); - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - current = ALIGN(current, 16); - madt = (acpi_madt_t *) current; - printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt); - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - current = ALIGN(current, 16); - srat = (acpi_srat_t *) current; - printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); - acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 16); - slit = (acpi_slit_t *) current; - printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); - - /* SSDT */ - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current); - return current; -} diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c new file mode 100644 index 0000000..204268c --- /dev/null +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -0,0 +1,23 @@ +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/amdk8_sysconf.h> + +extern u16 pm_base; + +static unsigned long mainboard_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 3f8861e..e79b6b2 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -23,6 +23,7 @@ config NORTHBRIDGE_AMD_AMDK8 select HAVE_DEBUG_SMBUS select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT + select PER_DEVICE_ACPI_TABLES if NORTHBRIDGE_AMD_AMDK8 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index f7134f6..499f3d2 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -253,7 +253,7 @@ static int k8acpi_write_pci_data(int dlen, const char *name, int offset) { return len + lenp; } -int k8acpi_write_vars(void) +unsigned long k8acpi_write_vars(unsigned long current, const char *oem_table_id) { int lens; msr_t msr; @@ -283,7 +283,7 @@ int k8acpi_write_vars(void) lens += k8acpi_write_HT(); //minus opcode acpigen_patch_len(lens - 1); - return lens; + return (unsigned long) (acpigen_get_current()); } void update_ssdtx(void *ssdtx, int i) diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index 9d0a73a..0570716 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -21,6 +21,6 @@ #define AMDK8_ACPI_H #include <arch/acpigen.h> -int k8acpi_write_vars(void); +unsigned long k8acpi_write_vars(unsigned long current, const char *oem_table_id); #endif diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 2c19b3a..bfd2c0f 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -16,6 +16,10 @@ #include <string.h> #include <lib.h> #include <cpu/cpu.h> +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +#include <arch/acpi.h> +#include "acpi.h" +#endif #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> @@ -580,10 +584,42 @@ static void mcf0_control_init(struct device *dev) #endif } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +static unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +{ + unsigned long current; + acpi_srat_t *srat; + acpi_slit_t *slit; + + current = start; + + current = ALIGN(current, 16); + srat = (acpi_srat_t *) current; + printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat); + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 16); + slit = (acpi_slit_t *) current; + printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit); + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit); + + return current; +} +#endif + static struct device_operations northbridge_operations = { .read_resources = amdk8_read_resources, .set_resources = amdk8_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .acpi_fill_ssdt_generator = k8acpi_write_vars, + .write_acpi_tables = northbridge_write_acpi_tables, +#endif .init = mcf0_control_init, .scan_bus = amdk8_scan_chains, .enable = 0, diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index 7353f76..33fce0f 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <lib.h> +#include <arch/acpi.h> #include "rs690.h" static void ht_dev_set_resources(device_t dev) @@ -84,6 +85,23 @@ static void ht_dev_set_resources(device_t dev) pci_dev_set_resources(dev); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ +#if CONFIG_EXT_CONF_SUPPORT + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default + + device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); + // we report mmconf base + res = probe_resource(dev, 0x1C); + if( res ) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? +#endif + return current; +} + static void ht_dev_read_resources(device_t dev) { #if CONFIG_EXT_CONF_SUPPORT diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 7ef49d1..10616ce 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -24,9 +24,13 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> #include "sb600.h" static void lpc_init(device_t dev) @@ -215,6 +219,24 @@ static void sb600_lpc_enable_resources(device_t dev) sb600_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +extern u16 pm_base; + +void get_bus_conf(void); + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); + return (unsigned long) (acpigen_get_current()); +} + +static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +{ + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + return acpi_write_hpet(start, rsdp); +} +#endif + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -223,6 +245,10 @@ static struct device_operations lpc_ops = { .read_resources = sb600_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = sb600_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .init = lpc_init, .scan_bus = scan_static_bus, /* .enable = sb600_enable, */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a175210..b7c1801 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -24,12 +24,22 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cbmem.h> +#include <cpu/amd/model_fxx_powernow.h> #include "sb700.h" +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + static void lpc_init(device_t dev) { u8 byte; @@ -74,7 +84,6 @@ static void lpc_init(device_t dev) is doing the acpi init */ #if CONFIG_HAVE_ACPI_RESUME { - extern u8 acpi_slp_type; u16 tmp = inw(ACPI_PM1_CNT_BLK); acpi_slp_type = ((tmp & (7 << 10)) >> 10); printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); @@ -259,6 +268,24 @@ static void sb700_lpc_enable_resources(device_t dev) sb700_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +void get_bus_conf(void); + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); + return (unsigned long) (acpigen_get_current()); +} + +static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +{ + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + return acpi_write_hpet(start, rsdp); +} + +#endif + + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -267,6 +294,10 @@ static struct device_operations lpc_ops = { .read_resources = sb700_lpc_read_resources, .set_resources = sb700_lpc_set_resources, .enable_resources = sb700_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index a2ba295..6ef39e3 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -24,6 +24,33 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "ck804.h" +#include <arch/acpi.h> + +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + unsigned long mcfg_base; + + dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); + if (!dev) + return current; + + mcfg_base = pci_read_config16(dev, 0x90); + if ((mcfg_base & 0x1000) == 0) + return current; + + mcfg_base = (mcfg_base & 0xf) << 28; + + printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, mcfg_base, 0x0, 0x0, 0xff); + return current; +} + +#endif static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index b3a9b00..d12dffb 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -30,6 +30,7 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <assert.h> @@ -316,6 +317,9 @@ static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = ck804_lpc_set_resources, .enable_resources = ck804_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_init, .scan_bus = scan_static_bus, // .enable = ck804_enable, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 585232d..29f653c 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -34,7 +34,10 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <cpu/x86/lapic.h> +#include <arch/acpi.h> #include <stdlib.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> #include "mcp55.h" #define NMI_OFF 0 @@ -275,10 +278,24 @@ static const struct pci_driver lpc_driver __pci_driver = { .devices = lpc_ids, }; +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +#endif + static struct device_operations lpc_slave_ops = { .read_resources = mcp55_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_slave_init, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index 464cb6c..0abb9af 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -21,6 +21,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/model_fxx_powernow.h> #include "k8t890.h" extern unsigned long log2(unsigned long x); @@ -122,11 +125,25 @@ static void traf_ctrl_enable_k8t890(struct device *dev) pci_write_config8(dev, 0x60, 0x80 | reg); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + +static unsigned long southbridge_acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +#endif + static const struct device_operations traf_ctrl_ops_m = { .read_resources = apic_mmconfig_read_resources, .set_resources = mmconfig_set_resources, .enable_resources = pci_dev_enable_resources, .enable = traf_ctrl_enable_k8m890, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .ops_pci = 0, }; @@ -135,11 +152,35 @@ static const struct device_operations traf_ctrl_ops_t = { .set_resources = mmconfig_set_resources, .enable_resources = pci_dev_enable_resources, .enable = traf_ctrl_enable_k8t890, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .ops_pci = 0, }; /* K8X800 chipsets have no APIC; no 800 PCI ids here */ +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + static const struct pci_driver northbridge_driver_t __pci_driver = { .ops = &traf_ctrl_ops_t,

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coreboot-gerrit September 2014