coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: f09f224 arm: libpayload: Make cache invalidation take pointers instead of integers
by gerrit＠coreboot.org 29 Aug '14

29 Aug '14

the following patch was just integrated into master: commit f09f2247d7584975d17a7d4755b279c1c3f6f001 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Aug 28 14:43:14 2013 -0700 arm: libpayload: Make cache invalidation take pointers instead of integers This minor refactoring patch changes the signature of all limited cache invalidation functions in coreboot and libpayload from unsigned long to void * for the address argument, since that's really what you have in 95% of the cases and I think it's ugly to have casting boilerplate all over the place. Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167338 (cherry picked from commit d550bec944736dfa29fcf109e30f17a94af03576) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6623 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6623 for details. -gerrit

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Patch set updated for coreboot: 132d265 AMD Steppe Eagle: Add 32-bit Fletcher's Checksum computation
by Bruce Griffith 29 Aug '14

29 Aug '14

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6676 -gerrit commit 132d265f9bf5ccd21f6478f998325a9de1f045df Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed Jul 16 11:25:21 2014 -0600 AMD Steppe Eagle: Add 32-bit Fletcher's Checksum computation The AMD Platform Security Processor (PSP) requires a Fletcher's Checksum at the end of the PSP directory. This code implements a Fletcher's Checksum by reading bytes from stdin and writes the bytes back to stdout with a checksum inserted into the byte stream at the appropriate offset. This utility is used on PSP binaries during coreboot build. Include a runtime debug option such that the command: fletcher --print <file.bin >file_with_cksum.bin will print out the computed checksum value for debugging. The compile-time debug option is retained that allows -DDEBUG to be added to the compilation line. This option has the same effect as "--print". Change-Id: I506a479d8204ca4f8267d53aa152ac4b473dbc75 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- util/fletcher/Makefile | 37 ++++++++++++++ util/fletcher/fletcher.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 165 insertions(+) diff --git a/util/fletcher/Makefile b/util/fletcher/Makefile new file mode 100644 index 0000000..4f3957c --- /dev/null +++ b/util/fletcher/Makefile @@ -0,0 +1,37 @@ +#***************************************************************************** +# +# Copyright (c) 2014, Sage Electronic Engineering, LLC +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** +HOSTCC ?= gcc + +fletcher_exe : fletcher.c + $(HOSTCC) fletcher.c -o fletcher + +fletcher : fletcher_exe + +clean: + @rm -f fletcher.o fletcher fletcher.exe diff --git a/util/fletcher/fletcher.c b/util/fletcher/fletcher.c new file mode 100644 index 0000000..3147d50 --- /dev/null +++ b/util/fletcher/fletcher.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 1998-2006 The TCPDUMP project + * 2014 Sage Electronic Engineering, LLC + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that: (1) source code + * distributions retain the above copyright notice and this paragraph + * in its entirety, and (2) distributions including binary code include + * the above copyright notice and this paragraph in its entirety in + * the documentation or other materials provided with the distribution. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND + * WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT + * LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Original code by Hannes Gredler <hannes(a)juniper.net> + * Rewritten for Fletcher32 by Bruce Griffith <Bruce.Griffith(a)se-eng.com> + */ + +#include <errno.h> +#include <stdio.h> +#include <sys/stat.h> +#include <sys/types.h> +#include <unistd.h> +#include <string.h> + +#define MAX_PSP_DIRECTORY_SIZE 512 + +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; + +/* + * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. + * The checksum field of the passed PDU does not need to be reset to zero. + * + * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of + * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an + * alternative to cyclical redundancy checks because it provides error- + * detection properties similar to cyclical redundancy checks but at the + * cost of a simple summation technique. Its characteristics were first + * published in IEEE Transactions on Communications in January 1982. One + * version has been adopted by ISO for use in the class-4 transport layer + * of the network protocol. + * + * This program expects: + * stdin: The input file to compute a checksum for. The input file + * not be longer than 256 bytes. + * stdout: Copied from the input file with the Fletcher's Checksum + * inserted 8 bytes after the beginning of the file. + * stderr: Used to print out error messages. + */ + +uint32_t fletcher32 (const uint16_t *pptr, int length) +{ + + uint32_t c0; + uint32_t c1; + uint32_t checksum; + int index; + + c0 = 0xFFFF; + c1 = 0xFFFF; + + for (index = 0; index < length; index++) { + /* + * Ignore the contents of the checksum field. + */ + c0 += *(pptr++); + c1 += c0; + if ((index % 360) == 0) { + c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow + c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow + } + + } + + c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow + c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow + checksum = (c1 << 16) | c0; + + return checksum; +} + +int main(int argc, char **argv) +{ + uint32_t checksum = 0xFFFFFFFF; + struct stat filestat = {}; + int retcode = EINVAL; + size_t filesize = 0; + char debugoption[] = "--print"; + + uint16_t buffer[MAX_PSP_DIRECTORY_SIZE / sizeof(uint16_t)]; + + retcode = fstat(fileno(stdin), &filestat); + filesize = filestat.st_size; + if (retcode < 0) { + perror("FLETCHER32"); + return errno; + } else if (!((12 < filesize) && (filesize <= sizeof(buffer)))) { + fprintf(stderr, "FLETCHER32: input file is not valid for this program.\n"); + return EINVAL; + } + retcode = read(fileno(stdin), (void *)buffer, filesize); + if (retcode < 0) { + perror("FLETCHER32"); + return errno; + } + + checksum = fletcher32(&buffer[2], filesize/2 - 2); + *((uint32_t *)& buffer[2]) = checksum; +#ifndef DEBUG + if ((argc == 2) && !strncmp(argv[1], debugoption, sizeof(debugoption+1))) { +#endif + fprintf(stderr, "Fletcher's Checksum: %x\n", checksum); +#ifndef DEBUG + } +#endif + + retcode = write(fileno(stdout), buffer, filesize); + if (retcode < 0) { + perror("FLETCHER32"); + return errno; + } + + return 0; +}

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Patch set updated for coreboot: 0bc8ea7 samus: Change SPD to indicate LPDDR
by Stefan Reinauer 28 Aug '14

28 Aug '14

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6777 -gerrit commit 0bc8ea7fce54bd397f0c70c10a2a248f11d646de Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 4 11:49:29 2013 -0700 samus: Change SPD to indicate LPDDR There is some magic new SPD SDRAM type 241 to indicate LPDDR. I cannot find it specificed in any JEDEC document but it is what the reference code uses. Change-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171900 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 0a1385515c62fd1e534b12568df8aaf2170e06f4) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/samus/micron_4Gb.spd.hex | 2 +- src/mainboard/google/samus/micron_8Gb.spd.hex | 2 +- src/mainboard/google/samus/samsung_4Gb.spd.hex | 2 +- src/mainboard/google/samus/samsung_8Gb.spd.hex | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/samus/micron_4Gb.spd.hex b/src/mainboard/google/samus/micron_4Gb.spd.hex index de3149a..fff0786 100644 --- a/src/mainboard/google/samus/micron_4Gb.spd.hex +++ b/src/mainboard/google/samus/micron_4Gb.spd.hex @@ -1,4 +1,4 @@ -92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +92 11 F1 03 04 19 02 02 03 11 01 08 0A 00 FE 00 69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 diff --git a/src/mainboard/google/samus/micron_8Gb.spd.hex b/src/mainboard/google/samus/micron_8Gb.spd.hex index 8848470..5900ad6 100644 --- a/src/mainboard/google/samus/micron_8Gb.spd.hex +++ b/src/mainboard/google/samus/micron_8Gb.spd.hex @@ -1,4 +1,4 @@ -92 11 0B 03 04 19 02 0A 03 11 01 08 0A 00 FE 00 +92 11 F1 03 04 19 02 0A 03 11 01 08 0A 00 FE 00 69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 diff --git a/src/mainboard/google/samus/samsung_4Gb.spd.hex b/src/mainboard/google/samus/samsung_4Gb.spd.hex index c8c2918..4d3eba9 100644 --- a/src/mainboard/google/samus/samsung_4Gb.spd.hex +++ b/src/mainboard/google/samus/samsung_4Gb.spd.hex @@ -1,4 +1,4 @@ -92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +92 11 F1 03 04 19 02 02 03 11 01 08 0A 00 FE 00 69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 diff --git a/src/mainboard/google/samus/samsung_8Gb.spd.hex b/src/mainboard/google/samus/samsung_8Gb.spd.hex index 0cc8431..85e2be4 100644 --- a/src/mainboard/google/samus/samsung_8Gb.spd.hex +++ b/src/mainboard/google/samus/samsung_8Gb.spd.hex @@ -1,4 +1,4 @@ -92 11 0B 03 04 19 02 0A 03 11 01 08 0A 00 FE 00 +92 11 F1 03 04 19 02 0A 03 11 01 08 0A 00 FE 00 69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00

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New patch to review for coreboot: 8de3119 Increase space for ACPI tables when using dynamic CBMEM
by Stefan Reinauer 28 Aug '14

28 Aug '14

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6795 -gerrit commit 8de3119d6a6ad05c726665735229f64164a3e12c Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Aug 28 23:03:15 2014 +0200 Increase space for ACPI tables when using dynamic CBMEM Unlike in old style CBMEM, dynamic CBMEM will not waste unused space, so allow up to 144K of space for ACPI tables. Change-Id: Id9dd7447c46d5fe7ed581be753d70e59add05320 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/tables.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 16c752a..42b8a67 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -109,7 +109,11 @@ void write_tables(void) #endif /* CONFIG_GENERATE_MP_TABLE */ #if CONFIG_GENERATE_ACPI_TABLES +#if CONFIG_DYNAMIC_CBMEM +#define MAX_ACPI_SIZE (144 * 1024) +#else #define MAX_ACPI_SIZE (45 * 1024) +#endif post_code(0x9c); /* Write ACPI tables to F segment and high tables area */

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Patch set updated for coreboot: f082fee i945/early_init Add FSB 800MHz and fix Bit 49 of CAPID0
by HAOUAS Elyes 28 Aug '14

28 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6794 -gerrit commit f082fee4730654328a4ae8e5df7c09c367b71c14 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Aug 28 19:42:29 2014 +0200 i945/early_init Add FSB 800MHz and fix Bit 49 of CAPID0 device 0:0f.0 do not exit. the CAPID0 is for D0:F0 , see datasheet mobile-945-express-chipset-datasheet.pdf page 109. Change-Id: Ia0909866e2c8dd30b7f532ff184728bbdaf07b2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/early_init.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..5424899 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,10 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: /* 945G/945GZ/945GC/945P/945PL */ + printk(BIOS_DEBUG, "up to DDR2-667"); + break; + case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,7 +198,7 @@ static void i945_setup_bars(void) /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -226,6 +230,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 = 0x00000014; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +248,11 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; } + if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 4) = 0x00f000f0; + } + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0;

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Patch set updated for coreboot: 88942c5 i945/early_init Add FSB 800MHz and fix Bit 49 of CAPID0
by HAOUAS Elyes 28 Aug '14

28 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6794 -gerrit commit 88942c50da68166236a0bec1bc3574b696b2fd72 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Aug 28 19:42:29 2014 +0200 i945/early_init Add FSB 800MHz and fix Bit 49 of CAPID0 Change-Id: Ia0909866e2c8dd30b7f532ff184728bbdaf07b2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/early_init.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..5424899 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,10 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: /* 945G/945GZ/945GC/945P/945PL */ + printk(BIOS_DEBUG, "up to DDR2-667"); + break; + case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,7 +198,7 @@ static void i945_setup_bars(void) /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -226,6 +230,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 = 0x00000014; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +248,11 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; } + if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 4) = 0x00f000f0; + } + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0;

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New patch to review for coreboot: 4b17a10 i945/early_init Add FSB 800MHz and fix Bit 49 of CAPID0
by HAOUAS Elyes 28 Aug '14

28 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6794 -gerrit commit 4b17a101458ace96dc3e5a22a6ada91de1a2a78b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Aug 28 19:42:29 2014 +0200 i945/early_init Add FSB 800MHz and fix Bit 49 of CAPID0 Change-Id: Ia0909866e2c8dd30b7f532ff184728bbdaf07b2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/early_init.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..603a89b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,10 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: /* 945G/945GZ/945GC/945P/945PL */ + printk(BIOS_DEBUG, "up to DDR2-667"); + break; + case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,7 +198,7 @@ static void i945_setup_bars(void) /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -226,6 +230,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 = 0x00000014; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +248,10 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; } + if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 4) = 0x00f000f0; + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0;

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Patch set updated for coreboot: 58269bd qemu: make MAX_ACPI_SIZE big enougth for qemu 2.1+
by Gerd Hoffmann 28 Aug '14

28 Aug '14

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6773 -gerrit commit 58269bd8c92189215a977231190a3031e673f9f9 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Wed Aug 27 13:22:20 2014 +0200 qemu: make MAX_ACPI_SIZE big enougth for qemu 2.1+ The size allocated for acpi tables in the recently released qemu 2.1 version has changed. In 2.0 it was automatically sized according to the actual size of the acpi tables. Which caused problems because the allocation size could change depending on qemu version and guest configuration. Now it is 128k fixed, which should be enougth even for very large guests. Problem with that is that MAX_ACPI_SIZE is 45k, i.e. too small. This patch adds a MAX_ACPI_SIZE_KB config option, defaulting to the traditional 45, which can be overridden by boards if needed. The new option is used to set the size for the qemu bords to 129k (128k for the bulk of tables plus some extra space for the rdsp table). Change-Id: I1268a4a443583f7a856d4b2e6416b866026d52bc Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/Kconfig | 5 +++++ src/arch/x86/boot/tables.c | 2 +- src/mainboard/emulation/qemu-i440fx/Kconfig | 4 ++++ src/mainboard/emulation/qemu-q35/Kconfig | 4 ++++ 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 6b674ed..f9893a7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -476,6 +476,11 @@ config GENERATE_ACPI_TABLES If unsure, say Y. +config MAX_ACPI_SIZE_KB + int + default 45 + depends on GENERATE_ACPI_TABLES + config GENERATE_MP_TABLE prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC bool diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 16c752a..22b0abc 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -109,7 +109,7 @@ void write_tables(void) #endif /* CONFIG_GENERATE_MP_TABLE */ #if CONFIG_GENERATE_ACPI_TABLES -#define MAX_ACPI_SIZE (45 * 1024) +#define MAX_ACPI_SIZE (CONFIG_MAX_ACPI_SIZE_KB * 1024) post_code(0x9c); /* Write ACPI tables to F segment and high tables area */ diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 34f3342..48f64a0 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -33,4 +33,8 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config MAX_ACPI_SIZE_KB + int + default 129 + endif # BOARD_EMULATION_QEMU_X86_I440FX diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3949937..9c6d086 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -44,4 +44,8 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config MAX_ACPI_SIZE_KB + int + default 129 + endif # BOARD_EMULATION_QEMU_X86_Q35

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Patch merged into coreboot/master: 7d7eedd soc/intel/baytrail/Kconfig: Remove empty line at top file
by gerrit＠coreboot.org 28 Aug '14

28 Aug '14

the following patch was just integrated into master: commit 7d7eeddbbdc3f39f351cf091bc1f920cf4799c85 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Aug 15 07:28:44 2014 +0200 soc/intel/baytrail/Kconfig: Remove empty line at top file Change-Id: I932e4566ec6313a7f2dbd58784bde71bca12abd7 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6671 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6671 for details. -gerrit

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Patch merged into coreboot/master: acfe1e5 qemu: log acpi table size
by gerrit＠coreboot.org 28 Aug '14

28 Aug '14

the following patch was just integrated into master: commit acfe1e5966ad2ea69c373ea613ec492007ac0129 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Wed Aug 27 13:21:43 2014 +0200 qemu: log acpi table size Change-Id: Ib2d7a3d9bda94f80886da96c2b766d29fc15a834 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-on: http://review.coreboot.org/6772 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/6772 for details. -gerrit

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coreboot-gerrit August 2014