coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 576ceed ec/lenovo/h8: return correctly typed package if battery is absent
by Vladimir Serbinenko 29 Aug '14

29 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6793 -gerrit commit 576ceed90cb3ebf495c65f0975c700c69b1a2968 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Aug 28 01:14:00 2014 +0200 ec/lenovo/h8: return correctly typed package if battery is absent Fixes "Discharge rate invalid message" and fwts error. Change-Id: I51f9d819f164552567d75f83c95ba7523e97343e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/acpi/battery.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 7dd49fe..6abd4a5 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -223,7 +223,7 @@ Device (BAT0) if (B0PR) { Return (BSTA(0, BATI, B0CH, B0DI)) } else { - Return (BATS) + Return (Package () { 0, 0, 0, 0 }) } } @@ -281,7 +281,7 @@ Device (BAT1) if (B1PR) { Return (BSTA(0x10, BATI, B1CH, B1DI)) } else { - Return (BATS) + Return (Package () { 0, 0, 0, 0 }) } }

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New patch to review for coreboot: 7ba91cc build: add what-jenkins-does target
by Patrick Georgi 29 Aug '14

29 Aug '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6797 -gerrit commit 7ba91ccd57e0e4c5b3cde19791962fed70df9b36 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Aug 29 20:10:38 2014 +0200 build: add what-jenkins-does target This target does (pretty much) exactly the same what jenkins is doing on our build nodes: - complete abuild run of our tree with a given payload - building all libpayload configs we ship - building the cbmem utility In fact at some point we could tell jenkins to just run this command. For debugging, pass along V and Q variables so inner make processes are slightly more noisy on demand. Change-Id: Ib515170603a151cc3c3b10c743f1468a9875dbdc Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile.inc | 6 ++++++ payloads/libpayload/Makefile.inc | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index d757c89..ad5064b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -560,3 +560,9 @@ $(obj)/coreboot.pre: $(objcbfs)/$(ROMSTAGE_ELF) $(obj)/coreboot.pre1 $(CBFSTOOL) -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ $(CBFSTOOL_PRE_OPTS) mv $@.tmp $@ + +JENKINS_PAYLOAD=none +what-jenkins-does: + util/abuild/abuild -B -J -y -c 4 -p $(JENKINS_PAYLOAD) + (cd payloads/libpayload; $(MAKE) CONFIG_CCACHE=y V=$(V) Q=$(Q) junit.xml) + $(MAKE) V=$(V) Q=$(Q) -C util/cbmem junit.xml diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index a5de4b3..5eeb907 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -122,9 +122,9 @@ junit.xml: echo '<?xml version="1.0" encoding="utf-8"?><testsuite>' > $@.tmp for i in $(filter-out %.old,$(wildcard configs/*)); do \ $(MAKE) clean; \ - yes | $(MAKE) oldconfig DOTCONFIG=$$i 2>/dev/null >/dev/null; \ + yes | $(MAKE) oldconfig DOTCONFIG=$$i V=$(V) Q=$(Q) 2>/dev/null >/dev/null; \ echo "<testcase classname='libpayload' name='$$i'>" >> $@.tmp; \ - $(MAKE) CONFIG_CCACHE=$(CONFIG_CCACHE) DOTCONFIG=$$i >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ + $(MAKE) V=$(V) Q=$(Q) CONFIG_CCACHE=$(CONFIG_CCACHE) DOTCONFIG=$$i >> $@.tmp.2 2>&1 && type="system-out" || type="failure"; \ if [ $$type = "failure" ]; then \ echo "<failure type='buildFailed'>" >> $@.tmp; \ else \

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Patch merged into coreboot/master: 71c0bf6 smbios: Define and use enclosure types.
by gerrit＠coreboot.org 29 Aug '14

29 Aug '14

the following patch was just integrated into master: commit 71c0bf6202bee2c17b3e64b377038207f6018dc6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Aug 27 23:23:14 2014 +0200 smbios: Define and use enclosure types. Change-Id: Ib5b92120cbe2ca41c9813e8caeb03161f4d3954c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6786 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6786 for details. -gerrit

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Patch set updated for coreboot: 4b1cb72 ec/lenovo/h8: return correctly typed package if battery is absent
by Vladimir Serbinenko 29 Aug '14

29 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6793 -gerrit commit 4b1cb7243e1a758e87c9c39f38a92083c2ebd32d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Aug 28 01:14:00 2014 +0200 ec/lenovo/h8: return correctly typed package if battery is absent Change-Id: I51f9d819f164552567d75f83c95ba7523e97343e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/acpi/battery.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 7dd49fe..6abd4a5 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -223,7 +223,7 @@ Device (BAT0) if (B0PR) { Return (BSTA(0, BATI, B0CH, B0DI)) } else { - Return (BATS) + Return (Package () { 0, 0, 0, 0 }) } } @@ -281,7 +281,7 @@ Device (BAT1) if (B1PR) { Return (BSTA(0x10, BATI, B1CH, B1DI)) } else { - Return (BATS) + Return (Package () { 0, 0, 0, 0 }) } }

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Patch set updated for coreboot: 4efa193 ec/lenovo/h8: return correctly typed package if battery is absent
by Vladimir Serbinenko 29 Aug '14

29 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6793 -gerrit commit 4efa19362e467a01a9d3cac7784578baf9479045 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Aug 28 01:14:00 2014 +0200 ec/lenovo/h8: return correctly typed package if battery is absent Change-Id: I51f9d819f164552567d75f83c95ba7523e97343e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/acpi/battery.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 7dd49fe..6abd4a5 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -223,7 +223,7 @@ Device (BAT0) if (B0PR) { Return (BSTA(0, BATI, B0CH, B0DI)) } else { - Return (BATS) + Return (Package () { 0, 0, 0, 0 }) } } @@ -281,7 +281,7 @@ Device (BAT1) if (B1PR) { Return (BSTA(0x10, BATI, B1CH, B1DI)) } else { - Return (BATS) + Return (Package () { 0, 0, 0, 0 }) } }

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New patch to review for coreboot: 960e7f5 cbfstool:linux_trampoline: config CS and DS segment descriptors
by Curt Brune 29 Aug '14

29 Aug '14

Curt Brune (curt(a)cumulusnetworks.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6796 -gerrit commit 960e7f56b1abd277fa1173a9d1c986e882d52537 Author: Curt Brune <curt(a)cumulusnetworks.com> Date: Fri Aug 29 10:43:36 2014 -0700 cbfstool:linux_trampoline: config CS and DS segment descriptors The Linux trampoline code does not set up the segment descriptors for __BOOT_CS and __BOOT_DS as described in the Linux kernel documentation: ... a GDT must be loaded with the descriptors for selectors __BOOT_CS(0x10) and __BOOT_DS(0x18); both descriptors must be 4G flat segment; __BOOT_CS must have execute/read permission, and __BOOT_DS must have read/write permission; This is not a problem when launching a Linux payload from coreboot, as coreboot configures the segment descriptors at selectors 0x10 and 0x18. Coreboot configures these selectors in the ramstage to match what the Linux kernel expects (see coreboot/src/arch/x86/lib/c_start.S). When the cbfs payload is launched in other environments, SeaBIOS for example, the segment descriptors are configured differently and the cbfs Linux payload does not work. If the cbfs Linux payload is to be used in multiple environments should the trampoline needs to take care of the descriptors that Linux requires. This patch updates the Linux trampoline code to configure the 4G flat descriptors that Linux expects. The configuration is borrowed from the descriptor configs in coreboot/src/arch/x86/lib/c_start.S for selectors 0x10 and 0x18. Testing Done: Verified the Linux payload is booted correctly in the following environments: 1. Coreboot -> Linux Payload 2. Coreboot -> SeaBIOS -> Linux Payload: (previously did not work) Change-Id: I888f74ff43073a6b7318f6713a8d4ecb804c0162 Signed-off-by: Curt Brune <curt(a)cumulusnetworks.com> --- util/cbfstool/linux_trampoline.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/util/cbfstool/linux_trampoline.c b/util/cbfstool/linux_trampoline.c index 368d63a..1a1dccf 100644 --- a/util/cbfstool/linux_trampoline.c +++ b/util/cbfstool/linux_trampoline.c @@ -101,6 +101,28 @@ add 4(%ebx), %ebx dec %ecx jnz .tableScan +/* Setup basic code and data segment selectors for Linux +** +** Flat code segment descriptor: +** selector: 0x10 +** base : 0x00000000 +** limit : 0xFFFFFFFF +** type : code, execute, read +** +** Flat data segment descriptor: +** selector: 0x18 +** base : 0x00000000 +** limit : 0xFFFFFFFF +** type : data, read/write +*/ +mov %esp, %eax +sgdt (%eax) +mov 2(%eax), %ebx +movl $0x0000ffff, 16(%ebx) +movl $0x00cf9b00, 20(%ebx) +movl $0x0000ffff, 24(%ebx) +movl $0x00cf9300, 28(%ebx) + /* finally: jump to kernel */ mov $LINUX_PARAM_LOC, %esi jmp *(LINUX_PARAM_LOC + LINUX_ENTRY_OFFSET) @@ -128,13 +150,15 @@ trampoline_size: const unsigned char trampoline[] = { 0xfc, 0x31, 0xd2, 0xb9, 0x00, 0x00, 0x00, 0x00, 0xbb, 0x00, 0x00, 0x01, 0x00, 0x01, 0xcb, 0x8b, 0x01, 0x3d, 0x4c, 0x42, 0x49, 0x4f, 0x74, 0x07, 0x83, 0xc1, 0x10, 0x39, 0xcb, 0x75, 0xe9, 0x39, -0xcb, 0x74, 0x60, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, 0x3b, 0x11, 0x75, 0x05, -0x8b, 0x4b, 0x08, 0xeb, 0xd3, 0x83, 0x3b, 0x01, 0x75, 0x33, 0x8b, 0x43, 0x04, 0x83, 0xe8, 0x08, -0xc1, 0xe8, 0x02, 0x3d, 0xa0, 0x00, 0x00, 0x00, 0x7e, 0x05, 0xb8, 0xa0, 0x00, 0x00, 0x00, 0x89, -0xc6, 0xbf, 0x05, 0x00, 0x00, 0x00, 0xf7, 0xf7, 0xa3, 0xe8, 0x01, 0x09, 0x00, 0x89, 0xf0, 0x91, -0x8d, 0x73, 0x08, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0xf3, 0xa5, 0x91, 0xeb, 0x05, 0x83, 0x3b, 0x12, -0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x75, 0xb3, 0xbe, 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, -0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd +0xcb, 0x0f, 0x84, 0x85, 0x00, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, +0x3b, 0x11, 0x75, 0x05, 0x8b, 0x4b, 0x08, 0xeb, 0xcf, 0x83, 0x3b, 0x01, 0x75, 0x33, 0x8b, 0x43, +0x04, 0x83, 0xe8, 0x08, 0xc1, 0xe8, 0x02, 0x3d, 0xa0, 0x00, 0x00, 0x00, 0x7e, 0x05, 0xb8, 0xa0, +0x00, 0x00, 0x00, 0x89, 0xc6, 0xbf, 0x05, 0x00, 0x00, 0x00, 0xf7, 0xf7, 0xa3, 0xe8, 0x01, 0x09, +0x00, 0x89, 0xf0, 0x91, 0x8d, 0x73, 0x08, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0xf3, 0xa5, 0x91, 0xeb, +0x05, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x75, 0xb3, 0x89, 0xe0, 0x0f, 0x01, +0x00, 0x8b, 0x58, 0x02, 0xc7, 0x43, 0x10, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x43, 0x14, 0x00, 0x9b, +0xcf, 0x00, 0xc7, 0x43, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x43, 0x1c, 0x00, 0x93, 0xcf, 0x00, +0xbe, 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd }; const void * const trampoline_start = &trampoline;

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Patch merged into coreboot/master: 04e6f07 samus: Add ACPI MADT interrupt override for GPIO IRQ 14
by gerrit＠coreboot.org 29 Aug '14

29 Aug '14

the following patch was just integrated into master: commit 04e6f070aa58338a8ac7852172f75914baab5382 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 4 11:54:54 2013 -0700 samus: Add ACPI MADT interrupt override for GPIO IRQ 14 This interrupt needs to be specified in the MADT before it can be used by the kernel driver. Change-Id: Ic920a792a203cb06cd4529815680584a21532106 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171902 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a330fddb62cb6346ad66ceb5b5c32b66aecd81e2) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6778 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6778 for details. -gerrit

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Patch merged into coreboot/master: ddc3e42 samus: Add coreboot board
by gerrit＠coreboot.org 29 Aug '14

29 Aug '14

the following patch was just integrated into master: commit ddc3e42c2267fe175dcc28e38f53f0adecf1aa4e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Oct 2 16:10:54 2013 -0700 samus: Add coreboot board Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/6775 for details. -gerrit

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Patch merged into coreboot/master: ca436cb tegra124: add custom uart
by gerrit＠coreboot.org 29 Aug '14

29 Aug '14

the following patch was just integrated into master: commit ca436cb247a78b234feb7975575883bdcbabc348 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Sep 29 07:06:08 2013 -0700 tegra124: add custom uart tegra124: Add a test function which spams exclamation points on the UART. This function spews characters on the console and, until we have a working console, is an easy way to see whether the system boots to a particular point. For some reason waiting for transmitter to be empty hangs, but transmitting characters still works. Old-Change-Id: I1622c8a58849f4b8bdcaa67500b81042d7346df4 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171030 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit e0059181958cfe8afec2f3a7ea732e81f5d55e5d) tegra124: Re-enable waiting for the transmitter to empty in the test function. The compiler was emitting code compatible with armv7-a, but the bootblock was running on a core which uses armv4t. By coincidence, it was emitting an instruction which is unavailable on armv4t when checking the value of the UART's LSR register. Now that the bootblock is compiled with more appropriate flags, this code can be re-introduced. Old-Change-Id: I7ecada4138b0889b963d1a8b19a4bab8e0bb1add Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/170997 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 2a0adceb5029c8ee633d17c82dbb11e48d30349d) tegra124: Seperate out the non-UART specific hardcoded init in the bootblock. The hardcoded init in the test function in the bootblock is actually useful generally because it doesn't belong in the UART driver itself but is necessary for the UART to work. Until we have real implementations for the pinmux, etc., we can use that code to get the UART and console going. Old-Change-Id: I2efe0b571d8b022eb2a2e5569620558540b28373 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171334 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit ae7d4d890be1936cc86dc15adeb33f3b46a51ae5) tegra124: Implement and enable serial console support for tegra124. The driver is very similar to the 8250 driver, except it isn't in two parts, and it also spaces its registers 4 bytes apart instead of having them directly adjacent to each other. Also, eliminate the UART test function in the bootblock. It's no longer needed since the actual console output serves the same purpose. Right now the clock divisor is fixed for now, and we'll want to actually figure out what value to use at some point. Old-Change-Id: Idd659222901eb76b0ed8cbb986deb5124096f2f6 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171337 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 86f5e2875b18901b349283cfbcd4f8cc88b7a019) Squashed 4 commits related to uart support for tegra124. Modified the new uart.c to look like the uart.c for exynos5420. Change-Id: I490cba014a43d58c30c48ca9ddcae2b00095b7a6 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6764 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6764 for details. -gerrit

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Patch merged into coreboot/master: d81f409 exynos: Fix the name of the chip_operations structures.
by gerrit＠coreboot.org 29 Aug '14

29 Aug '14

the following patch was just integrated into master: commit d81f409514b99189c943d06fa9a8fa01d8178fc8 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Oct 8 23:16:51 2013 -0700 exynos: Fix the name of the chip_operations structures. The exynos directories had been moved from src/cpu to src/soc, but the name of the chip_operations structure wasn't updated properly. That meant that the SOCs never installed their memory resources and the ram stage would fail to load the payload. Change-Id: Ib60489b6d3434e3ebd13827a804452f762747f1b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172400 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 9100d475ebcc4dae23184583a6cc0162577e70d1) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6781 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6781 for details. -gerrit

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coreboot-gerrit August 2014