coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

1 participants
861 discussions

New patch to review for coreboot: 0114200 src/device/Kconfig: fix typo in label "1024x768 256-color"
by Daniele Forsi 19 Jul '14

19 Jul '14

Daniele Forsi (dforsi(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6306 -gerrit commit 0114200fefed924963ab9c17833434c51d603127 Author: Daniele Forsi <dforsi(a)gmail.com> Date: Sat Jul 19 15:40:40 2014 +0200 src/device/Kconfig: fix typo in label "1024x768 256-color" It had an extraneous digit after 768. Change-Id: Ie415e365f3eac0ed326786cea4c4628c002c4762 Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> --- src/device/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 52d12c7..c9514c1 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -369,7 +369,7 @@ config FRAMEBUFFER_VESA_MODE_104 bool "1024x768 16-color" config FRAMEBUFFER_VESA_MODE_105 - bool "1024x7686 256-color" + bool "1024x768 256-color" config FRAMEBUFFER_VESA_MODE_106 bool "1280x1024 16-color"

1 0

Patch merged into coreboot/master: 4af1245 intel/model_2065x: Remove dead code.
by gerrit＠coreboot.org 19 Jul '14

19 Jul '14

the following patch was just integrated into master: commit 4af1245ea1b3504c28bfc27b351af3195141631f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Jun 11 18:52:11 2014 +0000 intel/model_2065x: Remove dead code. nehalem uses gm45-like approach to resume backup so this code is never used. Change-Id: Ic32aa73f8d5b164b1c57815f6f44b2732fdbdcdb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/5975 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5975 for details. -gerrit

1 0

Patch merged into coreboot/master: f2b3cd6 lenovo/x60: Support digitizer on X60t and X201t.
by gerrit＠coreboot.org 19 Jul '14

19 Jul '14

the following patch was just integrated into master: commit f2b3cd63cfa2fcf7874b1947c60c22b664a277c7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 17:00:46 2014 +0100 lenovo/x60: Support digitizer on X60t and X201t. Change-Id: I5b0399a8edca3b73aa7d515d2c446c31b3239fa5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/5239 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/5239 for details. -gerrit

1 0

Patch set updated for coreboot: eef7090 Fix romstage dev type, 'device_t' -> 'pci_devfn_t' in get_sbdn()
by Edward O'Callaghan 19 Jul '14

19 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6226 -gerrit commit eef70901e56aa59d777cc4b59d8f825fba1358fc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 05:22:32 2014 +1000 Fix romstage dev type, 'device_t' -> 'pci_devfn_t' in get_sbdn() Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: Ied3940d9b2ec119ca4b75b955305add59edbbb18 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/sis/sis966/early_ctrl.c | 2 +- 13 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 1dea57b..9604816 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index abe5f84..1261293 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 71455fd..cafadb6 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -67,7 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4d6bd60..e4b9c6b 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -88,7 +88,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index d374828..6e113c0 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -107,7 +107,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index a2c6a03..94b1251 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -91,7 +91,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..6797399 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..7208146 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..0a69e5e 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(

1 0

Patch set updated for coreboot: e68a560 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component
by Edward O'Callaghan 19 Jul '14

19 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6231 -gerrit commit e68a5605794ed881497bde965fefe2cdd6944c46 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 20:26:25 2014 +1000 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. This follows on from the rational given in: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/common/early_serial.c | 6 +++--- src/superio/fintek/common/fintek.h | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++---- src/superio/ite/common/early_serial.c | 16 ++++++++-------- src/superio/ite/common/ite.h | 10 +++++----- src/superio/ite/it8661f/early_serial.c | 10 +++++----- src/superio/ite/it8661f/it8661f.h | 2 +- src/superio/ite/it8671f/early_serial.c | 2 +- src/superio/ite/it8671f/it8671f.h | 2 +- src/superio/ite/it8718f/early_serial.c | 2 +- src/superio/ite/it8718f/it8718f.h | 2 +- src/superio/nsc/pc8374/early_init.c | 2 +- src/superio/nsc/pc87309/early_serial.c | 2 +- src/superio/nsc/pc87309/pc87309.h | 2 +- src/superio/nsc/pc87351/early_serial.c | 2 +- src/superio/nsc/pc87360/early_serial.c | 2 +- src/superio/nsc/pc87366/early_serial.c | 2 +- src/superio/nsc/pc87392/early_serial.c | 2 +- src/superio/nsc/pc87417/early_init.c | 6 +++--- src/superio/nsc/pc87417/early_serial.c | 4 ++-- src/superio/nsc/pc87417/pc87417.h | 4 ++-- src/superio/nsc/pc87427/early_init.c | 6 +++--- src/superio/nsc/pc97317/early_serial.c | 2 +- src/superio/nuvoton/common/early_serial.c | 6 +++--- src/superio/nuvoton/common/nuvoton.h | 2 +- src/superio/nuvoton/nct5104d/early_init.c | 6 +++--- src/superio/nuvoton/nct5104d/nct5104d.h | 2 +- src/superio/serverengines/pilot/early_init.c | 2 +- src/superio/serverengines/pilot/early_serial.c | 8 ++++---- src/superio/serverengines/pilot/pilot.h | 10 +++++----- src/superio/smsc/fdc37m60x/early_serial.c | 2 +- src/superio/smsc/kbc1100/early_init.c | 8 ++++---- src/superio/smsc/kbc1100/kbc1100.h | 2 +- src/superio/smsc/lpc47b272/early_serial.c | 6 +++--- src/superio/smsc/lpc47b397/early_serial.c | 6 +++--- src/superio/smsc/lpc47m10x/early_serial.c | 6 +++--- src/superio/smsc/lpc47m15x/early_serial.c | 6 +++--- src/superio/smsc/lpc47n217/early_serial.c | 10 +++++----- src/superio/smsc/lpc47n227/early_serial.c | 10 +++++----- src/superio/smsc/sch4037/sch4037_early_init.c | 6 +++--- src/superio/smsc/sio1036/sio1036_early_init.c | 8 ++++---- src/superio/smsc/smscsuperio/early_serial.c | 6 +++--- src/superio/smsc/smscsuperio/smscsuperio.h | 2 +- src/superio/winbond/common/early_serial.c | 6 +++--- src/superio/winbond/common/winbond.h | 2 +- src/superio/winbond/w83627dhg/early_serial.c | 8 ++++---- src/superio/winbond/w83627dhg/w83627dhg.h | 8 ++++---- src/superio/winbond/w83627ehg/early_serial.c | 4 ++-- src/superio/winbond/w83627ehg/w83627ehg.h | 4 ++-- src/superio/winbond/w83627hf/early_init.c | 6 +++--- src/superio/winbond/w83627hf/early_serial.c | 8 ++++---- src/superio/winbond/w83627hf/w83627hf.h | 4 ++-- src/superio/winbond/w83627thg/w83627thg.h | 6 +++--- src/superio/winbond/w83697hf/early_serial.c | 8 ++++---- src/superio/winbond/w83697hf/w83697hf.h | 4 ++-- src/superio/winbond/w83977f/early_serial.c | 6 +++--- src/superio/winbond/w83977tf/early_serial.c | 6 +++--- 57 files changed, 146 insertions(+), 146 deletions(-) diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c index d74b786..4433d11 100644 --- a/src/superio/fintek/common/early_serial.c +++ b/src/superio/fintek/common/early_serial.c @@ -46,7 +46,7 @@ #define FINTEK_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_ENTRY_KEY, port); @@ -54,14 +54,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void fintek_enable_serial(device_t dev, u16 iobase) +void fintek_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h index a08cf92..1bc308b 100644 --- a/src/superio/fintek/common/fintek.h +++ b/src/superio/fintek/common/fintek.h @@ -24,6 +24,6 @@ #include <arch/io.h> #include <stdint.h> -void fintek_enable_serial(device_t dev, u16 iobase); +void fintek_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_FINTEK_COMMON_ROMSTAGE_H */ diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..96bb550 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include "i3100.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -29,7 +29,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb(0x86, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -38,14 +38,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +static void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +static void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 73354d4..a57c047 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -33,14 +33,14 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ /* Helper procedure */ -static void ite_sio_write(device_t dev, u8 reg, u8 value) +static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) { pnp_set_logical_device(dev); pnp_write_config(dev, reg, value); } /* Enable configuration */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -51,12 +51,12 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); } -void ite_reg_write(device_t dev, u8 reg, u8 value) +void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value) { pnp_enter_conf_state(dev); ite_sio_write(dev, reg, value); @@ -71,13 +71,13 @@ void ite_reg_write(device_t dev, u8 reg, u8 value) * ITE_UART_CLK_PREDIVIDE_24 * ITE_UART_CLK_PREDIVIDE_48 (default) */ -void ite_conf_clkin(device_t dev, u8 predivide) +void ite_conf_clkin(pnp_devfn_t dev, u8 predivide) { ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); } /* Bring up early serial debugging output before the RAM is initialized. */ -void ite_enable_serial(device_t dev, u16 iobase) +void ite_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -101,7 +101,7 @@ void ite_enable_serial(device_t dev, u16 iobase) * and pass: GPIO_DEV */ -void ite_enable_3vsbsw(device_t dev) +void ite_enable_3vsbsw(pnp_devfn_t dev) { u8 tmp; pnp_enter_conf_state(dev); @@ -118,7 +118,7 @@ void ite_enable_3vsbsw(device_t dev) * and pass: GPIO_DEV */ -void ite_kill_watchdog(device_t dev) +void ite_kill_watchdog(pnp_devfn_t dev) { pnp_enter_conf_state(dev); ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00); diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 5389f14..c732664 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -27,12 +27,12 @@ #define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */ #define ITE_UART_CLK_PREDIVIDE_24 0x01 -void ite_conf_clkin(device_t dev, u8 predivide); -void ite_enable_serial(device_t dev, u16 iobase); +void ite_conf_clkin(pnp_devfn_t dev, u8 predivide); +void ite_enable_serial(pnp_devfn_t dev, u16 iobase); /* Some boards need to init wdt+gpio's very early */ -void ite_reg_write(device_t dev, u8 reg, u8 value); -void ite_enable_3vsbsw(device_t dev); -void ite_kill_watchdog(device_t dev); +void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); +void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_kill_watchdog(pnp_devfn_t dev); #endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */ diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c index 7373f71..19d60b1 100644 --- a/src/superio/ite/it8661f/early_serial.c +++ b/src/superio/ite/it8661f/early_serial.c @@ -26,7 +26,7 @@ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { int i; u16 port = dev >> 8; @@ -42,7 +42,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb(init_values[i], port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { pnp_write_config(dev, IT8661F_REG_CC, (1 << 1)); } @@ -55,21 +55,21 @@ static void pnp_exit_ext_func_mode(device_t dev) * * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved. */ -static void it8661f_enable_logical_devices(device_t dev) +static void it8661f_enable_logical_devices(pnp_devfn_t dev) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, IT8661F_REG_LDE, 0x1f); pnp_exit_ext_func_mode(dev); } -static void it8661f_set_clkin(device_t dev, u8 clkin) +static void it8661f_set_clkin(pnp_devfn_t dev, u8 clkin) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1)); pnp_exit_ext_func_mode(dev); } -void it8661f_enable_serial(device_t dev, u16 iobase) +void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/it8661f/it8661f.h b/src/superio/ite/it8661f/it8661f.h index 045a54c..297dea3 100644 --- a/src/superio/ite/it8661f/it8661f.h +++ b/src/superio/ite/it8661f/it8661f.h @@ -52,6 +52,6 @@ static const u8 init_values[] = { 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -void it8661f_enable_serial(device_t dev, u16 iobase); +void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_ITE_IT8661F_H */ diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index 9f35b8a..89feb5f 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -89,7 +89,7 @@ void it8671f_48mhz_clkin(void) } /* Enable the serial port(s). */ -void it8671f_enable_serial(device_t dev, u16 iobase) +void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase) { it8671f_enter_conf(); diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h index c3865ff..90f1481 100644 --- a/src/superio/ite/it8671f/it8671f.h +++ b/src/superio/ite/it8671f/it8671f.h @@ -34,6 +34,6 @@ #define IT8671F_KBCM 0x06 /* PS/2 mouse */ void it8671f_48mhz_clkin(void); -void it8671f_enable_serial(device_t dev, u16 iobase); +void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_ITE_IT8671F__H */ diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index 166c856..563132a 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -27,7 +27,7 @@ * mechanism. It lives in the GPIO LDN. However, register 0xEF is not * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ -void it8718f_disable_reboot(device_t dev) +void it8718f_disable_reboot(pnp_devfn_t dev) { ite_reg_write(dev, 0xEF, 0x7E); } diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 61c75cf..c0a79c2 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -35,6 +35,6 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -void it8718f_disable_reboot(device_t dev); +void it8718f_disable_reboot(pnp_devfn_t dev); #endif /* SUPERIO_ITE_IT8718F_H */ diff --git a/src/superio/nsc/pc8374/early_init.c b/src/superio/nsc/pc8374/early_init.c index d3f601d..a5e9b95 100644 --- a/src/superio/nsc/pc8374/early_init.c +++ b/src/superio/nsc/pc8374/early_init.c @@ -46,7 +46,7 @@ static void pc8374_enable(u16 iobase, u8 *init) } } -static void pc8374_enable_dev(device_t dev, u16 iobase) +static void pc8374_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87309/early_serial.c b/src/superio/nsc/pc87309/early_serial.c index 6e48e0c..da0d5d7 100644 --- a/src/superio/nsc/pc87309/early_serial.c +++ b/src/superio/nsc/pc87309/early_serial.c @@ -22,7 +22,7 @@ #include <device/pnp_def.h> #include "pc87309.h" -void pc87309_enable_serial(device_t dev, u16 iobase) +void pc87309_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h index 5f39b6e..513576e 100644 --- a/src/superio/nsc/pc87309/pc87309.h +++ b/src/superio/nsc/pc87309/pc87309.h @@ -34,6 +34,6 @@ #include <arch/io.h> #include <stdint.h> -void pc87309_enable_serial(device_t dev, u16 iobase); +void pc87309_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87351/early_serial.c b/src/superio/nsc/pc87351/early_serial.c index c34538f..a31f79c 100644 --- a/src/superio/nsc/pc87351/early_serial.c +++ b/src/superio/nsc/pc87351/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87351.h" -static void pc87351_enable_serial(device_t dev, u16 iobase) +static void pc87351_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c index da4abdb..3deac3b 100644 --- a/src/superio/nsc/pc87360/early_serial.c +++ b/src/superio/nsc/pc87360/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87360.h" -static void pc87360_enable_serial(device_t dev, u16 iobase) +static void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c index e173afd..e663df6 100644 --- a/src/superio/nsc/pc87366/early_serial.c +++ b/src/superio/nsc/pc87366/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87366.h" -static void pc87366_enable_serial(device_t dev, u16 iobase) +static void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87392/early_serial.c b/src/superio/nsc/pc87392/early_serial.c index 6e85fb9..f1e5716 100644 --- a/src/superio/nsc/pc87392/early_serial.c +++ b/src/superio/nsc/pc87392/early_serial.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include "pc87392.h" -static void pc87392_enable_serial(device_t dev, u16 iobase) +static void pc87392_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index d1870f9..42f8cd1 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "pc87417.h" -static void pc87417_disable_dev(device_t dev) +static void pc87417_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87417_enable_dev(device_t dev, u16 iobase) +static void pc87417_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -37,7 +37,7 @@ static void pc87417_enable_dev(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -static void xbus_cfg(device_t dev) +static void xbus_cfg(pnp_devfn_t dev) { u8 i, data; u16 xbus_index; diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 33bae7e..42ba941 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include "pc87417.h" -void pc87417_enable_serial(device_t dev, u16 iobase) +void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -31,7 +31,7 @@ void pc87417_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -void pc87417_enable_dev(device_t dev) +void pc87417_enable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 1); diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 73c1fbc..e7d5413 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -115,8 +115,8 @@ #define PC87417_XWBCNF 0x16 #if defined(__PRE_RAM__) -void pc87417_enable_serial(device_t dev, u16 iobase); -void pc87417_enable_dev(device_t dev); +void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase); +void pc87417_enable_dev(pnp_devfn_t dev); #endif #endif diff --git a/src/superio/nsc/pc87427/early_init.c b/src/superio/nsc/pc87427/early_init.c index 6df1b9f..adaa868 100644 --- a/src/superio/nsc/pc87427/early_init.c +++ b/src/superio/nsc/pc87427/early_init.c @@ -22,13 +22,13 @@ #include <arch/io.h> #include "pc87427.h" -static void pc87427_disable_dev(device_t dev) +static void pc87427_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87427_enable_dev(device_t dev, u16 iobase) +static void pc87427_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -36,7 +36,7 @@ static void pc87427_enable_dev(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -static void xbus_cfg(device_t dev) +static void xbus_cfg(pnp_devfn_t dev) { u8 i, data; u16 xbus_index; diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c index 0c21561..ad43010 100644 --- a/src/superio/nsc/pc97317/early_serial.c +++ b/src/superio/nsc/pc97317/early_serial.c @@ -25,7 +25,7 @@ #define PM_BASE 0xe8 /* The PC97317 needs clocks to be set up before the serial port will operate. */ -static void pc97317_enable_serial(device_t dev, u16 iobase) +static void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase) { /* Set base address of power management unit. */ pnp_set_logical_device(PM_DEV); diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 1cbcee8..dbb0d13 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -49,7 +49,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -57,14 +57,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void nuvoton_enable_serial(device_t dev, u16 iobase) +void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h index e9e8d4b..43d80a9 100644 --- a/src/superio/nuvoton/common/nuvoton.h +++ b/src/superio/nuvoton/common/nuvoton.h @@ -25,6 +25,6 @@ #include <arch/io.h> #include <stdint.h> -void nuvoton_enable_serial(device_t dev, u16 iobase); +void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */ diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c index c9a408e..96fac19 100644 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ b/src/superio/nuvoton/nct5104d/early_init.c @@ -28,7 +28,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -36,14 +36,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); } /* Route UARTD to pins 41-48 */ -void nct5104d_enable_uartd(device_t dev) +void nct5104d_enable_uartd(pnp_devfn_t dev) { u8 tmp; u16 port = dev >> 8; diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index e4dcf38..5b12cc5 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -48,6 +48,6 @@ #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V) #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V) -void nct5104d_enable_uartd(device_t dev); +void nct5104d_enable_uartd(pnp_devfn_t dev); #endif /* SUPERIO_NUVOTON_NCT5104D_H */ diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 002210f..6635645 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -32,7 +32,7 @@ * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -void pilot_early_init(device_t dev) +void pilot_early_init(pnp_devfn_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 82e124c..3e99ef4 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -26,20 +26,20 @@ #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x5A, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xA5, port); } /* Serial config is a fairly standard procedure. */ -void pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -48,7 +48,7 @@ void pilot_enable_serial(device_t dev, u16 iobase) pnp_exit_ext_func_mode(dev); } -void pilot_disable_serial(device_t dev) +void pilot_disable_serial(pnp_devfn_t dev) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index e19cf37..cffa258 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -31,12 +31,12 @@ #define PILOT_LD7 0x07 /* Logical device 7 */ /* should not expose these however early_init needs love */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); -void pilot_early_init(device_t dev); +void pilot_early_init(pnp_devfn_t dev); -void pilot_enable_serial(device_t dev, u16 iobase); -void pilot_disable_serial(device_t dev); +void pilot_enable_serial(pnp_devfn_t dev, u16 iobase); +void pilot_disable_serial(pnp_devfn_t dev); #endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */ diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c index 38cb0f8..80258a9 100644 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -46,7 +46,7 @@ static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) } /* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ -static void fdc37m60x_enable_serial(device_t dev, u16 iobase) +static void fdc37m60x_enable_serial(pnp_devfn_t dev, u16 iobase) { /* (1) Enter the configuration state. */ outb(0x55, FDC37M60X_CONFIGURATION_PORT); diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c index d075f9c..bd42288 100644 --- a/src/superio/smsc/kbc1100/early_init.c +++ b/src/superio/smsc/kbc1100/early_init.c @@ -26,19 +26,19 @@ #include "kbc1100.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void kbc1100_early_serial(device_t dev, u16 iobase) +void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -50,7 +50,7 @@ void kbc1100_early_serial(device_t dev, u16 iobase) void kbc1100_early_init(u16 port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, KBC1100_KBC); pnp_enter_conf_state(dev); diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 2b588f9..ec24dd3 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -36,7 +36,7 @@ #define KBC1100_EC1 0x0D /* EC Channel 1 */ #define KBC1100_EC2 0x0E /* EC Channel 2 */ -void kbc1100_early_serial(device_t dev, u16 iobase); +void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase); void kbc1100_early_init(u16 port); #endif /* SUPERIO_SMSC_KBC1100_H */ diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c index b2f0d1b..3624df2 100644 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "lpc47b272.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47b272_enable_serial(device_t dev, u16 iobase) +static void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c index 31d515b..953cd4b 100644 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -23,19 +23,19 @@ #include <arch/io.h> #include "lpc47b397.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void lpc47b397_enable_serial(device_t dev, u16 iobase) +static void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index fc6efb9..1174120 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -21,13 +21,13 @@ #include <arch/io.h> #include "lpc47m10x.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -40,7 +40,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47m10x_enable_serial(device_t dev, u16 iobase) +static void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index 5686f52..0a42ad3 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -25,19 +25,19 @@ #include "lpc47m15x.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void lpc47m15x_enable_serial(device_t dev, u16 iobase) +void lpc47m15x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 451628a..7405f32 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -24,13 +24,13 @@ #include <assert.h> #include "lpc47n217.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n217_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) { /* LPC47N217 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); @@ -74,7 +74,7 @@ static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -static void lpc47n217_pnp_set_enable(device_t dev, int enable) +static void lpc47n217_pnp_set_enable(pnp_devfn_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -109,7 +109,7 @@ static void lpc47n217_pnp_set_enable(device_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n217_enable_serial(device_t dev, u16 iobase) +static void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index 4aea7c5..64a6d84 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "lpc47n227.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -41,7 +41,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n227_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) { /* LPC47N227 requires base ports to be a multiple of 4. */ /* it's not very useful to do an ASSERT here: if it trips, @@ -76,7 +76,7 @@ static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -static void lpc47n227_pnp_set_enable(device_t dev, int enable) +static void lpc47n227_pnp_set_enable(pnp_devfn_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -111,7 +111,7 @@ static void lpc47n227_pnp_set_enable(device_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n227_enable_serial(device_t dev, u16 iobase) +static void lpc47n227_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c index 29517ed..5be8fa8 100644 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -21,13 +21,13 @@ #include <arch/io.h> #include "sch4037.h" -static inline void pnp_enter_conf_state(device_t dev) +static inline void pnp_enter_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0xaa, port); @@ -35,7 +35,7 @@ static void pnp_exit_conf_state(device_t dev) static inline void sch4037_early_init(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV(port, SMSCSUPERIO_SP1); pnp_enter_conf_state(dev); diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..9b1be52 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -25,13 +25,13 @@ #ifndef CONFIG_TTYS0_BASE #define CONFIG_TTYS0_BASE 0x3F8 #endif -static inline void sio1036_enter_conf_state(device_t dev) +static inline void sio1036_enter_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0x55, port); } -static inline void sio1036_exit_conf_state(device_t dev) +static inline void sio1036_exit_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0xaa, port); @@ -39,7 +39,7 @@ static inline void sio1036_exit_conf_state(device_t dev) static u8 detect_sio1036_chip(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, SIO1036_SP1); unsigned data; sio1036_enter_conf_state (dev); @@ -57,7 +57,7 @@ static u8 detect_sio1036_chip(unsigned port) static inline void sio1036_early_init(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, SIO1036_SP1); if (detect_sio1036_chip(port) != 0) { diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index e2eea6d..c058ef5 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -29,14 +29,14 @@ #define SMSC_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(SMSC_ENTRY_KEY, port); } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(SMSC_EXIT_KEY, port); @@ -49,7 +49,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev The device to use. * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). */ -void smscsuperio_enable_serial(device_t dev, u16 iobase) +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/smscsuperio/smscsuperio.h b/src/superio/smsc/smscsuperio/smscsuperio.h index 60a58e6..8a761ba 100644 --- a/src/superio/smsc/smscsuperio/smscsuperio.h +++ b/src/superio/smsc/smscsuperio/smscsuperio.h @@ -30,6 +30,6 @@ #define SMSCSUPERIO_SP1 4 /* Com1 */ #define SMSCSUPERIO_SP2 5 /* Com2 */ -void smscsuperio_enable_serial(device_t dev, u16 iobase); +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_SMSC_SMSCSUPERIO_H */ diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c index 747cc45..fd51cd5 100644 --- a/src/superio/winbond/common/early_serial.c +++ b/src/superio/winbond/common/early_serial.c @@ -46,7 +46,7 @@ #define WINBOND_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(WINBOND_ENTRY_KEY, port); @@ -54,14 +54,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(WINBOND_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void winbond_enable_serial(device_t dev, u16 iobase) +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 20eefc8..0f937c1 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -24,6 +24,6 @@ #include <arch/io.h> #include <stdint.h> -void winbond_enable_serial(device_t dev, u16 iobase); +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_COMMON_ROMSTAGE_H */ diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index 67aaa93..83f8e34 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -24,14 +24,14 @@ #include <stdint.h> #include "w83627dhg.h" -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ void pnp_exit_ext_func_mode(device_t dev) * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or * {RSTOUT3#, RSTOUT2#} or {SDA, SCL} */ -void w83627dhg_enable_i2c(device_t dev) +void w83627dhg_enable_i2c(pnp_devfn_t dev) { u8 val; @@ -56,7 +56,7 @@ void w83627dhg_enable_i2c(device_t dev) pnp_exit_ext_func_mode(dev); } -void w83627dhg_set_clksel_48(device_t dev) +void w83627dhg_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 08ea04f..c4ead34 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -52,9 +52,9 @@ /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); -void w83627dhg_enable_i2c(device_t dev); -void w83627dhg_set_clksel_48(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); +void w83627dhg_enable_i2c(pnp_devfn_t dev); +void w83627dhg_set_clksel_48(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627DHG_H */ diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 346d6cf..e052863 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -23,14 +23,14 @@ #include <device/pnp.h> #include "w83627ehg.h" -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..3d6f56f 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,7 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627EHG_H */ diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c index db616ae..2e275e6 100644 --- a/src/superio/winbond/w83627hf/early_init.c +++ b/src/superio/winbond/w83627hf/early_init.c @@ -25,14 +25,14 @@ #include <device/pnp.h> #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -43,7 +43,7 @@ static void pnp_exit_ext_func_mode(device_t dev) * work around a limitation of ROMCC where we can no make early_serial.c into * link-time symbols and #include early_serial.c. */ -void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index bc251a6..694a3fe 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -24,14 +24,14 @@ #include <arch/io.h> #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -49,7 +49,7 @@ static void pnp_exit_ext_func_mode(device_t dev) * XXX: ROMCC - everything is inlined, no forwarding function prototypes * declarations are accepted. */ -void w83627hf_enable_serial(device_t dev, u16 iobase) +void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -59,7 +59,7 @@ void w83627hf_enable_serial(device_t dev, u16 iobase) pnp_exit_ext_func_mode(dev); } -void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index bf7186e..6eeb62b 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -115,7 +115,7 @@ #include <arch/io.h> -void w83627hf_set_clksel_48(device_t dev); -void w83627hf_enable_serial(device_t dev, u16 iobase); +void w83627hf_set_clksel_48(pnp_devfn_t dev); +void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83627HF_H */ diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index ec857d3..8d85379 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,9 +34,9 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); -void w83627thg_set_clksel_48(device_t dev); +void w83627thg_set_clksel_48(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627THG_W83627THG_H */ diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 6c00b27..515fee9 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -22,20 +22,20 @@ #include <device/pnp_def.h> #include "w83697hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; @@ -47,7 +47,7 @@ void w83697hf_set_clksel_48(device_t dev) } /* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(device_t dev, u16 iobase) +void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index f711786..3bd1f44 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -34,9 +34,9 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ -void w83697hf_set_clksel_48(device_t); +void w83697hf_set_clksel_48(pnp_devfn_t); /* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(device_t dev, u16 iobase); +void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83697HF_H */ diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c index c572dcb..9b5785d 100644 --- a/src/superio/winbond/w83977f/early_serial.c +++ b/src/superio/winbond/w83977f/early_serial.c @@ -21,20 +21,20 @@ #include <arch/io.h> #include "w83977f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83977f_enable_serial(device_t dev, u16 iobase) +static void w83977f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83977tf/early_serial.c b/src/superio/winbond/w83977tf/early_serial.c index c016515..866d9f2 100644 --- a/src/superio/winbond/w83977tf/early_serial.c +++ b/src/superio/winbond/w83977tf/early_serial.c @@ -23,20 +23,20 @@ #include <arch/io.h> #include "w83977tf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83977tf_enable_serial(device_t dev, u16 iobase) +static void w83977tf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev);

1 0

Patch set updated for coreboot: 7f1d94d include/device/device.h: Duplicate '*_pnp_devfn_t' typedefs
by Edward O'Callaghan 19 Jul '14

19 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6230 -gerrit commit 7f1d94d1f2217ca480fb88d03619bbca1e63bc82 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 18:41:12 2014 +1000 include/device/device.h: Duplicate '*_pnp_devfn_t' typedefs 'pci_devfn_t' and 'pnp_devfn_t' are already defined in arch/io.h Change-Id: I006182bf6933fae21fe6671659b76e7031e74b71 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/include/arch/io.h | 9 ++++++--- src/include/device/device.h | 2 -- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index b6d82f9..d5cdf35 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -4,6 +4,11 @@ #include <stdint.h> #include <rules.h> +/* FIXME: Sources for romstage still use device_t. */ +/* Use pci_devfn_t or pnp_devfn_t instead */ +typedef u32 pci_devfn_t; +typedef u32 pnp_devfn_t; + /* * This file contains the definitions for the x86 IO instructions * inb/inw/inl/outb/outw/outl and the "string versions" of the same @@ -218,11 +223,9 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) /* FIXME: Sources for romstage still use device_t. */ +/* Use pci_devfn_t or pnp_devfn_t instead */ typedef u32 device_t; -typedef u32 pci_devfn_t; -typedef u32 pnp_devfn_t; - /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access diff --git a/src/include/device/device.h b/src/include/device/device.h index ec17adf..132e4ef 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -18,8 +18,6 @@ struct device; #ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; -typedef u32 pci_devfn_t; -typedef u32 pnp_devfn_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations;

1 0

Patch merged into coreboot/master: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32'
by gerrit＠coreboot.org 19 Jul '14

19 Jul '14

the following patch was just integrated into master: commit c2956e7752213f9eae5064e63d16afa84b7cc23f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 04:55:16 2014 +1000 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: I948801f5be968a934798f1bad7722649758cd4d3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6225 for details. -gerrit

1 0

New patch to review for coreboot: 6c8fafb build system: avoid warning about missing .xcompile
by Patrick Georgi 19 Jul '14

19 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6305 -gerrit commit 6c8fafb89915c7a7e4a2ab862f8e44c080fdd787 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Jul 19 10:55:30 2014 +0200 build system: avoid warning about missing .xcompile That file will be generated, but not before make managed to complain about it. So let's just generate it if missing - it won't hurt the dependency tracking some lines later which is looking at time stamps. Change-Id: I615f38457eb27a8ffb4352b5234e262ee95d84ac Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index fad8103..a55ad67 100644 --- a/Makefile +++ b/Makefile @@ -30,6 +30,10 @@ ## SUCH DAMAGE. ## +# in addition to the dependency below, create the file if it doesn't exist +# to silence stupid warnings about a file that would be generated anyway. +$(if $(wildcard .xcompile),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile))) + .xcompile: util/xcompile/xcompile A=`mktemp $@.XXXXXX`; $< $(XGCCPATH) > $$A && mv $$A $@ 2> /dev/null

1 0

Patch set updated for coreboot: 4f642d9 sconfig: Refuse devicetree with leaf "chip"s
by Stefan Reinauer 18 Jul '14

18 Jul '14

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3189 -gerrit commit 4f642d9a0c1c648745c3d31c2607908fbee11f23 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri May 3 20:31:56 2013 +0200 sconfig: Refuse devicetree with leaf "chip"s It doesn't make sense to have a chip without any containing device in the device tree, and it creates lots of funny issues when trying to make use of such a tree (ask Ron). Since the right thing is to refuse such devicetrees, this change makes them a syntax error. Change-Id: Ia35b518bd4acd631e78bdf63c4424c0fa6a81229 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/sconfig/sconfig.tab.c_shipped | 122 +++++++++++++++++++------------------ util/sconfig/sconfig.y | 2 +- 2 files changed, 63 insertions(+), 61 deletions(-) diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 3a56ac8..1347b89 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -387,16 +387,16 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 37 +#define YYLAST 48 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 28 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 13 /* YYNRULES -- Number of rules. */ -#define YYNRULES 22 +#define YYNRULES 24 /* YYNRULES -- Number of states. */ -#define YYNSTATES 41 +#define YYNSTATES 46 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ #define YYUNDEFTOK 2 @@ -444,30 +444,30 @@ static const yytype_uint8 yytranslate[] = YYRHS. */ static const yytype_uint8 yyprhs[] = { - 0, 0, 3, 4, 7, 10, 13, 16, 17, 20, - 23, 26, 29, 32, 33, 34, 40, 41, 49, 54, - 59, 63, 68 + 0, 0, 3, 4, 7, 10, 12, 15, 18, 21, + 24, 27, 30, 33, 36, 39, 40, 41, 47, 48, + 56, 61, 66, 70, 75 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int8 yyrhs[] = { 29, 0, -1, -1, 30, 33, -1, 31, 35, -1, - 31, 33, -1, 31, 38, -1, -1, 32, 35, -1, - 32, 33, -1, 32, 37, -1, 32, 39, -1, 32, - 40, -1, -1, -1, 3, 12, 34, 31, 9, -1, - -1, 4, 7, 22, 6, 36, 32, 9, -1, 8, - 22, 10, 22, -1, 5, 12, 10, 12, -1, 23, - 22, 22, -1, 23, 22, 22, 24, -1, 25, 22, - 27, 22, -1 + 35, -1, 31, 33, -1, 31, 38, -1, 38, 31, + -1, 33, 31, -1, 32, 35, -1, 32, 33, -1, + 32, 37, -1, 32, 39, -1, 32, 40, -1, -1, + -1, 3, 12, 34, 31, 9, -1, -1, 4, 7, + 22, 6, 36, 32, 9, -1, 8, 22, 10, 22, + -1, 5, 12, 10, 12, -1, 23, 22, 22, -1, + 23, 22, 22, 24, -1, 25, 22, 27, 22, -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { - 0, 35, 35, 35, 37, 37, 37, 37, 39, 39, - 39, 39, 39, 39, 41, 41, 51, 51, 63, 66, - 69, 72, 75 + 0, 35, 35, 35, 37, 37, 37, 37, 37, 37, + 39, 39, 39, 39, 39, 39, 41, 41, 51, 51, + 63, 66, 69, 72, 75 }; #endif @@ -499,17 +499,17 @@ static const yytype_uint16 yytoknum[] = /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 28, 30, 29, 31, 31, 31, 31, 32, 32, - 32, 32, 32, 32, 34, 33, 36, 35, 37, 38, - 39, 39, 40 + 0, 28, 30, 29, 31, 31, 31, 31, 31, 31, + 32, 32, 32, 32, 32, 32, 34, 33, 36, 35, + 37, 38, 39, 39, 40 }; /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { - 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 2, 0, 0, 5, 0, 7, 4, 4, - 3, 4, 4 + 0, 2, 0, 2, 2, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 0, 0, 5, 0, 7, + 4, 4, 3, 4, 4 }; /* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM. @@ -517,37 +517,37 @@ static const yytype_uint8 yyr2[] = means the default is an error. */ static const yytype_uint8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 14, 7, 0, 0, - 0, 15, 5, 4, 6, 0, 0, 0, 0, 16, - 19, 13, 0, 0, 17, 0, 0, 9, 8, 10, - 11, 12, 0, 0, 0, 0, 20, 0, 18, 21, - 22 + 2, 0, 0, 1, 0, 3, 16, 0, 0, 0, + 0, 0, 5, 0, 0, 0, 17, 6, 4, 7, + 9, 8, 0, 0, 18, 21, 15, 0, 0, 19, + 0, 0, 11, 10, 12, 13, 14, 0, 0, 0, + 0, 22, 0, 20, 23, 24 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 2, 8, 22, 5, 7, 13, 21, 29, - 14, 30, 31 + -1, 1, 2, 10, 27, 11, 7, 12, 26, 34, + 13, 35, 36 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ -#define YYPACT_NINF -9 +#define YYPACT_NINF -10 static const yytype_int8 yypact[] = { - -9, 3, 1, -9, -2, -9, -9, -9, 4, 5, - -1, -9, -9, -9, -9, -8, 7, 9, 6, -9, - -9, -9, -3, 2, -9, 8, 10, -9, -9, -9, - -9, -9, 11, 12, -4, 13, -5, 14, -9, -9, - -9 + -10, 2, 3, -10, -5, -10, -10, 24, 15, 11, + 12, 24, -10, 24, 9, 23, -10, -10, -10, -10, + 24, 24, 28, 25, -10, -10, -10, 1, 13, -10, + 14, 16, -10, -10, -10, -10, -10, 29, 18, 17, + 20, 21, 26, -10, -10, -10 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -9, -9, -9, -9, -9, -6, -9, 15, -9, -9, - -9, -9, -9 + -10, -10, -10, 19, -10, -2, -10, -7, -10, -10, + -9, -10, -10 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If @@ -556,35 +556,37 @@ static const yytype_int8 yypgoto[] = #define YYTABLE_NINF -1 static const yytype_uint8 yytable[] = { - 4, 9, 12, 3, 4, 23, 24, 4, 9, 10, - 6, 16, 15, 11, 17, 19, 27, 18, 20, 39, - 25, 35, 26, 37, 32, 0, 0, 0, 0, 0, - 33, 0, 34, 0, 36, 38, 40, 28 + 5, 19, 3, 18, 4, 8, 4, 6, 17, 28, + 29, 19, 19, 18, 18, 4, 8, 9, 17, 17, + 33, 16, 14, 15, 30, 32, 31, 4, 8, 9, + 20, 22, 21, 23, 24, 37, 38, 25, 39, 40, + 41, 0, 43, 0, 42, 44, 0, 0, 45 }; #define yypact_value_is_default(yystate) \ - ((yystate) == (-9)) + ((yystate) == (-10)) #define yytable_value_is_error(yytable_value) \ YYID (0) static const yytype_int8 yycheck[] = { - 3, 4, 8, 0, 3, 8, 9, 3, 4, 5, - 12, 12, 7, 9, 22, 6, 22, 10, 12, 24, - 23, 10, 25, 27, 22, -1, -1, -1, -1, -1, - 22, -1, 22, -1, 22, 22, 22, 22 + 2, 10, 0, 10, 3, 4, 3, 12, 10, 8, + 9, 20, 21, 20, 21, 3, 4, 5, 20, 21, + 27, 9, 7, 12, 23, 27, 25, 3, 4, 5, + 11, 22, 13, 10, 6, 22, 22, 12, 22, 10, + 22, -1, 22, -1, 27, 24, -1, -1, 22 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 29, 30, 0, 3, 33, 12, 34, 31, 4, - 5, 9, 33, 35, 38, 7, 12, 22, 10, 6, - 12, 36, 32, 8, 9, 23, 25, 33, 35, 37, - 39, 40, 22, 22, 22, 10, 22, 27, 22, 24, - 22 + 0, 29, 30, 0, 3, 33, 12, 34, 4, 5, + 31, 33, 35, 38, 7, 12, 9, 33, 35, 38, + 31, 31, 22, 10, 6, 12, 36, 32, 8, 9, + 23, 25, 33, 35, 37, 39, 40, 22, 22, 22, + 10, 22, 27, 22, 24, 22 }; #define yyerrok (yyerrstatus = 0) @@ -1428,7 +1430,7 @@ yyreduce: { postprocess_devtree(); } break; - case 14: + case 16: { (yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[(2) - (2)].string)); @@ -1436,7 +1438,7 @@ yyreduce: } break; - case 15: + case 17: { cur_parent = (yyvsp[(3) - (5)].device)->parent; @@ -1445,7 +1447,7 @@ yyreduce: } break; - case 16: + case 18: { (yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number)); @@ -1454,7 +1456,7 @@ yyreduce: } break; - case 17: + case 19: { cur_parent = (yyvsp[(5) - (7)].device)->parent; @@ -1464,27 +1466,27 @@ yyreduce: } break; - case 18: + case 20: { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); } break; - case 19: + case 21: { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); } break; - case 20: + case 22: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (3)].string), NULL, 16), strtol((yyvsp[(3) - (3)].string), NULL, 16), 0); } break; - case 21: + case 23: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), 1); } break; - case 22: + case 24: { add_ioapic_info(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), (yyvsp[(3) - (4)].string), strtol((yyvsp[(4) - (4)].string), NULL, 16)); } break; diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 8ea702e..f298ce2 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -34,7 +34,7 @@ static struct device *cur_parent, *cur_bus; %% devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; -chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; +chipchildren: chipchildren device | device | chipchildren chip | chipchildren registers | registers chipchildren | chip chipchildren ; devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | /* empty */ ;

1 0

Patch set updated for coreboot: 22aa8e1 mainboards/asrock/e350m1: use nct5572d as superio chip
by Felix Held 18 Jul '14

18 Jul '14

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6266 -gerrit commit 22aa8e1cdd5dd3f4953d336a12aca3c402196a29 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sat Jul 19 00:21:43 2014 +0200 mainboards/asrock/e350m1: use nct5572d as superio chip Using the right superio chip driver fixes the no ethernet device after reboot issue. Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/mainboard/asrock/e350m1/BiosCallOuts.c | 8 +++--- src/mainboard/asrock/e350m1/Kconfig | 2 +- src/mainboard/asrock/e350m1/devicetree.cb | 42 ++++++++++++++++-------------- src/mainboard/asrock/e350m1/romstage.c | 8 +++--- 4 files changed, 31 insertions(+), 29 deletions(-) diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 180708b..72a563f 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -25,11 +25,6 @@ #include <northbridge/amd/agesa/family14/dimmSpd.h> #include <stdlib.h> -/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess? - * - * Board is known to have some issues with integrated NIC and - * might need implementation to drive some GPIOs. - */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); @@ -101,6 +96,9 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + /* this seems to be just copy-pasted from the AMD reference boards and needs + * some investigation + */ switch(MemData->ParameterListPtr->DDR3Voltage){ case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 00cdaa7..2f2e58d 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -24,7 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_WINBOND_W83627HF + select SUPERIO_NUVOTON_NCT5572D select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index e2096c0..7fcf0ef 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -54,22 +54,15 @@ chip northbridge/amd/agesa/family14/root_complex end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end + device pci 14.3 on # LPC + chip superio/nuvoton/nct5572d + device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die + device pnp 2e.1 off end # LPT1; same as FDC device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off # IR io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -81,19 +74,30 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 2e.6 off # CIR io 0x60 = 0x100 + irq 0x70 = 0 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 + device pnp 2e.7 off end # GIPO689 + device pnp 2e.8 off end # WDT + device pnp 2e.9 off end # GPIO235 device pnp 2e.a on end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 + io 0x62 = 0x0000 # SB-TSI currently not implemented irq 0x70 = 5 end + device pnp 2e.c off end # PECI + device pnp 2e.d off end # SUSLED + device pnp 2e.e off # CIRWKUP + io 0x60 = 0x0000 + irq 0x70 = 0 + end + device pnp 2e.f off end # GPIO_PP_OD + device pnp 2e.009 on end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.107 off end # GPIO6 + device pnp 2e.307 on end # GPIO8 + device pnp 2e.407 off end # GPIO9 end end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 5c2f867..1e91b1f 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -32,14 +32,14 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5572d/nct5572d.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h" -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -60,7 +60,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); }

1 0

← Newer
1
...
33
34
35
36
37
38
39
...
87
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2014