Patch set updated for coreboot: db8c7d5 AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6359
-gerrit
commit db8c7d51773e405c51e741a7004aee5fa965ed17
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 10:24:20 2014 +0300
AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/inagua/get_bus_conf.c | 7 -----
src/mainboard/amd/inagua/mptable.c | 21 ++++++++-------
src/mainboard/amd/olivehill/get_bus_conf.c | 7 -----
src/mainboard/amd/olivehill/mptable.c | 31 +++++++++-------------
src/mainboard/amd/parmer/get_bus_conf.c | 7 -----
src/mainboard/amd/parmer/mptable.c | 29 +++++++++-----------
src/mainboard/amd/persimmon/get_bus_conf.c | 15 -----------
src/mainboard/amd/persimmon/mptable.c | 17 +++++++-----
src/mainboard/amd/south_station/get_bus_conf.c | 8 ------
src/mainboard/amd/south_station/mptable.c | 20 ++++++++------
src/mainboard/amd/thatcher/get_bus_conf.c | 7 -----
src/mainboard/amd/thatcher/mptable.c | 29 +++++++++-----------
src/mainboard/amd/union_station/get_bus_conf.c | 7 -----
src/mainboard/amd/union_station/mptable.c | 20 ++++++++------
src/mainboard/asrock/e350m1/get_bus_conf.c | 7 -----
src/mainboard/asrock/e350m1/mptable.c | 20 ++++++++------
src/mainboard/asrock/imb-a180/get_bus_conf.c | 8 ------
src/mainboard/asrock/imb-a180/mptable.c | 30 +++++++++------------
src/mainboard/asus/f2a85-m/get_bus_conf.c | 8 ------
src/mainboard/asus/f2a85-m/mptable.c | 28 +++++++++----------
src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 7 -----
src/mainboard/gizmosphere/gizmo/mptable.c | 20 ++++++++------
src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 7 -----
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 28 +++++++++----------
src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 17 ------------
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 16 +++++++----
.../lippert/frontrunner-af/get_bus_conf.c | 8 ------
src/mainboard/lippert/frontrunner-af/mptable.c | 21 ++++++++-------
src/mainboard/lippert/toucan-af/get_bus_conf.c | 7 -----
src/mainboard/lippert/toucan-af/mptable.c | 21 ++++++++-------
30 files changed, 180 insertions(+), 298 deletions(-)
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index c39decf..fb939ab 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -31,12 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +57,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 4a57d3c..7686bd2 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -22,13 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -48,6 +47,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -58,14 +65,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -75,13 +78,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
index 2765ed7..582d7ed 100644
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ b/src/mainboard/amd/olivehill/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_yangtze[6];
-u32 apicid_yangtze;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
memset(bus_yangtze, 0, sizeof(bus_yangtze));
@@ -59,8 +56,4 @@ void get_bus_conf(void)
bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_yangtze = apicid_base;
}
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index c06863b..db4a3ff 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_yangtze;
-
u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,19 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_yangtze = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
-
- smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
@@ -153,13 +148,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c
index 3b3daf9..8ff9ed3 100644
--- a/src/mainboard/amd/parmer/get_bus_conf.c
+++ b/src/mainboard/amd/parmer/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -64,8 +61,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 2f5179f..05da01a 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
-
u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 9434429..59881d1 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -32,14 +32,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-u32 apicver_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -63,15 +58,5 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
}
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 0d5f5ce..1227d89 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -31,14 +31,19 @@
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
-extern u32 apicid_sb800;
-extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -62,20 +67,20 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c
index 53c7953..dcdd0b2 100644
--- a/src/mainboard/amd/south_station/get_bus_conf.c
+++ b/src/mainboard/amd/south_station/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -63,9 +60,4 @@ void get_bus_conf(void)
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 57eaa0e..c2ec4a2 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -22,12 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -44,6 +44,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +62,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,13 +75,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c
index 9f5f15a..6d0f903 100644
--- a/src/mainboard/amd/thatcher/get_bus_conf.c
+++ b/src/mainboard/amd/thatcher/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,8 +58,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 7f9aa7c..8ddd1b6 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
-
u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c
index 52b5d88..8824ca1 100644
--- a/src/mainboard/amd/union_station/get_bus_conf.c
+++ b/src/mainboard/amd/union_station/get_bus_conf.c
@@ -31,12 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
device_t dev;
int i;
@@ -66,8 +63,4 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 57eaa0e..c2ec4a2 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -22,12 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -44,6 +44,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +62,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,13 +75,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index f2c8056..fed8075 100644
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,8 +58,4 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 2c945cf..14fa316 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/amd/amdfam14.h>
@@ -28,7 +29,6 @@
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -45,6 +45,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -55,14 +63,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -72,13 +76,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c
index 9a20b98..c2af8fa 100644
--- a/src/mainboard/asrock/imb-a180/get_bus_conf.c
+++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c
@@ -30,14 +30,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_yangtze[6];
-u32 apicid_yangtze;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +56,4 @@ void get_bus_conf(void)
bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_yangtze = apicid_base;
}
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index 11da130..d9ca7b7 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,8 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -70,9 +69,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,19 +93,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_yangtze = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
-
- smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
@@ -153,13 +149,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c
index fe8253e..81417e7 100644
--- a/src/mainboard/asus/f2a85-m/get_bus_conf.c
+++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c
@@ -31,14 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
-
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -62,7 +57,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index 3316b83..cc81819 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/amd/amdfam15.h>
#include <cpu/x86/lapic.h>
@@ -27,8 +28,6 @@
#include <string.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -69,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -86,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -113,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x0, 0x0, 0x10);
diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
index 2cc2c0c..54151f7 100755
--- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
+++ b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
@@ -32,13 +32,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -62,8 +59,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index c16c486..ed52722 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -23,12 +23,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -45,6 +45,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -55,14 +63,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -72,13 +76,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
index f0494ab..ef08e7f 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
@@ -32,13 +32,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -59,8 +56,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 9ef2b81..f47b9d9 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/amd/amdfam15.h>
@@ -28,8 +29,6 @@
#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -70,9 +69,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +93,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +110,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
index cc3ffbb..2cfc5c6 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
@@ -33,14 +33,9 @@
* mptable and acpi_tables where busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-u32 apicver_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,16 +56,4 @@ void get_bus_conf(void)
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
-
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index b621dd2..4390605 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -33,14 +33,20 @@
#include <southbridge/amd/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u32 apicid_sb800;
-extern u32 apicver_sb800;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -64,20 +70,20 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
index 42270af..1dc1cca 100644
--- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
+++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
@@ -31,13 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +56,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index eeae66f..de573b8 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -22,13 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -44,6 +43,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +61,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,13 +74,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c
index eb40c54..e67c27d 100644
--- a/src/mainboard/lippert/toucan-af/get_bus_conf.c
+++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -59,8 +56,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index eeae66f..de573b8 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -22,13 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -44,6 +43,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +61,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,13 +74,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
1
0
Patch set updated for coreboot: 03fcd18 AGESA boards: Drop get_bus_conf.c files
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6360
-gerrit
commit 03fcd18cc3508b5d4049f4bb9fe78882dd9cfc89
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 15:24:15 2014 +0300
AGESA boards: Drop get_bus_conf.c files
The only remaining purpose for get_bus_conf() was to fill in obscure
bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete
enumeration is available in devicetree and PCI configuration space so
discard these arrays.
Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/agesa/amd_late_init.c | 5 --
src/mainboard/amd/dinar/get_bus_conf.c | 58 -------------------
src/mainboard/amd/inagua/get_bus_conf.c | 60 --------------------
src/mainboard/amd/olivehill/get_bus_conf.c | 59 -------------------
src/mainboard/amd/parmer/get_bus_conf.c | 64 ---------------------
src/mainboard/amd/persimmon/get_bus_conf.c | 62 --------------------
src/mainboard/amd/south_station/get_bus_conf.c | 63 ---------------------
src/mainboard/amd/thatcher/get_bus_conf.c | 61 --------------------
src/mainboard/amd/torpedo/get_bus_conf.c | 63 ---------------------
src/mainboard/amd/union_station/get_bus_conf.c | 66 ----------------------
src/mainboard/asrock/e350m1/get_bus_conf.c | 61 --------------------
src/mainboard/asrock/imb-a180/get_bus_conf.c | 59 -------------------
src/mainboard/asus/f2a85-m/get_bus_conf.c | 60 --------------------
src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 62 --------------------
src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 59 -------------------
src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 59 -------------------
.../lippert/frontrunner-af/get_bus_conf.c | 59 -------------------
src/mainboard/lippert/toucan-af/get_bus_conf.c | 59 -------------------
src/mainboard/supermicro/h8qgi/get_bus_conf.c | 53 -----------------
src/mainboard/supermicro/h8scm/get_bus_conf.c | 53 -----------------
src/mainboard/tyan/s8226/get_bus_conf.c | 54 ------------------
21 files changed, 1199 deletions(-)
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index c8b941d..faba328 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -31,8 +31,6 @@
#include <sb_cimx.h>
#endif
-void get_bus_conf(void);
-
static void agesawrapper_post_device(void *unused)
{
if (acpi_is_wakeup_s3())
@@ -40,9 +38,6 @@ static void agesawrapper_post_device(void *unused)
AGESAWRAPPER(amdinitlate);
- /* Preparation for write_tables(). */
- get_bus_conf();
-
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
device_t dev;
u32 value;
diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c
deleted file mode 100644
index 5ab2ddd..0000000
--- a/src/mainboard/amd/dinar/get_bus_conf.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam15.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sb700[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
- printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
-
-
- for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) {
- bus_sb700[i] = 0;
- }
-
-
- /* sb700 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
-}
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
deleted file mode 100644
index fb939ab..0000000
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
deleted file mode 100644
index 582d7ed..0000000
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_yangtze[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
- memset(bus_yangtze, 0, sizeof(bus_yangtze));
-
-
-
- /* yangtze */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c
deleted file mode 100644
index 8ff9ed3..0000000
--- a/src/mainboard/amd/parmer/get_bus_conf.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
deleted file mode 100644
index 59881d1..0000000
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#include <arch/ioapic.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-
-}
diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c
deleted file mode 100644
index dcdd0b2..0000000
--- a/src/mainboard/amd/south_station/get_bus_conf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c
deleted file mode 100644
index 6d0f903..0000000
--- a/src/mainboard/amd/thatcher/get_bus_conf.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
deleted file mode 100644
index b88e3fb..0000000
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam12.h>
-#include "agesawrapper.h"
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb900[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
- printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__);
-
-
- memset(bus_sb900, 0, sizeof(bus_sb900));
-
-
-
- /* sb900 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0,
- PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb900[2 + i] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- printk(BIOS_DEBUG, "Mainboard - %s - %s - End.\n", __FILE__, __func__);
-}
diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c
deleted file mode 100644
index 8824ca1..0000000
--- a/src/mainboard/amd/union_station/get_bus_conf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
-
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-}
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
deleted file mode 100644
index fed8075..0000000
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-}
diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c
deleted file mode 100644
index c2af8fa..0000000
--- a/src/mainboard/asrock/imb-a180/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_yangtze[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_yangtze, 0, sizeof(bus_yangtze));
-
-
-
- /* yangtze */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c
deleted file mode 100644
index 81417e7..0000000
--- a/src/mainboard/asus/f2a85-m/get_bus_conf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <console/console.h>
-#include <cpu/amd/amdfam15.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
deleted file mode 100755
index 54151f7..0000000
--- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
deleted file mode 100644
index ef08e7f..0000000
--- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <console/console.h>
-#include <cpu/amd/amdfam15.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <southbridge/amd/agesa/hudson/imc.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
deleted file mode 100644
index 2cfc5c6..0000000
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <arch/ioapic.h>
-#include <console/console.h>
-#include <cpu/amd/amdfam14.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-/**
- * Global variables for mainboard layouts. These are shared by irqtable,
- * mptable and acpi_tables where busnum is default.
- */
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
deleted file mode 100644
index 1dc1cca..0000000
--- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c
deleted file mode 100644
index e67c27d..0000000
--- a/src/mainboard/lippert/toucan-af/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
deleted file mode 100644
index 8531e69..0000000
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-#include <cpu/amd/amdfam10_sysconf.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c
deleted file mode 100644
index 46ed054..0000000
--- a/src/mainboard/supermicro/h8scm/get_bus_conf.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-#include <cpu/amd/amdfam10_sysconf.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < 0; i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c
deleted file mode 100644
index 087c042..0000000
--- a/src/mainboard/tyan/s8226/get_bus_conf.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void);
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < 0; i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
1
0
New patch to review for coreboot: 22bdb7b AGESA: Have IRQ routing in mptables
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6361
-gerrit
commit 22bdb7b501d9cd4f0860ab6de116746b78c42cf4
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Jul 25 17:33:12 2014 +0300
AGESA: Have IRQ routing in mptables
MP table should be complete with IRQ routing information even
when we have ACPI tables.
Change-Id: Ieeaed442aea6217f4477b7ac7e06a1926eec8996
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/inagua/mptable.c | 4 ----
src/mainboard/amd/south_station/mptable.c | 4 ----
src/mainboard/amd/torpedo/mptable.c | 4 ----
src/mainboard/amd/union_station/mptable.c | 4 ----
src/mainboard/asrock/e350m1/mptable.c | 4 ----
src/mainboard/gizmosphere/gizmo/mptable.c | 4 ----
src/mainboard/lippert/frontrunner-af/mptable.c | 4 ----
src/mainboard/lippert/toucan-af/mptable.c | 4 ----
8 files changed, 32 deletions(-)
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 5fdac94..cfe1837 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -83,12 +83,8 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 4b4658c..32af39a 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -79,12 +79,8 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 821bcde..a9236ed 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -159,12 +159,8 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 4b4658c..32af39a 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -79,12 +79,8 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 198ac21..0b0626d 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -80,12 +80,8 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index 701cd7b..fddcc4d 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -80,12 +80,8 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index 8b57167..5aa6160 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -79,12 +79,8 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index 8b57167..5aa6160 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -79,12 +79,8 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
1
0
Patch set updated for coreboot: a24de45 AGESA boards: Use devicetree for PCI bus enumeration
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6358
-gerrit
commit a24de45585f6fa434f5c3b997437d093ec3d13af
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 15:24:15 2014 +0300
AGESA boards: Use devicetree for PCI bus enumeration
Previously MP table contained PCI_INT entries for PCI bus behind bridge
0:14.4 even if said PCI bridge function was disabled.
Remove these as invalid, indeterminate bus number could cause conflicts.
PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2]
were invalid as there is no PCI bridge hardware on device 0:14.0.
Remove these as invalid, indeterminate bus number could cause conflicts.
Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/dinar/mptable.c | 42 ++++++++++++-----------
src/mainboard/amd/inagua/mptable.c | 45 ++++++++++++-------------
src/mainboard/amd/olivehill/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/parmer/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/persimmon/mptable.c | 16 +++++----
src/mainboard/amd/south_station/mptable.c | 45 ++++++++++++-------------
src/mainboard/amd/thatcher/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/torpedo/mptable.c | 46 ++++++++++++--------------
src/mainboard/amd/union_station/mptable.c | 45 ++++++++++++-------------
src/mainboard/asrock/e350m1/mptable.c | 45 ++++++++++++-------------
src/mainboard/asrock/imb-a180/mptable.c | 44 ++++++++++++------------
src/mainboard/asus/f2a85-m/mptable.c | 20 +++++------
src/mainboard/gizmosphere/gizmo/mptable.c | 45 ++++++++++++-------------
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 44 ++++++++++++------------
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 16 +++++----
src/mainboard/lippert/frontrunner-af/mptable.c | 45 ++++++++++++-------------
src/mainboard/lippert/toucan-af/mptable.c | 45 ++++++++++++-------------
src/mainboard/supermicro/h8qgi/mptable.c | 41 ++++++++++++-----------
src/mainboard/supermicro/h8scm/mptable.c | 41 ++++++++++++-----------
src/mainboard/tyan/s8226/mptable.c | 41 ++++++++++++-----------
20 files changed, 386 insertions(+), 412 deletions(-)
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index d239a7e..4e481f5 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam15.h>
-extern u8 bus_sb700[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -126,24 +124,28 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index cfe1837..4a57d3c 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 4a4b15d..c06863b 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_yangtze[6];
-
extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
@@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 06c1791..2f5179f 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[0x54] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 1c7e86a..0d5f5ce 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -31,11 +31,9 @@
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
-extern u8 bus_sb800[6];
extern u32 apicid_sb800;
extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -110,11 +108,15 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
- /* PCI_SLOT 0 */
- PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0 */
+ PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
+ PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
+ PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
+ PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 32af39a..57eaa0e 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -104,27 +101,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 089d260..7f9aa7c 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index a9236ed..477d97a 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -30,9 +30,6 @@
#include "SbPlatform.h"
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_sb900[6];
-
-
u32 apicid_sb900;
u8 picr_data[] = {
@@ -189,27 +186,28 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb900[1], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb900[1], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb900[1], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 32af39a..57eaa0e 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -104,27 +101,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 0b0626d..2c945cf 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -28,11 +28,8 @@
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -105,27 +102,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index a8326a0..11da130 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_yangtze[6];
-
extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
@@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index cc3e9ec..3316b83 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -28,8 +28,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[] = {
@@ -155,15 +153,15 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index fddcc4d..c16c486 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -28,11 +28,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -105,27 +102,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 40b2e04..9ef2b81 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -29,8 +29,6 @@
#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[0x54] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 1bbe487..b621dd2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -33,11 +33,9 @@
#include <southbridge/amd/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u8 bus_sb800[6];
extern u32 apicid_sb800;
extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -112,11 +110,15 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
- /* PCI_SLOT 0 */
- PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0 */
+ PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
+ PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
+ PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
+ PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ }
/* On-board Realtek NIC 2. (PCIe PortA) */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index 5aa6160..eeae66f 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -104,27 +101,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index 5aa6160..eeae66f 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -104,27 +101,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/tyan/s8226/mptable.c
+++ b/src/mainboard/tyan/s8226/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
1
0
Patch set updated for coreboot: 12c7516 AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6359
-gerrit
commit 12c7516c1a1a97a89537fbb047cb769a355e0a6e
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 10:24:20 2014 +0300
AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/inagua/get_bus_conf.c | 7 -----
src/mainboard/amd/inagua/mptable.c | 21 ++++++++-------
src/mainboard/amd/olivehill/get_bus_conf.c | 7 -----
src/mainboard/amd/olivehill/mptable.c | 31 +++++++++-------------
src/mainboard/amd/parmer/get_bus_conf.c | 7 -----
src/mainboard/amd/parmer/mptable.c | 29 +++++++++-----------
src/mainboard/amd/persimmon/get_bus_conf.c | 15 -----------
src/mainboard/amd/persimmon/mptable.c | 17 +++++++-----
src/mainboard/amd/south_station/get_bus_conf.c | 8 ------
src/mainboard/amd/south_station/mptable.c | 20 ++++++++------
src/mainboard/amd/thatcher/get_bus_conf.c | 7 -----
src/mainboard/amd/thatcher/mptable.c | 29 +++++++++-----------
src/mainboard/amd/union_station/get_bus_conf.c | 7 -----
src/mainboard/amd/union_station/mptable.c | 20 ++++++++------
src/mainboard/asrock/e350m1/get_bus_conf.c | 7 -----
src/mainboard/asrock/e350m1/mptable.c | 20 ++++++++------
src/mainboard/asrock/imb-a180/get_bus_conf.c | 8 ------
src/mainboard/asrock/imb-a180/mptable.c | 30 +++++++++------------
src/mainboard/asus/f2a85-m/get_bus_conf.c | 8 ------
src/mainboard/asus/f2a85-m/mptable.c | 28 +++++++++----------
src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 7 -----
src/mainboard/gizmosphere/gizmo/mptable.c | 20 ++++++++------
src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 7 -----
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 28 +++++++++----------
src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 17 ------------
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 16 +++++++----
.../lippert/frontrunner-af/get_bus_conf.c | 8 ------
src/mainboard/lippert/frontrunner-af/mptable.c | 20 +++++++-------
src/mainboard/lippert/toucan-af/get_bus_conf.c | 7 -----
src/mainboard/lippert/toucan-af/mptable.c | 20 +++++++-------
30 files changed, 178 insertions(+), 298 deletions(-)
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index c39decf..fb939ab 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -31,12 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +57,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 4a57d3c..7686bd2 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -22,13 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -48,6 +47,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -58,14 +65,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -75,13 +78,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
index 2765ed7..582d7ed 100644
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ b/src/mainboard/amd/olivehill/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_yangtze[6];
-u32 apicid_yangtze;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
memset(bus_yangtze, 0, sizeof(bus_yangtze));
@@ -59,8 +56,4 @@ void get_bus_conf(void)
bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_yangtze = apicid_base;
}
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index c06863b..db4a3ff 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_yangtze;
-
u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,19 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_yangtze = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
-
- smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
@@ -153,13 +148,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c
index 3b3daf9..8ff9ed3 100644
--- a/src/mainboard/amd/parmer/get_bus_conf.c
+++ b/src/mainboard/amd/parmer/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -64,8 +61,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 2f5179f..05da01a 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
-
u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 9434429..59881d1 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -32,14 +32,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-u32 apicver_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -63,15 +58,5 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
}
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 0d5f5ce..1227d89 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -31,14 +31,19 @@
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
-extern u32 apicid_sb800;
-extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -62,20 +67,20 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c
index 53c7953..dcdd0b2 100644
--- a/src/mainboard/amd/south_station/get_bus_conf.c
+++ b/src/mainboard/amd/south_station/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -63,9 +60,4 @@ void get_bus_conf(void)
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 57eaa0e..c2ec4a2 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -22,12 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -44,6 +44,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +62,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,13 +75,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c
index 9f5f15a..6d0f903 100644
--- a/src/mainboard/amd/thatcher/get_bus_conf.c
+++ b/src/mainboard/amd/thatcher/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,8 +58,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 7f9aa7c..8ddd1b6 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
-
u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c
index 52b5d88..8824ca1 100644
--- a/src/mainboard/amd/union_station/get_bus_conf.c
+++ b/src/mainboard/amd/union_station/get_bus_conf.c
@@ -31,12 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
device_t dev;
int i;
@@ -66,8 +63,4 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 57eaa0e..c2ec4a2 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -22,12 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -44,6 +44,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +62,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,13 +75,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index f2c8056..fed8075 100644
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,8 +58,4 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 2c945cf..14fa316 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/amd/amdfam14.h>
@@ -28,7 +29,6 @@
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -45,6 +45,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -55,14 +63,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -72,13 +76,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c
index 9a20b98..c2af8fa 100644
--- a/src/mainboard/asrock/imb-a180/get_bus_conf.c
+++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c
@@ -30,14 +30,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_yangtze[6];
-u32 apicid_yangtze;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +56,4 @@ void get_bus_conf(void)
bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_yangtze = apicid_base;
}
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index 11da130..d9ca7b7 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,8 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -70,9 +69,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,19 +93,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_yangtze = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
-
- smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
@@ -153,13 +149,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c
index fe8253e..81417e7 100644
--- a/src/mainboard/asus/f2a85-m/get_bus_conf.c
+++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c
@@ -31,14 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
-
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -62,7 +57,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index 3316b83..cc81819 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/amd/amdfam15.h>
#include <cpu/x86/lapic.h>
@@ -27,8 +28,6 @@
#include <string.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -69,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -86,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -113,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x0, 0x0, 0x10);
diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
index 2cc2c0c..54151f7 100755
--- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
+++ b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
@@ -32,13 +32,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -62,8 +59,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index c16c486..ed52722 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -23,12 +23,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -45,6 +45,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -55,14 +63,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -72,13 +76,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
index f0494ab..ef08e7f 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
@@ -32,13 +32,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -59,8 +56,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 9ef2b81..f47b9d9 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/amd/amdfam15.h>
@@ -28,8 +29,6 @@
#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -70,9 +69,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +93,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +110,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
index cc3ffbb..2cfc5c6 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
@@ -33,14 +33,9 @@
* mptable and acpi_tables where busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-u32 apicver_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,16 +56,4 @@ void get_bus_conf(void)
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
-
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index b621dd2..4390605 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -33,14 +33,20 @@
#include <southbridge/amd/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u32 apicid_sb800;
-extern u32 apicver_sb800;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -64,20 +70,20 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
index 42270af..1dc1cca 100644
--- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
+++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
@@ -31,13 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +56,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index eeae66f..0a9088f 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -27,8 +27,6 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -44,6 +42,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +60,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,13 +73,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c
index eb40c54..e67c27d 100644
--- a/src/mainboard/lippert/toucan-af/get_bus_conf.c
+++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -59,8 +56,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index eeae66f..0a9088f 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -27,8 +27,6 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -44,6 +42,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +60,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,13 +73,13 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
1
0
Patch set updated for coreboot: e316e6b AGESA boards: Drop get_bus_conf.c files
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6360
-gerrit
commit e316e6bc5c72067e6f3f292fae9e62272357cc1d
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 15:24:15 2014 +0300
AGESA boards: Drop get_bus_conf.c files
The only remaining purpose for get_bus_conf() was to fill in obscure
bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete
enumeration is available in devicetree and PCI configuration space so
discard these arrays.
Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/agesa/amd_late_init.c | 5 --
src/mainboard/amd/dinar/get_bus_conf.c | 58 -------------------
src/mainboard/amd/inagua/get_bus_conf.c | 60 --------------------
src/mainboard/amd/olivehill/get_bus_conf.c | 59 -------------------
src/mainboard/amd/parmer/get_bus_conf.c | 64 ---------------------
src/mainboard/amd/persimmon/get_bus_conf.c | 62 --------------------
src/mainboard/amd/south_station/get_bus_conf.c | 63 ---------------------
src/mainboard/amd/thatcher/get_bus_conf.c | 61 --------------------
src/mainboard/amd/torpedo/get_bus_conf.c | 63 ---------------------
src/mainboard/amd/union_station/get_bus_conf.c | 66 ----------------------
src/mainboard/asrock/e350m1/get_bus_conf.c | 61 --------------------
src/mainboard/asrock/imb-a180/get_bus_conf.c | 59 -------------------
src/mainboard/asus/f2a85-m/get_bus_conf.c | 60 --------------------
src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 62 --------------------
src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 59 -------------------
src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 59 -------------------
.../lippert/frontrunner-af/get_bus_conf.c | 59 -------------------
src/mainboard/lippert/toucan-af/get_bus_conf.c | 59 -------------------
src/mainboard/supermicro/h8qgi/get_bus_conf.c | 53 -----------------
src/mainboard/supermicro/h8scm/get_bus_conf.c | 53 -----------------
src/mainboard/tyan/s8226/get_bus_conf.c | 54 ------------------
21 files changed, 1199 deletions(-)
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index c8b941d..faba328 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -31,8 +31,6 @@
#include <sb_cimx.h>
#endif
-void get_bus_conf(void);
-
static void agesawrapper_post_device(void *unused)
{
if (acpi_is_wakeup_s3())
@@ -40,9 +38,6 @@ static void agesawrapper_post_device(void *unused)
AGESAWRAPPER(amdinitlate);
- /* Preparation for write_tables(). */
- get_bus_conf();
-
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
device_t dev;
u32 value;
diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c
deleted file mode 100644
index 5ab2ddd..0000000
--- a/src/mainboard/amd/dinar/get_bus_conf.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam15.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sb700[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
- printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
-
-
- for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) {
- bus_sb700[i] = 0;
- }
-
-
- /* sb700 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
-}
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
deleted file mode 100644
index fb939ab..0000000
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
deleted file mode 100644
index 582d7ed..0000000
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_yangtze[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
- memset(bus_yangtze, 0, sizeof(bus_yangtze));
-
-
-
- /* yangtze */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c
deleted file mode 100644
index 8ff9ed3..0000000
--- a/src/mainboard/amd/parmer/get_bus_conf.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
deleted file mode 100644
index 59881d1..0000000
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#include <arch/ioapic.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-
-}
diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c
deleted file mode 100644
index dcdd0b2..0000000
--- a/src/mainboard/amd/south_station/get_bus_conf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c
deleted file mode 100644
index 6d0f903..0000000
--- a/src/mainboard/amd/thatcher/get_bus_conf.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
deleted file mode 100644
index b88e3fb..0000000
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam12.h>
-#include "agesawrapper.h"
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb900[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
- printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__);
-
-
- memset(bus_sb900, 0, sizeof(bus_sb900));
-
-
-
- /* sb900 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0,
- PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb900[2 + i] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- printk(BIOS_DEBUG, "Mainboard - %s - %s - End.\n", __FILE__, __func__);
-}
diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c
deleted file mode 100644
index 8824ca1..0000000
--- a/src/mainboard/amd/union_station/get_bus_conf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
-
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-}
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
deleted file mode 100644
index fed8075..0000000
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-}
diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c
deleted file mode 100644
index c2af8fa..0000000
--- a/src/mainboard/asrock/imb-a180/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_yangtze[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_yangtze, 0, sizeof(bus_yangtze));
-
-
-
- /* yangtze */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c
deleted file mode 100644
index 81417e7..0000000
--- a/src/mainboard/asus/f2a85-m/get_bus_conf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <console/console.h>
-#include <cpu/amd/amdfam15.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
deleted file mode 100755
index 54151f7..0000000
--- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
deleted file mode 100644
index ef08e7f..0000000
--- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <console/console.h>
-#include <cpu/amd/amdfam15.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <southbridge/amd/agesa/hudson/imc.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
deleted file mode 100644
index 2cfc5c6..0000000
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <arch/ioapic.h>
-#include <console/console.h>
-#include <cpu/amd/amdfam14.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-/**
- * Global variables for mainboard layouts. These are shared by irqtable,
- * mptable and acpi_tables where busnum is default.
- */
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
deleted file mode 100644
index 1dc1cca..0000000
--- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c
deleted file mode 100644
index e67c27d..0000000
--- a/src/mainboard/lippert/toucan-af/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
deleted file mode 100644
index 8531e69..0000000
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-#include <cpu/amd/amdfam10_sysconf.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c
deleted file mode 100644
index 46ed054..0000000
--- a/src/mainboard/supermicro/h8scm/get_bus_conf.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-#include <cpu/amd/amdfam10_sysconf.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < 0; i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c
deleted file mode 100644
index 087c042..0000000
--- a/src/mainboard/tyan/s8226/get_bus_conf.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void);
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < 0; i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
1
0
New patch to review for coreboot: d80b2fb AGESA boards: Drop get_bus_conf.c files
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6360
-gerrit
commit d80b2fb184268b9ceb9f37b7de59380327ac2570
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 15:24:15 2014 +0300
AGESA boards: Drop get_bus_conf.c files
The only remaining purpose for get_bus_conf() was to fill in obscure
bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete
enumeration is available in devicetree and PCI configuration space so
discard these arrays.
Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/agesa/amd_late_init.c | 5 --
src/mainboard/amd/dinar/get_bus_conf.c | 58 -------------------
src/mainboard/amd/inagua/get_bus_conf.c | 60 --------------------
src/mainboard/amd/olivehill/get_bus_conf.c | 59 -------------------
src/mainboard/amd/parmer/get_bus_conf.c | 64 ---------------------
src/mainboard/amd/persimmon/get_bus_conf.c | 62 --------------------
src/mainboard/amd/south_station/get_bus_conf.c | 63 ---------------------
src/mainboard/amd/thatcher/get_bus_conf.c | 61 --------------------
src/mainboard/amd/torpedo/get_bus_conf.c | 63 ---------------------
src/mainboard/amd/union_station/get_bus_conf.c | 66 ----------------------
src/mainboard/asrock/e350m1/get_bus_conf.c | 61 --------------------
src/mainboard/asrock/imb-a180/get_bus_conf.c | 59 -------------------
src/mainboard/asus/f2a85-m/get_bus_conf.c | 60 --------------------
src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 62 --------------------
src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 59 -------------------
src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 59 -------------------
.../lippert/frontrunner-af/get_bus_conf.c | 59 -------------------
src/mainboard/lippert/toucan-af/get_bus_conf.c | 59 -------------------
src/mainboard/supermicro/h8qgi/get_bus_conf.c | 53 -----------------
src/mainboard/supermicro/h8scm/get_bus_conf.c | 53 -----------------
src/mainboard/tyan/s8226/get_bus_conf.c | 54 ------------------
21 files changed, 1199 deletions(-)
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index c8b941d..faba328 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -31,8 +31,6 @@
#include <sb_cimx.h>
#endif
-void get_bus_conf(void);
-
static void agesawrapper_post_device(void *unused)
{
if (acpi_is_wakeup_s3())
@@ -40,9 +38,6 @@ static void agesawrapper_post_device(void *unused)
AGESAWRAPPER(amdinitlate);
- /* Preparation for write_tables(). */
- get_bus_conf();
-
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
device_t dev;
u32 value;
diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c
deleted file mode 100644
index 5ab2ddd..0000000
--- a/src/mainboard/amd/dinar/get_bus_conf.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam15.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sb700[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
- printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
-
-
- for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) {
- bus_sb700[i] = 0;
- }
-
-
- /* sb700 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
-}
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
deleted file mode 100644
index fb939ab..0000000
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
deleted file mode 100644
index 582d7ed..0000000
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_yangtze[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
- memset(bus_yangtze, 0, sizeof(bus_yangtze));
-
-
-
- /* yangtze */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c
deleted file mode 100644
index 8ff9ed3..0000000
--- a/src/mainboard/amd/parmer/get_bus_conf.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
deleted file mode 100644
index 59881d1..0000000
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#include <arch/ioapic.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-
-}
diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c
deleted file mode 100644
index dcdd0b2..0000000
--- a/src/mainboard/amd/south_station/get_bus_conf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c
deleted file mode 100644
index 6d0f903..0000000
--- a/src/mainboard/amd/thatcher/get_bus_conf.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
-#include "imc.h"
-#endif
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
deleted file mode 100644
index b88e3fb..0000000
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam12.h>
-#include "agesawrapper.h"
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb900[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
- printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__);
-
-
- memset(bus_sb900, 0, sizeof(bus_sb900));
-
-
-
- /* sb900 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0,
- PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb900[2 + i] =
- pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
- printk(BIOS_DEBUG, "Mainboard - %s - %s - End.\n", __FILE__, __func__);
-}
diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c
deleted file mode 100644
index 8824ca1..0000000
--- a/src/mainboard/amd/union_station/get_bus_conf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
-
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
-
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-}
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
deleted file mode 100644
index fed8075..0000000
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-
-}
diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c
deleted file mode 100644
index c2af8fa..0000000
--- a/src/mainboard/asrock/imb-a180/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_yangtze[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
-
- memset(bus_yangtze, 0, sizeof(bus_yangtze));
-
-
-
- /* yangtze */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c
deleted file mode 100644
index 81417e7..0000000
--- a/src/mainboard/asus/f2a85-m/get_bus_conf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <console/console.h>
-#include <cpu/amd/amdfam15.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
deleted file mode 100755
index 54151f7..0000000
--- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
deleted file mode 100644
index ef08e7f..0000000
--- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <console/console.h>
-#include <cpu/amd/amdfam15.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <southbridge/amd/agesa/hudson/imc.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_hudson[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_hudson, 0, sizeof(bus_hudson));
-
-
- /* Hudson */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
deleted file mode 100644
index 2cfc5c6..0000000
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "agesawrapper.h"
-
-#include <arch/ioapic.h>
-#include <console/console.h>
-#include <cpu/amd/amdfam14.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-/**
- * Global variables for mainboard layouts. These are shared by irqtable,
- * mptable and acpi_tables where busnum is default.
- */
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-}
diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
deleted file mode 100644
index 1dc1cca..0000000
--- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c
deleted file mode 100644
index e67c27d..0000000
--- a/src/mainboard/lippert/toucan-af/get_bus_conf.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/amdfam14.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sb800[6];
-
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- memset(bus_sb800, 0, sizeof(bus_sb800));
-
-
- /* sb800 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- for (i = 0; i < 4; i++) {
- dev = dev_find_slot(0, PCI_DEVFN(0x14, i));
- if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- }
-
-}
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
deleted file mode 100644
index 8531e69..0000000
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-#include <cpu/amd/amdfam10_sysconf.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c
deleted file mode 100644
index 46ed054..0000000
--- a/src/mainboard/supermicro/h8scm/get_bus_conf.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-#include <cpu/amd/amdfam10_sysconf.h>
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < 0; i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c
deleted file mode 100644
index 087c042..0000000
--- a/src/mainboard/tyan/s8226/get_bus_conf.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "agesawrapper.h"
-
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
- * and acpi_tables busnum is default.
- */
-u8 bus_sp5100[2];
-
-void get_bus_conf(void);
-
-void get_bus_conf(void)
-{
- device_t dev;
- int i;
-
-
- for (i = 0; i < 0; i++) {
- bus_sp5100[i] = 0;
- }
-
- bus_sp5100[0] = 0;
-
- /* sp5100 */
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-
- if (dev) {
- bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-}
1
0
New patch to review for coreboot: bdfa67b AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6359
-gerrit
commit bdfa67b1a38ef1a9c5440da2e27312674941adc4
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 10:24:20 2014 +0300
AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/inagua/get_bus_conf.c | 7 -----
src/mainboard/amd/inagua/mptable.c | 21 ++++++++-------
src/mainboard/amd/olivehill/get_bus_conf.c | 7 -----
src/mainboard/amd/olivehill/mptable.c | 31 +++++++++-------------
src/mainboard/amd/parmer/get_bus_conf.c | 7 -----
src/mainboard/amd/parmer/mptable.c | 29 +++++++++-----------
src/mainboard/amd/persimmon/get_bus_conf.c | 15 -----------
src/mainboard/amd/persimmon/mptable.c | 17 +++++++-----
src/mainboard/amd/south_station/get_bus_conf.c | 8 ------
src/mainboard/amd/south_station/mptable.c | 20 ++++++++------
src/mainboard/amd/thatcher/get_bus_conf.c | 7 -----
src/mainboard/amd/thatcher/mptable.c | 29 +++++++++-----------
src/mainboard/amd/union_station/get_bus_conf.c | 7 -----
src/mainboard/amd/union_station/mptable.c | 20 ++++++++------
src/mainboard/asrock/e350m1/get_bus_conf.c | 7 -----
src/mainboard/asrock/e350m1/mptable.c | 20 ++++++++------
src/mainboard/asrock/imb-a180/get_bus_conf.c | 8 ------
src/mainboard/asrock/imb-a180/mptable.c | 30 +++++++++------------
src/mainboard/asus/f2a85-m/get_bus_conf.c | 8 ------
src/mainboard/asus/f2a85-m/mptable.c | 28 +++++++++----------
src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 7 -----
src/mainboard/gizmosphere/gizmo/mptable.c | 20 ++++++++------
src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 7 -----
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 28 +++++++++----------
src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 17 ------------
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 16 +++++++----
.../lippert/frontrunner-af/get_bus_conf.c | 8 ------
src/mainboard/lippert/frontrunner-af/mptable.c | 20 +++++++-------
src/mainboard/lippert/toucan-af/get_bus_conf.c | 7 -----
src/mainboard/lippert/toucan-af/mptable.c | 20 +++++++-------
30 files changed, 178 insertions(+), 298 deletions(-)
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index c39decf..fb939ab 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -31,12 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +57,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 5be5dbc..93f7ac0 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -22,13 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -48,6 +47,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -58,14 +65,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -75,14 +78,14 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
index 2765ed7..582d7ed 100644
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ b/src/mainboard/amd/olivehill/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_yangtze[6];
-u32 apicid_yangtze;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
memset(bus_yangtze, 0, sizeof(bus_yangtze));
@@ -59,8 +56,4 @@ void get_bus_conf(void)
bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_yangtze = apicid_base;
}
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index c06863b..db4a3ff 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_yangtze;
-
u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,19 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_yangtze = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
-
- smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
@@ -153,13 +148,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c
index 3b3daf9..8ff9ed3 100644
--- a/src/mainboard/amd/parmer/get_bus_conf.c
+++ b/src/mainboard/amd/parmer/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -64,8 +61,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 2f5179f..05da01a 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
-
u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 9434429..59881d1 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -32,14 +32,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-u32 apicver_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -63,15 +58,5 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
}
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 0d5f5ce..1227d89 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -31,14 +31,19 @@
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
-extern u32 apicid_sb800;
-extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -62,20 +67,20 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c
index 53c7953..dcdd0b2 100644
--- a/src/mainboard/amd/south_station/get_bus_conf.c
+++ b/src/mainboard/amd/south_station/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -63,9 +60,4 @@ void get_bus_conf(void)
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index d7a4357..6539327 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -22,12 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -44,6 +44,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +62,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,14 +75,14 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c
index 9f5f15a..6d0f903 100644
--- a/src/mainboard/amd/thatcher/get_bus_conf.c
+++ b/src/mainboard/amd/thatcher/get_bus_conf.c
@@ -33,13 +33,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,8 +58,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 7f9aa7c..8ddd1b6 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
-
u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c
index 52b5d88..8824ca1 100644
--- a/src/mainboard/amd/union_station/get_bus_conf.c
+++ b/src/mainboard/amd/union_station/get_bus_conf.c
@@ -31,12 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
device_t dev;
int i;
@@ -66,8 +63,4 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index d7a4357..6539327 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -22,12 +22,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -44,6 +44,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +62,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,14 +75,14 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index f2c8056..fed8075 100644
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,8 +58,4 @@ void get_bus_conf(void)
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index fd2f712..4d563ea 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/amd/amdfam14.h>
@@ -28,7 +29,6 @@
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -45,6 +45,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -55,14 +63,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -72,14 +76,14 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c
index 9a20b98..c2af8fa 100644
--- a/src/mainboard/asrock/imb-a180/get_bus_conf.c
+++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c
@@ -30,14 +30,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_yangtze[6];
-u32 apicid_yangtze;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +56,4 @@ void get_bus_conf(void)
bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_yangtze = apicid_base;
}
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index 11da130..d9ca7b7 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam15.h>
@@ -28,8 +29,6 @@
#include <cpu/x86/lapic.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -70,9 +69,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,19 +93,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_yangtze = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
-
- smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
@@ -153,13 +149,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c
index fe8253e..81417e7 100644
--- a/src/mainboard/asus/f2a85-m/get_bus_conf.c
+++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c
@@ -31,14 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
-
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -62,7 +57,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index 3316b83..cc81819 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/amd/amdfam15.h>
#include <cpu/x86/lapic.h>
@@ -27,8 +28,6 @@
#include <string.h>
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -69,9 +68,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -86,17 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -113,13 +109,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x0, 0x0, 0x10);
diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
index 2cc2c0c..54151f7 100755
--- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
+++ b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c
@@ -32,13 +32,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -62,8 +59,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index aa2fad4..2a3f32a 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -23,12 +23,12 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -45,6 +45,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -55,14 +63,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -72,14 +76,14 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
index f0494ab..ef08e7f 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c
@@ -32,13 +32,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_hudson[6];
-u32 apicid_hudson;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -59,8 +56,4 @@ void get_bus_conf(void)
bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_hudson = apicid_base;
}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 9ef2b81..f47b9d9 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/amd/amdfam15.h>
@@ -28,8 +29,6 @@
#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */
-#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -70,9 +69,16 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u32 dword;
u8 byte;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +93,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
-
- dword = 0;
- dword = pm_read8(0x34) & 0xF0;
- dword |= (pm_read8(0x35) & 0xFF) << 8;
- dword |= (pm_read8(0x36) & 0xFF) << 16;
- dword |= (pm_read8(0x37) & 0xFF) << 24;
- /* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_hudson = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +110,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
index cc3ffbb..2cfc5c6 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
@@ -33,14 +33,9 @@
* mptable and acpi_tables where busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-u32 apicver_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,16 +56,4 @@ void get_bus_conf(void)
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
-
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index b621dd2..4390605 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -33,14 +33,20 @@
#include <southbridge/amd/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u32 apicid_sb800;
-extern u32 apicver_sb800;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -64,20 +70,20 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
index 42270af..1dc1cca 100644
--- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
+++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c
@@ -31,13 +31,9 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -60,8 +56,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index f5de39e..d9cdc2f 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -27,8 +27,6 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -44,6 +42,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +60,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,14 +73,14 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c
index eb40c54..e67c27d 100644
--- a/src/mainboard/lippert/toucan-af/get_bus_conf.c
+++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c
@@ -31,13 +31,10 @@
* and acpi_tables busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -59,8 +56,4 @@ void get_bus_conf(void)
}
}
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
-
}
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index f5de39e..d9cdc2f 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -27,8 +27,6 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -44,6 +42,14 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +60,10 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
- u32 dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
@@ -71,14 +73,14 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
1
0
New patch to review for coreboot: c4eb66b AGESA boards: Use devicetree for PCI bus enumeration
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6358
-gerrit
commit c4eb66bf74931c69a81606688062e7be0cf7ca89
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 15:24:15 2014 +0300
AGESA boards: Use devicetree for PCI bus enumeration
Previously MP table contained PCI_INT entries for PCI bus behind bridge
0:14.4 even if said PCI bridge function was disabled.
Remove these as invalid, indeterminate bus number could cause conflicts.
PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2]
were invalid as there is no PCI bridge hardware on device 0:14.0.
Remove these as invalid, indeterminate bus number could cause conflicts.
Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/dinar/mptable.c | 42 ++++++++++++-----------
src/mainboard/amd/inagua/mptable.c | 45 ++++++++++++-------------
src/mainboard/amd/olivehill/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/parmer/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/persimmon/mptable.c | 16 +++++----
src/mainboard/amd/south_station/mptable.c | 45 ++++++++++++-------------
src/mainboard/amd/thatcher/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/torpedo/mptable.c | 46 ++++++++++++--------------
src/mainboard/amd/union_station/mptable.c | 45 ++++++++++++-------------
src/mainboard/asrock/e350m1/mptable.c | 45 ++++++++++++-------------
src/mainboard/asrock/imb-a180/mptable.c | 44 ++++++++++++------------
src/mainboard/asus/f2a85-m/mptable.c | 20 +++++------
src/mainboard/gizmosphere/gizmo/mptable.c | 45 ++++++++++++-------------
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 44 ++++++++++++------------
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 16 +++++----
src/mainboard/lippert/frontrunner-af/mptable.c | 45 ++++++++++++-------------
src/mainboard/lippert/toucan-af/mptable.c | 45 ++++++++++++-------------
src/mainboard/supermicro/h8qgi/mptable.c | 41 ++++++++++++-----------
src/mainboard/supermicro/h8scm/mptable.c | 41 ++++++++++++-----------
src/mainboard/tyan/s8226/mptable.c | 41 ++++++++++++-----------
20 files changed, 386 insertions(+), 412 deletions(-)
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index d239a7e..4e481f5 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam15.h>
-extern u8 bus_sb700[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -126,24 +124,28 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 5fdac94..5be5dbc 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -112,27 +109,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 4a4b15d..c06863b 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_yangtze[6];
-
extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
@@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 06c1791..2f5179f 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[0x54] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 1c7e86a..0d5f5ce 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -31,11 +31,9 @@
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
-extern u8 bus_sb800[6];
extern u32 apicid_sb800;
extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -110,11 +108,15 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
- /* PCI_SLOT 0 */
- PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0 */
+ PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
+ PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
+ PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
+ PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 4b4658c..d7a4357 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 089d260..7f9aa7c 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 821bcde..151243a 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -30,9 +30,6 @@
#include "SbPlatform.h"
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_sb900[6];
-
-
u32 apicid_sb900;
u8 picr_data[] = {
@@ -193,27 +190,28 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb900[1], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb900[1], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb900[1], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 4b4658c..d7a4357 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 198ac21..fd2f712 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -28,11 +28,8 @@
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -109,27 +106,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index a8326a0..11da130 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_yangtze[6];
-
extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
@@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index cc3e9ec..3316b83 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -28,8 +28,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[] = {
@@ -155,15 +153,15 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index 701cd7b..aa2fad4 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -28,11 +28,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -109,27 +106,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 40b2e04..9ef2b81 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -29,8 +29,6 @@
#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[0x54] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 1bbe487..b621dd2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -33,11 +33,9 @@
#include <southbridge/amd/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u8 bus_sb800[6];
extern u32 apicid_sb800;
extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -112,11 +110,15 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
- /* PCI_SLOT 0 */
- PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0 */
+ PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
+ PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
+ PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
+ PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ }
/* On-board Realtek NIC 2. (PCIe PortA) */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index 8b57167..f5de39e 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index 8b57167..f5de39e 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/tyan/s8226/mptable.c
+++ b/src/mainboard/tyan/s8226/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
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New patch to review for coreboot: ac11f4f AGESA fam16kb: Move NB config fam16kb out of get_bus_conf()
by Kyösti Mälkki 25 Jul '14
by Kyösti Mälkki 25 Jul '14
25 Jul '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6357
-gerrit
commit ac11f4f96201c91418fe216f02a7ee30a941175d
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 19:27:52 2014 +0300
AGESA fam16kb: Move NB config fam16kb out of get_bus_conf()
Change-Id: Iedb5e1c72afe70f63f39c2dbce4896863d1d275f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/agesa/amd_late_init.c | 14 ++++++++++++++
src/mainboard/amd/olivehill/get_bus_conf.c | 14 --------------
src/mainboard/asrock/imb-a180/get_bus_conf.c | 10 ----------
3 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index f893741..c8b941d 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -43,6 +43,20 @@ static void agesawrapper_post_device(void *unused)
/* Preparation for write_tables(). */
get_bus_conf();
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
+ device_t dev;
+ u32 value;
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
+ pci_write_config32(dev, 0xF8, 0);
+ pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
+
+ /* disable No Snoop */
+ dev = dev_find_slot(0, PCI_DEVFN(1, 1));
+ value = pci_read_config32(dev, 0x60);
+ value &= ~(1 << 11);
+ pci_write_config32(dev, 0x60, value);
+#endif
+
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
/* AMD AGESA does not enable thermal zone, so we enable it here. */
enable_imc_thermal_zone();
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
index a58c61f..2765ed7 100644
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ b/src/mainboard/amd/olivehill/get_bus_conf.c
@@ -39,23 +39,9 @@ u32 apicid_yangtze;
void get_bus_conf(void)
{
u32 apicid_base;
- u32 value;
device_t dev;
int i;
-
-
- dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
- pci_write_config32(dev, 0xF8, 0);
- pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
-
- /* disable No Snoop */
- dev = dev_find_slot(0, PCI_DEVFN(1, 1));
- value = pci_read_config32(dev, 0x60);
- value &= ~(1 << 11);
- pci_write_config32(dev, 0x60, value);
-
-
memset(bus_yangtze, 0, sizeof(bus_yangtze));
diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c
index 17ff8a5..9a20b98 100644
--- a/src/mainboard/asrock/imb-a180/get_bus_conf.c
+++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c
@@ -37,20 +37,10 @@ u32 apicid_yangtze;
void get_bus_conf(void)
{
u32 apicid_base;
- u32 value;
device_t dev;
int i;
- dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
- pci_write_config32(dev, 0xF8, 0);
- pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
-
- /* disable No Snoop */
- dev = dev_find_slot(0, PCI_DEVFN(1, 1));
- value = pci_read_config32(dev, 0x60);
- value &= ~(1 << 11);
- pci_write_config32(dev, 0x60, value);
memset(bus_yangtze, 0, sizeof(bus_yangtze));
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