coreboot-gerrit June 2014

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New patch to review for filo: 25eadf5 Create bzImage formatted FILO image
by Patrick Georgi 13 Jun '14

13 Jun '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5989 -gerrit commit 25eadf5befebb35afdc836cdd17c546e95fea659 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jun 22 14:48:01 2012 +0200 Create bzImage formatted FILO image This can be booted from FILO (ideally by all our versions). Tested on FILO HEAD (eg. booted by itself). Change-Id: I3fa8fe00a8816987c7043c4b64c0792dd90b1691 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- Makefile | 6 ++++ i386/linux_head.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/Makefile b/Makefile index 46010b3..a860236 100644 --- a/Makefile +++ b/Makefile @@ -131,6 +131,12 @@ $(obj)/filo: $(OBJS) $(LIBPAYLOAD) printf " LD $(subst $(shell pwd)/,,$(@))\n" $(LD) -N -T $(ARCHDIR-y)/ldscript $(OBJS) --start-group $(LIBS) --end-group -o $@ +$(obj)/filo.bzImage: $(TARGET) $(obj)/i386/linux_head.o + $(OBJCOPY) -O binary $(obj)/i386/linux_head.o $@.tmp1 + $(OBJCOPY) -O binary $< $@.tmp2 + cat $@.tmp1 $@.tmp2 > $@.tmp + mv $@.tmp $@ + $(TARGET): $(obj)/filo $(obj)/filo.map printf " STRIP $(subst $(shell pwd)/,,$(@))\n" $(STRIP) -s $< -o $@ diff --git a/i386/linux_head.c b/i386/linux_head.c new file mode 100644 index 0000000..f089502 --- /dev/null +++ b/i386/linux_head.c @@ -0,0 +1,89 @@ +/* + * This file is part of FILO. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Linux/i386 loader + * Supports bzImage, zImage and Image format. + * + * Based on work by Steve Gehlbach. + * Portions are taken from mkelfImage. + * + * 2003-09 by SONE Takeshi + */ + +#include <libpayload.h> +#include <libpayload-config.h> + +/* The header of Linux/i386 kernel */ +struct linux_header { + u8 reserved1[0x1f1]; /* 0x000 */ + u8 setup_sects; /* 0x1f1 */ + u16 root_flags; /* 0x1f2 */ + u32 syssize; /* 0x1f4 (2.04+) */ + u8 reserved2[2]; /* 0x1f8 */ + u16 vid_mode; /* 0x1fa */ + u16 root_dev; /* 0x1fc */ + u16 boot_sector_magic; /* 0x1fe */ + /* 2.00+ */ + u8 reserved3[2]; /* 0x200 */ + u8 header_magic[4]; /* 0x202 */ + u16 protocol_version; /* 0x206 */ + u32 realmode_swtch; /* 0x208 */ + u16 start_sys; /* 0x20c */ + u16 kver_addr; /* 0x20e */ + u8 type_of_loader; /* 0x210 */ + u8 loadflags; /* 0x211 */ + u16 setup_move_size; /* 0x212 */ + u32 code32_start; /* 0x214 */ + u32 ramdisk_image; /* 0x218 */ + u32 ramdisk_size; /* 0x21c */ + u8 reserved4[4]; /* 0x220 */ + /* 2.01+ */ + u16 heap_end_ptr; /* 0x224 */ + u8 reserved5[2]; /* 0x226 */ + /* 2.02+ */ + u32 cmd_line_ptr; /* 0x228 */ + /* 2.03+ */ + u32 initrd_addr_max; /* 0x22c */ + /* 2.05+ */ + u32 kernel_alignment; /* 0x230 */ + u8 relocatable_kernel; /* 0x234 */ + u8 min_alignment; /* 0x235 (2.10+) */ + u8 reserved6[2]; /* 0x236 */ + /* 2.06+ */ + u32 cmdline_size; /* 0x238 */ + /* 2.07+ */ + u32 hardware_subarch; /* 0x23c */ + u64 hardware_subarch_data;/* 0x240 */ + /* 2.08+ */ + u32 payload_offset; /* 0x248 */ + u32 payload_length; /* 0x24c */ + /* 2.09+ */ + u64 setup_data; /* 0x250 */ + /* 2.10+ */ + u64 pref_address; /* 0x258 */ + u32 init_size; /* 0x260 */ + u8 filler[0x1000-0x264]; +} __attribute__ ((packed)); + +struct linux_header data = { + .setup_sects = 7, + .boot_sector_magic = 0xaa55, + .header_magic = { 'H', 'd', 'r', 'S' }, + .protocol_version = 0x200, + .loadflags = 1, +};

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New patch to review for filo: aabf16e Add flashupdate command
by Patrick Georgi 13 Jun '14

13 Jun '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5988 -gerrit commit aabf16e761d8c6eb2c25a1aceffa336356492c0d Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jul 19 16:40:06 2011 +0200 Add flashupdate command This command allows the user to load a coreboot image, configure its cmos.default file and write it to flash, all from FILO. Change-Id: Ia011deb64bcf75aebe8b67554ad9d9738d90fe59 --- Config.in | 15 ++- Makefile | 1 + flashupdate/Makefile.inc | 29 +++++ flashupdate/flashrom-bridge.c | 73 +++++++++++ flashupdate/flashupdate.c | 277 ++++++++++++++++++++++++++++++++++++++++++ main/grub/builtins.c | 19 ++- x86/ldscript | 6 +- 7 files changed, 413 insertions(+), 7 deletions(-) diff --git a/Config.in b/Config.in index cc48bd3..d9f977a 100644 --- a/Config.in +++ b/Config.in @@ -189,8 +189,7 @@ config FLASHROM_LOCKDOWN default n help Enable system flash memory write protections and lock them down prior - starting the kernel. Flash memory lockdown can be disabled per boot - entry with the new command 'flashrom_unlock'. + starting the kernel. NOTE: Only supported on selected hardware: @@ -199,6 +198,18 @@ config FLASHROM_LOCKDOWN o Intel Cougar Point / Panther Point PCH (FWH + SPI) o AMD SB600 (SPI by locking the flash chip itself) +config FLASHROM_UNLOCK + bool "Provide flashrom_unlock command" + default n + depends on FLASHROM_LOCKDOWN + help + FlashROM lockdown can be disabled per boot entry with the new + command 'flashrom_unlock'. + +config FLASHUPDATE + bool "add flashrom utility to FILO" + default y + endmenu menu "Filesystems" diff --git a/Makefile b/Makefile index 46010b3..570bd87 100644 --- a/Makefile +++ b/Makefile @@ -101,6 +101,7 @@ CFLAGS += $(call cc-option, -fno-stack-protector,) LIBS := $(LIBPAYLOAD) $(LIBGCC) +SUBDIRS-$(CONFIG_USE_GRUB) += flashupdate/ SUBDIRS-y += main/ fs/ drivers/ SUBDIRS-y += $(ARCHDIR-y)/ diff --git a/flashupdate/Makefile.inc b/flashupdate/Makefile.inc new file mode 100644 index 0000000..319add3 --- /dev/null +++ b/flashupdate/Makefile.inc @@ -0,0 +1,29 @@ +# +# Copyright (C) 2011 secunet AG +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +LIBFLASHROM_PREFIX ?= $(obj)/libflashrom +LIBFLASHROM = $(LIBFLASHROM_PREFIX)/lib/libflashrom.a +INCFLASHROM = $(LIBFLASHROM_PREFIX)/include + +ifeq ($(CONFIG_FLASHUPDATE),y) +CPPFLAGS += -I$(INCFLASHROM) +LIBS += $(LIBFLASHROM) +endif + +TARGETS-$(CONFIG_FLASHUPDATE) += flashupdate/flashupdate.o +TARGETS-$(CONFIG_FLASHUPDATE) += flashupdate/flashrom-bridge.o diff --git a/flashupdate/flashrom-bridge.c b/flashupdate/flashrom-bridge.c new file mode 100644 index 0000000..0940389 --- /dev/null +++ b/flashupdate/flashrom-bridge.c @@ -0,0 +1,73 @@ +#include <stdarg.h> +#include <string.h> + +#include "flashchips.h" +#include "flash.h" +#include "programmer.h" + +int new_rom_size; +void *new_rom_data; + +int old_rom_size; +void *old_rom_data; + +// for flashrom +int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +int print(int type, const char *fmt, ...) +{ +#ifdef DEBUG + if (type > MSG_INFO) return 0; + int ret; + va_list args; + va_start(args, fmt); + ret = vprintf(fmt, args); + va_end(args); + return ret; +#else + return 0; +#endif +} + +/* returned memory must be freed by caller */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + return strdup("Unknown"); +} + +int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename) +{ + // we need at least enough space for our image. + if (size < new_rom_size) + return 1; + + // top-align our image into the chip + memcpy(buf + size - new_rom_size, new_rom_data, new_rom_size); + + return 0; +} + +int read_flash_to_file(struct flashctx *flash, const char *filename) +{ + int ret = 0; + unsigned long size = flash->total_size * 1024; + if (size > old_rom_size) { + msg_cerr("old rom buffer not large enough for flash\n"); + ret = 1; + goto out_free; + } + + if (!flash->read) { + msg_cerr("No read function available for this flash chip.\n"); + ret = 1; + goto out_free; + } + if (flash->read(flash, old_rom_data, 0, size)) { + msg_cerr("Read operation failed!\n"); + ret = 1; + goto out_free; + } + +out_free: + return ret; +} + diff --git a/flashupdate/flashupdate.c b/flashupdate/flashupdate.c new file mode 100644 index 0000000..c0f337d --- /dev/null +++ b/flashupdate/flashupdate.c @@ -0,0 +1,277 @@ +#include <stdlib.h> +#include <getopt.h> +#include <libpayload.h> +#include <coreboot_tables.h> +#include <cbfs.h> +#include <grub/shared.h> +#include <fs.h> +#include <pci/pci.h> + +/* flashrom defines */ +#define CONFIG_INTERNAL 1 +#include "flashchips.h" +#include "flash.h" +#include "programmer.h" + +extern int new_rom_size; +extern void *new_rom_data; + +struct flashctx flashchip; + +static void beep_success() +{ + int i; + for (i = 0; i < 5; i++) { + speaker_tone(440, 200); mdelay(300); + speaker_tone(660, 200); mdelay(300); + speaker_tone(880, 200); mdelay(300); + mdelay(3*1000); + } +} + +static void beep_fail() +{ + int i; + for (i = 0; i < 5; i++) { + speaker_tone(1200, 200); mdelay(300); + speaker_tone( 660, 200); mdelay(300); + mdelay(3*1000); + } +} + +static int init_flash(const char* flashtype) +{ + int j; + verbose++; + if (programmer_init(PROGRAMMER_INTERNAL, NULL)) { + grub_printf("Could not initialize programmer\n"); + return -1; + } + for (j = 0; j < registered_programmer_count; j++) { + int current_chip = -1; + do { + current_chip = probe_flash(&registered_programmers[j], ++current_chip, &flashchip, 0); + if ((current_chip != -1) && ((flashtype == NULL) || (strcasecmp(flashchip.name, flashtype) == 0))) { + return 0; + } + } while (current_chip != -1); + } + + grub_printf("Could not find flash chip\n"); + return -1; +} + +static int write_flash(void *imgdata, int size) +{ + return doit(&flashchip, 1, imgdata, 0, 1, 0, 1); +} + +static int test_id_section(void *romarea, unsigned int romsize, int offset, char **vendor, char **model, char **version) +{ + /* data[-1]: romsize + data[-2]: offset top-of-rom to board model + data[-3]: offset top-of-rom to board vendor + data[-4]: offset top-of-rom to build version */ + unsigned int *data = romarea+romsize-offset; + *version = romarea+romsize-data[-4]; + *vendor = romarea+romsize-data[-3]; + *model = romarea+romsize-data[-2]; + /* Assume that data[-1] matches filesize, and that vendor and model are laid out without extra space. + DO NOT assume that model aligns to the offsets, there may be future additions. */ + return ((data[-1] == romsize) && (*vendor+strnlen(*vendor, data[-2])+1 == *model)); +} + +int flashupdate_func(char *arg, int flags) +{ + int result = -1; + int force = 0; + char *chiptype = NULL; + char *vendor = NULL; + char *board = NULL; + char *region = NULL; + + char **argv; + int argc = to_argc_argv(arg, &argv); + + new_rom_data = NULL; + + char opt; + optreset = optind = 1; + while ((opt = getopt(argc, argv, "fc:v:b:i:")) != -1) { + switch (opt) { + case 'f': + force = 1; + break; + case 'c': + chiptype = optarg; + break; + case 'v': + vendor = optarg; + break; + case 'b': + board = optarg; + break; + case 'i': + region = optarg; + break; + default: + grub_printf("unsupported option -%c.\n", opt); + goto out; + break; + } + } + + if (optind >= argc) { + grub_printf("No filename specified.\n"); + goto out; + } + const char *filename = argv[optind]; + + if (vendor && board && + ((strcmp(vendor, cb_mb_vendor_string(lib_sysinfo.mainboard)) != 0) || + (strcmp(board, cb_mb_part_string(lib_sysinfo.mainboard)) != 0))) { + /* since flashupdate semantics is: iff board matches, write flash; + it's a success not to flash on another board. */ + result = 0; + goto out; + } + + if (region) { + register_include_arg(region); + layout_use_ifd(); + } + + /* Step 0: Init programmer/flash to find out if we _can_ flash (we should) */ + if (init_flash(chiptype) == -1) { + grub_printf("Could not initialize flash programmer.\n"); + goto out; + } + + /* Step 1: read requested image file */ + if (!file_open(filename)) { + grub_printf("Could not open file '%s'\n", filename); + goto out; + } + + /* 16K of extra space, since we don't have feof() */ + new_rom_size = flashchip.total_size * 1024 + 16384; + new_rom_data = malloc(new_rom_size); + if (new_rom_data == NULL) { + grub_printf("Could not allocate memory.\n"); + goto out; + } + void *readbuf = new_rom_data; + int len; + grub_printf("Loading image file... "); + while ((len = file_read(readbuf, 16384)) != 0) { + readbuf += len; + /* We can abort if we cut into the last 16K: + * it's more than the flash is able to carry + */ + if (readbuf - new_rom_data > new_rom_size - 16384) { + file_close(); + grub_printf("File too large for flash\n"); + goto out; + } + } + new_rom_size = readbuf - new_rom_data; + file_close(); + grub_printf("done\n"); + + /* retarget all CBFS accesses to new image */ + setup_cbfs_from_ram(new_rom_data, new_rom_size); + + /* Step 2: Check Board IDs (that we work on the right image) */ + const char *cur_version = lib_sysinfo.cb_version; + const char *cur_vendor = cb_mb_vendor_string(lib_sysinfo.mainboard); + const char *cur_board = cb_mb_part_string(lib_sysinfo.mainboard); + + /* Step 2a: check if this is a coreboot image by looking for a CBFS master header */ + if (get_cbfs_header() != 0xffffffff) { + /* Step 2b: look for .id section in new ROM */ + /* There are currently two locations where .id can reside: top-0x10 and top-0x80. There's + no indicator which one is used in any given image, though it should be stable on any given + board. As a heuristic, we can check if the data is sane at each location. */ + char *new_vendor; + char *new_board; + char *new_version; + if (!test_id_section(new_rom_data, new_rom_size, 0x10, &new_vendor, &new_board, &new_version)) + if (!test_id_section(new_rom_data, new_rom_size, 0x80, &new_vendor, &new_board, &new_version)) { + grub_printf("Could not detect if file supports this system.\n"); + goto out; + } + if ((strcmp(cur_vendor, new_vendor) != 0) || (strcmp(cur_board, new_board) != 0)) { + grub_printf("File (%s %s) seems to be incompatible with current system (%s %s).\n", + new_vendor, new_board, cur_vendor, cur_board); + goto out; + } + + /* Step 3: Check image version (so that we don't reflash the same image again and again) */ + if (strcmp(cur_version, new_version) == 0) { + grub_printf("No need to update to the same version '%s'.\n", cur_version); + /* TODO: exit successfully. right? */ + result = 0; + goto out; + } + + /* Step 4: Merge current CMOS data with cmos.defaults */ + /* Step 4a: Load new CMOS data */ + void *cmos_defaults = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT); + void *cmos_layout = cbfs_find_file("cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT); + /* Step 4a1: Point use_mem to cmos.default. */ + mem_accessor_base = cmos_defaults; + if (cmos_defaults && cmos_layout) { + /* Step 4b: Check if current CMOS data is valid. */ + if (options_checksum_valid(use_nvram)) { + /* Step 4c: Iterate over current CMOS data */ + struct cb_cmos_entries *cmos_entry = first_cmos_entry(get_system_option_table()); + do { + /* Step 4c1: Attempt to update new CMOS data with current values. Ignore failures */ + char *val = NULL; + get_option_as_string(use_nvram, get_system_option_table(), &val, cmos_entry->name); + if (val) { + set_option_from_string(use_mem, cmos_layout, val, cmos_entry->name); + } + } while (cmos_entry = next_cmos_entry(cmos_entry)); + } + + /* Step 5: Write merged CMOS image to CMOS */ + /* TODO: do we need to skip 0x32 (RTC century)? */ + int i; + for (i = 14; i < 256; i++) + nvram_write(((u8*)cmos_defaults)[i], i); + + /* Step 6: Set cmos_defaults_loaded=no in CMOS data using new layout */ + set_option_from_string(use_nvram, cmos_layout, "No", "cmos_defaults_loaded"); + + /* Step 6a: Set cmos_defaults_loaded=Yes in cmos.default in ROM image. */ + set_option_from_string(use_mem, cmos_layout, "Yes", "cmos_defaults_loaded"); + } + } else { + if (!force) { + grub_printf("This is a not a coreboot image. Aborting.\n"); + goto out; + } + } + + grub_printf("Writing image to flash, please wait.\n"); + /* Step 7: Flash image */ + if (write_flash(new_rom_data, new_rom_size) == 0) { + grub_printf("Flash was updated successfully.\n"); + result = 0; + beep_success(); + } else { + grub_printf("WARNING: Error while updating flash!!\n"); + beep_fail(); + } + + /* success */ + programmer_shutdown(); + +out: + if (new_rom_data) free(new_rom_data); + new_rom_data = NULL; + if (argv) free(argv); + return result; +} + diff --git a/main/grub/builtins.c b/main/grub/builtins.c index f77a21a..8ebb829 100644 --- a/main/grub/builtins.c +++ b/main/grub/builtins.c @@ -549,7 +549,7 @@ static struct builtin builtin_find = { }; #endif -#ifdef CONFIG_FLASHROM_LOCKDOWN +#ifdef CONFIG_FLASHROM_UNLOCK /* flashrom_unlock */ /* Disable lockdown of flash memory on boot */ static int flashrom_unlock_func(char *arg, int flags) @@ -568,6 +568,18 @@ static struct builtin builtin_flashrom_unlock = { }; #endif +#ifdef CONFIG_FLASHUPDATE +int flashupdate_func(char *arg, int flags); + +static struct builtin builtin_flashupdate = { + "flashupdate", + flashupdate_func, + BUILTIN_CMDLINE | BUILTIN_HELP_LIST, + "flashupdate DEVICE", + "Update flash ROM from a file loaded from DEVICE (selected by the user)." +}; +#endif + /* help */ #define MAX_SHORT_DOC_LEN 39 #define MAX_LONG_DOC_LEN 66 @@ -1924,9 +1936,12 @@ struct builtin *builtin_table[] = { #ifdef CONFIG_EXPERIMENTAL &builtin_find, #endif -#ifdef CONFIG_FLASHROM_LOCKDOWN +#ifdef CONFIG_FLASHROM_UNLOCK &builtin_flashrom_unlock, #endif +#ifdef CONFIG_FLASHUPDATE + &builtin_flashupdate, +#endif &builtin_help, &builtin_hiddenmenu, &builtin_initrd, diff --git a/x86/ldscript b/x86/ldscript index b260c51..f701d37 100644 --- a/x86/ldscript +++ b/x86/ldscript @@ -26,9 +26,9 @@ OUTPUT_ARCH(i386) ENTRY(entry) -/* 1024KB heap and 64KB stack */ -HEAP_SIZE = 1 * 1024 * 1024; -STACK_SIZE = 64 * 1024; +/* 96MB heap and 256KB stack */ +HEAP_SIZE = 96 * 1024 * 1024; +STACK_SIZE = 256 * 1024; SECTIONS {

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Patch merged into coreboot/master: 4dfc50b mainboard.c: Fix typo in appro*p*riate in comment
by gerrit＠coreboot.org 13 Jun '14

13 Jun '14

the following patch was just integrated into master: commit 4dfc50b8773a2ddc3f87f9e6d988de1d8751ba53 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jun 13 08:47:32 2014 +0200 mainboard.c: Fix typo in appro*p*riate in comment Use the following command to fix all occurences. $ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g' Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5987 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5987 for details. -gerrit

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New patch to review for coreboot: 8d7aa7a mainboard.c: Fix typo in appro*p*riate in comment
by Paul Menzel 13 Jun '14

13 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5987 -gerrit commit 8d7aa7aa4003562d0b975557ef2635f48a8ae365 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jun 13 08:47:32 2014 +0200 mainboard.c: Fix typo in appro*p*riate in comment Use the following command to fix all occurences. $ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g' Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/olivehill/mainboard.c | 2 +- src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/thatcher/mainboard.c | 2 +- src/mainboard/asrock/imb-a180/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mainboard.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index 0a3f9a5..3913898 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -37,7 +37,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index f41d010..8aa76ff 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -37,7 +37,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 266c813..bfb664f 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -53,7 +53,7 @@ static void mainboard_enable(device_t dev) /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index 0a3f9a5..3913898 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -37,7 +37,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 16a2e1c..c37fd76 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -53,7 +53,7 @@ static void mainboard_enable(device_t dev) /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index 81260f1..60a8a55 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -49,7 +49,7 @@ static void mainboard_enable(device_t dev) hudson_enable_smi_generation(); /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index b3c9e3d..7e1c367 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -60,7 +60,7 @@ static void mainboard_enable(device_t dev) /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 57543c2..4e16b3e 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -169,7 +169,7 @@ static void mainboard_enable(device_t dev) /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index f6cf09c..7518203 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -136,7 +136,7 @@ static void mainboard_enable(device_t dev) /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type();

1 0

Patch set updated for coreboot: 9fca6cc superio/fintek/f71869ad: Make SIO HWM conf conditional
by Edward O'Callaghan 13 Jun '14

13 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5841 -gerrit commit 9fca6cc913ceb65c9d43d35c39484a589c78e86b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 14:43:03 2014 +1000 superio/fintek/f71869ad: Make SIO HWM conf conditional Not everyone may like to enable the Super I/O HWM on their board or for their purposes. Hence, make hwm configuration conditional in Kconfig. Change-Id: I8f75bda30a1df4d6f33b73f3d0e6dd2e5dc9963f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 1 + src/superio/fintek/Kconfig | 7 +++++++ src/superio/fintek/f71869ad/Makefile.inc | 4 ++-- src/superio/fintek/f71869ad/chip.h | 2 ++ src/superio/fintek/f71869ad/fintek_internal.h | 5 +++++ 5 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index d90e7a1..bcb95f6 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_FINTEK_F71869AD + select SUPERIO_FINTEK_F71869AD_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index f577898..cad7ff3 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -39,6 +39,13 @@ config SUPERIO_FINTEK_F71869AD bool select SUPERIO_FINTEK_COMMON_ROMSTAGE +config SUPERIO_FINTEK_F71869AD_HWM + bool "Fintek F71869AD HWM" + depends on SUPERIO_FINTEK_F71869AD + help + Configure the Fintek Super I/O hardware monitor fan control registers in + devicetree.cb. + config SUPERIO_FINTEK_F71872 bool select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 1d8cc6a..4de156d 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c -ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD_HWM) += f71869ad_multifunc.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD_HWM) += f71869ad_hwm.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index e12e51d..7dfd3a3 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -24,6 +24,7 @@ #include <stdint.h> struct superio_fintek_f71869ad_config { +#if IS_ENABLED(CONFIG_SUPERIO_FINTEK_F71869AD_HWM) /* Member variables are defined in devicetree.cb. */ uint8_t multi_function_register_1; uint8_t multi_function_register_2; @@ -41,6 +42,7 @@ struct superio_fintek_f71869ad_config { uint8_t hwm_fan1_seg2_speed_count; uint8_t hwm_fan1_seg3_speed_count; uint8_t hwm_fan1_temp_map_sel; +#endif /* CONFIG_SUPERIO_FINTEK_F71869AD_HWM */ }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h index 6856c01..4b3a760 100644 --- a/src/superio/fintek/f71869ad/fintek_internal.h +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -24,7 +24,12 @@ #include <arch/io.h> #include <device/pnp.h> +#if IS_ENABLED(CONFIG_SUPERIO_FINTEK_F71869AD_HWM) void f71869ad_multifunc_init(device_t dev); void f71869ad_hwm_init(device_t dev); +#else +void f71869ad_multifunc_init(device_t dev) {} +void f71869ad_hwm_init(device_t dev) {} +#endif /* CONFIG_SUPERIO_FINTEK_F71869AD_HWM */ #endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */

1 0

Patch set updated for coreboot: 8ddbfd7 mainboard/jetway/nf81-t56n-lf: Port recent Persimmon changes
by Edward O'Callaghan 13 Jun '14

13 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5882 -gerrit commit 8ddbfd79c78fce09b05b61dc09e70194b50b8d8f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 30 11:35:33 2014 +1000 mainboard/jetway/nf81-t56n-lf: Port recent Persimmon changes Port to recent reference board (AMD Persimmon) changes in commits: c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing Change-Id: I307709bfee554bc64788a973da6d9313ca7c0de2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 11 +- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 105 ++++++++++++++++- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 140 +++++++++++------------ 3 files changed, 178 insertions(+), 78 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 8fb0795..688f9dd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -19,6 +19,7 @@ #include "agesawrapper.h" +#include <arch/ioapic.h> #include <console/console.h> #include <cpu/amd/amdfam14.h> #include <device/pci.h> @@ -37,6 +38,7 @@ u8 bus_isa; u8 bus_sb800[6]; u32 apicid_sb800; +u32 apicver_sb800; /** * Here you only need to set value in pci1234 for HT-IO that could be @@ -145,7 +147,14 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; - apicid_sb800 = apicid_base; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); + apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); #if CONFIG_AMD_SB_CIMX sb_Late_Post(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index b3c9e3d..7ad3002 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,11 +31,107 @@ #include <device/pci_def.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <southbridge/amd/cimx/cimx_util.h> +#include <northbridge/amd/agesa/family14/pci_devs.h> void set_pcie_reset(void); void set_pcie_dereset(void); +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + * + * The Persimmon PCI INTA/B/C/D pins are connected to + * FCH pins INTE/F/G/H on the schematic so these need + * to be routed as well. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + /* IDE, SATA */ + [0x40] = 0x0B,0x0B, + /* GPPInt0 - 3 */ + [0x50] = 0x0A,0x0B,0x0A,0x0B +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22/20 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* IDE, SATA */ + [0x40] = 0x11,0x13, + /* GPPInt0 - 3 */ + [0x50] = 0x10,0x11,0x12,0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +/* + * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because PCI INT_PIN swizzling isnt implemented to match + * the IDSEL (dev 3) of the slot, the table is adjusted for the + * swizzle and INTA is connected to PIRQH so PINA/B/C/D on + * off-chip devices should get mapped to PIRQH/E/F/G. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg:06.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + /** * TODO * SB CIMx callback @@ -60,7 +158,7 @@ static void mainboard_enable(device_t dev) /* * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. + * for S3 resume and call the appropriate AGESA/CIMx resume functions. */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); @@ -83,6 +181,9 @@ static void mainboard_enable(device_t dev) */ pm_iowrite(0x29, 0x80); pm_iowrite(0x28, 0x61); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 9be4854..a97810c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,133 +21,121 @@ #include <arch/io.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/amdfam14.h> #include <device/pci.h> +#include <drivers/generic/ioapic/chip.h> #include <stdint.h> #include <string.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +#include <southbridge/amd/cimx/cimx_util.h> extern u8 bus_sb800[6]; - extern u32 apicid_sb800; +extern u32 apicver_sb800; extern u32 bus_type[256]; extern u32 sbdn_sb800; -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; + /* Intialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "JETWAY ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); + /* Get Bus Configuration */ get_bus_conf(); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ - - u32 dword; - u8 byte; - - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword &= 0xFFFFFFF0; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR); + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) -#else -#define PCI_INT(bus, dev, fn, pin) -#endif - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); /* SATA */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); /* On-board NIC & Slot PCIE. */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); - - /* On-board Realtek NIC 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + /* PCI_SLOT 0 */ + PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ + PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ + PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ + PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ /* On-board Realtek NIC 2. (PCIe PortA) */ - PCI_INT(0x0, 0x15, 0x0, 0x10); + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - /* Local Ints: - * Type | Polarity | Trigger | Bus ID | IRQ | APIC ID PIN# - */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ @@ -157,6 +147,6 @@ static void *smp_write_config_table(void *v) unsigned long write_smp_table(unsigned long addr) { void *v; - v = smp_write_floating_table(addr, 0); + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ return (unsigned long)smp_write_config_table(v); }

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New patch to review for coreboot: 8375b84 fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcode
by Martin Roth 12 Jun '14

12 Jun '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5986 -gerrit commit 8375b843cba36297882c250b9c7e0b6b8594a284 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jun 12 12:38:34 2014 -0600 fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcode - Add the Bay Trail B0/B1 microcode. These versions of the SOC were released as a "Super SKU" which had features of all the different SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the number 2 in the third character from the left in the microcode name. - Update the size of the microcode blob. We should be pushing a patch to eliminate the need for this shortly. Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/Kconfig | 2 +- src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 870147e..bce5542 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -102,7 +102,7 @@ config CPU_MICROCODE_CBFS_LOC config CPU_MICROCODE_CBFS_LEN hex - default 0xcc00 + default 0x19800 help This should be updated when the microcode patch changes. diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 9df84dd..43cbf00 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,7 +19,8 @@ unsigned microcode[] = { -/* Size is 0xCC00 - update in Kconfig when the patch gets updated. */ +/* Size is 0x19800 - update in Kconfig when the patch gets updated. */ +#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 #include "M013067331E.h" // M0130673: Baytrail I B2 / B3 };

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New patch to review for coreboot: 1742f18 fsp_baytrail: Add the default FSP location
by Martin Roth 12 Jun '14

12 Jun '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5985 -gerrit commit 1742f184cff4f254e537aa027cab39540b4003ed Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jun 12 12:31:59 2014 -0600 fsp_baytrail: Add the default FSP location The default FSP location needs to be in the chipset, not the mainboard. This was removed from the Bayley Bay mainboard in another patch. Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/fsp/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig index 5df6374..0e4b3b3 100644 --- a/src/soc/intel/fsp_baytrail/fsp/Kconfig +++ b/src/soc/intel/fsp_baytrail/fsp/Kconfig @@ -29,3 +29,13 @@ config FSP_FILE help The path and filename of the Intel FSP binary for this platform. +config FSP_LOC + hex "Intel FSP Binary location in CBFS" + default 0xfffc0000 + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with the Intel's BCT (tool). + + The Bay Trail FSP is built with a preferred base address of + 0xFFFC0000

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New patch to review for coreboot: ab74ca9 fsp_baytrail: remove version from default vbios path
by Martin Roth 12 Jun '14

12 Jun '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5984 -gerrit commit ab74ca954dff0f1fc6384f340a6cabcba77e1cf5 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jun 12 12:20:26 2014 -0600 fsp_baytrail: remove version from default vbios path Intel requested that we remove the version number from the default vbios path. Change-Id: I2590fed0db157e3e430212336fc55eb099d28a72 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 220edf7..870147e 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -154,7 +154,7 @@ config ENABLE_BUILTIN_COM1 config VGA_BIOS_FILE string - default "../intel/cpu/baytrail/vbios/Baytrail_I_36_2_2/Vga.dat" if VGA_BIOS + default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS ## Baytrail Specific FSP Kconfig source src/soc/intel/fsp_baytrail/fsp/Kconfig

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New patch to review for coreboot: 146521e bayleybay_fsp: Add bakersport board variant
by Martin Roth 12 Jun '14

12 Jun '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5983 -gerrit commit 146521eb6eb8c8f8fccca627f8aaeff0c1c86c06 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jun 12 12:08:26 2014 -0600 bayleybay_fsp: Add bakersport board variant The Bakersport board is a variant of the Bayley Bay mainboard that uses one ECC DIMM instead of two non-ECC dimms. This commit uses the Bayley Bay mainboard directory and just modifies the required pieces to add the Bakersport board variant. It disables the second DIMM, points to an ECC version of the FSP, and sets the board name to be Bakersport instead of Bayley Bay. Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/Kconfig | 2 ++ src/mainboard/intel/bayleybay_fsp/Kconfig | 8 +++++--- src/mainboard/intel/bayleybay_fsp/romstage.c | 7 +++++++ 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 4940c54..5e49d8f 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -3,6 +3,8 @@ if VENDOR_INTEL choice prompt "Mainboard model" +config BOARD_INTEL_BAKERSPORT_FSP + bool "Bakersport FSP-based CRB" config BOARD_INTEL_BAYLEYBAY_FSP bool "Bayley Bay FSP-based CRB" config BOARD_INTEL_COUGAR_CANYON2 diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 8dcc199..f28b8dd 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -if BOARD_INTEL_BAYLEYBAY_FSP +if BOARD_INTEL_BAYLEYBAY_FSP || BOARD_INTEL_BAKERSPORT_FSP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -47,7 +47,8 @@ config LOCK_MANAGEMENT_ENGINE config MAINBOARD_PART_NUMBER string - default "Bayley Bay CRB" + default "Bayley Bay CRB" if BOARD_INTEL_BAYLEYBAY_FSP + default "Bakersport CRB" if BOARD_INTEL_BAKERSPORT_FSP config IRQ_SLOT_COUNT int @@ -63,7 +64,8 @@ config CACHE_ROM_SIZE_OVERRIDE config FSP_FILE string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" if BOARD_INTEL_BAYLEYBAY_FSP + default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP config MRC_CACHE_LOC_OVERRIDE hex diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index 34199bd..1e91332 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -173,4 +173,11 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) /* Initialize the Azalia Verb Tables to mainboard specific version */ UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; + + /* Disable 2nd DIMM on Bakersport*/ +#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP) + UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */ +#endif + + return; }

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coreboot-gerrit June 2014