coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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922 discussions

New patch to review for coreboot: 1114c27 panther: Disable power-failure gating for the PSON# signal
by Matt DeVillier 13 Jun '14

13 Jun '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5996 -gerrit commit 1114c27381d996b5af03d2129bc88f69050b07c0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Dec 11 11:09:45 2013 -0800 panther: Disable power-failure gating for the PSON# signal When the system loses AC power, the system will power back on automatically as soon as the AC power is reapplied. BUG=chrome-os-partner:24066 BRANCH=firmware-panther-4920.24.B TEST=boot tested on panther Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/179537 Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/panther/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 1966a30..f461c58 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -111,6 +111,7 @@ chip northbridge/intel/haswell io 0x60 = 0x700 io 0x62 = 0x710 irq 0x70 = 0x09 + irq 0xf4 = 0x20 irq 0xfa = 0x12 end device pnp 2e.7 on # GPIO

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New patch to review for coreboot: 8357c0c panther: Configure USB_ILIM_SEL to low
by Matt DeVillier 13 Jun '14

13 Jun '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5995 -gerrit commit 8357c0c6e9d0b2fd45eb1c515d7cf52a36991acf Author: Mohammed Habibulla <moch(a)chromium.org> Date: Wed Nov 20 16:30:09 2013 -0800 panther: Configure USB_ILIM_SEL to low (panther port of Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e) BUG=none BRANCH=none TEST=boot tested on Panther Change-Id: Iedcc107a43be170762d42d515c7e2a16ec395452 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/177474 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)google.com> Tested-by: Mohammed Habibulla <moch(a)google.com> --- src/mainboard/google/panther/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/panther/gpio.h b/src/mainboard/google/panther/gpio.h index 620acef..9951984 100644 --- a/src/mainboard/google/panther/gpio.h +++ b/src/mainboard/google/panther/gpio.h @@ -51,7 +51,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 25: UNUSED */ LP_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ LP_GPIO_UNUSED, /* 27: UNUSED */ - LP_GPIO_OUT_HIGH, /* 28: USB_ILIM_SEL */ + LP_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ LP_GPIO_UNUSED, /* 29: UNUSED */ LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ LP_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */

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New patch to review for coreboot: 2d5ba00 panther: Set default interrupt value for Environmental Controller
by Matt DeVillier 13 Jun '14

13 Jun '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5994 -gerrit commit 2d5ba0005318abbd84ccf1b62e20fe1071b18c17 Author: Mohammed Habibulla <moch(a)chromium.org> Date: Wed Nov 20 16:24:58 2013 -0800 panther: Set default interrupt value for Environmental Controller This writes the default value to the register, but it gets rid of the error that disturbs some of our tests: ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned (panther port of Ieab1c776b553c996a7d06e4059110943aaf41338) BRANCH=none BUG=chrome-os-partner:23945 TEST=boot test on Panther Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/177468 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)google.com> Tested-by: Mohammed Habibulla <moch(a)google.com> --- src/mainboard/google/panther/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 8bce691..1966a30 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -110,6 +110,7 @@ chip northbridge/intel/haswell device pnp 2e.4 on # Environment Controller io 0x60 = 0x700 io 0x62 = 0x710 + irq 0x70 = 0x09 irq 0xfa = 0x12 end device pnp 2e.7 on # GPIO

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New patch to review for coreboot: 77361d6 panther: make sure the S5 power status is on track
by Matt DeVillier 13 Jun '14

13 Jun '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5993 -gerrit commit 77361d6883de20520c3218de356ba7e59735280b Author: Mohammed Habibulla <moch(a)chromium.org> Date: Tue Nov 12 13:29:43 2013 -0800 panther: make sure the S5 power status is on track (panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6) BUG=none BRANCH=none TEST=boot test on panther Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/176563 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)chromium.org> Tested-by: Mohammed Habibulla <moch(a)chromium.org> --- src/mainboard/google/panther/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 39d4f06..8bce691 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -110,6 +110,7 @@ chip northbridge/intel/haswell device pnp 2e.4 on # Environment Controller io 0x60 = 0x700 io 0x62 = 0x710 + irq 0xfa = 0x12 end device pnp 2e.7 on # GPIO io 0x60 = 0x720

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New patch to review for coreboot: d58d848 panther: Disable LPSS I2C controllers
by Matt DeVillier 13 Jun '14

13 Jun '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5992 -gerrit commit d58d848fc7593e92f6e6bb6542f72bf8809716d0 Author: Mohammed Habibulla <moch(a)chromium.org> Date: Tue Oct 29 11:13:14 2013 -0700 panther: Disable LPSS I2C controllers There is nothing attached to these devices so we can disable them as well as the function 0 DMA controller. Also remove the EC SMI/SCI mappings since there is no EC. (panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87) BUG=chrome-os-partner:23563 TEST=none BRANCH=panther Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/174944 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)chromium.org> Tested-by: Mohammed Habibulla <moch(a)chromium.org> --- src/mainboard/google/panther/devicetree.cb | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 95f1084..39d4f06 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -46,11 +46,9 @@ chip northbridge/intel/haswell # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" + register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" + register "gpe0_en_2" = "0x00000000" register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" @@ -73,9 +71,9 @@ chip northbridge/intel/haswell device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 device pci 15.3 off end # GSPI0 device pci 15.4 off end # GSPI1 device pci 15.5 off end # UART0

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New patch to review for coreboot: 8f7c8a6 panther: Fix thermal zone to use SIO PWM/TACH port 2
by Matt DeVillier 13 Jun '14

13 Jun '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5991 -gerrit commit 8f7c8a6fb159feb04eedf44cbe3bb11ef934a484 Author: Mohammed Habibulla <moch(a)chromium.org> Date: Tue Oct 29 11:02:30 2013 -0700 panther: Fix thermal zone to use SIO PWM/TACH port 2 Fan is attached to port 2 instead of 3. (panther port of I9878063a24b0b908c74522580f776a4ce7d03d75) BUG=chrome-os-partner:23563 TEST=none BRANCH=panther Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/174984 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)chromium.org> Tested-by: Mohammed Habibulla <moch(a)chromium.org> --- src/mainboard/google/panther/acpi/thermal.asl | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl index d96d955..d5b1290 100644 --- a/src/mainboard/google/panther/acpi/thermal.asl +++ b/src/mainboard/google/panther/acpi/thermal.asl @@ -141,12 +141,12 @@ Scope (\_TZ) } Method (_ON) { Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } Method (_OFF) { Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } } @@ -162,12 +162,12 @@ Scope (\_TZ) } Method (_ON) { Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } Method (_OFF) { Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } } @@ -183,12 +183,12 @@ Scope (\_TZ) } Method (_ON) { Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } Method (_OFF) { Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } } @@ -204,12 +204,12 @@ Scope (\_TZ) } Method (_ON) { Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } Method (_OFF) { Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } } @@ -225,12 +225,12 @@ Scope (\_TZ) } Method (_ON) { Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } Method (_OFF) { Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) Notify (\_TZ.THRM, 0x81) } }

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Patch set updated for coreboot: b094d61 lynxpoint: Build intermediate step to add LynxPoint ME image
by Matt DeVillier 13 Jun '14

13 Jun '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4132 -gerrit commit b094d61d3101df8e7a958adceabe54cc8130dd57 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 19 11:03:40 2013 -0700 lynxpoint: Build intermediate step to add LynxPoint ME image This is needed to successfully build fox_wtm2 from external repo. BUG=chrome-os-partner:18638 BRANCH=none TEST=manual: successfully compile coreboot for fox_wtm2 and create an image with chromeos-bootimage/cros_bundle_firmware Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48676 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index ce948f4..f0b6a7a 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -20,8 +20,7 @@ # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS -# FIXME, uncomment as soon as we have ME firmware in the blobs repo -# INTERMEDIATE:=lynxpoint_add_me +INTERMEDIATE:=lynxpoint_add_me ramstage-y += pch.c ramstage-y += azalia.c

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New patch to review for coreboot: fd7f4b5 panther: Initial coreboot commit
by Matt DeVillier 13 Jun '14

13 Jun '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5990 -gerrit commit fd7f4b561dbe8359be2f6eed5b525b2837d733cc Author: Mohammed Habibulla <moch(a)chromium.org> Date: Thu Oct 24 16:44:06 2013 -0700 panther: Initial coreboot commit (Panther clone of Ia41af8425ab6c24746253abd025acd3365dd5a18 by reinauer) BUG=chrome-os-partner:23563 TEST=emerge-panther chromeos-coreboot-panther Change-Id: I50fd5c02da154e424dfefbe2020f4ce7ef9a4f8f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://chromium-review.googlesource.com/174555 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Mohammed Habibulla <moch(a)chromium.org> Tested-by: Mohammed Habibulla <moch(a)chromium.org> --- configs/config.panther | 36 +++ payloads/libpayload/configs/config.panther | 71 +++++ src/mainboard/google/Kconfig | 3 + src/mainboard/google/panther/Kconfig | 52 ++++ src/mainboard/google/panther/Makefile.inc | 25 ++ src/mainboard/google/panther/acpi/chromeos.asl | 23 ++ src/mainboard/google/panther/acpi/ec.asl | 0 .../google/panther/acpi/haswell_pci_irqs.asl | 87 ++++++ src/mainboard/google/panther/acpi/mainboard.asl | 29 ++ src/mainboard/google/panther/acpi/platform.asl | 72 +++++ src/mainboard/google/panther/acpi/superio.asl | 36 +++ src/mainboard/google/panther/acpi/thermal.asl | 274 +++++++++++++++++++ src/mainboard/google/panther/acpi/video.asl | 43 +++ src/mainboard/google/panther/acpi_tables.c | 304 +++++++++++++++++++++ src/mainboard/google/panther/chromeos.c | 117 ++++++++ src/mainboard/google/panther/cmos.layout | 139 ++++++++++ src/mainboard/google/panther/devicetree.cb | 136 +++++++++ src/mainboard/google/panther/dsdt.asl | 62 +++++ src/mainboard/google/panther/fadt.c | 156 +++++++++++ src/mainboard/google/panther/gpio.h | 124 +++++++++ src/mainboard/google/panther/hda_verb.h | 112 ++++++++ src/mainboard/google/panther/lan.c | 178 ++++++++++++ src/mainboard/google/panther/mainboard.c | 170 ++++++++++++ src/mainboard/google/panther/onboard.h | 9 + src/mainboard/google/panther/romstage.c | 150 ++++++++++ src/mainboard/google/panther/smihandler.c | 161 +++++++++++ src/mainboard/google/panther/thermal.h | 57 ++++ 27 files changed, 2626 insertions(+) diff --git a/configs/config.panther b/configs/config.panther new file mode 100644 index 0000000..bb0a2d2 --- /dev/null +++ b/configs/config.panther @@ -0,0 +1,36 @@ +CONFIG_COLLECT_TIMESTAMPS=y +CONFIG_USE_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_PANTHER=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="/build/panther/firmware/mrc.bin" +CONFIG_CBFS_SIZE=0x100000 +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_PCI_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_S3_VGA_ROM_RUN is not set +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_114=y +CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y +CONFIG_VGA_BIOS_ID="8086,0406" +CONFIG_VGA_BIOS=y +CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/google/panther/vgabios.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_CACHE_ROM=y +CONFIG_MARK_GRAPHICS_MEM_WRCOMB=y +CONFIG_ELOG=y +CONFIG_ELOG_GSMI=y +CONFIG_ELOG_BOOT_COUNT=y +CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 +CONFIG_SPI_FLASH_SMM=y +CONFIG_CMOS_POST=y +CONFIG_CMOS_POST_OFFSET=0x70 +CONFIG_CMOS_POST_EXTRA=y +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y +CONFIG_VBOOT_VERIFY_FIRMWARE=y +CONFIG_FLASHMAP_OFFSET=0x00610000 +# CONFIG_MULTIBOOT is not set +CONFIG_PAYLOAD_NONE=y diff --git a/payloads/libpayload/configs/config.panther b/payloads/libpayload/configs/config.panther new file mode 100644 index 0000000..e3af099 --- /dev/null +++ b/payloads/libpayload/configs/config.panther @@ -0,0 +1,71 @@ +# +# Automatically generated make config: don't edit +# libpayload version: 0.2.0 +# Thu May 2 16:10:03 2013 +# + +# +# Generic Options +# +# CONFIG_LP_EXPERIMENTAL is not set +# CONFIG_LP_OBSOLETE is not set +# CONFIG_LP_DEVELOPER is not set +CONFIG_LP_CHROMEOS=y + +# +# Architecture Options +# +# CONFIG_LP_ARCH_ARM is not set +# CONFIG_LP_ARCH_POWERPC is not set +CONFIG_LP_ARCH_X86=y +# CONFIG_LP_MEMMAP_RAM_ONLY is not set +# CONFIG_LP_MULTIBOOT is not set + +# +# Standard Libraries +# +CONFIG_LP_LIBC=y +# CONFIG_LP_CURSES is not set +CONFIG_LP_CBFS=y +CONFIG_LP_LZMA=y + +# +# Console Options +# +CONFIG_LP_SKIP_CONSOLE_INIT=y +CONFIG_LP_CBMEM_CONSOLE=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_8250_SERIAL_CONSOLE=y +CONFIG_LP_SERIAL_IOBASE=0x3f8 +# CONFIG_LP_SERIAL_SET_SPEED is not set +# CONFIG_LP_SERIAL_ACS_FALLBACK is not set +CONFIG_LP_VIDEO_CONSOLE=y +# CONFIG_LP_VGA_VIDEO_CONSOLE is not set +# CONFIG_LP_GEODELX_VIDEO_CONSOLE is not set +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +CONFIG_LP_PC_KEYBOARD=y +CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y +# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set + +# +# Drivers +# +CONFIG_LP_PCI=y +CONFIG_LP_NVRAM=y +# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set +# CONFIG_LP_SPEAKER is not set +# CONFIG_LP_STORAGE is not set +CONFIG_LP_USB=y +# CONFIG_LP_USB_UHCI is not set +# CONFIG_LP_USB_OHCI is not set +# CONFIG_LP_USB_EHCI is not set +CONFIG_LP_USB_XHCI=y +CONFIG_LP_USB_HID=y +CONFIG_LP_USB_HUB=y +CONFIG_LP_USB_MSC=y +CONFIG_LP_USB_PCI=y +# CONFIG_LP_USB_MEMORY is not set +# CONFIG_LP_BIG_ENDIAN is not set +CONFIG_LP_LITTLE_ENDIAN=y +CONFIG_LP_IO_ADDRESS_SPACE=y +CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 85c8592..c456b5a 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -29,6 +29,8 @@ config BOARD_GOOGLE_FALCO bool "Falco" config BOARD_GOOGLE_LINK bool "Link" +config BOARD_GOOGLE_PANTHER + bool "Panther" config BOARD_GOOGLE_PARROT bool "Parrot" config BOARD_GOOGLE_PEPPY @@ -50,6 +52,7 @@ source "src/mainboard/google/bolt/Kconfig" source "src/mainboard/google/butterfly/Kconfig" source "src/mainboard/google/falco/Kconfig" source "src/mainboard/google/link/Kconfig" +source "src/mainboard/google/panther/Kconfig" source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/peppy/Kconfig" source "src/mainboard/google/pit/Kconfig" diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig new file mode 100644 index 0000000..83cce9d --- /dev/null +++ b/src/mainboard/google/panther/Kconfig @@ -0,0 +1,52 @@ +if BOARD_GOOGLE_PANTHER + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select INTEL_LYNXPOINT_LP + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_ITE_IT8772F + select VIRTUAL_DEV_SWITCH + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select CHROMEOS + select EXTERNAL_MRC_BLOB + select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB + select MONOTONIC_TIMER_MSR + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config MAINBOARD_DIR + string + default google/panther + +config MAINBOARD_PART_NUMBER + string + default "Panther" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +endif diff --git a/src/mainboard/google/panther/Makefile.inc b/src/mainboard/google/panther/Makefile.inc new file mode 100644 index 0000000..1300be6 --- /dev/null +++ b/src/mainboard/google/panther/Makefile.inc @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += lan.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + diff --git a/src/mainboard/google/panther/acpi/chromeos.asl b/src/mainboard/google/panther/acpi/chromeos.asl new file mode 100644 index 0000000..0189cfa --- /dev/null +++ b/src/mainboard/google/panther/acpi/chromeos.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + Package () { 0x0001, 0, 12, "LynxPoint" }, // recovery button + Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect +}) diff --git a/src/mainboard/google/panther/acpi/ec.asl b/src/mainboard/google/panther/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/panther/acpi/haswell_pci_irqs.asl b/src/mainboard/google/panther/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..7ebd8e5 --- /dev/null +++ b/src/mainboard/google/panther/acpi/haswell_pci_irqs.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 18 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 22 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, + Package() { 0x001fffff, 3, 0, 16 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, 0, 23 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } +} + diff --git a/src/mainboard/google/panther/acpi/mainboard.asl b/src/mainboard/google/panther/acpi/mainboard.asl new file mode 100644 index 0000000..59ed710 --- /dev/null +++ b/src/mainboard/google/panther/acpi/mainboard.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } + +} diff --git a/src/mainboard/google/panther/acpi/platform.asl b/src/mainboard/google/panther/acpi/platform.asl new file mode 100644 index 0000000..e6aaf75 --- /dev/null +++ b/src/mainboard/google/panther/acpi/platform.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/google/panther/acpi/superio.asl b/src/mainboard/google/panther/acpi/superio.asl new file mode 100644 index 0000000..e1c9d1c --- /dev/null +++ b/src/mainboard/google/panther/acpi/superio.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ + +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR + +#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 + +#include "superio/ite/it8772f/acpi/superio.asl" + diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl new file mode 100644 index 0000000..d96d955 --- /dev/null +++ b/src/mainboard/google/panther/acpi/thermal.asl @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (\F2ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (\F0OF)) + } Else { + Return (CTOK (\F0ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (\F1OF)) + } Else { + Return (CTOK (\F1ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (\F2OF)) + } Else { + Return (CTOK (\F2ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (\F3OF)) + } Else { + Return (CTOK (\F3ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (\F4OF)) + } Else { + Return (CTOK (\F4ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (0, \FLVL) + Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (1, \FLVL) + Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (2, \FLVL) + Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (2, \FLVL) + Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (3, \FLVL) + Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (3, \FLVL) + Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (4, \FLVL) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/google/panther/acpi/video.asl b/src/mainboard/google/panther/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/google/panther/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/google/panther/acpi_tables.c b/src/mainboard/google/panther/acpi_tables.c new file mode 100644 index 0000000..0960100 --- /dev/null +++ b/src/mainboard/google/panther/acpi_tables.c @@ -0,0 +1,304 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <ec/google/chromeec/ec.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->f4of = FAN4_THRESHOLD_OFF; + gnvs->f4on = FAN4_THRESHOLD_ON; + gnvs->f4pw = FAN4_PWM; + + gnvs->f3of = FAN3_THRESHOLD_OFF; + gnvs->f3on = FAN3_THRESHOLD_ON; + gnvs->f3pw = FAN3_PWM; + + gnvs->f2of = FAN2_THRESHOLD_OFF; + gnvs->f2on = FAN2_THRESHOLD_ON; + gnvs->f2pw = FAN2_PWM; + + gnvs->f1of = FAN1_THRESHOLD_OFF; + gnvs->f1on = FAN1_THRESHOLD_ON; + gnvs->f1pw = FAN1_PWM; + + gnvs->f0of = FAN0_THRESHOLD_OFF; + gnvs->f0on = FAN0_THRESHOLD_ON; + gnvs->f0pw = FAN0_PWM; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 5; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = 0; + + /* TPM Present */ + gnvs->tpmp = 1; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + +#if CONFIG_CHROMEOS + // TODO(reinauer) this could move elsewhere? + chromeos_init_vboot(&(gnvs->chromeos)); + + // SuperIO is always RO + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif + + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); + ssdt = (acpi_header_t *)current; + acpi_create_serialio_ssdt(ssdt); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c new file mode 100644 index 0000000..074f648 --- /dev/null +++ b/src/mainboard/google/panther/chromeos.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPIO_SPI_WP 58 +#define GPIO_REC_MODE 12 + +#define FLAG_SPI_WP 0 +#define FLAG_REC_MODE 1 +#define FLAG_DEV_MODE 2 + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static void fill_lb_gpio(struct lb_gpio *gpio, int num, + int polarity, const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = num; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + else if (num >= 0) + gpio->value = get_gpio(num); + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", + get_recovery_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif + +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; +} + +#ifdef __PRE_RAM__ +void save_chromeos_gpios(void) +{ + u32 flags = 0; + + /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ + if (get_gpio(GPIO_SPI_WP)) + flags |= (1 << FLAG_SPI_WP); + + /* Recovery: GPIO12 = RECOVERY_L, active low */ + if (!get_gpio(GPIO_REC_MODE)) + flags |= (1 << FLAG_REC_MODE); + + /* Developer: Virtual */ + + pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); +} +#endif diff --git a/src/mainboard/google/panther/cmos.layout b/src/mainboard/google/panther/cmos.layout new file mode 100644 index 0000000..afdd3c6 --- /dev/null +++ b/src/mainboard/google/panther/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb new file mode 100644 index 0000000..95f1084 --- /dev/null +++ b/src/mainboard/google/panther/devicetree.cb @@ -0,0 +1,136 @@ +chip northbridge/intel/haswell + + # Disable eDP Hotplug + register "gpu_dp_d_hotplug" = "0x00" + + # Enable DisplayPort C Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/haswell + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) + + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) + end + end + + device domain 0 on + subsystemid 0x1ae0 0xc000 inherit + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + + register "sio_acpi_mode" = "0" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + # Route all USB ports to XHCI per default + register "xhci_default" = "1" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Enable FAN2 + register "fan2_enable" = "1" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 on + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 on + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl new file mode 100644 index 0000000..1316ebf --- /dev/null +++ b/src/mainboard/google/panther/dsdt.asl @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ENABLE_TPM + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <cpu/intel/haswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } + } + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> +} diff --git a/src/mainboard/google/panther/fadt.c b/src/mainboard/google/panther/fadt.c new file mode 100644 index 0000000..7afbbfa --- /dev/null +++ b/src/mainboard/google/panther/fadt.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = get_pmbase(); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/panther/gpio.h b/src/mainboard/google/panther/gpio.h new file mode 100644 index 0000000..620acef --- /dev/null +++ b/src/mainboard/google/panther/gpio.h @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef FALCO_GPIO_H +#define FALCO_GPIO_H + +struct pch_lp_gpio_map; + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + LP_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: SMBALERT */ + LP_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + LP_GPIO_UNUSED, /* 13: UNUSED */ + LP_GPIO_UNUSED, /* 14: UNUSED */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 16: UNUSED */ + LP_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + LP_GPIO_UNUSED, /* 18: UNUSED */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + LP_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + LP_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + LP_GPIO_UNUSED, /* 25: UNUSED */ + LP_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_OUT_HIGH, /* 28: USB_ILIM_SEL */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + LP_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + LP_GPIO_UNUSED, /* 44: UNUSED */ + LP_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + LP_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + LP_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_UNUSED, /* 49: UNUSED */ + LP_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + LP_GPIO_UNUSED, /* 51: UNUSED */ + LP_GPIO_UNUSED, /* 52: UNUSED */ + LP_GPIO_UNUSED, /* 53: UNUSED */ + LP_GPIO_UNUSED, /* 54: UNUSED */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + LP_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + LP_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + LP_GPIO_UNUSED, /* 61: UNUSED */ + LP_GPIO_UNUSED, /* 62: UNUSED */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_UNUSED, /* 72: UNUSED */ + LP_GPIO_UNUSED, /* 73: UNUSED */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/panther/hda_verb.h b/src/mainboard/google/panther/hda_verb.h new file mode 100644 index 0000000..ba0da1c --- /dev/null +++ b/src/mainboard/google/panther/hda_verb.h @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000c, // Number of jacks (NID entries) + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ + 0x00172083, + 0x00172102, + 0x001722ec, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ + 0x01271c10, + 0x01271d10, + 0x01271ea6, + 0x01271fb7, + + /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ + 0x01471c10, // group 1, front left/right + 0x01471d01, // no connector, no jack detect + 0x01471e17, // speaker out, analog + 0x01471f90, // fixed function, internal + + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, + + /* Pin Complex (NID 0x18) MIC1 PORTB */ + 0x01971c11, // group 1, cap 1 + 0x01971d10, // black, jack detect + 0x01971ea7, // mic in, analog + 0x01971f03, // connector, left panel + + /* Pin Complex (NID 0x19) MIC2 PORTF */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + + /* Pin Complex (NID 0x1A) LINE1 PORTC */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1B) LINE2 PORTE */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1d) PCBeep */ + 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable + 0x01d71d81, // mute spkr on hpout + 0x01d71e15, // pcbeep en able, checksum + 0x01d71f40, // no physical, internal + + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + + /* Pin Complex (NID 0x21) HPOUT PORT-I */ + 0x02171c1f, // group1, + 0x02171d10, // black, jack detect + 0x02171e21, // HPOut, 1/8 stereo + 0x02171f03, // connector, left panel + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, +}; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +static const u32 mainboard_pc_beep_verbs_size = + sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c new file mode 100644 index 0000000..64f53f3 --- /dev/null +++ b/src/mainboard/google/panther/lan.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <vendorcode/google/chromeos/fmap.h> +#include "onboard.h" + +static unsigned int search(char *p, char *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(char *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, (unsigned char)*offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u32 search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, (char *)search_address, + sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit((char *)(search_address + offset)) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit((char *)(search_address + offset + 1)) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit((char *)(search_address + offset)) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit((char *)(search_address + offset + 1)) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base, u32 search_address, + u32 search_length) +{ + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (search_length != -1) + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + outb(0xc0, io_base + 0x50); /* Disable register protection */ + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + outb(0x00, io_base + 0x50); /* Enable register protection again */ + } +} + +void lan_init(void) +{ + char **vpd_region_ptr = NULL; + u32 search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); + u32 search_address = (unsigned long)(*vpd_region_ptr); + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(PANTHER_NIC_VENDOR_ID, + PANTHER_NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base, search_address, search_length); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((PANTHER_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} + diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c new file mode 100644 index 0000000..e3823c3 --- /dev/null +++ b/src/mainboard/google/panther/mainboard.c @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <smbios.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "hda_verb.h" +#include "onboard.h" +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 0; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +/* Audio Setup */ + +extern const u32 * cim_verb_data; +extern u32 cim_verb_data_size; +extern const u32 * pc_beep_verbs; +extern u32 pc_beep_verbs_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; + +} + +static void mainboard_init(device_t dev) +{ + lan_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h new file mode 100644 index 0000000..794dd8d --- /dev/null +++ b/src/mainboard/google/panther/onboard.h @@ -0,0 +1,9 @@ +void lan_init(void); + +/* defines for programming the MAC address */ +#define PANTHER_NIC_VENDOR_ID 0x10EC +#define PANTHER_NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define PANTHER_NIC_LED_MODE 0x00 + diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c new file mode 100644 index 0000000..0f39b3b --- /dev/null +++ b/src/mainboard/google/panther/romstage.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> +#include "gpio.h" +#include "superio/ite/it8772f/it8772f.h" +#include "superio/ite/it8772f/early_serial.c" + +const struct rcba_config_instruction rcba_config[] = { + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + + /* Device interrupt route registers */ + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ + + /* Disable unused devices (board specific) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + pei_version: PEI_VERSION, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: DEFAULT_PCIEXBAR, + smbusbar: SMBUS_IO_BASE, + wdbbar: 0x4000000, + wdbsize: 0x1000, + hpet_address: HPET_ADDR, + rcba: DEFAULT_RCBA, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, + temp_mmio_base: 0xfed08000, + system_type: 5, /* ULT */ + tseg_size: CONFIG_SMM_TSEG_SIZE, + spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 }, + ec_present: 0, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + dimm_channel0_disabled: 2, + dimm_channel1_disabled: 2, + // Enable 2x refresh mode + ddr_refresh_2x: 1, + dq_pins_interleaved: 1, + max_ddr3_freq: 1600, + usb_xhci_on_resume: 1, + usb2_ports: { + /* Length, Enable, OCn#, Location */ + { 0x0064, 1, 0, /* P0: VP8 */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN22 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 1, /* P2: Port B, CN23 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 2, /* P4: Port C, CN25 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 2, /* P5: Port D, CN25 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ + USB_PORT_INTERNAL }, + { 0x0000, 0, 0, /* P7: N/C */ + USB_PORT_SKIP }, + }, + usb3_ports: { + /* Enable, OCn# */ + { 1, 0 }, /* P1; CN22 */ + { 1, 1 }, /* P2; CN23 */ + { 1, 2 }, /* P3; CN25 */ + { 1, 2 }, /* P4; CN25 */ + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; + + /* Early SuperIO setup */ + it8772f_kill_watchdog(); + it8772f_ac_resume_southbridge(); + pch_enable_lpc(); + it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1), + CONFIG_TTYS0_BASE); + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); +} diff --git a/src/mainboard/google/panther/smihandler.c b/src/mainboard/google/panther/smihandler.c new file mode 100644 index 0000000..2ad2498 --- /dev/null +++ b/src/mainboard/google/panther/smihandler.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/me.h> +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h> +#include <elog.h> + +/* GPIO46 controls the WLAN_DISABLE_L signal. */ +#define GPIO_WLAN_DISABLE_L 46 +#define GPIO_LTE_DISABLE_L 59 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#if 0 +static u8 mainboard_smi_ec(void) +{ + u8 cmd = 0;// google_chromeec_get_event(); + +#if CONFIG_ELOG_GSMI + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + return cmd; +} +#endif + +/* gpi_sts is GPIO 47:32 */ +void mainboard_smi_gpi(u32 gpi_sts) +{ +#if 0 + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0); + } +#endif +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: + //if (smm_get_gnvs()->s3u0 == 0) + // google_chromeec_set_usb_charge_mode( + // 0, USB_CHARGE_MODE_DISABLED); + //if (smm_get_gnvs()->s3u1 == 0) + // google_chromeec_set_usb_charge_mode( + // 1, USB_CHARGE_MODE_DISABLED); + + /* Prevent leak from standby rail to WLAN rail in S3. */ + //set_gpio(GPIO_WLAN_DISABLE_L, 0); + /* Disable LTE */ + //set_gpio(GPIO_LTE_DISABLE_L, 0); + + /* Enable wake events */ + //google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; + case 5: + //if (smm_get_gnvs()->s5u0 == 0) + // google_chromeec_set_usb_charge_mode( + // 0, USB_CHARGE_MODE_DISABLED); + //if (smm_get_gnvs()->s5u1 == 0) + // google_chromeec_set_usb_charge_mode( + // 1, USB_CHARGE_MODE_DISABLED); + + /* Prevent leak from standby rail to WLAN rail in S5. */ + //set_gpio(GPIO_WLAN_DISABLE_L, 0); + /* Disable LTE */ + //set_gpio(GPIO_LTE_DISABLE_L, 0); + + /* Enable wake events */ + //google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); + break; + } + + /* Disable SCI and SMI events */ + //google_chromeec_set_smi_mask(0); + //google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + //while (google_chromeec_get_event() != 0); +} + +#define APMC_FINALIZE 0xcb + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APMC_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return 0; + } + + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); + + mainboard_finalized = 1; + break; + case APM_CNT_ACPI_ENABLE: + //google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + //while (google_chromeec_get_event() != 0); + //google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + break; + case APM_CNT_ACPI_DISABLE: + //google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + //while (google_chromeec_get_event() != 0); + //google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + break; + } + return 0; +} diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h new file mode 100644 index 0000000..794065e --- /dev/null +++ b/src/mainboard/google/panther/thermal.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x00 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 48 +#define FAN3_THRESHOLD_ON 55 +#define FAN3_PWM 0x40 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 52 +#define FAN2_THRESHOLD_ON 64 +#define FAN2_PWM 0x80 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 60 +#define FAN1_THRESHOLD_ON 68 +#define FAN1_PWM 0xb0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 66 +#define FAN0_THRESHOLD_ON 78 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif

1 0

Patch merged into coreboot/master: d866e58 fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT
by gerrit＠coreboot.org 13 Jun '14

13 Jun '14

the following patch was just integrated into master: commit d866e5872d5570fded81a4d392884725009a17dd Author: Martin Roth <martin.roth(a)se-eng.com> Date: Wed Jun 11 09:35:37 2014 -0600 fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT While pushing the fsp_baytrail code, it was requested that we change CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT. These were missed in the change. Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/5972 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5972 for details. -gerrit

1 0

Patch set updated for filo: dd51816 Add flashupdate command
by Patrick Georgi 13 Jun '14

13 Jun '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5988 -gerrit commit dd51816080264c2719781ffc5fb40b4de2b0b3d2 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jul 19 16:40:06 2011 +0200 Add flashupdate command This command allows the user to load a coreboot image, configure its cmos.default file and write it to flash, all from FILO. Change-Id: Ia011deb64bcf75aebe8b67554ad9d9738d90fe59 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- Config.in | 15 ++- Makefile | 1 + flashupdate/Makefile.inc | 29 +++++ flashupdate/flashrom-bridge.c | 73 +++++++++++ flashupdate/flashupdate.c | 277 ++++++++++++++++++++++++++++++++++++++++++ main/grub/builtins.c | 19 ++- x86/ldscript | 6 +- 7 files changed, 413 insertions(+), 7 deletions(-) diff --git a/Config.in b/Config.in index cc48bd3..d9f977a 100644 --- a/Config.in +++ b/Config.in @@ -189,8 +189,7 @@ config FLASHROM_LOCKDOWN default n help Enable system flash memory write protections and lock them down prior - starting the kernel. Flash memory lockdown can be disabled per boot - entry with the new command 'flashrom_unlock'. + starting the kernel. NOTE: Only supported on selected hardware: @@ -199,6 +198,18 @@ config FLASHROM_LOCKDOWN o Intel Cougar Point / Panther Point PCH (FWH + SPI) o AMD SB600 (SPI by locking the flash chip itself) +config FLASHROM_UNLOCK + bool "Provide flashrom_unlock command" + default n + depends on FLASHROM_LOCKDOWN + help + FlashROM lockdown can be disabled per boot entry with the new + command 'flashrom_unlock'. + +config FLASHUPDATE + bool "add flashrom utility to FILO" + default y + endmenu menu "Filesystems" diff --git a/Makefile b/Makefile index 46010b3..570bd87 100644 --- a/Makefile +++ b/Makefile @@ -101,6 +101,7 @@ CFLAGS += $(call cc-option, -fno-stack-protector,) LIBS := $(LIBPAYLOAD) $(LIBGCC) +SUBDIRS-$(CONFIG_USE_GRUB) += flashupdate/ SUBDIRS-y += main/ fs/ drivers/ SUBDIRS-y += $(ARCHDIR-y)/ diff --git a/flashupdate/Makefile.inc b/flashupdate/Makefile.inc new file mode 100644 index 0000000..319add3 --- /dev/null +++ b/flashupdate/Makefile.inc @@ -0,0 +1,29 @@ +# +# Copyright (C) 2011 secunet AG +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +LIBFLASHROM_PREFIX ?= $(obj)/libflashrom +LIBFLASHROM = $(LIBFLASHROM_PREFIX)/lib/libflashrom.a +INCFLASHROM = $(LIBFLASHROM_PREFIX)/include + +ifeq ($(CONFIG_FLASHUPDATE),y) +CPPFLAGS += -I$(INCFLASHROM) +LIBS += $(LIBFLASHROM) +endif + +TARGETS-$(CONFIG_FLASHUPDATE) += flashupdate/flashupdate.o +TARGETS-$(CONFIG_FLASHUPDATE) += flashupdate/flashrom-bridge.o diff --git a/flashupdate/flashrom-bridge.c b/flashupdate/flashrom-bridge.c new file mode 100644 index 0000000..0940389 --- /dev/null +++ b/flashupdate/flashrom-bridge.c @@ -0,0 +1,73 @@ +#include <stdarg.h> +#include <string.h> + +#include "flashchips.h" +#include "flash.h" +#include "programmer.h" + +int new_rom_size; +void *new_rom_data; + +int old_rom_size; +void *old_rom_data; + +// for flashrom +int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +int print(int type, const char *fmt, ...) +{ +#ifdef DEBUG + if (type > MSG_INFO) return 0; + int ret; + va_list args; + va_start(args, fmt); + ret = vprintf(fmt, args); + va_end(args); + return ret; +#else + return 0; +#endif +} + +/* returned memory must be freed by caller */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + return strdup("Unknown"); +} + +int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename) +{ + // we need at least enough space for our image. + if (size < new_rom_size) + return 1; + + // top-align our image into the chip + memcpy(buf + size - new_rom_size, new_rom_data, new_rom_size); + + return 0; +} + +int read_flash_to_file(struct flashctx *flash, const char *filename) +{ + int ret = 0; + unsigned long size = flash->total_size * 1024; + if (size > old_rom_size) { + msg_cerr("old rom buffer not large enough for flash\n"); + ret = 1; + goto out_free; + } + + if (!flash->read) { + msg_cerr("No read function available for this flash chip.\n"); + ret = 1; + goto out_free; + } + if (flash->read(flash, old_rom_data, 0, size)) { + msg_cerr("Read operation failed!\n"); + ret = 1; + goto out_free; + } + +out_free: + return ret; +} + diff --git a/flashupdate/flashupdate.c b/flashupdate/flashupdate.c new file mode 100644 index 0000000..c0f337d --- /dev/null +++ b/flashupdate/flashupdate.c @@ -0,0 +1,277 @@ +#include <stdlib.h> +#include <getopt.h> +#include <libpayload.h> +#include <coreboot_tables.h> +#include <cbfs.h> +#include <grub/shared.h> +#include <fs.h> +#include <pci/pci.h> + +/* flashrom defines */ +#define CONFIG_INTERNAL 1 +#include "flashchips.h" +#include "flash.h" +#include "programmer.h" + +extern int new_rom_size; +extern void *new_rom_data; + +struct flashctx flashchip; + +static void beep_success() +{ + int i; + for (i = 0; i < 5; i++) { + speaker_tone(440, 200); mdelay(300); + speaker_tone(660, 200); mdelay(300); + speaker_tone(880, 200); mdelay(300); + mdelay(3*1000); + } +} + +static void beep_fail() +{ + int i; + for (i = 0; i < 5; i++) { + speaker_tone(1200, 200); mdelay(300); + speaker_tone( 660, 200); mdelay(300); + mdelay(3*1000); + } +} + +static int init_flash(const char* flashtype) +{ + int j; + verbose++; + if (programmer_init(PROGRAMMER_INTERNAL, NULL)) { + grub_printf("Could not initialize programmer\n"); + return -1; + } + for (j = 0; j < registered_programmer_count; j++) { + int current_chip = -1; + do { + current_chip = probe_flash(&registered_programmers[j], ++current_chip, &flashchip, 0); + if ((current_chip != -1) && ((flashtype == NULL) || (strcasecmp(flashchip.name, flashtype) == 0))) { + return 0; + } + } while (current_chip != -1); + } + + grub_printf("Could not find flash chip\n"); + return -1; +} + +static int write_flash(void *imgdata, int size) +{ + return doit(&flashchip, 1, imgdata, 0, 1, 0, 1); +} + +static int test_id_section(void *romarea, unsigned int romsize, int offset, char **vendor, char **model, char **version) +{ + /* data[-1]: romsize + data[-2]: offset top-of-rom to board model + data[-3]: offset top-of-rom to board vendor + data[-4]: offset top-of-rom to build version */ + unsigned int *data = romarea+romsize-offset; + *version = romarea+romsize-data[-4]; + *vendor = romarea+romsize-data[-3]; + *model = romarea+romsize-data[-2]; + /* Assume that data[-1] matches filesize, and that vendor and model are laid out without extra space. + DO NOT assume that model aligns to the offsets, there may be future additions. */ + return ((data[-1] == romsize) && (*vendor+strnlen(*vendor, data[-2])+1 == *model)); +} + +int flashupdate_func(char *arg, int flags) +{ + int result = -1; + int force = 0; + char *chiptype = NULL; + char *vendor = NULL; + char *board = NULL; + char *region = NULL; + + char **argv; + int argc = to_argc_argv(arg, &argv); + + new_rom_data = NULL; + + char opt; + optreset = optind = 1; + while ((opt = getopt(argc, argv, "fc:v:b:i:")) != -1) { + switch (opt) { + case 'f': + force = 1; + break; + case 'c': + chiptype = optarg; + break; + case 'v': + vendor = optarg; + break; + case 'b': + board = optarg; + break; + case 'i': + region = optarg; + break; + default: + grub_printf("unsupported option -%c.\n", opt); + goto out; + break; + } + } + + if (optind >= argc) { + grub_printf("No filename specified.\n"); + goto out; + } + const char *filename = argv[optind]; + + if (vendor && board && + ((strcmp(vendor, cb_mb_vendor_string(lib_sysinfo.mainboard)) != 0) || + (strcmp(board, cb_mb_part_string(lib_sysinfo.mainboard)) != 0))) { + /* since flashupdate semantics is: iff board matches, write flash; + it's a success not to flash on another board. */ + result = 0; + goto out; + } + + if (region) { + register_include_arg(region); + layout_use_ifd(); + } + + /* Step 0: Init programmer/flash to find out if we _can_ flash (we should) */ + if (init_flash(chiptype) == -1) { + grub_printf("Could not initialize flash programmer.\n"); + goto out; + } + + /* Step 1: read requested image file */ + if (!file_open(filename)) { + grub_printf("Could not open file '%s'\n", filename); + goto out; + } + + /* 16K of extra space, since we don't have feof() */ + new_rom_size = flashchip.total_size * 1024 + 16384; + new_rom_data = malloc(new_rom_size); + if (new_rom_data == NULL) { + grub_printf("Could not allocate memory.\n"); + goto out; + } + void *readbuf = new_rom_data; + int len; + grub_printf("Loading image file... "); + while ((len = file_read(readbuf, 16384)) != 0) { + readbuf += len; + /* We can abort if we cut into the last 16K: + * it's more than the flash is able to carry + */ + if (readbuf - new_rom_data > new_rom_size - 16384) { + file_close(); + grub_printf("File too large for flash\n"); + goto out; + } + } + new_rom_size = readbuf - new_rom_data; + file_close(); + grub_printf("done\n"); + + /* retarget all CBFS accesses to new image */ + setup_cbfs_from_ram(new_rom_data, new_rom_size); + + /* Step 2: Check Board IDs (that we work on the right image) */ + const char *cur_version = lib_sysinfo.cb_version; + const char *cur_vendor = cb_mb_vendor_string(lib_sysinfo.mainboard); + const char *cur_board = cb_mb_part_string(lib_sysinfo.mainboard); + + /* Step 2a: check if this is a coreboot image by looking for a CBFS master header */ + if (get_cbfs_header() != 0xffffffff) { + /* Step 2b: look for .id section in new ROM */ + /* There are currently two locations where .id can reside: top-0x10 and top-0x80. There's + no indicator which one is used in any given image, though it should be stable on any given + board. As a heuristic, we can check if the data is sane at each location. */ + char *new_vendor; + char *new_board; + char *new_version; + if (!test_id_section(new_rom_data, new_rom_size, 0x10, &new_vendor, &new_board, &new_version)) + if (!test_id_section(new_rom_data, new_rom_size, 0x80, &new_vendor, &new_board, &new_version)) { + grub_printf("Could not detect if file supports this system.\n"); + goto out; + } + if ((strcmp(cur_vendor, new_vendor) != 0) || (strcmp(cur_board, new_board) != 0)) { + grub_printf("File (%s %s) seems to be incompatible with current system (%s %s).\n", + new_vendor, new_board, cur_vendor, cur_board); + goto out; + } + + /* Step 3: Check image version (so that we don't reflash the same image again and again) */ + if (strcmp(cur_version, new_version) == 0) { + grub_printf("No need to update to the same version '%s'.\n", cur_version); + /* TODO: exit successfully. right? */ + result = 0; + goto out; + } + + /* Step 4: Merge current CMOS data with cmos.defaults */ + /* Step 4a: Load new CMOS data */ + void *cmos_defaults = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT); + void *cmos_layout = cbfs_find_file("cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT); + /* Step 4a1: Point use_mem to cmos.default. */ + mem_accessor_base = cmos_defaults; + if (cmos_defaults && cmos_layout) { + /* Step 4b: Check if current CMOS data is valid. */ + if (options_checksum_valid(use_nvram)) { + /* Step 4c: Iterate over current CMOS data */ + struct cb_cmos_entries *cmos_entry = first_cmos_entry(get_system_option_table()); + do { + /* Step 4c1: Attempt to update new CMOS data with current values. Ignore failures */ + char *val = NULL; + get_option_as_string(use_nvram, get_system_option_table(), &val, cmos_entry->name); + if (val) { + set_option_from_string(use_mem, cmos_layout, val, cmos_entry->name); + } + } while (cmos_entry = next_cmos_entry(cmos_entry)); + } + + /* Step 5: Write merged CMOS image to CMOS */ + /* TODO: do we need to skip 0x32 (RTC century)? */ + int i; + for (i = 14; i < 256; i++) + nvram_write(((u8*)cmos_defaults)[i], i); + + /* Step 6: Set cmos_defaults_loaded=no in CMOS data using new layout */ + set_option_from_string(use_nvram, cmos_layout, "No", "cmos_defaults_loaded"); + + /* Step 6a: Set cmos_defaults_loaded=Yes in cmos.default in ROM image. */ + set_option_from_string(use_mem, cmos_layout, "Yes", "cmos_defaults_loaded"); + } + } else { + if (!force) { + grub_printf("This is a not a coreboot image. Aborting.\n"); + goto out; + } + } + + grub_printf("Writing image to flash, please wait.\n"); + /* Step 7: Flash image */ + if (write_flash(new_rom_data, new_rom_size) == 0) { + grub_printf("Flash was updated successfully.\n"); + result = 0; + beep_success(); + } else { + grub_printf("WARNING: Error while updating flash!!\n"); + beep_fail(); + } + + /* success */ + programmer_shutdown(); + +out: + if (new_rom_data) free(new_rom_data); + new_rom_data = NULL; + if (argv) free(argv); + return result; +} + diff --git a/main/grub/builtins.c b/main/grub/builtins.c index f77a21a..8ebb829 100644 --- a/main/grub/builtins.c +++ b/main/grub/builtins.c @@ -549,7 +549,7 @@ static struct builtin builtin_find = { }; #endif -#ifdef CONFIG_FLASHROM_LOCKDOWN +#ifdef CONFIG_FLASHROM_UNLOCK /* flashrom_unlock */ /* Disable lockdown of flash memory on boot */ static int flashrom_unlock_func(char *arg, int flags) @@ -568,6 +568,18 @@ static struct builtin builtin_flashrom_unlock = { }; #endif +#ifdef CONFIG_FLASHUPDATE +int flashupdate_func(char *arg, int flags); + +static struct builtin builtin_flashupdate = { + "flashupdate", + flashupdate_func, + BUILTIN_CMDLINE | BUILTIN_HELP_LIST, + "flashupdate DEVICE", + "Update flash ROM from a file loaded from DEVICE (selected by the user)." +}; +#endif + /* help */ #define MAX_SHORT_DOC_LEN 39 #define MAX_LONG_DOC_LEN 66 @@ -1924,9 +1936,12 @@ struct builtin *builtin_table[] = { #ifdef CONFIG_EXPERIMENTAL &builtin_find, #endif -#ifdef CONFIG_FLASHROM_LOCKDOWN +#ifdef CONFIG_FLASHROM_UNLOCK &builtin_flashrom_unlock, #endif +#ifdef CONFIG_FLASHUPDATE + &builtin_flashupdate, +#endif &builtin_help, &builtin_hiddenmenu, &builtin_initrd, diff --git a/x86/ldscript b/x86/ldscript index b260c51..f701d37 100644 --- a/x86/ldscript +++ b/x86/ldscript @@ -26,9 +26,9 @@ OUTPUT_ARCH(i386) ENTRY(entry) -/* 1024KB heap and 64KB stack */ -HEAP_SIZE = 1 * 1024 * 1024; -STACK_SIZE = 64 * 1024; +/* 96MB heap and 256KB stack */ +HEAP_SIZE = 96 * 1024 * 1024; +STACK_SIZE = 256 * 1024; SECTIONS {

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coreboot-gerrit June 2014