Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5752
-gerrit
commit 1023f8a8ae87362f6ea2918f2590db0c82543719
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Thu May 15 19:37:24 2014 +1000
vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdp
The function GfxPowerPlayLocateTdp() sets MinDeltaSclk to a maximum
sentinel value and checks DeltaSclk in a loop to minimize MinDeltaSclk.
However, MinDeltaSclk incorrectly self-assigns.
Change-Id: Id01c792057681516bba411adec268769a3549aa8
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
.../f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 2 +-
.../f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 12 ++++++------
.../Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 2 +-
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index 6642c8a..7ecb6fa 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -211,7 +211,7 @@ GfxPowerPlayLocateTdp (
DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader);
DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk);
if (DeltaSclk < MinDeltaSclk) {
- MinDeltaSclk = MinDeltaSclk;
+ MinDeltaSclk = DeltaSclk;
DpmIndex = Index;
}
}
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index feb6123..5f06eb6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -17,7 +17,7 @@
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
@@ -25,10 +25,10 @@
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -39,7 +39,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
* ***************************************************************************
*
*/
@@ -204,7 +204,7 @@ GfxPowerPlayLocateTdp (
DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader);
DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk);
if (DeltaSclk < MinDeltaSclk) {
- MinDeltaSclk = MinDeltaSclk;
+ MinDeltaSclk = DeltaSclk;
DpmIndex = Index;
}
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index 0c3e7a1..1bbb397 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -147,7 +147,7 @@ GfxPowerPlayLocateTdp (
DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader);
DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk);
if (DeltaSclk < MinDeltaSclk) {
- MinDeltaSclk = MinDeltaSclk;
+ MinDeltaSclk = DeltaSclk;
DpmIndex = Index;
}
}
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5778
-gerrit
commit 1ba063b8decec728b7493b873ab46c7be3b185b3
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sun May 18 10:33:31 2014 +1000
mainboard/ibase/mb899: Indent devicetree.cb
Change-Id: I29037c322dac5ed9ebc36b95bc1981acf21e5bd0
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/ibase/mb899/devicetree.cb | 91 ++++++++++++++++-----------------
1 file changed, 43 insertions(+), 48 deletions(-)
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index 7e5076d..5679b54 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -1,18 +1,17 @@
chip northbridge/intel/i945
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_mFCPGA478
+ device lapic 0 on end
+ end
+ end
- device cpu_cluster 0 on
- chip cpu/intel/socket_mFCPGA478
- device lapic 0 on end
- end
- end
-
- device domain 0 on
- device pci 00.0 on end # host bridge
+ device domain 0 on
+ device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
device pci 02.0 on end # vga controller
device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx
+ chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x07"
register "pirqc_routing" = "0x05"
@@ -28,44 +27,42 @@ chip northbridge/intel/i945
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1"
- register "ide_legacy_combined" = "0x0"
- register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x0"
- register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x1"
- #device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
- device pci 1c.1 on end # PCIe
- device pci 1c.2 on end # PCIe
+ #device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe
+ device pci 1c.1 on end # PCIe
+ device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
- device pci 1d.1 on end # USB UHCI
- device pci 1d.2 on end # USB UHCI
- device pci 1d.3 on end # USB UHCI
- device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1d.0 on end # USB UHCI
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
+ device pci 1d.3 on end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
- chip superio/winbond/w83627ehg
- device pnp 4e.0 off # Floppy
- end
- device pnp 4e.1 off # Parport
+ device pci 1f.0 on # LPC bridge
+ chip superio/winbond/w83627ehg
+ device pnp 4e.0 off end # Floppy
+ device pnp 4e.1 off end # Parport
+ device pnp 4e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
end
- device pnp 4e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
+ device pnp 4e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
- end
+ end
device pnp 4e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
+ io 0x60 = 0x60
+ io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
irq 0xf0 = 0x82 # HW accel A20.
@@ -97,14 +94,12 @@ chip northbridge/intel/i945
io 0x60 = 0x290
irq 0x70 = 0
end
-
- end
-
- end
+ end # LPC bridge
device pci 1f.1 on end # IDE
- device pci 1f.2 on end # SATA
- device pci 1f.3 on end # SMBus
- #device pci 1f.4 off end # Realtek ID Codec
- end
- end
-end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ # device pci 1f.4 off end # Realtek ID Codec
+ end # chip southbridge/intel/i82801gx
+
+ end # device domain0
+end # chip northbridge/intel/i945
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5777
-gerrit
commit 1abf758e308e7d0c95114784cf71dd97877b148e
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sun May 18 09:42:46 2014 +1000
drivers/marvell: Provide mvy88e8053 GbE stub driver
This stub driver initializes the Marvell Yukon 88E8053 Gigabit Ethernet
adapter to keep coreboot from trying to execute an option ROM. Following
the reasoning of RTL8168_ROM_DISABLE.
Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/drivers/marvell/Kconfig | 6 +++++
src/drivers/marvell/Makefile.inc | 20 ++++++++++++++
src/drivers/marvell/mvy88e8053.c | 48 +++++++++++++++++++++++++++++++++
src/mainboard/ibase/mb899/Kconfig | 1 +
src/mainboard/ibase/mb899/Makefile.inc | 20 --------------
src/mainboard/ibase/mb899/mv88e8053.c | 49 ----------------------------------
6 files changed, 75 insertions(+), 69 deletions(-)
diff --git a/src/drivers/marvell/Kconfig b/src/drivers/marvell/Kconfig
new file mode 100644
index 0000000..1870179
--- /dev/null
+++ b/src/drivers/marvell/Kconfig
@@ -0,0 +1,6 @@
+config MVY88E8053_ROM_DISABLE
+ bool "Disable MVY88E8053 ROM"
+ default n
+ help
+ Just enough of a driver to make coreboot not look for an Option ROM.
+ No configuration is necessary for the OS to pick up the device.
diff --git a/src/drivers/marvell/Makefile.inc b/src/drivers/marvell/Makefile.inc
new file mode 100644
index 0000000..be19414
--- /dev/null
+++ b/src/drivers/marvell/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 secunet Security Networks AG
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_MVY88E8053_ROM_DISABLE) += mvy88e8053.c
diff --git a/src/drivers/marvell/mvy88e8053.c b/src/drivers/marvell/mvy88e8053.c
new file mode 100644
index 0000000..5f5c029
--- /dev/null
+++ b/src/drivers/marvell/mvy88e8053.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This code should work for all ICH* southbridges with a NIC. */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void nic_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "Initializing Marvell Yukon 88E8053 Gigabit Ethernet\n");
+ // Nothing to do yet, but this has to be here to keep
+ // coreboot from trying to execute an option ROM.
+}
+
+static struct device_operations nic_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = nic_init,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver mvy88e8053_nic __pci_driver = {
+ .ops = &nic_ops,
+ .vendor = 0x11ab, /* Marvell Yukon */
+ .device = 0x4362,
+};
diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig
index 8975be2..6b44e4b 100644
--- a/src/mainboard/ibase/mb899/Kconfig
+++ b/src/mainboard/ibase/mb899/Kconfig
@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627EHG
+ select MVY88E8053_ROM_DISABLE
select EARLY_CBMEM_INIT
select HAVE_ACPI_TABLES
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/ibase/mb899/Makefile.inc b/src/mainboard/ibase/mb899/Makefile.inc
deleted file mode 100644
index 4fb55f5..0000000
--- a/src/mainboard/ibase/mb899/Makefile.inc
+++ /dev/null
@@ -1,20 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-ramstage-y += mv88e8053.c
diff --git a/src/mainboard/ibase/mb899/mv88e8053.c b/src/mainboard/ibase/mb899/mv88e8053.c
deleted file mode 100644
index 7db7fd8..0000000
--- a/src/mainboard/ibase/mb899/mv88e8053.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This code should work for all ICH* southbridges with a NIC. */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-static void nic_init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n");
- // Nothing to do yet, but this has to be here to keep
- // coreboot from trying to execute an option ROM.
-}
-
-static struct device_operations nic_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = nic_init,
- .scan_bus = 0,
-};
-
-static const struct pci_driver rtl8169_nic __pci_driver = {
- .ops = &nic_ops,
- .vendor = 0x11ab,
- .device = 0x4362,
-};
-
-
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5776
-gerrit
commit bce7f46160bf3e8ea87934b15df9fad43e3ae3e9
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat May 17 21:50:06 2014 +0200
abuild: Only build boards with Kconfig
We have dupes in the tree for aliases,
board variants and the like,
for board-status reporting purposes.
But we don't need to build all of them.
Change-Id: Ic1c6415568800350bdc0db97471e3875d9eac98c
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
util/abuild/abuild | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/abuild/abuild b/util/abuild/abuild
index d4ee752..85b6406 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -113,7 +113,7 @@ function vendors
{
# make this a function so we can easily select
# without breaking readability
- ls -1 "$ROOT/src/mainboard" | grep -v Kconfig | grep -v Makefile
+ ls -1 $ROOT/src/mainboard/*/Kconfig 2>/dev/null | sed "s:^$ROOT/src/mainboard/\(.*\)/Kconfig$:\1:"
}
function mainboards
@@ -123,7 +123,7 @@ function mainboards
VENDOR=$1
- ls -1 $ROOT/src/mainboard/$VENDOR | grep -v Kconfig
+ ls -1 $ROOT/src/mainboard/$VENDOR/*/Kconfig 2>/dev/null | sed "s:^$ROOT/src/mainboard/$VENDOR/\(.*\)/Kconfig$:\1:"
}
function architecture
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5747
-gerrit
commit 57c2f2e916debe5117a2713e3660330391686a85
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Wed May 14 21:05:35 2014 +0200
build system: re-enable clang use
Change-Id: I6e07fdec449d0b259d77986f65a60aa36d367cc8
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
Makefile | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index cc2d27c..9e91a24 100644
--- a/Makefile
+++ b/Makefile
@@ -107,13 +107,33 @@ else
include $(HAVE_DOTCONFIG)
-include toolchain.inc
-
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-CC:=clang -m32 -mno-mmx -mno-sse -no-integrated-as
+# FIXME: CC_* contains more than one word and quotes don't work either
+# armv7/aarch64 won't build right now
+CFLAGS_x86_32 = -target i386-elf -m32
+CC_x86_32:=clang
+
+ifneq ($(CONFIG_MMX),y)
+CFLAGS_x86_32 += -mno-mmx
+endif
+
+ifneq ($(CONFIG_SSE),y)
+CFLAGS_x86_32 += -mno-sse
+endif
+
+CFLAGS_armv7 = -target armv7-eabi -ccc-gcc-name $(CC_armv7)
+CC_armv7:=clang
+
+CFLAGS_aarch64 = -target aarch64-eabi -ccc-gcc-name $(CC_aarch64)
+CC_aarch64:=clang
+
+CFLAGS_common += -no-integrated-as
+
HOSTCC:=clang
endif
+include toolchain.inc
+
strip_quotes = $(subst ",,$(subst \",,$(1)))
# The primary target needs to be here before we include the
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5718
-gerrit
commit 17a2ede08432e61bae424004faf0effccafabb54
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Oct 18 11:02:46 2013 +0300
Add guard for UMA globals
We no longer need these globally. Guard them so we get to declare
static replacements at few locations until complete removal.
Change-Id: Ie33e2a680fc9bbb7e28c8fbe17e5181e626736a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/include/device/device.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 0ae4f88..a4ef456 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -131,9 +131,11 @@ extern struct bus *free_links;
extern const char mainboard_name[];
+#if CONFIG_GFXUMA
/* IGD UMA memory */
extern uint64_t uma_memory_base;
extern uint64_t uma_memory_size;
+#endif
/* Generic device interface functions */
device_t alloc_dev(struct bus *parent, struct device_path *path);