coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch merged into coreboot/master: c867626 device/oprom/yabel/vbe.c: Avoid unused func warn
by gerrit＠coreboot.org 18 May '14

18 May '14

the following patch was just integrated into master: commit c86762657dc7013a56b1d281286789dae17ad936 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 11:28:43 2014 +1000 device/oprom/yabel/vbe.c: Avoid unused func warn Change-Id: Idd74893c1fc3d0818d00c1f727c9fdc27168af0c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5782 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5782 for details. -gerrit

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Patch merged into coreboot/master: 9c8532b drivers/spi/sst.c: Remove unused func to_sst_spi_flash()
by gerrit＠coreboot.org 18 May '14

18 May '14

the following patch was just integrated into master: commit 9c8532b350d00dbd1aa184f162ef0448c941c822 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 10:40:26 2014 +1000 drivers/spi/sst.c: Remove unused func to_sst_spi_flash() Trips up clang builds with a warn treated as error. Change-Id: I9c0e2930ba8a60c7ad6063e9826b1b8638185505 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5779 for details. -gerrit

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New patch to review for coreboot: a6d7944 cpu/amd/agesa: select SSE for northbridge code
by Edward O'Callaghan 18 May '14

18 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5783 -gerrit commit a6d7944d45cf75c6c3500beefd6119ff6303d50a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 11:29:23 2014 +1000 cpu/amd/agesa: select SSE for northbridge code SSE intrinsics are used in the case of inclusion of: vendorcode/amd/agesa/f*/Include/gcc-intrin.h Change-Id: Ic71be775ea2924f43b626fc809c5d906e7310469 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/agesa/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 21f0c6f..14b2a54 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -31,6 +31,7 @@ config CPU_AMD_AGESA select ARCH_RAMSTAGE_X86_32 select TSC_SYNC_LFENCE select UDELAY_LAPIC + select SSE select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME @@ -74,4 +75,3 @@ source src/cpu/amd/agesa/family14/Kconfig source src/cpu/amd/agesa/family15/Kconfig source src/cpu/amd/agesa/family15tn/Kconfig source src/cpu/amd/agesa/family16kb/Kconfig -

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New patch to review for coreboot: 77df957 device/oprom/yabel/vbe.c: Avoid unused func warn
by Edward O'Callaghan 18 May '14

18 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5782 -gerrit commit 77df9571b8c5d4d275acffe628d7a09246f653db Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 11:28:43 2014 +1000 device/oprom/yabel/vbe.c: Avoid unused func warn Change-Id: Idd74893c1fc3d0818d00c1f727c9fdc27168af0c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/oprom/yabel/vbe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 333bdb4..6283bbb 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -45,6 +45,7 @@ u8 *vbe_info_buffer = 0; u8 *biosmem; u32 biosmem_size; +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE static inline u8 vbe_prepare(void) { @@ -63,7 +64,6 @@ vbe_prepare(void) return 0; // successfull init } -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE // VBE Function 00h static u8 vbe_info(vbe_info_t * info)

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Patch set updated for coreboot: 15427cb vendorcode/amd/agesa, cimx: Integer comparisons always true
by Edward O'Callaghan 18 May '14

18 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5749 -gerrit commit 15427cbe13ff5c49c86460736230edd7935a2220 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 05:23:09 2014 +1000 vendorcode/amd/agesa,cimx: Integer comparisons always true Change-Id: I6a3f36cd7e4f2cf26a72f3e849fed0b2da691d1d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Lib/amdlib.c | 9 +++++---- src/vendorcode/amd/cimx/sb800/SATA.c | 12 ++++++------ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c index 31b3f1e..2bee185 100644 --- a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c @@ -348,11 +348,12 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - UINTN Index; - for (Index = 31; Index >= 0; Index--){ - if (value & (1 << Index)) break; + UINT8 Index; + for (Index = 31; Index > 0; Index--){ + if (value & (1 << Index)) + return Index; } - return (UINT8) Index; + return 0xFF; } VOID LibAmdMsrRead ( diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index a301208..c2f2162 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -17,7 +17,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -25,10 +25,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -39,7 +39,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -568,7 +568,7 @@ sataDriveDetection ( UINT8 dbPortNum; UINT8 dbVar0; UINT16 dwIoBase; - UINT16 dwVar0; + UINT32 dwVar0; if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) { for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) { ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);

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Patch set updated for coreboot: 1482e3f vendorcode/amd/agesa: unsigned enum is strictly positive
by Edward O'Callaghan 18 May '14

18 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5757 -gerrit commit 1482e3ff3c0494d0b7ad330fdb6e5c9d017772a5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:07:16 2014 +1000 vendorcode/amd/agesa: unsigned enum is strictly positive Comparison of unsigned enum expression >= 0 is always true Change-Id: Id2f03596c44b68e861e939f3528256d4b08c45ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c index f85e56d..e92dec0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c @@ -17,7 +17,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -25,10 +25,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -39,7 +39,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -187,7 +187,7 @@ MemNCmnGetSetFieldON ( UINT8 Instance; Value = 0; - if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + if (FieldName < BFEndOfList) { Address = NBPtr->NBRegTable[FieldName]; if (Address) { Lowbit = TSEFO_END (Address);

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Patch set updated for coreboot: 03721cb drivers/spi/sst.c: Remove unused func to_sst_spi_flash()
by Edward O'Callaghan 18 May '14

18 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5779 -gerrit commit 03721cb83ef579f521082a54b95d44fcd78f8166 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 10:40:26 2014 +1000 drivers/spi/sst.c: Remove unused func to_sst_spi_flash() Trips up clang builds with a warn treated as error. Change-Id: I9c0e2930ba8a60c7ad6063e9826b1b8638185505 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/spi/sst.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 8cf3f96..3cf6c50 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -46,11 +46,6 @@ struct sst_spi_flash { const struct sst_spi_flash_params *params; }; -static inline struct sst_spi_flash *to_sst_spi_flash(struct spi_flash *flash) -{ - return container_of(flash, struct sst_spi_flash, flash); -} - #define SST_SECTOR_SIZE (4 * 1024) static const struct sst_spi_flash_params sst_spi_flash_table[] = { {

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Patch set updated for coreboot: 4312c01 vendorcode/amd/agesa: Silence warn of assigment in if-statement
by Edward O'Callaghan 18 May '14

18 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5759 -gerrit commit 4312c01701287bf37114ef28821268cd45809f2d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:22:17 2014 +1000 vendorcode/amd/agesa: Silence warn of assigment in if-statement Change-Id: I86a475a2ae101cc3ebfee742de0c75cacd352fbe Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c index c2f9372..20a90d5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c @@ -290,7 +290,7 @@ MemTDIMMPresence3 ( // as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will // be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks. // - if (ChannelPtr->LrDimmPresent |= DimmMask) { + if ((ChannelPtr->LrDimmPresent |= DimmMask)) { // // LRDIMM Physical Ranks //

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Patch set updated for coreboot: 0e39cce amd/agesa: Implicit assigment between enum without cast
by Edward O'Callaghan 18 May '14

18 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5760 -gerrit commit 0e39cce9357d0717acbc38c767d18b6072ea8721 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:23:51 2014 +1000 amd/agesa: Implicit assigment between enum without cast Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c index 613aadd..9ff66f2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c @@ -186,7 +186,7 @@ MemNSyncTargetSpeedNb ( ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) : ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY)); - MemClkFreq = ChnlTmgMod[1]; + MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1]; } }

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Patch set updated for coreboot: 20f8c47 amd/agesa/*/gcc-intrin.h: Invaild inline asm
by Edward O'Callaghan 18 May '14

18 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5758 -gerrit commit 20f8c47156f2275076a11b8351d217c06651e993 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:13:33 2014 +1000 amd/agesa/*/gcc-intrin.h: Invaild inline asm The 'm' (a memory reference) constraint makes little sense here since we are talking about a fs relative read, rather 'ir' (immediate or register) constraint is more sensible. N.B. The 'p' constraint allows anything which fits the form of an address calculation where the 'ir' constraint is just a register /xor/ immediate. Hence would produce better code here however, unfortunately, clang does not currently support it properly. The %b and %w constraints are also redundant and only hide errors. The functions writefsword() and writefsdword() should use ir instead of iq. iq is unnecessarily restrictive (it is only required for writing bytes). The cld in stosb is redundant (and the constraints are unnecessarily complicated). Line wrap these extraneously long lines found with these particular functions. Many thanks to Christoph Mallon <christoph.mallon(a)gmx.de> from #llvm for helping me with this. Change-Id: Iaf3ad65791640e1060a2029e7ebb043f57b338a9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 205 ++++++++++++---------- 1 file changed, 110 insertions(+), 95 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 5ce3ee3..bd48bee 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -1,7 +1,7 @@ /* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * + * Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2014, Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + #if defined (__GNUC__) /* I/O intrin functions. */ @@ -34,9 +34,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned unsigned char value; __asm__ __volatile__ ( - "in %%dx, %%al" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -47,9 +47,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne unsigned short value; __asm__ __volatile__ ( - "in %%dx, %%ax" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -60,9 +60,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne unsigned long value; __asm__ __volatile__ ( - "in %%dx, %%eax" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -71,81 +71,81 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) { __asm__ __volatile__ ( - "out %%al, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) { __asm__ __volatile__ ( - "out %%ax, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) { __asm__ __volatile__ ( - "out %%eax, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insb " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insb" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insw " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insw" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insl " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insl" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsb " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsb" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsw " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsw" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsl " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsl" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } @@ -154,7 +154,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr0, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -164,7 +164,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr1, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -174,7 +174,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr2, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -184,7 +184,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr3, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -194,7 +194,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr7, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -230,45 +230,45 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr0" + "mov %0, %%dr0" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr1" + "mov %0, %%dr1" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr2" + "mov %0, %%dr2" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr3" + "mov %0, %%dr3" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr7" + "mov %0, %%dr7" : - : "a" (Data) + : "r" (Data) ); } @@ -297,17 +297,15 @@ static __inline__ __attribute__((always_inline)) void __writedr(unsigned long re default: ; - } + } } - + static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) { unsigned long value; __asm__ __volatile__ ( - "mov %%cr0, %[value]" - : [value] "=a" (value) - : - : "memory"); + "mov %%cr0, %[value]" + : [value] "=r" (value)); return value; } @@ -316,7 +314,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr2, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -325,7 +323,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr3, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -334,7 +332,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr4, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -343,7 +341,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr8, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -378,9 +376,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr0" + "mov %0, %%cr0" : - : "a" (Data) + : "r" (Data) : "memory" ); } @@ -388,36 +386,36 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr2" + "mov %0, %%cr2" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr3" + "mov %0, %%cr3" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr4" + "mov %0, %%cr4" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr8" + "mov %0, %%cr8" : - : "a" (Data) + : "r" (Data) ); } @@ -453,7 +451,7 @@ static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr) { UINT64 retval; __asm__ __volatile__( - "rdmsr\n\t" + "rdmsr" : "=A" (retval) : "c" (msr) ); @@ -463,7 +461,7 @@ static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr) static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value) { __asm__ __volatile__ ( - "wrmsr\n\t" + "wrmsr" : : "c" (msr), "A" (Value) ); @@ -526,39 +524,57 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); } -static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data) +static __inline__ __attribute__((always_inline)) void +__writefsbyte(const unsigned long Offset, const unsigned char Data) { - __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movb %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data) +static __inline__ __attribute__((always_inline)) void +__writefsword(const unsigned long Offset, const unsigned short Data) { - __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movw %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data) +static __inline__ __attribute__((always_inline)) void +__writefsdword(const unsigned long Offset, const unsigned long Data) { - __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movl %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned char +__readfsbyte(const unsigned long Offset) { unsigned char value; - __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movb %%fs:%a[Offset], %[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned short +__readfsword(const unsigned long Offset) { unsigned short value; - __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movw %%fs:%a[Offset], %[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset) +static __inline__ __attribute__((always_inline)) unsigned long +__readfsdword(unsigned long Offset) { - unsigned long long value; - __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + unsigned long value; + __asm__ ("movl %%fs:%a[Offset], %[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; } @@ -594,23 +610,22 @@ static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) { __builtin_ia32_sfence (); } -#endif +#endif /* __SSE3__ */ static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) { __asm__ __volatile__ ( - "cld ; rep ; stosb " - : "=D" (dest), "=c" (count) - : "a"(data), "0"(dest), "1" (count) + "rep ; stosb " + : "+D" (dest), "+c" (count) + : "a"(data) ); } static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count) { __asm__ __volatile__ ( - "cld ; rep ; movsb " - : "=D" (dest), "=S"(data), "=c" (count) - : "S"(data), "0"(dest), "1" (count) + "movsb " + : "+D" (dest), "+S"(data), "+c" (count) ); }

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coreboot-gerrit May 2014