coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 0e3ca27 mainboard/*/acpi/ide.asl: Serialize ACPI methods to avoid races.
by gerrit＠coreboot.org 13 Apr '14

13 Apr '14

the following patch was just integrated into master: commit 0e3ca273151b9c13da7ae53923cb6387dd9d2cdf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 6 01:57:42 2014 +1100 mainboard/*/acpi/ide.asl: Serialize ACPI methods to avoid races. Serialize methods against the construction of same (named) objects by competing threads. See ACPICA BZ 909 for further details. This change fixes issues that show up with the Ubuntu firmware test suite (fwts) ACPI table sanity checker. Change-Id: I49e3050a2a5aece6f031122b0211c056938d1a89 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5458 for details. -gerrit

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Patch merged into coreboot/master: 374251d cpu/amd/agesa/s3_resume.c: Specify include paths from AGESA_ROOT
by gerrit＠coreboot.org 13 Apr '14

13 Apr '14

the following patch was just integrated into master: commit 374251d9019ad0d99b8ea309e0e3eb2b55251a4c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 18:06:57 2014 -0500 cpu/amd/agesa/s3_resume.c: Specify include paths from AGESA_ROOT Following the same reasoning as in commit * 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes include AGESA files with a path relative to AGESA_ROOT. We cannot with more than one generation of AGESA, hence the path being relative to AGESA_ROOT. Change-Id: If15c4cbfd42e0264264fdb3e8c426a47609ad41f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5426 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5426 for details. -gerrit

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Patch set updated for coreboot: 7f25355 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
by Edward O'Callaghan 13 Apr '14

13 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5481 -gerrit commit 7f25355990d67e392fac2c93d2a26a564536b28a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 10 19:12:28 2014 +1000 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics Keep under 80 colums and Doxygen'ify inline documentation somewhat. Strip some whitespace bulk while here. Additionally, following the reasoning of: 0b2fa34 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables remove some fluff from buildOpts.c Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 24 +-- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h | 13 +- src/mainboard/jetway/nf81-t56n-lf/Makefile.inc | 2 - .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 126 +++++++++---- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 88 +++++---- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 10 +- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 29 --- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 46 +---- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 203 ++++++--------------- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 61 ++++--- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 24 +-- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 4 +- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 13 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 +- 14 files changed, 284 insertions(+), 361 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 0502e5a..441661e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -401,13 +401,13 @@ AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr) ResetType = Data; StdHeader = ConfigPtr; - // - // Perform the RESET based upon the ResetType. In case of - // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to - // AmdResetManager. During the critical condition, where reset is required - // immediately, the reset will be invoked directly by writing 0x04 to port - // 0xCF9 (Reset Port). - // + /* + * Perform the RESET based upon the ResetType. In case of + * WARM_RESET_WHENEVER and COLD_RESET_WHENEVER, the request will go to + * AmdResetManager. During the critical condition, where reset is required + * immediately, the reset will be invoked directly by writing 0x04 to port + * 0xCF9 (Reset Port). + */ switch (ResetType) { case WARM_RESET_WHENEVER: case COLD_RESET_WHENEVER: @@ -453,8 +453,9 @@ AGESA_STATUS BiosHookBeforeDQSTraining (uint32_t Func, uint32_t Data, void *Conf /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (uint32_t Func, uint32_t Data, void *ConfigPtr) { - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. + /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + * Make sure the right speed settings are selected. + */ ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } @@ -470,6 +471,7 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void * { return AGESA_SUCCESS; } + /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr) { @@ -484,7 +486,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16=Data8<<8; @@ -496,7 +498,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */ switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h index 1d63f9b..2c509a2 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h @@ -40,13 +40,12 @@ typedef struct _BIOS_BUFFER_NODE { uint32_t BufferSize; uint32_t NextNodeOffset; } BIOS_BUFFER_NODE; -/* - * CALLOUTS - */ + +/* Callouts */ AGESA_STATUS GetBiosCallout (uint32_t Func, uint32_t Data, void *ConfigPtr); -/* REQUIRED CALLOUTS - * AGESA ADVANCED CALLOUTS - CPU +/* Required Callouts + * AGESA Advanced Callouts - CPU */ AGESA_STATUS BiosAllocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); @@ -56,7 +55,7 @@ AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr); AGESA_STATUS BiosGetIdsInitData (uint32_t Func, uint32_t Data, void *ConfigPtr); /* AGESA Advanced Callouts - Memory */ -AGESA_STATUS BiosReadSpd (uint32_t Func,uint32_t Data,void *ConfigPtr); +AGESA_STATUS BiosReadSpd (uint32_t Func, uint32_t Data, void *ConfigPtr); /* BIOS default RET */ AGESA_STATUS BiosDefaultRet (uint32_t Func, uint32_t Data, void *ConfigPtr); @@ -72,4 +71,4 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void * /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr); -#endif //_BIOS_CALLOUT_H_ +#endif /* _BIOS_CALLOUT_H_ */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index e1f18a9..0630008 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -33,5 +33,3 @@ ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c - - diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 3cc9c89..697c595 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -26,7 +26,6 @@ #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE -/*---------------------------------------------------------------------------------------*/ /** * OemCustomizeInitEarly * @@ -48,52 +47,95 @@ void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; +/** + * @brief Initialize Port descriptors + */ PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) } }; +/** + * @brief Initialize Ddi descriptors + */ PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* (DDI interface Lanes 8:11, DdA, ...) */ { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* (DDI interface Lanes 12:15, DdB, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -105,38 +147,46 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting - - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + /** + * @brief GNB PCIe topology Porting + * + * Allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + AllocHeapParams.RequestedBufferSize = + sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); - if ( Status!= AGESA_SUCCESS) { - // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); - return; + + /** + * Could not allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + if (Status!= AGESA_SUCCESS) { + ASSERT(FALSE); + return; } - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); - - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index 20877f1..dd6f7d7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,46 +24,61 @@ #include <vendorcode/amd/agesa/f14/AGESA.h> #include <vendorcode/amd/agesa/f14/Lib/amdlib.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/** + * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) + * + * GNB_GPP_PORT?_PORT_PRESENT + * 0:Disable 1:Enable + * + * GNB_GPP_PORT?_SPEED_MODE + * 0:Auto 1:GEN1 2:GEN2 + * + * GNB_GPP_PORT?_LINK_ASPM + * 0:Disable 1:L0s 2:L1 3:L0s+L1 + * + * GNB_GPP_PORT?_CHANNEL_TYPE - + * 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + * 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) + * + * GNB_GPP_PORT?_HOTPLUG_SUPPORT + * 0:Disable 1:Basic 3:Enhanced + */ + +/* GNB GPP 4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 90f556b..3ad7b9b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -31,7 +31,6 @@ #define DUMP_ACPI_TABLES 0 #if DUMP_ACPI_TABLES == 1 - static void dump_mem(u32 start, u32 end) { @@ -45,7 +44,7 @@ static void dump_mem(u32 start, u32 end) } print_debug("\n"); } -#endif +#endif /* DUMP_ACPI_TABLES */ extern const unsigned char AmlCode[]; @@ -60,6 +59,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta lens += acpigen_write_name_dword("TOM1", msr.lo); msr = rdmsr(TOP_MEM2); /* + * FIXME: remove this work-around and url.. WinXP is EOL'ed any way. * Since XP only implements parts of ACPI 2.0, we can't use a qword * here. * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt @@ -124,7 +124,7 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest) unsigned long acpi_fill_slit(unsigned long current) { - // Not implemented + /* Not implemented */ return current; } @@ -180,7 +180,7 @@ unsigned long write_acpi_tables(unsigned long start) memcpy(dsdt, &AmlCode, dsdt->length); printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - /* FACS */ // it needs 64 bit alignment + /* FACS - it needs 64 bit alignment */ current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; @@ -313,7 +313,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "hest\n"); dump_mem(hest, ((void *)hest) + hest->header.length); -#endif +#endif /* DUMP_ACPI_TABLES */ printk(BIOS_INFO, "ACPI: done.\n"); return current; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index c9824f1..4f25756 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -17,11 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*----------------------------------------------------------------------------- - * M O D U L E S U S E D - *----------------------------------------------------------------------------- - */ - #include "agesawrapper.h" #include "BiosCallOuts.h" #include "PlatformGnbPcieComplex.h" @@ -41,11 +36,6 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -/*------------------------------------------------------------------------------ - * D E F I N I T I O N S A N D M A C R O S - *------------------------------------------------------------------------------ - */ - #define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ @@ -58,25 +48,6 @@ void *AcpiWheaMce = NULL; void *AcpiWheaCmc = NULL; void *AcpiAlib = NULL; -/*------------------------------------------------------------------------------ - * T Y P E D E F S A N D S T R U C T U R E S - *------------------------------------------------------------------------------ - */ - -/*------------------------------------------------------------------------------ - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *------------------------------------------------------------------------------ - */ - -/*------------------------------------------------------------------------------ - * E X P O R T E D F U N C T I O N S - *------------------------------------------------------------------------------ - */ - -/*------------------------------------------------------------------------------ - * L O C A L F U N C T I O N S - *------------------------------------------------------------------------------ - */ AGESA_STATUS agesawrapper_amdinitcpuio(void) { pci_devfn_t dev; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index bad9b80..b97b6d5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -17,11 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - #ifndef _AGESAWRAPPER_H_ #define _AGESAWRAPPER_H_ @@ -29,49 +24,28 @@ #include <vendorcode/amd/agesa/f14/AGESA.h> -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- +/** + * Define AMD Ontario APU SSID/SVID */ -/* Define AMD Ontario APPU SSID/SVID */ #define AMD_APU_SVID 0x1022 #define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_DMI, /**< DMI Interface */ + PICK_PSTATE, /**< Acpi Pstate SSDT Table */ + PICK_SRAT, /**< SRAT Table */ + PICK_SLIT, /**< SLIT Table */ + PICK_WHEA_MCE, /**< WHEA MCE table */ + PICK_WHEA_CMC, /**< WHEA CMV table */ + PICK_ALIB, /**< SACPI SSDT table with ALIB implementation */ }; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - typedef struct { uint32_t CalloutName; AGESA_STATUS (*CalloutPtr) (uint32_t Func, uint32_t Data, void* ConfigPtr); } BIOS_CALLOUT_STRUCT; -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ AGESA_STATUS agesawrapper_amdinitreset(void); AGESA_STATUS agesawrapper_amdinitearly(void); @@ -92,4 +66,4 @@ void * agesawrapper_getlateinitptr(int); uint32_t GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); -#endif +#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index aa985a5..7cf274e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -50,14 +50,13 @@ #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE - -/* Select the cpu family. */ +/* Select the cpu family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the cpu socket type. */ +/* Select the cpu socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -69,8 +68,8 @@ #define INSTALL_FT1_SOCKET_SUPPORT TRUE #define INSTALL_AM3_SOCKET_SUPPORT FALSE -/* - * Agesa optional capabilities selection. +/** + * AGESA optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. * Comment out or mark TRUE those features you want to REMOVE from the build. */ @@ -102,13 +101,13 @@ #define BLDOPT_REMOVE_DQS_TRAINING FALSE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE + #define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_SLIT FALSE #define BLDOPT_REMOVE_WHEA FALSE @@ -123,7 +122,7 @@ #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE /* - * Agesa entry points used in this implementation. + * AGESA entry points used in this implementation. */ #define AGESA_ENTRY_INIT_RESET TRUE #define AGESA_ENTRY_INIT_RECOVERY FALSE @@ -233,8 +232,8 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -/* - * Agesa configuration values selection. +/** + * AGESA configuration values selection. * Uncomment and specify the value for the configuration options * needed by the system. */ @@ -256,8 +255,8 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/***************************************************************************** - * Define the RELEASE VERSION string +/** + * @brief Define the RELEASE VERSION string * * The Release Version string should identify the next planned release. * When a branch is made in preparation for a release, the release manager @@ -268,42 +267,48 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * The release manager will need to remove the trailing 'X' and update the * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long + */ + +/* + * This is the delivery package title, "BrazosPI" + * This string MUST be exactly 8 characters long + */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component + * This string MUST be exactly 12 characters long + */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /**< DDR 400 */ +#define DDR533_FREQUENCY 266 /**< DDR 533 */ +#define DDR667_FREQUENCY 333 /**< DDR 667 */ +#define DDR800_FREQUENCY 400 /**< DDR 800 */ +#define DDR1066_FREQUENCY 533 /**< DDR 1066 */ +#define DDR1333_FREQUENCY 667 /**< DDR 1333 */ +#define DDR1600_FREQUENCY 800 /**< DDR 1600 */ +#define DDR1866_FREQUENCY 933 /**< DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /**< Max limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /**< Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /**< Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /**< Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /**< Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /**< Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/** + * The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common + * file. The values below are based on product and BKDG content. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -316,121 +321,25 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = /* Instantiate all solution relevant data. */ #include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h> -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. +/** + * @brief Customer Overides Memory Table + * + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). + * If PlatformSpecificTable is populated, AGESA will base its settings on the + * data from the table. Otherwise, it will use its default conservative settings. */ const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -//DA Customer table +/* DA Customer table */ const uint8_t AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = { - // Hardcoded Memory Training Values - - // The following macro should be used to override training values for your platform - // - // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), - // - // NOTE: - // The following training hardcode values are example values that were taken from a tilapia motherboard - // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in - // the table and replace the byte lane values with your own. - // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC - // Write Data Timing - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 - - // DQS Receiver Enable - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 - - // Write DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 - - // Read DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 - //-------------------------------------------------------------------------------------------------------------------------------------------------- - // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), /* End of Table */ }; const uint8_t SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 1491f29..8fb0795 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -30,18 +30,19 @@ #include <southbridge/amd/cimx/sb800/sb_cimx.h> -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ +/** + * Global variables for mainboard layouts. These are shared by irqtable, + * mptable and acpi_tables where busnum is default. + */ u8 bus_isa; u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ +/** + * Here you only need to set value in pci1234 for HT-IO that could be + * installed or not. You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ u32 pci1234x[] = { 0x0000ff0, }; @@ -53,7 +54,7 @@ static u32 get_bus_conf_done = 0; #if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ void get_bus_conf(void) { @@ -63,26 +64,31 @@ void get_bus_conf(void) device_t dev; int i, j; + /* Be sure func is called exactly once */ if (get_bus_conf_done == 1) - return; /* do it only once */ + return; get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ + /* + * This is the call to AmdInitLate. It is really in the wrong place, + * conceptually, but functionally within the coreboot model, this is the + * best place to make the call. The logically correct place to call + * AmdInitLate is after PCI scan is done, after the decision about S3 + * resume is made, and before the system tables are written into RAM. The + * routine that is + * responsible for writing the tables is "write_tables", called near the + * end of "main". There is no platform specific entry point between the S3 + * resume decision point and the call to "write_tables", and the next + * platform specific entry points are the calls to the ACPI table write + * functions. The first of ose would seem to be the right place, but other + * table write + * functions, e.g. the PIRQ table write function, are called before the + * ACPI tables are written. This routine is called at the beginning of each + * of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + #if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { status = agesawrapper_amdinitlate(); @@ -96,7 +102,8 @@ void get_bus_conf(void) status = agesawrapper_amdinitlate(); if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ + sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); @@ -142,5 +149,5 @@ void get_bus_conf(void) #if CONFIG_AMD_SB_CIMX sb_Late_Post(); -#endif +#endif /* CONFIG_AMD_SB_CIMX */ } diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index b77c375..259034b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -26,9 +26,9 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -58,15 +58,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; + /* Find all Bus num and APIC's that are share with + * mptable.c and acpi_tables.c + */ + get_bus_conf(); - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ + /* Align table on 16 byte boundary. */ addr += 15; addr &= ~15; - /* This table must be betweeen 0xf0000 & 0x100000 */ + /* This table must be between 0xf0000 & 0x100000 */ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); @@ -90,19 +92,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - - /* pci bridge */ + /* PCI Bridge */ write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) @@ -117,5 +114,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "write_pirq_routing_table done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d5f2d03..b3c9e3d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -64,7 +64,7 @@ static void mainboard_enable(device_t dev) */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ /* enable GPP CLK0 thru CLK3 (interleaved) */ /* disable GPP CLK4 thru SLT_GFX_CLK */ @@ -77,7 +77,7 @@ static void mainboard_enable(device_t dev) /* * Initialize ASF registers to an arbitrary address because someone - * long ago set things up this way inside the SPD read code. The + * long ago set things up this way inside the SPD read code. The * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index d7fe6a0..7a08726 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -95,7 +95,6 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); @@ -107,10 +106,10 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - /* sata */ + /* SATA */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* on board NIC & Slot PCIE. */ + /* On-board NIC & Slot PCIE. */ /* PCI slots */ /* PCI_SLOT 0. */ @@ -119,7 +118,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); - /* PCI_SLOT 1. */ + /* On-board Realtek NIC 1. */ PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); @@ -135,7 +134,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); - /* PCIe PortA */ + /* On-board Realtek NIC 2. (PCIe PortA) */ PCI_INT(0x0, 0x15, 0x0, 0x10); /* PCIe PortB */ PCI_INT(0x0, 0x15, 0x1, 0x11); @@ -144,7 +143,9 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: + * Type | Polarity | Trigger | Bus ID | IRQ | APIC ID PIN# + */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 846d5c7..3406edf 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ /* Initialize i8259 pic */ post_code(0x43);

1 0

Patch set updated for coreboot: 82e865a mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
by Edward O'Callaghan 13 Apr '14

13 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5481 -gerrit commit 82e865a7762e1d96f47e90eab29042eab2e667ba Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 10 19:12:28 2014 +1000 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics Keep under 80 colums and Doxygen'ify inline documentation somewhat. Strip some whitespace bulk while here. Additionally, following the reasoning of: 0b2fa34 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables remove some fluff from buildOpts.c Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 24 +-- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h | 11 +- src/mainboard/jetway/nf81-t56n-lf/Makefile.inc | 2 - .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 125 +++++++++---- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 88 +++++---- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 10 +- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 29 --- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 46 +---- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 201 ++++++--------------- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 57 +++--- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 24 +-- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 4 +- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 13 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 +- 14 files changed, 279 insertions(+), 357 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 0502e5a..0463e81 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -401,13 +401,13 @@ AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr) ResetType = Data; StdHeader = ConfigPtr; - // - // Perform the RESET based upon the ResetType. In case of - // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to - // AmdResetManager. During the critical condition, where reset is required - // immediately, the reset will be invoked directly by writing 0x04 to port - // 0xCF9 (Reset Port). - // + /** + * Perform the RESET based upon the ResetType. In case of + * WARM_RESET_WHENEVER and COLD_RESET_WHENEVER, the request will go to + * AmdResetManager. During the critical condition, where reset is required + * immediately, the reset will be invoked directly by writing 0x04 to port + * 0xCF9 (Reset Port). + */ switch (ResetType) { case WARM_RESET_WHENEVER: case COLD_RESET_WHENEVER: @@ -453,8 +453,9 @@ AGESA_STATUS BiosHookBeforeDQSTraining (uint32_t Func, uint32_t Data, void *Conf /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (uint32_t Func, uint32_t Data, void *ConfigPtr) { - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. + /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. + * Make sure the right speed settings are selected. + */ ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } @@ -470,6 +471,7 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void * { return AGESA_SUCCESS; } + /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr) { @@ -484,7 +486,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr FcnData = Data; ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) + /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16=Data8<<8; @@ -496,7 +498,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot + case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */ switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h index 1d63f9b..1a746e7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h @@ -40,13 +40,14 @@ typedef struct _BIOS_BUFFER_NODE { uint32_t BufferSize; uint32_t NextNodeOffset; } BIOS_BUFFER_NODE; + /* - * CALLOUTS + * Callouts */ AGESA_STATUS GetBiosCallout (uint32_t Func, uint32_t Data, void *ConfigPtr); -/* REQUIRED CALLOUTS - * AGESA ADVANCED CALLOUTS - CPU +/* Required Callouts + * AGESA Advanced Callouts - CPU */ AGESA_STATUS BiosAllocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); @@ -56,7 +57,7 @@ AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr); AGESA_STATUS BiosGetIdsInitData (uint32_t Func, uint32_t Data, void *ConfigPtr); /* AGESA Advanced Callouts - Memory */ -AGESA_STATUS BiosReadSpd (uint32_t Func,uint32_t Data,void *ConfigPtr); +AGESA_STATUS BiosReadSpd (uint32_t Func, uint32_t Data, void *ConfigPtr); /* BIOS default RET */ AGESA_STATUS BiosDefaultRet (uint32_t Func, uint32_t Data, void *ConfigPtr); @@ -72,4 +73,4 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void * /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr); -#endif //_BIOS_CALLOUT_H_ +#endif /* _BIOS_CALLOUT_H_ */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index e1f18a9..0630008 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -33,5 +33,3 @@ ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c - - diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 3cc9c89..04bec9c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -26,7 +26,6 @@ #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE -/*---------------------------------------------------------------------------------------*/ /** * OemCustomizeInitEarly * @@ -48,52 +47,95 @@ void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly) ALLOCATE_HEAP_PARAMS AllocHeapParams; +/** + * @brief Initialize Port descriptors + */ PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) } }; +/** + * @brief Initialize Ddi descriptors + */ PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + /* (DDI interface Lanes 8:11, DdA, ...) */ { - 0, //Descriptor flags + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ {ConnectorTypeLvds, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + /* (DDI interface Lanes 12:15, DdB, ...) */ { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ {ConnectorTypeDP, Aux2, Hdp2} } }; @@ -105,38 +147,45 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { &DdiList[0] }; - // GNB PCIe topology Porting - - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + /** + * @brief GNB PCIe topology Porting + * + * Allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + AllocHeapParams.RequestedBufferSize = \ + sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); - if ( Status!= AGESA_SUCCESS) { - // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); - return; + + /** + * Could not allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + if (Status!= AGESA_SUCCESS) { + ASSERT(FALSE); + return; } - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); - - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = \ + (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = \ + (PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index 20877f1..dd6f7d7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,46 +24,61 @@ #include <vendorcode/amd/agesa/f14/AGESA.h> #include <vendorcode/amd/agesa/f14/Lib/amdlib.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/** + * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) + * + * GNB_GPP_PORT?_PORT_PRESENT + * 0:Disable 1:Enable + * + * GNB_GPP_PORT?_SPEED_MODE + * 0:Auto 1:GEN1 2:GEN2 + * + * GNB_GPP_PORT?_LINK_ASPM + * 0:Disable 1:L0s 2:L1 3:L0s+L1 + * + * GNB_GPP_PORT?_CHANNEL_TYPE - + * 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + * 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) + * + * GNB_GPP_PORT?_HOTPLUG_SUPPORT + * 0:Disable 1:Basic 3:Enhanced + */ + +/* GNB GPP 4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 90f556b..3ad7b9b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -31,7 +31,6 @@ #define DUMP_ACPI_TABLES 0 #if DUMP_ACPI_TABLES == 1 - static void dump_mem(u32 start, u32 end) { @@ -45,7 +44,7 @@ static void dump_mem(u32 start, u32 end) } print_debug("\n"); } -#endif +#endif /* DUMP_ACPI_TABLES */ extern const unsigned char AmlCode[]; @@ -60,6 +59,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta lens += acpigen_write_name_dword("TOM1", msr.lo); msr = rdmsr(TOP_MEM2); /* + * FIXME: remove this work-around and url.. WinXP is EOL'ed any way. * Since XP only implements parts of ACPI 2.0, we can't use a qword * here. * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt @@ -124,7 +124,7 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest) unsigned long acpi_fill_slit(unsigned long current) { - // Not implemented + /* Not implemented */ return current; } @@ -180,7 +180,7 @@ unsigned long write_acpi_tables(unsigned long start) memcpy(dsdt, &AmlCode, dsdt->length); printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - /* FACS */ // it needs 64 bit alignment + /* FACS - it needs 64 bit alignment */ current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; @@ -313,7 +313,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "hest\n"); dump_mem(hest, ((void *)hest) + hest->header.length); -#endif +#endif /* DUMP_ACPI_TABLES */ printk(BIOS_INFO, "ACPI: done.\n"); return current; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index c9824f1..4f25756 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -17,11 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*----------------------------------------------------------------------------- - * M O D U L E S U S E D - *----------------------------------------------------------------------------- - */ - #include "agesawrapper.h" #include "BiosCallOuts.h" #include "PlatformGnbPcieComplex.h" @@ -41,11 +36,6 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -/*------------------------------------------------------------------------------ - * D E F I N I T I O N S A N D M A C R O S - *------------------------------------------------------------------------------ - */ - #define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ @@ -58,25 +48,6 @@ void *AcpiWheaMce = NULL; void *AcpiWheaCmc = NULL; void *AcpiAlib = NULL; -/*------------------------------------------------------------------------------ - * T Y P E D E F S A N D S T R U C T U R E S - *------------------------------------------------------------------------------ - */ - -/*------------------------------------------------------------------------------ - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *------------------------------------------------------------------------------ - */ - -/*------------------------------------------------------------------------------ - * E X P O R T E D F U N C T I O N S - *------------------------------------------------------------------------------ - */ - -/*------------------------------------------------------------------------------ - * L O C A L F U N C T I O N S - *------------------------------------------------------------------------------ - */ AGESA_STATUS agesawrapper_amdinitcpuio(void) { pci_devfn_t dev; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index bad9b80..b97b6d5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -17,11 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - #ifndef _AGESAWRAPPER_H_ #define _AGESAWRAPPER_H_ @@ -29,49 +24,28 @@ #include <vendorcode/amd/agesa/f14/AGESA.h> -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- +/** + * Define AMD Ontario APU SSID/SVID */ -/* Define AMD Ontario APPU SSID/SVID */ #define AMD_APU_SVID 0x1022 #define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_DMI, /**< DMI Interface */ + PICK_PSTATE, /**< Acpi Pstate SSDT Table */ + PICK_SRAT, /**< SRAT Table */ + PICK_SLIT, /**< SLIT Table */ + PICK_WHEA_MCE, /**< WHEA MCE table */ + PICK_WHEA_CMC, /**< WHEA CMV table */ + PICK_ALIB, /**< SACPI SSDT table with ALIB implementation */ }; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - typedef struct { uint32_t CalloutName; AGESA_STATUS (*CalloutPtr) (uint32_t Func, uint32_t Data, void* ConfigPtr); } BIOS_CALLOUT_STRUCT; -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ AGESA_STATUS agesawrapper_amdinitreset(void); AGESA_STATUS agesawrapper_amdinitearly(void); @@ -92,4 +66,4 @@ void * agesawrapper_getlateinitptr(int); uint32_t GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); -#endif +#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index aa985a5..e5d6637 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -50,14 +50,13 @@ #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE - -/* Select the cpu family. */ +/* Select the cpu family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the cpu socket type. */ +/* Select the cpu socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -69,8 +68,8 @@ #define INSTALL_FT1_SOCKET_SUPPORT TRUE #define INSTALL_AM3_SOCKET_SUPPORT FALSE -/* - * Agesa optional capabilities selection. +/** + * AGESA optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. * Comment out or mark TRUE those features you want to REMOVE from the build. */ @@ -103,12 +102,12 @@ #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE +#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_SLIT FALSE #define BLDOPT_REMOVE_WHEA FALSE @@ -123,7 +122,7 @@ #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE /* - * Agesa entry points used in this implementation. + * AGESA entry points used in this implementation. */ #define AGESA_ENTRY_INIT_RESET TRUE #define AGESA_ENTRY_INIT_RECOVERY FALSE @@ -233,8 +232,8 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -/* - * Agesa configuration values selection. +/** + * AGESA configuration values selection. * Uncomment and specify the value for the configuration options * needed by the system. */ @@ -256,8 +255,8 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/***************************************************************************** - * Define the RELEASE VERSION string +/** + * @brief Define the RELEASE VERSION string * * The Release Version string should identify the next planned release. * When a branch is made in preparation for a release, the release manager @@ -268,42 +267,48 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * The release manager will need to remove the trailing 'X' and update the * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long + */ + +/* + * This is the delivery package title, "BrazosPI" + * This string MUST be exactly 8 characters long + */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long +/* This is the release version number of the AGESA component + * This string MUST be exactly 12 characters long + */ #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 /**< DDR 400 */ +#define DDR533_FREQUENCY 266 /**< DDR 533 */ +#define DDR667_FREQUENCY 333 /**< DDR 667 */ +#define DDR800_FREQUENCY 400 /**< DDR 800 */ +#define DDR1066_FREQUENCY 533 /**< DDR 1066 */ +#define DDR1333_FREQUENCY 667 /**< DDR 1333 */ +#define DDR1600_FREQUENCY 800 /**< DDR 1600 */ +#define DDR1866_FREQUENCY 933 /**< DDR 1866 */ +#define UNSUPPORTED_DDR_FREQUENCY 934 /**< Max limit of DDR frequency */ /* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 /**< Quadrank registered DIMM */ +#define QUADRANK_UNBUFFERED 1 /**< Quadrank unbuffered DIMM */ /* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 /**< Use best rate possible */ +#define TIMING_MODE_LIMITED 1 /**< Set user top limit */ +#define TIMING_MODE_SPECIFIC 2 /**< Set user specified speed */ /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */ +#define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */ -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/** + * The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common + * file. The values below are based on product and BKDG content. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -316,121 +321,25 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = /* Instantiate all solution relevant data. */ #include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h> -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. +/** + * @brief Customer Overides Memory Table + * + * Platform Specific Overriding Table allows IBV/OEM to pass in platform + * information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). + * If PlatformSpecificTable is populated, AGESA will base its settings on the + * data from the table. Otherwise, it will use its default conservative settings. */ const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -//DA Customer table +/* DA Customer table */ const uint8_t AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = { - // Hardcoded Memory Training Values - - // The following macro should be used to override training values for your platform - // - // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), - // - // NOTE: - // The following training hardcode values are example values that were taken from a tilapia motherboard - // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in - // the table and replace the byte lane values with your own. - // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC - // Write Data Timing - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 - - // DQS Receiver Enable - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 - - // Write DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 - - // Read DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 - //-------------------------------------------------------------------------------------------------------------------------------------------------- - // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), /* End of Table */ }; const uint8_t SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 1491f29..9d84d09 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -30,18 +30,19 @@ #include <southbridge/amd/cimx/sb800/sb_cimx.h> -/* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ +/** + * Global variables for mainboard layouts. These are shared by irqtable, + * mptable and acpi_tables where busnum is default. + */ u8 bus_isa; u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ +/** + * Here you only need to set value in pci1234 for HT-IO that could be + * installed or not. You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ u32 pci1234x[] = { 0x0000ff0, }; @@ -53,7 +54,7 @@ static u32 get_bus_conf_done = 0; #if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ void get_bus_conf(void) { @@ -63,26 +64,29 @@ void get_bus_conf(void) device_t dev; int i, j; + /* Be sure func is called exactly once */ if (get_bus_conf_done == 1) - return; /* do it only once */ + return; get_bus_conf_done = 1; -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "main". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. +/** + * This is the call to AmdInitLate. It is really in the wrong place, + * conceptually, but functionally within the coreboot model, this is the best + * place to make the call. The logically correct place to call AmdInitLate is + * after PCI scan is done, after the decision about S3 resume is made, and + * before the system tables are written into RAM. The routine that is + * responsible for writing the tables is "write_tables", called near the end of + * "main". There is no platform specific entry point between the S3 resume + * decision point and the call to "write_tables", and the next platform + * specific entry points are the calls to the ACPI table write functions. The + * first of ose would seem to be the right place, but other table write + * functions, e.g. the PIRQ table write function, are called before the ACPI + * tables are written. This routine is called at the beginning of each of the + * write functions called prior to the ACPI write functions, so this becomes + * the best place for this call. */ + #if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { status = agesawrapper_amdinitlate(); @@ -96,7 +100,8 @@ void get_bus_conf(void) status = agesawrapper_amdinitlate(); if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ + sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); @@ -142,5 +147,5 @@ void get_bus_conf(void) #if CONFIG_AMD_SB_CIMX sb_Late_Post(); -#endif +#endif /* CONFIG_AMD_SB_CIMX */ } diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index b77c375..40fb58f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -26,9 +26,9 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -58,15 +58,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) u8 sum = 0; int i; + /* Find all Bus num and APIC's that are share with + * mptable.c and acpi_tables.c + */ + get_bus_conf(); - get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ - - /* Align the table to be 16 byte aligned. */ + /* Align table on 16Byte boundary. */ addr += 15; addr &= ~15; - /* This table must be betweeen 0xf0000 & 0x100000 */ + /* This table must be between 0xf0000 & 0x100000 */ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); @@ -90,19 +92,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - - /* pci bridge */ + /* PCI Bridge */ write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) @@ -117,5 +114,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "write_pirq_routing_table done.\n"); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d5f2d03..1d82cb9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -64,7 +64,7 @@ static void mainboard_enable(device_t dev) */ #if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ /* enable GPP CLK0 thru CLK3 (interleaved) */ /* disable GPP CLK4 thru SLT_GFX_CLK */ @@ -75,7 +75,7 @@ static void mainboard_enable(device_t dev) *(misc_mem_clk_cntrl + 3) = 0x00; *(misc_mem_clk_cntrl + 4) = 0x00; - /* + /** * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The * SPD read code has been made generic and moved out of the board diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index d7fe6a0..7a08726 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -95,7 +95,6 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); @@ -107,10 +106,10 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - /* sata */ + /* SATA */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* on board NIC & Slot PCIE. */ + /* On-board NIC & Slot PCIE. */ /* PCI slots */ /* PCI_SLOT 0. */ @@ -119,7 +118,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); - /* PCI_SLOT 1. */ + /* On-board Realtek NIC 1. */ PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); @@ -135,7 +134,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); - /* PCIe PortA */ + /* On-board Realtek NIC 2. (PCIe PortA) */ PCI_INT(0x0, 0x15, 0x0, 0x10); /* PCIe PortB */ PCI_INT(0x0, 0x15, 0x1, 0x11); @@ -144,7 +143,9 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: + * Type | Polarity | Trigger | Bus ID | IRQ | APIC ID PIN# + */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 846d5c7..3406edf 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ /* Initialize i8259 pic */ post_code(0x43);

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Patch merged into coreboot/master: c21bd88 jetway/nf81-t56n-lf: Replace AGESA types with stdint types
by gerrit＠coreboot.org 13 Apr '14

13 Apr '14

the following patch was just integrated into master: commit c21bd8839b68dbc46b11e50697b041ba2b20d59c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Apr 12 04:12:14 2014 +1000 jetway/nf81-t56n-lf: Replace AGESA types with stdint types Try to use void and uint*_t type specifiers in place of VOID and UINT* respectively. Use const in place of CONST type modifier. Remove some useless type casts. A few unneeded comments containing the AGESA redefenied types are also removed. Change-Id: I4bff96a222507fc35333488331c3f35ef1158132 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5486 Tested-by: build bot (Jenkins) See http://review.coreboot.org/5486 for details. -gerrit

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Patch merged into coreboot/master: e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
by gerrit＠coreboot.org 13 Apr '14

13 Apr '14

the following patch was just integrated into master: commit e2f3bfc5b372227223c3ce869e2c82e1dffd469a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Apr 11 12:56:13 2014 +1000 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5484 Tested-by: build bot (Jenkins) See http://review.coreboot.org/5484 for details. -gerrit

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New patch to review for coreboot: 50f6be1 southbridge/amd/agesa/hudson: Add initial support for SMM
by Alexandru Gagniuc 13 Apr '14

13 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5494 -gerrit commit 50f6be198c93786917ccd956c2c9ee31e782e38b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Apr 10 14:35:59 2014 -0500 southbridge/amd/agesa/hudson: Add initial support for SMM This sets up the infrastructure to handle SMIs generated by the Hudson sothbridge. An API for interfacing to mainboard handlers is not defined at this point. SMIs are always acknowledged and cleared, as not clearing an SMI will cause us to re-enter the SMI, effectively bricking the machine if a southbridge-generated SMI without a handler occurs. Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 2 + src/southbridge/amd/agesa/hudson/smihandler.c | 154 ++++++++++++++++++++++++++ src/southbridge/amd/agesa/hudson/smm.c | 9 ++ 3 files changed, 165 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 54a93d2..3211259 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -22,6 +22,8 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c romstage-y += imc.c ramstage-y += imc.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +ramstage-y += smm.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ # |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c new file mode 100644 index 0000000..0c3001e --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -0,0 +1,154 @@ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <delay.h> +#include <arch/io.h> + +/* ACPI base is hardcoded by AGESA, and SMI BASE is at offset 0x200 from it */ +#define SMI_BASE 0xfed80200 + +enum smi_source { + SMI_SOURCE_SCI = (1 << 0), + SMI_SOURCE_GPE = (1 << 1), + SMI_SOURCE_0x84 = (1 << 2), + SMI_SOURCE_0x88 = (1 << 3), + SMI_SOURCE_IRQ_TRAP = (1 << 4), + SMI_SOURCE_0x90 = (1 << 5) +}; + +static inline uint32_t smi_read32(uint8_t offset) +{ + return read32(SMI_BASE + offset); +} + +static inline void smi_write32(uint8_t offset, uint32_t value) +{ + write32(SMI_BASE + offset, value); +} + +static inline uint16_t smi_read16(uint8_t offset) +{ + return read16(SMI_BASE + offset); +} + +static inline void smi_write16(uint8_t offset, uint16_t value) +{ + write16(SMI_BASE + offset, value); +} + +void udelay(unsigned usecs) +{ + print_debug("udelay STUB!!!\n"); + /* Stub */ +} + +int southbridge_io_trap_handler(int smif) +{ + return 0; +} + +void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +{ + print_debug("southbridge_smi_handler STUB!!!\n"); + /* Stub */ + u8 cunt = read8(0xfed80240); + if (++cunt == 23) + cunt++; + write8(0xfed80240, cunt); +} + +static void process_smi_sci(void) +{ + uint32_t status; + + status = smi_read32(0x10); + + (void) status; + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x10, 0xffffffff); +} + +static void process_gpe_smi(void) +{ + uint32_t status; + + status = smi_read32(0x80); + + (void) status; + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x80, 0xffffffff); +} + +static void process_smi_0x84(void) +{ + uint32_t status; + + status = smi_read32(0x84); + + (void) status; + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x84, 0xffffffff); +} + +static void process_smi_0x88(void) +{ + uint32_t status; + + status = smi_read32(0x88); + + (void) status; + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x88, 0xffffffff); +} + +static void process_smi_0x8c(void) +{ + uint32_t status; + + status = smi_read32(0x8c); + + (void) status; + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x8c, 0xffffffff); +} + +static void process_smi_0x90(void) +{ + uint32_t status; + + status = smi_read32(0x90); + + (void) status; + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x90, 0xffffffff); +} + +void southbridge_smi_set_eos(void) +{ + uint16_t smi_src; + + u32 reg = smi_read32(0x98); + reg |= (1 << 28); + smi_write32(0x98, reg); + + smi_src = smi_read16(0x94); + + if (smi_src & SMI_SOURCE_SCI) + process_smi_sci(); + if (smi_src & SMI_SOURCE_GPE) + process_gpe_smi(); + if (smi_src & SMI_SOURCE_0x84) + process_smi_0x84(); + if (smi_src & SMI_SOURCE_0x88) + process_smi_0x88(); + if (smi_src & SMI_SOURCE_IRQ_TRAP) + process_smi_0x8c(); + if (smi_src & SMI_SOURCE_0x90) + process_smi_0x90(); +} diff --git a/src/southbridge/amd/agesa/hudson/smm.c b/src/southbridge/amd/agesa/hudson/smm.c new file mode 100644 index 0000000..a3a02ea --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/smm.c @@ -0,0 +1,9 @@ + +#include <console/console.h> +#include <cpu/cpu.h> + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + print_debug("smm_setup_structures STUB!!!\n"); + /* Stub */ +}

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New patch to review for coreboot: 0a159b2 cpu/amd/agesa/family15tn: Add initial support for SMM mode
by Alexandru Gagniuc 13 Apr '14

13 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5493 -gerrit commit 0a159b2dc32c593a77fecdd01c19168b23734169 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 12 21:57:18 2014 -0500 cpu/amd/agesa/family15tn: Add initial support for SMM mode This is the minimal setup needed to be able to execute SMI handlers. Only support for ASEG handlers is added, which should be sufficient for Trinity (up to 4 cores). There are a few hacks which need to be introduced in generic code in order to make this work properly, but these hacks are self-contained. They are a not a result of any special needs of this CPU, but rather from a poorly designed infrastructure. Comments are added to explain how such code could be refactored in the future. Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/cpu/amd/agesa/family15tn/model_15_init.c | 14 ++++++++++++++ src/cpu/x86/smm/smmhandler.S | 8 ++++++++ src/cpu/x86/smm/smmrelocate.S | 3 ++- src/include/cpu/amd/amdfam15.h | 2 ++ 5 files changed, 27 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..a447044 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -457,6 +457,7 @@ romstage-y += $(agesa_lib_src) ramstage-y += $(agesa_lib_src) subdirs-y += ../../mtrr +subdirs-y += ../../smm subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index f396201..fd4720d 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <device/device.h> #include <string.h> @@ -110,6 +111,19 @@ static void model_15_init(device_t dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + printk(BIOS_DEBUG, "Initializing SMM for CPU %u\n", cpu_info()->index); + /* Set SMM base address for this CPU */ + msr = rdmsr(MSR_SMM_BASE); + msr.lo = SMM_BASE - (cpu_info()->index * 0x400); + printk(BIOS_DEBUG, "SMM basin 0x%x 0x%x\n", msr.hi, msr.lo); + wrmsr(MSR_SMM_BASE, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(MSR_SMM_MASK); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(MSR_SMM_MASK, msr); + } /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 774088e..484b643 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -105,6 +105,14 @@ smm_handler_start: movl (%esi), %ecx shr $24, %ecx + /* This is an ugly hack, and we should find a way to read the CPU index + * without relying on the LAPIC ID. + */ +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) + /* LAPIC IDs start from 0x10; map that to the proper core index */ + subl $0x10, %ecx +#endif + /* calculate stack offset by multiplying the APIC ID * by 1024 (0x400), and save that offset in ebp. */ diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 71f74e7..bdc9771 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -23,7 +23,8 @@ #define __PRE_RAM__ /* On AMD's platforms we can set SMBASE by writing an MSR */ -#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 \ + && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 0c2cf7b..66c0175 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -23,6 +23,8 @@ #include <cpu/x86/msr.h> #define MCI_STATUS 0x00000401 +#define MSR_SMM_BASE 0xc0010111 +#define MSR_SMM_MASK 0xC0010113 #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f

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Patch set updated for coreboot: c5f4f67 jetway/nf81-t56n-lf: Replace AGESA types with stdint types
by Alexandru Gagniuc 12 Apr '14

12 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5486 -gerrit commit c5f4f6786b041caeac10806b51259377bf6757d8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Apr 12 04:12:14 2014 +1000 jetway/nf81-t56n-lf: Replace AGESA types with stdint types Try to use void and uint*_t type specifiers in place of VOID and UINT* respectively. Use const in place of CONST type modifier. Remove some useless type casts. A few unneeded comments containing the AGESA redefenied types are also removed. Change-Id: I4bff96a222507fc35333488331c3f35ef1158132 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 105 ++++++------ src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h | 54 +++--- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 16 +- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 5 +- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 4 +- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 188 ++++++++------------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 34 ++-- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 22 +-- 8 files changed, 186 insertions(+), 242 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 1d2aef0..0502e5a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -24,6 +24,7 @@ #include <northbridge/amd/agesa/family14/dimmSpd.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <vendorcode/amd/cimx/sb800/SB800.h> +#include <stdint.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -76,11 +77,11 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = }, }; -AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS GetBiosCallout (uint32_t Func, uint32_t Data, void *ConfigPtr) { - UINTN i; + size_t i; AGESA_STATUS CalloutStatus; - UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + size_t CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); /* * printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func); @@ -98,16 +99,16 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } -AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosAllocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + uint32_t AvailableHeapSize; + uint8_t *BiosHeapBaseAddr; + uint32_t CurrNodeOffset; + uint32_t PrevNodeOffset; + uint32_t FreedNodeOffset; + uint32_t BestFitNodeOffset; + uint32_t BestFitPrevNodeOffset; + uint32_t NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -120,7 +121,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = (uint8_t *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); @@ -132,7 +133,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) CurrNodePtr->BufferHandle = AllocParams->BufferHandle; CurrNodePtr->BufferSize = AllocParams->BufferLength; CurrNodePtr->NextNodeOffset = 0; - AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + AllocParams->BufferPointer = (uint8_t *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); /* Update the remaining free space */ FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); @@ -222,22 +223,22 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BestFitNodePtr->NextNodeOffset = 0; /* Remove BestFitNode from list of Freed nodes */ - AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + AllocParams->BufferPointer = (uint8_t *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); } } return AGESA_SUCCESS; } -AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosDeallocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + uint8_t *BiosHeapBaseAddr; + uint32_t AllocNodeOffset; + uint32_t PrevNodeOffset; + uint32_t NextNodeOffset; + uint32_t FreedNodeOffset; + uint32_t EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -247,7 +248,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = (uint8_t *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; /* Find target node to deallocate in list of allocated nodes. @@ -271,7 +272,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; /* Zero out the buffer, and clear the BufferHandle */ - LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + LibAmdMemFill ((uint8_t *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); AllocNodePtr->BufferHandle = 0; AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); @@ -348,17 +349,17 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } -AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosLocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + uint32_t AllocNodeOffset; + uint8_t *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = (uint8_t *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; @@ -375,14 +376,14 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } } - AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferPointer = (uint8_t *) ((uint8_t *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); AllocParams->BufferLength = AllocNodePtr->BufferSize; return AGESA_SUCCESS; } -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosRunFuncOnAp (uint32_t Func, uint32_t Data, void *ConfigPtr) { AGESA_STATUS Status; @@ -390,11 +391,11 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } -AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr) { AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + uint8_t Value; + uint32_t ResetType; AMD_CONFIG_PARAMS *StdHeader; ResetType = Data; @@ -426,7 +427,7 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosReadSpd (uint32_t Func, uint32_t Data, void *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ @@ -438,17 +439,19 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } -AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosDefaultRet (uint32_t Func, uint32_t Data, void *ConfigPtr) { return AGESA_UNSUPPORTED; } -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (uint32_t Func, uint32_t Data, void *ConfigPtr) { return AGESA_SUCCESS; } -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (uint32_t Func, uint32_t Data, void *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. @@ -456,28 +459,28 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (uint32_t Func, uint32_t Data, void *ConfigPtr) { return AGESA_SUCCESS; } -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void *ConfigPtr) { return AGESA_SUCCESS; } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; + uint32_t FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; + uint32_t GpioMmioAddr; + uint32_t AcpiMmioAddr; + uint8_t Data8; + uint16_t Data16; FcnData = Data; ResetInfo = ConfigPtr; @@ -488,7 +491,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; + AcpiMmioAddr = (uint32_t)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) @@ -497,7 +500,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(uint8_t)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h index c4f4f70..1d63f9b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h @@ -23,51 +23,53 @@ #include "Porting.h" #include "AGESA.h" +#include <stdint.h> + #define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */ #define BIOS_HEAP_SIZE 0x20000 #define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { - //UINT32 AvailableSize; - UINT32 StartOfAllocatedNodes; - UINT32 StartOfFreedNodes; + //uint32_t AvailableSize; + uint32_t StartOfAllocatedNodes; + uint32_t StartOfFreedNodes; } BIOS_HEAP_MANAGER; typedef struct _BIOS_BUFFER_NODE { - UINT32 BufferHandle; - UINT32 BufferSize; - UINT32 NextNodeOffset; + uint32_t BufferHandle; + uint32_t BufferSize; + uint32_t NextNodeOffset; } BIOS_BUFFER_NODE; /* * CALLOUTS */ -AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS GetBiosCallout (uint32_t Func, uint32_t Data, void *ConfigPtr); /* REQUIRED CALLOUTS * AGESA ADVANCED CALLOUTS - CPU */ -AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosAllocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (uint32_t Func, uint32_t Data, void *ConfigPtr); -/* AGESA ADVANCED CALLOUTS - MEMORY */ -AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); +/* AGESA Advanced Callouts - Memory */ +AGESA_STATUS BiosReadSpd (uint32_t Func,uint32_t Data,void *ConfigPtr); -/* BIOS DEFAULT RET */ -AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* BIOS default RET */ +AGESA_STATUS BiosDefaultRet (uint32_t Func, uint32_t Data, void *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (uint32_t Func, uint32_t Data, void *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (uint32_t Func, uint32_t Data, void *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (uint32_t Func, uint32_t Data, void *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void *ConfigPtr); /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr); #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index ccd3589..3cc9c89 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -38,19 +38,13 @@ * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID - * **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly) { - AGESA_STATUS Status; - VOID *BrazosPcieComplexListPtr; - VOID *BrazosPciePortPtr; - VOID *BrazosPcieDdiPtr; + AGESA_STATUS Status; + void *BrazosPcieComplexListPtr; + void *BrazosPciePortPtr; + void *BrazosPcieDdiPtr; ALLOCATE_HEAP_PARAMS AllocHeapParams; diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index 47ed1a5..20877f1 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -63,9 +63,6 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); +void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index e7772aa..90f556b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -113,11 +113,11 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(uint16_t *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(uint16_t *)addr - 2); return (unsigned long)current; } diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 3315eab..c9824f1 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -49,14 +49,14 @@ #define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +void *DmiTable = NULL; +void *AcpiPstate = NULL; +void *AcpiSrat = NULL; +void *AcpiSlit = NULL; -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +void *AcpiWheaMce = NULL; +void *AcpiWheaCmc = NULL; +void *AcpiAlib = NULL; /*------------------------------------------------------------------------------ * T Y P E D E F S A N D S T R U C T U R E S @@ -77,7 +77,7 @@ VOID *AcpiAlib = NULL; * L O C A L F U N C T I O N S *------------------------------------------------------------------------------ */ -uint32_t agesawrapper_amdinitcpuio(void) +AGESA_STATUS agesawrapper_amdinitcpuio(void) { pci_devfn_t dev; msr_t msr; @@ -112,25 +112,21 @@ uint32_t agesawrapper_amdinitcpuio(void) return AGESA_SUCCESS; } -UINT32 -agesawrapper_amdinitmmio ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitmmio(void) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; + uint64_t MsrReg; + uint32_t PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - UINT8 BusRangeVal = 0; - UINT8 BusNum; - UINT8 Index; + uint8_t BusRangeVal = 0; + uint8_t BusNum; + uint8_t Index; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ + * Set the MMIO Configuration Base Address and Bus Range onto MMIO + * configuration base Address MSR register. + */ for (Index = 0; Index < 8; Index++) { BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; @@ -140,7 +136,7 @@ agesawrapper_amdinitmmio ( } } - MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (uint64_t)(BusRangeVal << 2) | MMCONF_ENABLE); LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); /* @@ -158,14 +154,10 @@ agesawrapper_amdinitmmio ( PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + return AGESA_SUCCESS; } -UINT32 -agesawrapper_amdinitreset ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitreset(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -188,17 +180,15 @@ agesawrapper_amdinitreset ( status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + + return status; } -UINT32 -agesawrapper_amdinitearly ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitearly(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); @@ -217,19 +207,19 @@ agesawrapper_amdinitearly ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return status; } -UINT32 GetHeapBase( +uint32_t GetHeapBase( AMD_CONFIG_PARAMS *StdHeader ) { - UINT32 heap; + uint32_t heap; #if CONFIG_HAVE_ACPI_RESUME /* Both romstage and ramstage has this S3 detect. */ if (acpi_get_sleep_type() == 3) - heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ + heap = (uint32_t)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ else #endif heap = BIOS_HEAP_START_ADDRESS; /* low mem */ @@ -237,14 +227,11 @@ UINT32 GetHeapBase( return heap; } -UINT32 -agesawrapper_amdinitpost ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitpost(void) { AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; + uint16_t i; + uint32_t *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; @@ -265,7 +252,7 @@ agesawrapper_amdinitpost ( /* Initialize heap space */ BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); - HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + HeadPtr = (uint32_t *) ((uint8_t *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { *HeadPtr = 0x00000000; HeadPtr++; @@ -273,18 +260,15 @@ agesawrapper_amdinitpost ( BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0; - return (UINT32)status; + return status; } -UINT32 -agesawrapper_amdinitenv ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitenv(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; PCI_ADDR PciAddress; - UINT32 PciValue; + uint32_t PciValue; memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); @@ -371,13 +355,10 @@ agesawrapper_amdinitenv ( LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return status; } -VOID * -agesawrapper_getlateinitptr ( - int pick - ) +void * agesawrapper_getlateinitptr(int pick) { switch (pick) { case PICK_DMI: @@ -399,10 +380,7 @@ agesawrapper_getlateinitptr ( } } -UINT32 -agesawrapper_amdinitmid ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitmid(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -425,15 +403,12 @@ agesawrapper_amdinitmid ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return status; } -UINT32 -agesawrapper_amdinitlate ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitlate(void) { - AGESA_STATUS Status; + AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; @@ -451,10 +426,10 @@ agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); - Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { + status = AmdInitLate (AmdLateParamsPtr); + if (status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); + ASSERT(status == AGESA_SUCCESS); } DmiTable = AmdLateParamsPtr->DmiTable; @@ -475,14 +450,11 @@ agesawrapper_amdinitlate ( * AmdReleaseStruct (&AmdLateParams); */ - return (UINT32)Status; + return status; } #if CONFIG_HAVE_ACPI_RESUME -UINT32 -agesawrapper_amdinitresume ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -514,15 +486,12 @@ agesawrapper_amdinitresume ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return status; } -UINT32 -agesawrapper_amds3laterestore ( - VOID - ) +AGESA_STATUS agesawrapper_amds3laterestore(void) { - AGESA_STATUS Status; + AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdInterfaceParams; AMD_S3LATE_PARAMS AmdS3LateParams; AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; @@ -547,22 +516,19 @@ agesawrapper_amds3laterestore ( (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { + status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); + ASSERT(status == AGESA_SUCCESS); } - return (UINT32)Status; + return status; } #ifndef __PRE_RAM__ -UINT32 -agesawrapper_amdS3Save ( - VOID - ) +AGESA_STATUS agesawrapper_amdS3Save(void) { - AGESA_STATUS Status; + AGESA_STATUS status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; @@ -581,15 +547,15 @@ agesawrapper_amdS3Save ( AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - Status = AmdS3Save (AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { + status = AmdS3Save (AmdS3SaveParamsPtr); + if (status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); + ASSERT(status == AGESA_SUCCESS); } S3DataType = S3DataTypeNonVolatile; - Status = OemAgesaSaveS3Info ( + status = OemAgesaSaveS3Info ( S3DataType, AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, AmdS3SaveParamsPtr->S3DataBlock.NvStorage); @@ -597,7 +563,7 @@ agesawrapper_amdS3Save ( if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { S3DataType = S3DataTypeVolatile; - Status = OemAgesaSaveS3Info ( + status = OemAgesaSaveS3Info ( S3DataType, AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage @@ -607,19 +573,18 @@ agesawrapper_amdS3Save ( OemAgesaSaveMtrr(); AmdReleaseStruct (&AmdInterfaceParams); - return (UINT32)Status; + return status; } #endif /* #ifndef __PRE_RAM__ */ #endif /* CONFIG_HAVE_ACPI_RESUME */ -UINT32 -agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr +AGESA_STATUS agesawrapper_amdlaterunaptask ( + uint32_t Func, + uint32_t Data, + void *ConfigPtr ) { - AGESA_STATUS Status; + AGESA_STATUS status; AP_EXE_PARAMS ApExeParams; memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); @@ -631,21 +596,18 @@ agesawrapper_amdlaterunaptask ( ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr; - Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { + status = AmdLateRunApTask (&ApExeParams); + if (status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); + ASSERT(status == AGESA_SUCCESS); } - return (UINT32)Status; + return status; } -UINT32 -agesawrapper_amdreadeventlog ( - VOID - ) +AGESA_STATUS agesawrapper_amdreadeventlog(void) { - AGESA_STATUS Status; + AGESA_STATUS status; EVENT_PARAMS AmdEventParams; memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); @@ -654,13 +616,13 @@ agesawrapper_amdreadeventlog ( AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog (&AmdEventParams); + status = AmdReadEventLog (&AmdEventParams); while (AmdEventParams.EventClass != 0) { printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); + status = AmdReadEventLog (&AmdEventParams); } - return (UINT32)Status; + return status; } diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index 6af5e5f..bad9b80 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -54,8 +54,8 @@ enum { */ typedef struct { - UINT32 CalloutName; - AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); + uint32_t CalloutName; + AGESA_STATUS (*CalloutPtr) (uint32_t Func, uint32_t Data, void* ConfigPtr); } BIOS_CALLOUT_STRUCT; /*---------------------------------------------------------------------------------------- @@ -73,23 +73,23 @@ typedef struct { *--------------------------------------------------------------------------------------- */ -UINT32 agesawrapper_amdinitreset (void); -UINT32 agesawrapper_amdinitearly (void); -UINT32 agesawrapper_amdinitenv (void); -UINT32 agesawrapper_amdinitlate (void); -UINT32 agesawrapper_amdinitpost (void); -UINT32 agesawrapper_amdinitmid (void); +AGESA_STATUS agesawrapper_amdinitreset(void); +AGESA_STATUS agesawrapper_amdinitearly(void); +AGESA_STATUS agesawrapper_amdinitenv(void); +AGESA_STATUS agesawrapper_amdinitlate(void); +AGESA_STATUS agesawrapper_amdinitpost(void); +AGESA_STATUS agesawrapper_amdinitmid(void); -UINT32 agesawrapper_amdreadeventlog (void); +AGESA_STATUS agesawrapper_amdreadeventlog(void); -uint32_t agesawrapper_amdinitcpuio (void); -UINT32 agesawrapper_amdinitmmio (void); -UINT32 agesawrapper_amdinitresume (void); -UINT32 agesawrapper_amdS3Save (void); -UINT32 agesawrapper_amds3laterestore (void); -UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); +AGESA_STATUS agesawrapper_amdinitcpuio(void); +AGESA_STATUS agesawrapper_amdinitmmio(void); +AGESA_STATUS agesawrapper_amdinitresume(void); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amds3laterestore(void); +AGESA_STATUS agesawrapper_amdlaterunaptask(uint32_t, uint32_t, void *); +void * agesawrapper_getlateinitptr(int); -UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); +uint32_t GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); #endif diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index c6594d3..aa985a5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -240,7 +240,7 @@ */ /* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, @@ -327,7 +327,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // // The following macros are supported (use comma to separate macros): // @@ -391,7 +391,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { //DA Customer table -CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = +const uint8_t AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = { // Hardcoded Memory Training Values @@ -433,18 +433,4 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // TABLE END NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; -CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); - -/* *************************************************************************** - * Optional User code to be included into the AGESA build - * These may be 32-bit call-out routines... - */ -//AGESA_STATUS -//AgesaReadSpd ( -// IN UINTN FcnData, -// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd -// ) -//{ -// /* platform code to read an SPD... */ -// return Status; -//} +const uint8_t SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);

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Patch set updated for coreboot: 5076aff jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
by Alexandru Gagniuc 12 Apr '14

12 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5484 -gerrit commit 5076affa8c369339a35d3969a890bfec1906744d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Apr 11 12:56:13 2014 +1000 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 23 ++------ src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 62 +++++----------------- 2 files changed, 18 insertions(+), 67 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index d7413cd..ccd3589 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +21,7 @@ #include "PlatformGnbPcieComplex.h" #include "BiosCallOuts.h" +#include <string.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -133,24 +135,9 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill (BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); - - LibAmdMemFill (BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); - - LibAmdMemFill (BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); - - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 1627f25..3315eab 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -171,15 +171,8 @@ agesawrapper_amdinitreset ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); + memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -207,10 +200,7 @@ agesawrapper_amdinitearly ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -258,10 +248,7 @@ agesawrapper_amdinitpost ( AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -299,10 +286,7 @@ agesawrapper_amdinitenv ( PCI_ADDR PciAddress; UINT32 PciValue; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -426,10 +410,7 @@ agesawrapper_amdinitmid ( /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -456,10 +437,7 @@ agesawrapper_amdinitlate ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -511,10 +489,7 @@ agesawrapper_amdinitresume ( AMD_RESUME_PARAMS *AmdResumeParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -553,10 +528,8 @@ agesawrapper_amds3laterestore ( AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -594,10 +567,7 @@ agesawrapper_amdS3Save ( AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -652,10 +622,7 @@ agesawrapper_amdlaterunaptask ( AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -681,10 +648,7 @@ agesawrapper_amdreadeventlog ( AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL;

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coreboot-gerrit April 2014