coreboot-gerrit April 2014

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Patch merged into coreboot/master: b4417fb hp/pavilion_m6_1035dx: Add basic EC initialization
by gerrit＠coreboot.org 13 Apr '14

13 Apr '14

the following patch was just integrated into master: commit b4417fb1390d627090ee1e838623ac73af1fc634 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 6 23:57:57 2014 -0500 hp/pavilion_m6_1035dx: Add basic EC initialization The EC is now set to ACPI mode, and properly generates SCIs on external events. This fixes the issue where battery notifications were not working. The keyboard matrix type is also explicitly set up. Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5471 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5471 for details. -gerrit

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Patch set updated for coreboot: dda9b74 mainboard/jetway/nf81-t56n-lf: Init SIO HWM multi-func regs
by Edward O'Callaghan 13 Apr '14

13 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5500 -gerrit commit dda9b74773d257ed4fc533add6a1de25ab87af50 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 13 22:31:08 2014 +1000 mainboard/jetway/nf81-t56n-lf: Init SIO HWM multi-func regs The Fintek F71869AD found on this board needs special "Multifunction registers" to be tweaked before it will control the CPU fan properly. Change-Id: I0b93c878b532bfa39b9ceb10ce6bada079408b6b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/Makefile.inc | 4 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 6 ++ src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c | 129 ++++++++++++++++++++++++ src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h | 29 ++++++ 4 files changed, 166 insertions(+), 2 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index e1f18a9..2e9bd0c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -29,9 +29,9 @@ romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c +romstage-y += superio_hwm.c + ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c - - diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 846d5c7..336dc17 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -19,6 +19,7 @@ */ #include "agesawrapper.h" +#include "superio_hwm.h" #include <arch/cpu.h> #include <arch/io.h> @@ -52,6 +53,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) +#define HWM_DEV PNP_DEV(0x2e, F71869AD_HWM) + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -79,6 +82,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); } + /* Fintek F71869AD Hardware Monitor needs special configuration */ + superio_enable_hwm(HWM_DEV); + /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); diff --git a/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c new file mode 100644 index 0000000..29b4786 --- /dev/null +++ b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Just enough of a driver to make coreboot control system fans. + * No configuration is necessary for the OS to pick up the device. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> + +#include "superio_hwm.h" + +#define DEBUG_SUPERIO_HWM 0 + +typedef struct superio_hwm_config { + u32 base; +} hwm_config_t; + +static void write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +static u8 read_index(u16 port, u8 reg) +{ + outb(reg, port); + return inb(port + 1); +} + +static void init_hwm_registers(u16 base, u8 * hwm_reg_values, int size) +{ + u8 reg, value; + int i; + + for (i = 0; i < size; i += 3) { + reg = hwm_reg_values[i]; + value = read_index(base, reg); + value &= 0xff & hwm_reg_values[i + 1]; + value |= 0xff & hwm_reg_values[i + 2]; + printk(BIOS_DEBUG, "Super I/O HWM: base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); + write_index(base, reg, value); +#if DEBUG_SUPERIO_HWM == 1 + value = read_index(base, reg); + printk(BIOS_DEBUG, "Super I/O HWM (read back): base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); +#endif /* DEBUG_SUPERIO_HWM */ + } +} + +/* Initialize F71869AD hardware monitor registers, usually at 0x225. */ +void superio_enable_hwm(device_t dev) +{ + hwm_config_t * config = dev->chip_info; + + /* return if hwm is disabled in devicetree.cb */ + if (!dev->enabled || !config) + return; + + u32 hwm_base = config->base; + + printk(BIOS_DEBUG, "Super I/O HWM: Initializing Hardware Monitor at pnp %04x\n" + , hwm_base); + + struct resource *res = find_resource(dev, PNP_IDX_IO0); + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "Super I/O HWM: Base Address at 0x%x\n", (u32)res->base); + printk(BIOS_DEBUG, "Super I/O HWM: Configuring registers...\n"); + + /* Fintek F71869AD AMD mode HWM (ordered) programming sequence. */ + u8 hwm_reg_values[] = { + /* reg mask data */ + 0x08, 0x00, 0x98, /* SMBus Address p.53 */ + 0x0a, 0x00, 0x02, /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ + /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ + 0xaf, 0x00, 0x8c, /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ + 0x9f, 0x00, 0x8a, /* set FAN_PROG_SEL = 1 */ + 0x94, 0x00, 0x00, /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */ + 0x96, 0x00, 0x07, /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ + 0x95, 0x00, 0x33, /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = 1, p.88 */ + 0x9f, 0x00, 0x0a, /* set FAN_PROG_SEL = 0 */ + /* .. */ + 0x02, 0x00, 0x30, /* OVT_MODE p.52 */ + 0x60, 0x00, 0x22, /* Temperature PME# Enable Register p.79 */ + 0x63, 0x00, 0x20, /* Temperature BEEP Enable Register p.58 */ + 0x64, 0x00, 0x22, /* T1 OVT and High Limit Temperature Select Register p.82 */ + 0x66, 0x00, 0x22, /* OVT and Alert Output Enable Register 1 p.59 */ + 0x82, 0x00, 0x76, /* Temperature sensors 1 OVT limit p.61 */ + 0x91, 0x00, 0x07, /* FAN Interrupt Status Register p.63 */ + 0x90, 0x00, 0x02, /* FAN PME# Enable Register p.85 */ + 0xa3, 0x00, 0x0e, /* FAN1 RPM mode p.70 */ + 0xa9, 0x00, 0x14, /* VT1 Boundary 2 Temperature p.71 */ + 0xaa, 0x00, 0xff, /* FAN1 Segment 1 Speed Count */ + 0xab, 0x00, 0x0e, /* FAN1 Segment 2 Speed Count */ + 0xae, 0x00, 0x07, /* FAN1 Segment 3 Speed Count */ + /* .. */ + 0xee, 0x00, 0x01, /* SMB_Status p.83 */ + 0xed, 0x00, 0x01, /* SMB/TSI Command Byte p.83 */ + 0xef, 0x00, 0x82, /* SMB_Protocal p.83 */ + }; + + init_hwm_registers(res->base, hwm_reg_values, ARRAY_SIZE(hwm_reg_values)); +} diff --git a/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h new file mode 100644 index 0000000..012cb66 --- /dev/null +++ b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +#include <device/device.h> + +/* Initialize F71869AD hardware monitor registers, usually at 0x225. */ +void superio_enable_hwm(device_t); + +#endif /* SUPERIO_HWM_H */

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New patch to review for coreboot: 667b901 mainboard/jetway/nf81-t56n-lf: Init SIO HWM special multi-func regs
by Edward O'Callaghan 13 Apr '14

13 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5500 -gerrit commit 667b90114c5eea11f1bd2bf7c7e9b0ee5a01e752 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 13 22:31:08 2014 +1000 mainboard/jetway/nf81-t56n-lf: Init SIO HWM special multi-func regs The Fintek F71869AD found on this board needs special "Multifunction registers" to be tweaked before it will control the CPU fan properly. Change-Id: I0b93c878b532bfa39b9ceb10ce6bada079408b6b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/Makefile.inc | 4 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 6 ++ src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c | 124 ++++++++++++++++++++++++ src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h | 27 ++++++ 4 files changed, 159 insertions(+), 2 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index e1f18a9..2e9bd0c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -29,9 +29,9 @@ romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c +romstage-y += superio_hwm.c + ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c - - diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 846d5c7..336dc17 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -19,6 +19,7 @@ */ #include "agesawrapper.h" +#include "superio_hwm.h" #include <arch/cpu.h> #include <arch/io.h> @@ -52,6 +53,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) +#define HWM_DEV PNP_DEV(0x2e, F71869AD_HWM) + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -79,6 +82,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); } + /* Fintek F71869AD Hardware Monitor needs special configuration */ + superio_enable_hwm(HWM_DEV); + /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); diff --git a/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c new file mode 100644 index 0000000..bda55b1 --- /dev/null +++ b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Just enough of a driver to make coreboot control system fans. + * No configuration is necessary for the OS to pick up the device. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> + +#include "superio_hwm.h" + +#define DEBUG_SUPERIO_HWM 0 + +static void write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +static u8 read_index(u16 port, u8 reg) +{ + outb(reg, port); + return inb(port + 1); +} + +static void init_hwm_registers(u16 base, u8 * hwm_reg_values, int size) +{ + u8 reg, value; + int i; + + for (i = 0; i < size; i += 3) { + reg = hwm_reg_values[i]; + value = read_index(base, reg); + value &= 0xff & hwm_reg_values[i + 1]; + value |= 0xff & hwm_reg_values[i + 2]; + printk(BIOS_DEBUG, "Super I/O HWM: base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); + write_index(base, reg, value); +#if DEBUG_SUPERIO_HWM == 1 + value = read_index(base, reg); + printk(BIOS_DEBUG, "Super I/O HWM (read back): base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); +#endif /* DEBUG_SUPERIO_HWM */ + } +} + +/* Initialize F71869AD hardware monitor registers, usually at 0x225. */ +void superio_enable_hwm(device_t dev) +{ + /* return if hwm is disabled in devicetree.cb */ + struct drivers_superio_hwm_config *config = dev->chip_info; + if (!dev->enabled || !config) + return; + + u32 hwm_base = config->base; + + printk(BIOS_DEBUG, "Super I/O HWM: Initializing Hardware Monitor at pnp %04x\n" + , hwm_base); + + struct resource *res = find_resource(dev, PNP_IDX_IO0); + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "Super I/O HWM: Base Address at 0x%x\n", (u32)res->base); + printk(BIOS_DEBUG, "Super I/O HWM: Configuring registers...\n"); + + /* Fintek F71869AD AMD mode HWM (ordered) programming sequence. */ + u8 hwm_reg_values[] = { + /* reg mask data */ + 0x08, 0x00, 0x98, /* SMBus Address p.53 */ + 0x0a, 0x00, 0x02, /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ + /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ + 0xaf, 0x00, 0x8c, /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ + 0x9f, 0x00, 0x8a, /* set FAN_PROG_SEL = 1 */ + 0x94, 0x00, 0x00, /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */ + 0x96, 0x00, 0x07, /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ + 0x95, 0x00, 0x33, /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = 1, p.88 */ + 0x9f, 0x00, 0x0a, /* set FAN_PROG_SEL = 0 */ + /* .. */ + 0x02, 0x00, 0x30, /* OVT_MODE p.52 */ + 0x60, 0x00, 0x22, /* Temperature PME# Enable Register p.79 */ + 0x63, 0x00, 0x20, /* Temperature BEEP Enable Register p.58 */ + 0x64, 0x00, 0x22, /* T1 OVT and High Limit Temperature Select Register p.82 */ + 0x66, 0x00, 0x22, /* OVT and Alert Output Enable Register 1 p.59 */ + 0x82, 0x00, 0x76, /* Temperature sensors 1 OVT limit p.61 */ + 0x91, 0x00, 0x07, /* FAN Interrupt Status Register p.63 */ + 0x90, 0x00, 0x02, /* FAN PME# Enable Register p.85 */ + 0xa3, 0x00, 0x0e, /* FAN1 RPM mode p.70 */ + 0xa9, 0x00, 0x14, /* VT1 Boundary 2 Temperature p.71 */ + 0xaa, 0x00, 0xff, /* FAN1 Segment 1 Speed Count */ + 0xab, 0x00, 0x0e, /* FAN1 Segment 2 Speed Count */ + 0xae, 0x00, 0x07, /* FAN1 Segment 3 Speed Count */ + /* .. */ + 0xee, 0x00, 0x01, /* SMB_Status p.83 */ + 0xed, 0x00, 0x01, /* SMB/TSI Command Byte p.83 */ + 0xef, 0x00, 0x82, /* SMB_Protocal p.83 */ + }; + + init_hwm_registers(res->base, hwm_reg_values, ARRAY_SIZE(hwm_reg_values)); +} diff --git a/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h new file mode 100644 index 0000000..75feb42 --- /dev/null +++ b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +/* Initialize F71869AD hardware monitor registers, usually at 0x225. */ +void superio_enable_hwm(device_t); + +#endif /* SUPERIO_HWM_H */

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New patch to review for coreboot: 4762d95 superio/ite/it8728f: Fix headers and prototype location
by Edward O'Callaghan 13 Apr '14

13 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5499 -gerrit commit 4762d95f0bdc8c9f1f1d8cd39f976b8357a80bf2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 13 20:21:56 2014 +1000 superio/ite/it8728f: Fix headers and prototype location Try to conform to some kind of standard/consensus for prototype location. Correct headers while here. Change-Id: Ie99b1801fa42ddefb9f25d54f326ba7131bd7089 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8728f/early_serial.c | 5 ++++- src/superio/ite/it8728f/early_serial.h | 40 ---------------------------------- src/superio/ite/it8728f/it8728f.h | 18 ++++++++++++--- 3 files changed, 19 insertions(+), 44 deletions(-) diff --git a/src/superio/ite/it8728f/early_serial.c b/src/superio/ite/it8728f/early_serial.c index 7fbd061..c2632ef 100644 --- a/src/superio/ite/it8728f/early_serial.c +++ b/src/superio/ite/it8728f/early_serial.c @@ -18,7 +18,10 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "early_serial.h" + +#include <arch/io.h> +#include <device/pnp.h> +#include "it8728f.h" /* Superio raw commands */ static void it8728f_sio_write(device_t dev, u8 index, u8 value) diff --git a/src/superio/ite/it8728f/early_serial.h b/src/superio/ite/it8728f/early_serial.h deleted file mode 100644 index a146f4c..0000000 --- a/src/superio/ite/it8728f/early_serial.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Damien Zammit <damien(a)zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef SUPERIO_ITE_IT8728F_EARLY_SERIAL_H -#define SUPERIO_ITE_IT8728F_EARLY_SERIAL_H - -#include <stdint.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include "it8728f.h" - -/* - * Superio low level commands - * Pass dev = PNP_DEV(superiobase, LDN) - */ -void it8728f_reg_write(device_t dev, u8 index, u8 value); - -/* Select 24MHz CLKIN (48MHz default). */ -void it8728f_24mhz_clkin(device_t dev); - -/* Enable the serial port(s). */ -void it8728f_enable_serial(device_t dev, u16 iobase); - -#endif diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 603e467..55bdf69 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8728F_IT8728F_H -#define SUPERIO_ITE_IT8728F_IT8728F_H +#ifndef SUPERIO_ITE_IT8728F_H +#define SUPERIO_ITE_IT8728F_H #define IT8728F_FDC 0x00 /* Floppy */ #define IT8728F_SP1 0x01 /* Com1 */ @@ -39,4 +39,16 @@ #define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. 'Special register' */ -#endif +/* + * Superio low level commands + * Pass dev = PNP_DEV(superiobase, LDN) + */ +void it8728f_reg_write(device_t dev, u8 index, u8 value); + +/* Select 24MHz CLKIN (48MHz default). */ +void it8728f_24mhz_clkin(device_t dev); + +/* Enable the serial port(s). */ +void it8728f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_ITE_IT8728F_H */

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New patch to review for coreboot: 6a9c9da mainboard/*/devicetree.cb: Toggle lacking IDE off
by Edward O'Callaghan 13 Apr '14

13 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5498 -gerrit commit 6a9c9da0ac3d46f23741564ef184a9d11621cab4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 13 17:57:31 2014 +1000 mainboard/*/devicetree.cb: Toggle lacking IDE off These boards do not have 'IDE' or emulation of IDE/PATA on the 6 chipset supported SATA channels. Many of these boards only have =<4 AHCI ports mapped off the SATA channels. Change-Id: I1c529eb94a90a97ddc51aece1be3df9f4728a309 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/devicetree.cb | 2 +- src/mainboard/asrock/e350m1/devicetree.cb | 2 +- src/mainboard/avalue/eax-785e/devicetree.cb | 2 +- src/mainboard/gizmosphere/gizmo/devicetree.cb | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index f7db1cc..1c8b690 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/amd/amdfam10/root_complex device i2c 53 on end end end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on chip superio/winbond/w83627hf diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index c908421..64e889d 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -51,7 +51,7 @@ chip northbridge/amd/agesa/family14/root_complex device i2c 51 on end end end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627hf diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb index 42ddf01..f392a2a 100644 --- a/src/mainboard/avalue/eax-785e/devicetree.cb +++ b/src/mainboard/avalue/eax-785e/devicetree.cb @@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on chip superio/winbond/w83627hf diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb index 301f79a..bdbe3dc 100755 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb @@ -45,7 +45,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed

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Patch merged into coreboot/master: 99e2bf8 cimx/sb800 boards: Don't require ide.asl on boards without IDE
by gerrit＠coreboot.org 13 Apr '14

13 Apr '14

the following patch was just integrated into master: commit 99e2bf87ef9e91196bf19eaa9091c2a945352316 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 6 02:53:49 2014 +1100 cimx/sb800 boards: Don't require ide.asl on boards without IDE Not all boards which use the AMD cimx/sb800 southbridge have IDE. However, the southbridge's asl included an 'ide.asl' file which had to be present in $(mainboard_dir)/acpi. Address this issue by including ide.asl only in boards which have IDE, and remove it from all other cimx/sb800 boards. Change-Id: I57fcb4db9f85234b05ae1705ef81a576c478cee6 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5460 for details. -gerrit

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New patch to review for coreboot: fa7bb8d f2a85-m: various clean ups
by Patrick Georgi 13 Apr '14

13 Apr '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5497 -gerrit commit fa7bb8d42984fafa9bbff0a8ea59b406a986052e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Apr 13 08:58:38 2014 +0200 f2a85-m: various clean ups Two defines were unused, another two now use AGESA names in the background to avoid them drifting apart (if someone copy&pastes this board as a template for a new chipset). Also avoid to mention early_serial.h Change-Id: I291ec5eae03e5db20b5672ec9f53972fb060c2be Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/asus/f2a85-m/romstage.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 990343b..cbe059f 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include "agesawrapper.h" +#include <Proc/Fch/Fch.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -39,7 +40,7 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" /* Note that the IT8603E is a strip down version of this chip */ -#include "superio/ite/it8728f/early_serial.h" +#include <superio/ite/it8728f/it8728f.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) @@ -47,10 +48,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void disable_cache_as_ram(void); -#define MMIO_NON_POSTED_START 0xfed00000 -#define MMIO_NON_POSTED_END 0xfedfffff -#define SB_MMIO 0xFED80000 -#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) +#define SB_MMIO ACPI_MMIO_BASE +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + MISC_BASE + (x)) static void sbxxx_enable_48mhzout(void) {

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New patch to review for coreboot: bf5c63b it8728f: move prototypes to it8728f.h
by Patrick Georgi 13 Apr '14

13 Apr '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5496 -gerrit commit bf5c63b8a3abf2504845d177ce9274086f37f3ef Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Apr 13 08:57:35 2014 +0200 it8728f: move prototypes to it8728f.h early_serial.h includes it, so this still works. But long(er) term we want to de-emphasize early_serial. Change-Id: I633f491bff5bc999e90dbd857bbade5cb35fde0c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/superio/ite/it8728f/early_serial.h | 15 --------------- src/superio/ite/it8728f/it8728f.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/superio/ite/it8728f/early_serial.h b/src/superio/ite/it8728f/early_serial.h index 3443e0d..1090545 100644 --- a/src/superio/ite/it8728f/early_serial.h +++ b/src/superio/ite/it8728f/early_serial.h @@ -25,19 +25,4 @@ #include <device/pnp_def.h> #include "it8728f.h" -/* - * Superio low level commands - * Pass dev = PNP_DEV(superiobase, LDN) - */ -void it8728f_reg_write(device_t dev, u8 index, u8 value); - -/* Select 24MHz CLKIN (48MHz default). */ -void it8728f_24mhz_clkin(device_t dev); - -/* Enable the serial port(s). */ -void it8728f_enable_serial(device_t dev, u16 iobase); - -void it8728f_kill_watchdog(device_t dev); -void it8728f_enable_3vsbsw(device_t dev); - #endif diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 9a92f5a..687fa13 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -41,4 +41,19 @@ #define IT8728F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ #define IT8728F_CONFIG_REG_MFC 0x2a /* Multi-function control */ +/* + * Superio low level commands + * Pass dev = PNP_DEV(superiobase, LDN) + */ +void it8728f_reg_write(device_t dev, u8 index, u8 value); + +/* Select 24MHz CLKIN (48MHz default). */ +void it8728f_24mhz_clkin(device_t dev); + +/* Enable the serial port(s). */ +void it8728f_enable_serial(device_t dev, u16 iobase); + +void it8728f_kill_watchdog(device_t dev); +void it8728f_enable_3vsbsw(device_t dev); + #endif

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New patch to review for coreboot: 0489e75 cimx/sb800/cfg.c: Cut out purposeless ROM reading noise.
by Edward O'Callaghan 13 Apr '14

13 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5495 -gerrit commit 0489e750825d5aebec59f48d943ed3e65f353b28 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 13 16:45:12 2014 +1000 cimx/sb800/cfg.c: Cut out purposeless ROM reading noise. Follow along hudson, cut out "SLP_TYP type was 0" excessively filling the buffer. We could make this conditional on non-zero? Change-Id: Iffd4c146b2ac4f57dbc3a011a683c92b6e132e39 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/cimx/sb800/cfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 8520548..78aab79 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -31,7 +31,7 @@ int acpi_get_sleep_type(void) { u16 tmp = inw(PM1_CNT_BLK_ADDRESS); tmp = ((tmp & (7 << 10)) >> 10); - printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); + /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ return (int)tmp; } #endif

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Patch set updated for coreboot: 90b99a6 mainboard/jetway/nf81-t56n-lf: Use hexdump inplace of custom
by Edward O'Callaghan 13 Apr '14

13 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5466 -gerrit commit 90b99a65b5858bac117db970af77cff80ab04448 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 6 20:18:27 2014 +1000 mainboard/jetway/nf81-t56n-lf: Use hexdump inplace of custom Use hexdump() instead of a local implementation for dumping ACPI_TABLES. Change-Id: I20354a4f9dff4105de5af696bb9da4a4f6cca788 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 39 +++++++++---------------- 1 file changed, 13 insertions(+), 26 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 90f556b..fb3d1c8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -31,21 +31,8 @@ #define DUMP_ACPI_TABLES 0 #if DUMP_ACPI_TABLES == 1 - -static void dump_mem(u32 start, u32 end) -{ - - u32 i; - print_debug("dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - print_debug("\n"); -} -#endif +#include <lib.h> +#endif /* DUMP_ACPI_TABLES */ extern const unsigned char AmlCode[]; @@ -285,35 +272,35 @@ unsigned long write_acpi_tables(unsigned long start) #if DUMP_ACPI_TABLES == 1 printk(BIOS_DEBUG, "rsdp\n"); - dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + hexdump(rsdp, sizeof(acpi_rsdp_t)); printk(BIOS_DEBUG, "rsdt\n"); - dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + hexdump(rsdt, sizeof(acpi_rsdt_t)); printk(BIOS_DEBUG, "madt\n"); - dump_mem(madt, ((void *)madt) + madt->header.length); + hexdump(madt, madt->header.length); printk(BIOS_DEBUG, "srat\n"); - dump_mem(srat, ((void *)srat) + srat->header.length); + hexdump(srat, srat->header.length); printk(BIOS_DEBUG, "slit\n"); - dump_mem(slit, ((void *)slit) + slit->header.length); + hexdump(slit, slit->header.length); printk(BIOS_DEBUG, "alib\n"); - dump_mem(ssdt, ((void *)alib) + alib->length); + hexdump(ssdt, alib->length); printk(BIOS_DEBUG, "ssdt\n"); - dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + hexdump(ssdt, ssdt->length); printk(BIOS_DEBUG, "ssdt2\n"); - dump_mem(ssdt2, ((void *)ssdt2) + ssdt2->length); + hexdump(ssdt2, ssdt2->length); printk(BIOS_DEBUG, "fadt\n"); - dump_mem(fadt, ((void *)fadt) + fadt->header.length); + hexdump(fadt, fadt->header.length); printk(BIOS_DEBUG, "hest\n"); - dump_mem(hest, ((void *)hest) + hest->header.length); -#endif + hexdump(hest, hest->header.length); +#endif /* DUMP_ACPI_TABLES */ printk(BIOS_INFO, "ACPI: done.\n"); return current;

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coreboot-gerrit April 2014