coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

1 participants
1135 discussions

Patch set updated for coreboot: a63616f lenovo/x60: Support digitizer on X60t and X201t.
by Vladimir Serbinenko 15 Feb '14

15 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5239 -gerrit commit a63616f9d4ae8de131ce9c6a49f9a888d78c2203 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 17:00:46 2014 +0100 lenovo/x60: Support digitizer on X60t and X201t. Change-Id: I5b0399a8edca3b73aa7d515d2c446c31b3239fa5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/Kconfig | 4 +- src/mainboard/lenovo/x201/Kconfig | 4 +- src/mainboard/lenovo/x201/acpi_tables.c | 2 + src/mainboard/lenovo/x201/devicetree.cb | 14 +++ src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x60/Kconfig | 3 +- src/mainboard/lenovo/x60/acpi_tables.c | 2 + src/mainboard/lenovo/x60/devicetree.cb | 7 +- src/odm_oem/Kconfig | 2 + src/odm_oem/lenovo/Kconfig | 28 +++++ src/odm_oem/lenovo/Makefile.inc | 1 + src/odm_oem/lenovo/lenovo.h | 3 + src/odm_oem/lenovo/wacom.c | 175 ++++++++++++++++++++++++++++++++ src/superio/nsc/pc87382/superio.c | 9 ++ 14 files changed, 249 insertions(+), 7 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..1de11a8 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -4,7 +4,7 @@ choice prompt "Mainboard model" config BOARD_LENOVO_X60 - bool "ThinkPad X60 / X60s" + bool "ThinkPad X60 / X60s / X60t" help The following X60 series ThinkPad machines have been verified to work correctly: @@ -13,7 +13,7 @@ config BOARD_LENOVO_X60 ThinkPad X60 (Model 1709) config BOARD_LENOVO_X201 - bool "ThinkPad X201" + bool "ThinkPad X201 / X201s / X201t" help Lenovo X201 laptop. Consult wiki for details. diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 8e7ebae..4caf58c 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -18,6 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select EARLY_CBMEM_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT + select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_WACOM config MAINBOARD_DIR string @@ -29,7 +31,7 @@ config MAINBOARD_PART_NUMBER config MAINBOARD_VERSION string - default "ThinkPad X201" + default "ThinkPad X201 / X201s / X201t" config MAINBOARD_VENDOR string diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 165de0d..981c52e 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -31,6 +31,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "southbridge/intel/ibexpeak/nvs.h" +#include "odm_oem/lenovo/lenovo.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -93,6 +94,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); return (unsigned long)(acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..0b978de 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -139,6 +139,20 @@ chip northbridge/intel/nehalem end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index f0874d3..9b99c4e 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + COMA_LPC_EN | GAMEL_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..8c1417e 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select DRIVERS_LENOVO_WACOM config MAINBOARD_DIR string @@ -41,7 +42,7 @@ config DCACHE_RAM_SIZE config MAINBOARD_PART_NUMBER string - default "ThinkPad X60 / X60s" + default "ThinkPad X60 / X60s / X60t" config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index f6ed4ae..d6ce4ba 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -29,6 +29,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "odm_oem/lenovo/lenovo.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -86,6 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); return (unsigned long) (acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 3880f18..5b4e37f 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -127,8 +127,11 @@ chip northbridge/intel/i945 io 0x60 = 0x2f8 end - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 end device pnp 164e.7 on # GPIO diff --git a/src/odm_oem/Kconfig b/src/odm_oem/Kconfig index 6eb2993..e1f5243 100644 --- a/src/odm_oem/Kconfig +++ b/src/odm_oem/Kconfig @@ -1,3 +1,5 @@ menu "OEM / ODM" +source "src/odm_oem/lenovo/Kconfig" + endmenu diff --git a/src/odm_oem/lenovo/Kconfig b/src/odm_oem/lenovo/Kconfig new file mode 100644 index 0000000..5056b1e --- /dev/null +++ b/src/odm_oem/lenovo/Kconfig @@ -0,0 +1,28 @@ +config DRIVERS_LENOVO_WACOM + bool + default n + +if DRIVERS_LENOVO_WACOM + +choice + prompt "Digitizer" + +config DIGITIZER_AUTODETECT + bool "Autodetect" + help + The presence of digitizer is inferred from model number stored in + AT24RF chip. + +config DIGITIZER_PRESENT + bool "Present" + help + The digitizer is assumed to be present. + +config DIGITIZER_ABSENT + bool "Absent" + help + The digitizer is assumed to be absent. + +endchoice + +endif diff --git a/src/odm_oem/lenovo/Makefile.inc b/src/odm_oem/lenovo/Makefile.inc index 18e2110..bbb39d4 100644 --- a/src/odm_oem/lenovo/Makefile.inc +++ b/src/odm_oem/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-y += serials.c +ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c diff --git a/src/odm_oem/lenovo/lenovo.h b/src/odm_oem/lenovo/lenovo.h index 6824eb6..25074bc 100644 --- a/src/odm_oem/lenovo/lenovo.h +++ b/src/odm_oem/lenovo/lenovo.h @@ -1 +1,4 @@ const char *lenovo_mainboard_partnumber(void); +int drivers_lenovo_is_wacom_present(void); +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, + int have_dock_serial); diff --git a/src/odm_oem/lenovo/wacom.c b/src/odm_oem/lenovo/wacom.c new file mode 100644 index 0000000..d30ed45 --- /dev/null +++ b/src/odm_oem/lenovo/wacom.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2, or (at your + * option) any later version, of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pnp.h> +#include <string.h> +#include "odm_oem/lenovo/lenovo.h" + +const char tablet_numbers[][5] = { + /* X60t. */ + "6363", "6364", "6365", "6366", + "6367", "6368", "7762", "7763", + "7764", "7767", "7768", "7769", + /* X201t. */ + "0053", "0831", "2985", "3093", + "3113", "3144", "3239", "4184", + "7448", "7449", "7450", "7453", + "2263", "2266", +}; + +int +drivers_lenovo_is_wacom_present(void) +{ +#if IS_ENABLED(CONFIG_DIGITIZER_PRESENT) + printk (BIOS_INFO, "Digitizer state forced as present\n"); + return 1; +#elif IS_ENABLED(CONFIG_DIGITIZER_ABSENT) + printk (BIOS_INFO, "Digitizer state forced as absent\n"); + return 0; +#else + const char *pn; + int i; + static int result = -1; + device_t superio; + u8 sioid; + + if (result != -1) + return result; + superio = dev_find_slot_pnp (0x164e, 3); + if (!superio) { + printk (BIOS_INFO, "No Super I/O, skipping wacom\n"); + return (result = 0); + } + + /* Probe ID. */ + sioid = pnp_read_config(superio, 0x20); + if (sioid == 0xff) { + printk (BIOS_INFO, "Super I/O probe failed, skipping wacom\n"); + return (result = 0); + } + + pn = lenovo_mainboard_partnumber(); + if (!pn) + return 0; + printk (BIOS_DEBUG, "Lenovo P/N is %s\n", pn); + for (i = 0; i < sizeof (tablet_numbers) / sizeof (tablet_numbers[0]); + i++) + if (memcmp (tablet_numbers[i], pn, 4) == 0) { + printk (BIOS_DEBUG, "Lenovo P/N %s is a tablet\n", pn); + return (result = 1); + } + printk (BIOS_DEBUG, "Lenovo P/N %s is not a tablet\n", pn); + return (result = 0); +#endif +} + +void +drivers_lenovo_serial_ports_ssdt_generate(const char *scope, + int have_dock_serial) +{ + int scopelen, devicelen, reslen, methodlen; + + scopelen = acpigen_write_scope(scope); + + if (drivers_lenovo_is_wacom_present()) { + /* Device op. */ + scopelen += acpigen_emit_byte(0x5b); + scopelen += acpigen_emit_byte(0x82); + devicelen = acpigen_write_len_f(); + devicelen += acpigen_emit_namestring("DTR"); + + devicelen += acpigen_write_name("_HID"); + devicelen += acpigen_emit_eisaid("WACF004"); + + devicelen += acpigen_write_name("_CRS"); + + reslen = acpigen_write_resourcetemplate_header(); + reslen += acpigen_write_io16(0x200, 0x200, 1, 8, 1); + reslen += acpigen_write_irq(0x20); + + devicelen += reslen; + devicelen += acpigen_write_resourcetemplate_footer(reslen); + + /* method op */ + devicelen += acpigen_emit_byte(0x14); + methodlen = acpigen_write_len_f(); + methodlen += acpigen_emit_namestring("_STA"); + /* no fnarg */ + methodlen += acpigen_emit_byte(0x00); + /* return */ + methodlen += acpigen_emit_byte(0xa4); + methodlen += acpigen_write_byte(0xf); + + acpigen_patch_len(methodlen - 1); + devicelen += methodlen; + + acpigen_patch_len(devicelen - 1); + scopelen += devicelen; + } + + if (have_dock_serial) { + /* Device op. */ + scopelen += acpigen_emit_byte(0x5b); + scopelen += acpigen_emit_byte(0x82); + devicelen = acpigen_write_len_f(); + devicelen += acpigen_emit_namestring("COMA"); + + devicelen += acpigen_write_name("_HID"); + devicelen += acpigen_emit_eisaid("PNP0511"); + devicelen += acpigen_write_name("_UID"); + /* Byte */ + methodlen += acpigen_write_byte(0xa); + methodlen += acpigen_write_byte(0x2); + + devicelen += acpigen_write_name("_CRS"); + + reslen = acpigen_write_resourcetemplate_header(); + reslen += acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); + reslen += acpigen_write_irq(0x10); + + devicelen += reslen; + devicelen += acpigen_write_resourcetemplate_footer(reslen); + + /* method op */ + devicelen += acpigen_emit_byte(0x14); + methodlen = acpigen_write_len_f(); + methodlen += acpigen_emit_namestring("_STA"); + /* no fnarg */ + methodlen += acpigen_emit_byte(0x00); + /* return */ + methodlen += acpigen_emit_byte(0xa4); + methodlen += acpigen_write_byte(0xf); + acpigen_patch_len(methodlen - 1); + + devicelen += methodlen; + + acpigen_patch_len(devicelen - 1); + scopelen += devicelen; + } + + acpigen_patch_len(scopelen - 1); +} diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 3c0cda0..0867639 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -26,9 +26,18 @@ #include <pc80/keyboard.h> #include <stdlib.h> #include "pc87382.h" +#if IS_ENABLED(CONFIG_DRIVERS_LENOVO_WACOM) +#include "odm_oem/lenovo/lenovo.h" +#endif static void init(device_t dev) { +#if IS_ENABLED(CONFIG_DRIVERS_LENOVO_WACOM) + if (dev->path.type == DEVICE_PATH_PNP && + dev->path.pnp.device == 3) + dev->enabled = drivers_lenovo_is_wacom_present(); +#endif + if (!dev->enabled) return;

1 0

Patch set updated for coreboot: 96ff33c lenovo/t60: Enable Infrared port.
by Vladimir Serbinenko 15 Feb '14

15 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5243 -gerrit commit 96ff33c0f7203b1bca9555f7a40d42b8197a8572 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:17:10 2014 +0100 lenovo/t60: Enable Infrared port. Change-Id: I10f05334328c9929a99352185d286a7a17898801 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t60/acpi/superio.asl | 16 ++++++++++++++++ src/mainboard/lenovo/t60/devicetree.cb | 4 ++++ src/mainboard/lenovo/t60/romstage.c | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t60/acpi/superio.asl b/src/mainboard/lenovo/t60/acpi/superio.asl index e69de29..a0d8e0a 100644 --- a/src/mainboard/lenovo/t60/acpi/superio.asl +++ b/src/mainboard/lenovo/t60/acpi/superio.asl @@ -0,0 +1,16 @@ + Device (FIR) // Infrared + { + Name(_HID, EISAID("IBM0071")) + Name(_CID, EISAID("PNP0511")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08) + IRQNoFlags () {3} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index b87a223..cce5f93 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -148,6 +148,10 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + drq 0x74 = 0x1 + irq 0xf0 = 0x82 end device pnp 164e.3 off # Serial Port diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..237e967 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -79,7 +79,7 @@ static void ich7_enable_lpc(void) // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f); /* range 0x1600 - 0x167f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);

1 0

Patch set updated for coreboot: a809b83 lenovo/x60: Enable Infrared port.
by Vladimir Serbinenko 15 Feb '14

15 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5242 -gerrit commit a809b838cef73645c470ddf4fb3fd56d479aedc9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:13:00 2014 +0100 lenovo/x60: Enable Infrared port. Change-Id: I8ce0195bc85a983627826b31eb9879c3dbc80dd9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/acpi_tables.c | 2 +- src/mainboard/lenovo/x60/acpi_tables.c | 2 +- src/mainboard/lenovo/x60/devicetree.cb | 4 +++ src/mainboard/lenovo/x60/romstage.c | 2 +- src/odm_oem/lenovo/lenovo.h | 3 ++- src/odm_oem/lenovo/wacom.c | 44 ++++++++++++++++++++++++++++++++- 6 files changed, 52 insertions(+), 5 deletions(-) diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 981c52e..26c8f02 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -94,7 +94,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0, 0); return (unsigned long)(acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index d6ce4ba..c7c0a1a 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -87,7 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1, 1); return (unsigned long) (acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 5b4e37f..acd5af3 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -125,6 +125,10 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + drq 0x74 = 0x1 + irq 0xf0 = 0x82 end device pnp 164e.3 on # Digitizer diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..8eca464 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -86,7 +86,7 @@ static void ich7_enable_lpc(void) // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f); /* range 0x1600 - 0x167f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); diff --git a/src/odm_oem/lenovo/lenovo.h b/src/odm_oem/lenovo/lenovo.h index 25074bc..9abda4b 100644 --- a/src/odm_oem/lenovo/lenovo.h +++ b/src/odm_oem/lenovo/lenovo.h @@ -1,4 +1,5 @@ const char *lenovo_mainboard_partnumber(void); int drivers_lenovo_is_wacom_present(void); void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial); + int have_dock_serial, + int have_infrared); diff --git a/src/odm_oem/lenovo/wacom.c b/src/odm_oem/lenovo/wacom.c index d30ed45..a99e75c 100644 --- a/src/odm_oem/lenovo/wacom.c +++ b/src/odm_oem/lenovo/wacom.c @@ -89,7 +89,8 @@ drivers_lenovo_is_wacom_present(void) void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial) + int have_dock_serial, + int have_infrared) { int scopelen, devicelen, reslen, methodlen; @@ -131,6 +132,47 @@ drivers_lenovo_serial_ports_ssdt_generate(const char *scope, scopelen += devicelen; } + if (have_infrared) { + /* Device op. */ + scopelen += acpigen_emit_byte(0x5b); + scopelen += acpigen_emit_byte(0x82); + devicelen = acpigen_write_len_f(); + devicelen += acpigen_emit_namestring("FIR"); + + devicelen += acpigen_write_name("_HID"); + devicelen += acpigen_emit_eisaid("IBM0071"); + devicelen += acpigen_write_name("_CID"); + devicelen += acpigen_emit_eisaid("PNP0511"); + devicelen += acpigen_write_name("_UID"); + + /* One */ + methodlen += acpigen_write_byte(0x1); + devicelen += acpigen_write_name("_CRS"); + + reslen = acpigen_write_resourcetemplate_header(); + reslen += acpigen_write_io16(0x2f8, 0x2f8, 1, 8, 1); + reslen += acpigen_write_irq(0x80); + + devicelen += reslen; + devicelen += acpigen_write_resourcetemplate_footer(reslen); + + /* method op */ + devicelen += acpigen_emit_byte(0x14); + methodlen = acpigen_write_len_f(); + methodlen += acpigen_emit_namestring("_STA"); + /* no fnarg */ + methodlen += acpigen_emit_byte(0x00); + /* return */ + methodlen += acpigen_emit_byte(0xa4); + methodlen += acpigen_write_byte(0xf); + acpigen_patch_len(methodlen - 1); + + devicelen += methodlen; + + acpigen_patch_len(devicelen - 1); + scopelen += devicelen; + } + if (have_dock_serial) { /* Device op. */ scopelen += acpigen_emit_byte(0x5b);

1 0

New patch to review for coreboot: f473abe lenovo/x60: Fix EDID byte-swapping.
by Vladimir Serbinenko 15 Feb '14

15 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5249 -gerrit commit f473abeab2e88f380d6fd072b666bf52d43582cb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 23:42:43 2014 +0100 lenovo/x60: Fix EDID byte-swapping. Change-Id: I75305ff7c5a8ba6142ef460e813acc014d9992bb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x60/i915.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 3d4644f..4870fd8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -64,15 +64,15 @@ static unsigned int physbase; static u32 htotal, hblank, hsync, vtotal, vblank, vsync; -const u32 x60_edid_data[] = { - 0x00ffffff, 0xffffff00, 0x30ae0040, 0x00000000, - 0x000f0103, 0x80191278, 0xeaed7591, 0x574f8b26, - 0x21505421, 0x08000101, 0x01010101, 0x01010101, - 0x01010101, 0x01012815, 0x00404100, 0x26301888, - 0x3600f6b9, 0x00000018, 0xed100040, 0x41002630, - 0x18883600, 0xf6b90000, 0x00180000, 0x000f0061, - 0x43326143, 0x280f0100, 0x4ca3584a, 0x000000fe, - 0x004c544e, 0x31323158, 0x4a2d4c30, 0x370a0000, +const u8 x60_edid_data[] = { + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, + 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, + 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, + 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, + 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, + 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, }; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr)

1 0

Patch merged into coreboot/master: 497df49 console/uart8250*: Remove inclusion of mc146818rtc.h
by gerrit＠coreboot.org 15 Feb '14

15 Feb '14

the following patch was just integrated into master: commit 497df496adb6e0d3d3a7d357af4ebb0cd8bcbf70 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 18:27:56 2013 -0500 console/uart8250*: Remove inclusion of mc146818rtc.h The RTC functionality provided by the include is specific to x86, but is not used in these files. Change-Id: I82d0dfdb6e8b67bc81291a7a5d63ced91e095772 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4586 for details. -gerrit

1 0

Patch set updated for coreboot: c757e97 uart8250: Split register definitions
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5233 -gerrit commit c757e977efa6abaa9bd86c5fe7fb3e383b6421ae Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 06:59:51 2014 +0200 uart8250: Split register definitions Change-Id: Ideb7f55f329e1ae037debc156d3cb4a5b95bde22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart.c | 7 +-- src/drivers/uart/uart8250reg.h | 108 +++++++++++++++++++++++++++++++++++++++++ src/include/uart8250.h | 85 -------------------------------- src/lib/uart8250.c | 1 + src/lib/uart8250mem.c | 1 + 5 files changed, 111 insertions(+), 91 deletions(-) diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index dc98bff..c2c184e 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -7,12 +7,7 @@ #include "uart.h" #include <arch/io.h> - -/* Give me my 8250 UART definitions!!!! */ -/* TODO: Clean this up when uart8250mem works on ARM */ -#undef CONFIG_CONSOLE_SERIAL8250MEM -#define CONFIG_CONSOLE_SERIAL8250MEM 1 -#include <uart8250.h> +#include "drivers/uart/uart8250reg.h" /** * \brief Configure line control settings for UART diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h new file mode 100644 index 0000000..cdfbb1b --- /dev/null +++ b/src/drivers/uart/uart8250reg.h @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef UART8250REG_H +#define UART8250REG_H + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +#define UART_IIR 0x02 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +#define UART_FCR 0x02 +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define UART_LCR 0x03 +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity enable */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +#define UART_MCR 0x04 +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR 0x06 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +#define UART_SCR 0x07 +#define UART_SPR 0x07 + +#endif /* UART8250REG_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 598cdfa..a214ce1 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -22,91 +22,6 @@ #if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -#define UART_IIR 0x02 -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ - -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ - -#define UART_FCR 0x02 -#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ -#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ -#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ -#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ -#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ - -#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ -#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ - -#define UART_LCR 0x03 -#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ -#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ -#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ -#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ -#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ -#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define UART_LCR_PEN 0x08 /* Parity enable */ -#define UART_LCR_EPS 0x10 /* Even Parity Select */ -#define UART_LCR_STKP 0x20 /* Stick Parity */ -#define UART_LCR_SBRK 0x40 /* Set Break */ -#define UART_LCR_BKSE 0x80 /* Bank select enable */ -#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ - -#define UART_MCR 0x04 -#define UART_MCR_DTR 0x01 /* DTR */ -#define UART_MCR_RTS 0x02 /* RTS */ -#define UART_MCR_OUT1 0x04 /* Out 1 */ -#define UART_MCR_OUT2 0x08 /* Out 2 */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ - -#define UART_MCR_DMA_EN 0x04 -#define UART_MCR_TX_DFR 0x08 - -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_LSR_DR 0x01 /* Data ready */ -#define UART_LSR_OE 0x02 /* Overrun */ -#define UART_LSR_PE 0x04 /* Parity error */ -#define UART_LSR_FE 0x08 /* Framing error */ -#define UART_LSR_BI 0x10 /* Break */ -#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ -#define UART_LSR_TEMT 0x40 /* Xmitter empty */ -#define UART_LSR_ERR 0x80 /* Error */ - -#define UART_MSR 0x06 -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ - -#define UART_SCR 0x07 -#define UART_SPR 0x07 - #if ((115200 % CONFIG_TTYS0_BAUD) != 0) #error Bad ttyS0 baud rate #endif diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index bcb137a..4d2cb63 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <uart8250.h> #include <trace.h> +#include "drivers/uart/uart8250reg.h" /* Should support 8250, 16450, 16550, 16550A type UARTs */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 26c83fa..cff67d7 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -22,6 +22,7 @@ #include <uart8250.h> #include <device/device.h> #include <delay.h> +#include "drivers/uart/uart8250reg.h" /* Should support 8250, 16450, 16550, 16550A type UARTs */

1 0

Patch set updated for coreboot: 1fe4133 console: Fix includes
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5232 -gerrit commit 1fe4133be5d1578683c620bdf207d81bee3b2fe4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 06:11:01 2014 +0200 console: Fix includes Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 2 ++ src/arch/x86/lib/romcc_console.c | 1 + src/arch/x86/lib/romstage_console.c | 14 +++++--------- src/console/console.c | 6 ++++++ src/include/console/console.h | 16 ---------------- src/lib/cbmem.c | 1 + src/lib/cbmem_console.c | 1 + src/lib/coreboot_table.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + 9 files changed, 18 insertions(+), 25 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index b6339fc..93ea38d 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -18,6 +18,8 @@ */ #include <console/console.h> +#include <console/cbmem_console.h> +#include <console/uart.h> #include <console/vtxprintf.h> /* FIXME: need to make console driver more generic */ diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index e517428..0f0e017 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <console/loglevel.h> #include <console/post_codes.h> +#include <console/ne2k.h> /* __PRE_RAM__ */ /* Using a global varible can cause problems when we reset the stack diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4ef702f..4981f39 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -19,20 +19,16 @@ #include <smp/node.h> #include <console/console.h> +#include <console/cbmem_console.h> +#include <console/uart.h> +#include <console/usb.h> +#include <console/ne2k.h> +#include <console/spkmodem.h> #include <console/vtxprintf.h> #if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif -#if CONFIG_USBDEBUG -#include <console/usb.h> -#endif -#if CONFIG_CONSOLE_NE2K -#include <console/ne2k.h> -#endif -#if CONFIG_SPKMODEM -#include <console/spkmodem.h> -#endif void console_tx_byte(unsigned char byte) { diff --git a/src/console/console.c b/src/console/console.c index 081113c..334e140 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -18,6 +18,12 @@ */ #include <console/console.h> +#include <console/cbmem_console.h> +#include <console/uart.h> +#include <console/usb.h> +#include <console/ne2k.h> +#include <console/spkmodem.h> + #include <build.h> #include <arch/hlt.h> #include <arch/io.h> diff --git a/src/include/console/console.h b/src/include/console/console.h index 4df8cb6..a089729 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,22 +24,6 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#if CONFIG_CONSOLE_SERIAL -#include <console/uart.h> -#endif -#if CONFIG_USBDEBUG && !defined(__ROMCC__) -#include <console/usb.h> -#endif -#if CONFIG_CONSOLE_NE2K -#include <console/ne2k.h> -#endif -#if CONFIG_CONSOLE_CBMEM -#include <console/cbmem_console.h> -#endif -#if CONFIG_SPKMODEM -#include <console/spkmodem.h> -#endif - #ifndef __PRE_RAM__ unsigned char console_rx_byte(void); int console_tst_byte(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index d97f6af..3fea49a 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -23,6 +23,7 @@ #include <cbmem.h> #include <boot/coreboot_tables.h> #include <console/console.h> +#include <console/cbmem_console.h> #include <arch/early_variables.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 83d44e3..9d5419a 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <console/cbmem_console.h> #include <cbmem.h> #include <arch/early_variables.h> #include <string.h> diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..167eda0 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -21,6 +21,7 @@ */ #include <console/console.h> +#include <console/uart.h> #include <ip_checksum.h> #include <boot/coreboot_tables.h> #include <string.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b9c3839..bfb4033 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <console/usb.h> #include <string.h> #include <arch/hlt.h> #include <arch/io.h>

1 0

Patch set updated for coreboot: 54b40ee RFC: console: Make 8250 memmaped console independent of Oxford PCIe952
by Alexandru Gagniuc 15 Feb '14

15 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4587 -gerrit commit 54b40eedb527a4d591088290ea5a5ab7ca1ddcb5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 19:33:06 2013 -0500 RFC: console: Make 8250 memmaped console independent of Oxford PCIe952 RFC: Request for comments. DO NOT MERGE (YET) Running the console on an 8250-compatible memory-mapped UART was only possible via an Oxford PCIe952 adapter, as the console code explicitly depended on variables and functions defined by the Oxford driver. Change-Id: Icde4cdb2d671865502293183aed5664e8690a9ac Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 5 +-- src/console/console.c | 6 +-- src/drivers/oxford/oxpcie/Makefile.inc | 1 + src/drivers/oxford/oxpcie/oxpcie_early.c | 13 ++++-- src/drivers/oxford/oxpcie/oxpcie_memconsole.c | 62 +++++++++++++++++++++++++++ src/include/uart8250.h | 9 ++-- src/lib/uart8250mem.c | 53 +---------------------- 7 files changed, 81 insertions(+), 68 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 68b10eb..0ab0187 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -40,10 +40,7 @@ void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart8250_mem_tx_byte(uart8250_mem_get_baseaddr(), byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/console/console.c b/src/console/console.c index 38ac3e7..c0d3f2c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -106,11 +106,11 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_CONSOLE_SERIAL +#if CONFIG_CONSOLE_SERIAL && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif -#if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM - oxford_init(); +#if CONFIG_CONSOLE_SERIAL8250MEM + uart_mem_init(); #endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 6cc29c4..b967e02 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -2,4 +2,5 @@ ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c +ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_memconsole.c endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d04e9d4..ed6a7ff 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -38,7 +38,12 @@ #if defined(__PRE_RAM__) int oxford_oxpcie_present CAR_GLOBAL; -void oxford_init(void) +u32 uart8250_mem_get_baseaddr(void) +{ + return CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +} + +u32 uart_mem_init(void) { u16 reg16; oxford_oxpcie_present = 1; @@ -92,7 +97,7 @@ void oxford_init(void) */ id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; + return -1; device = OXPCIE_DEVICE_3; break; case 0xc1581415: /* e.g. Startech MPEX2S952 */ @@ -101,7 +106,7 @@ void oxford_init(void) default: /* No UART here. */ oxford_oxpcie_present = 0; - return; + return -1; } /* Setup base address on device */ @@ -117,6 +122,8 @@ void oxford_init(void) u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); + + return uart0_base; } #endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_memconsole.c b/src/drivers/oxford/oxpcie/oxpcie_memconsole.c new file mode 100644 index 0000000..d1d0ce4 --- /dev/null +++ b/src/drivers/oxford/oxpcie/oxpcie_memconsole.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Subject to the GNU GPL version 2. + */ + +#include <uart8250.h> +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#include "option_table.h" +#endif + +u32 uart_mem_init(void) +{ + unsigned uart_baud = CONFIG_TTYS0_BAUD; + u32 uart_bar = 0; + unsigned div; + + /* find out the correct baud rate */ +#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE + static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; + unsigned b_index = 0; +#if defined(__PRE_RAM__) && CONFIG_USE_OPTION_TABLE + b_index = read_option(baud_rate, 0); + b_index &= 7; + uart_baud = baud[b_index]; +#else + if (get_option(&b_index, "baud_rate") == CB_SUCCESS) + uart_baud = baud[b_index]; +#endif +#endif + + /* Now find the UART base address and calculate the divisor */ + +#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) + device_t dev = dev_find_device(0x1415, 0xc158, NULL); + if (!dev) + dev = dev_find_device(0x1415, 0xc11b, NULL); + + if (dev) { + struct resource *res = find_resource(dev, 0x10); + + if (res) { + uart_bar = res->base + 0x1000; // for 1st UART + // uart_bar = res->base + 0x2000; // for 2nd UART + } + } + + if (!uart_bar) +#endif + uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART + // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART + + div = 4000000 / uart_baud; + + if (uart_bar) + uart8250_mem_init(uart_bar, div); + + return uart_bar; +} diff --git a/src/include/uart8250.h b/src/include/uart8250.h index a3868c5..493e32a 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,6 +20,8 @@ #ifndef UART8250_H #define UART8250_H +#include <types.h> + /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -130,13 +132,8 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); void uart8250_mem_tx_flush(unsigned base_port); void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); +u32 uart8250_mem_get_baseaddr(void); -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; - -void oxford_init(void); -#endif #endif #endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..39dec37 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,8 +20,8 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> #if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> #include "option_table.h" #endif #include <device/device.h> @@ -102,54 +102,3 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) /* Set to 3 for 8N1 */ write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } - -u32 uart_mem_init(void) -{ - unsigned uart_baud = CONFIG_TTYS0_BAUD; - u32 uart_bar = 0; - unsigned div; - - /* find out the correct baud rate */ -#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE - static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; - unsigned b_index = 0; -#if defined(__PRE_RAM__) - b_index = read_option(baud_rate, 0); - b_index &= 7; - uart_baud = baud[b_index]; -#else - if (get_option(&b_index, "baud_rate") == CB_SUCCESS) - uart_baud = baud[b_index]; -#endif -#endif - - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE - -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); - - if (dev) { - struct resource *res = find_resource(dev, 0x10); - - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } - - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART - - div = 4000000 / uart_baud; -#endif - - if (uart_bar) - uart8250_mem_init(uart_bar, div); - - return uart_bar; -}

1 0

Patch set updated for coreboot: 497df49 console/uart8250*: Remove inclusion of mc146818rtc.h
by Alexandru Gagniuc 15 Feb '14

15 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4586 -gerrit commit 497df496adb6e0d3d3a7d357af4ebb0cd8bcbf70 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 18:27:56 2013 -0500 console/uart8250*: Remove inclusion of mc146818rtc.h The RTC functionality provided by the include is specific to x86, but is not used in these files. Change-Id: I82d0dfdb6e8b67bc81291a7a5d63ced91e095772 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/console/uart8250_console.c | 1 - src/console/uart8250mem_console.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 330ed68..196412c 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static void ttyS0_init(void) { diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..3833e47 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static u32 uart_bar = 0;

1 0

Patch set updated for coreboot: b8eefbe uart8250.h: Do not guard entire include file by config options
by Alexandru Gagniuc 15 Feb '14

15 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4585 -gerrit commit b8eefbecafad0d1f0a5efcc1d1b81d5716c90d73 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 18:13:58 2013 -0500 uart8250.h: Do not guard entire include file by config options Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or CONFIG_CONSOLE_SERIAL8250MEM. The config-specific options are already properly guarded, and there is no need to guard the register and bit definitions. Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/include/uart8250.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/include/uart8250.h b/src/include/uart8250.h index bec3637..a3868c5 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,8 +20,6 @@ #ifndef UART8250_H #define UART8250_H -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -141,6 +139,4 @@ void oxford_init(void); #endif #endif -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - #endif /* UART8250_H */

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2014