coreboot-gerrit December 2014

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New patch to review for coreboot: fe6153a vendorcode/amd/agesa/fam15: Build as a static library
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7698 -gerrit commit fe6153a63ef029a015d6384243e2341f2b982d81 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 06:55:38 2014 +1100 vendorcode/amd/agesa/fam15: Build as a static library Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I7798b689db3e582649eb4af4ccd1877bb1d49063 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f15/Makefile.inc | 898 +++++++++++++++--------------- 1 file changed, 455 insertions(+), 443 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index fd9ff59..d709199 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,10 +18,12 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + ## ABSOLUTE AGESA V5 ROOT PATH ## AGESA_ROOT ?= $(PWD) +AGESA_ROOT = src/vendorcode/amd/agesa/f15 -AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) +AGESA_INC = -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/../common AGESA_INC += -I$(AGESA_ROOT)/Include @@ -54,465 +57,474 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Main AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem +## AGESA need sse feature ## +CFLAGS_x86_32 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing + +export AGESA_ROOT := $(AGESA_ROOT) +export AGESA_INC := $(AGESA_INC) +CPPFLAGS_x86_32 += $(AGESA_INC) +####################################################################### + +classes-y += libagesa +$(eval $(call create_class_compiler,libagesa,x86_32)) -agesa_lib_src += ./Legacy/Proc/agesaCallouts.c -agesa_lib_src += ./Legacy/Proc/Dispatcher.c -agesa_lib_src += ./Legacy/Proc/hobTransfer.c -agesa_lib_src += ./Lib/amdlib.c -agesa_lib_src += ./Proc/Common/AmdInitEarly.c -agesa_lib_src += ./Proc/Common/AmdInitEnv.c -agesa_lib_src += ./Proc/Common/AmdInitLate.c -agesa_lib_src += ./Proc/Common/AmdInitMid.c -agesa_lib_src += ./Proc/Common/AmdInitPost.c -agesa_lib_src += ./Proc/Common/AmdInitReset.c -agesa_lib_src += ./Proc/Common/AmdInitResume.c -agesa_lib_src += ./Proc/Common/AmdLateRunApTask.c -agesa_lib_src += ./Proc/Common/AmdS3LateRestore.c -agesa_lib_src += ./Proc/Common/AmdS3Save.c -agesa_lib_src += ./Proc/Common/CommonInits.c -agesa_lib_src += ./Proc/Common/CommonReturns.c -agesa_lib_src += ./Proc/Common/CreateStruct.c -agesa_lib_src += ./Proc/Common/S3RestoreState.c -agesa_lib_src += ./Proc/Common/S3SaveState.c -agesa_lib_src += ./Proc/CPU/cahaltasm.S -agesa_lib_src += ./Proc/CPU/cahalt.c -agesa_lib_src += ./Proc/CPU/cpuApicUtilities.c -agesa_lib_src += ./Proc/CPU/cpuBist.c -agesa_lib_src += ./Proc/CPU/cpuBrandId.c -agesa_lib_src += ./Proc/CPU/cpuEarlyInit.c -agesa_lib_src += ./Proc/CPU/cpuEventLog.c -agesa_lib_src += ./Proc/CPU/cpuFamilyTranslation.c -agesa_lib_src += ./Proc/CPU/cpuGeneralServices.c -agesa_lib_src += ./Proc/CPU/cpuInitEarlyTable.c -agesa_lib_src += ./Proc/CPU/cpuLateInit.c -agesa_lib_src += ./Proc/CPU/cpuMicrocodePatch.c -agesa_lib_src += ./Proc/CPU/cpuPostInit.c -agesa_lib_src += ./Proc/CPU/cpuPowerMgmt.c -agesa_lib_src += ./Proc/CPU/cpuPowerMgmtMultiSocket.c -agesa_lib_src += ./Proc/CPU/cpuPowerMgmtSingleSocket.c -agesa_lib_src += ./Proc/CPU/cpuWarmReset.c -agesa_lib_src += ./Proc/CPU/heapManager.c -agesa_lib_src += ./Proc/CPU/S3.c -agesa_lib_src += ./Proc/CPU/Table.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuCommonF10Utilities.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10BrandId.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10BrandIdC32.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10BrandIdG34.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10CacheDefaults.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10Cpb.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10Dmi.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10EarlyInit.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10HtPhyTables.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10MsrTables.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10PciTables.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10PowerCheck.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10PowerPlane.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10Pstate.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10Utilities.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c -agesa_lib_src += ./Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c -agesa_lib_src += ./Proc/CPU/Family/0x10/F10InitEarlyTable.c -agesa_lib_src += ./Proc/CPU/Family/0x10/F10IoCstate.c -agesa_lib_src += ./Proc/CPU/Family/0x10/F10MultiLinkPciTables.c -agesa_lib_src += ./Proc/CPU/Family/0x10/F10PmAsymBoostInit.c -agesa_lib_src += ./Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c -agesa_lib_src += ./Proc/CPU/Family/0x10/F10PmNbCofVidInit.c -agesa_lib_src += ./Proc/CPU/Family/0x10/F10PmNbPstateInit.c -agesa_lib_src += ./Proc/CPU/Family/0x10/F10SingleLinkPciTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuCommonF15Utilities.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15Apm.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15BrandId.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15CacheDefaults.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15Dmi.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15MsrTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15PciTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15PowerCheck.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15Utilities.c -agesa_lib_src += ./Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/F15PstateHpcMode.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrC6State.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrCpb.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrIoCstate.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrL3Features.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrMsrTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrPciTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrUtilities.c -agesa_lib_src += ./Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c -agesa_lib_src += ./Proc/CPU/Feature/cpuApm.c -agesa_lib_src += ./Proc/CPU/Feature/cpuC6State.c -agesa_lib_src += ./Proc/CPU/Feature/cpuCacheFlushOnHalt.c -agesa_lib_src += ./Proc/CPU/Feature/cpuCacheInit.c -agesa_lib_src += ./Proc/CPU/Feature/cpuCoreLeveling.c -agesa_lib_src += ./Proc/CPU/Feature/cpuCpb.c -agesa_lib_src += ./Proc/CPU/Feature/cpuDmi.c -agesa_lib_src += ./Proc/CPU/Feature/cpuFeatureLeveling.c -agesa_lib_src += ./Proc/CPU/Feature/cpuFeatures.c -agesa_lib_src += ./Proc/CPU/Feature/cpuHwC1e.c -agesa_lib_src += ./Proc/CPU/Feature/cpuIoCstate.c -agesa_lib_src += ./Proc/CPU/Feature/cpuL3Features.c -agesa_lib_src += ./Proc/CPU/Feature/cpuLowPwrPstate.c -agesa_lib_src += ./Proc/CPU/Feature/cpuMsgBasedC1e.c -agesa_lib_src += ./Proc/CPU/Feature/cpuPstateGather.c -agesa_lib_src += ./Proc/CPU/Feature/cpuPstateHpcMode.c -agesa_lib_src += ./Proc/CPU/Feature/cpuPstateLeveling.c -agesa_lib_src += ./Proc/CPU/Feature/cpuPstateTables.c -agesa_lib_src += ./Proc/CPU/Feature/cpuSlit.c -agesa_lib_src += ./Proc/CPU/Feature/cpuSrat.c -agesa_lib_src += ./Proc/CPU/Feature/cpuSwC1e.c -agesa_lib_src += ./Proc/CPU/Feature/cpuWhea.c -agesa_lib_src += ./Proc/CPU/Feature/PreserveMailbox.c -agesa_lib_src += ./Proc/HT/htFeat.c -agesa_lib_src += ./Proc/HT/htInterface.c -agesa_lib_src += ./Proc/HT/htInterfaceCoherent.c -agesa_lib_src += ./Proc/HT/htInterfaceGeneral.c -agesa_lib_src += ./Proc/HT/htInterfaceNonCoherent.c -agesa_lib_src += ./Proc/HT/htMain.c -agesa_lib_src += ./Proc/HT/htNb.c -agesa_lib_src += ./Proc/HT/htNotify.c -agesa_lib_src += ./Proc/HT/Fam10/htNbCoherentFam10.c -agesa_lib_src += ./Proc/HT/Fam10/htNbFam10.c -agesa_lib_src += ./Proc/HT/Fam10/htNbNonCoherentFam10.c -agesa_lib_src += ./Proc/HT/Fam10/htNbOptimizationFam10.c -agesa_lib_src += ./Proc/HT/Fam10/htNbSystemFam10.c -agesa_lib_src += ./Proc/HT/Fam10/htNbUtilitiesFam10.c -agesa_lib_src += ./Proc/HT/Fam15/htNbCoherentFam15.c -agesa_lib_src += ./Proc/HT/Fam15/htNbFam15.c -agesa_lib_src += ./Proc/HT/Fam15/htNbNonCoherentFam15.c -agesa_lib_src += ./Proc/HT/Fam15/htNbOptimizationFam15.c -agesa_lib_src += ./Proc/HT/Fam15/htNbSystemFam15.c -agesa_lib_src += ./Proc/HT/Fam15/htNbUtilitiesFam15.c -agesa_lib_src += ./Proc/HT/Features/htFeatDynamicDiscovery.c -agesa_lib_src += ./Proc/HT/Features/htFeatGanging.c -agesa_lib_src += ./Proc/HT/Features/htFeatNoncoherent.c -agesa_lib_src += ./Proc/HT/Features/htFeatOptimization.c -agesa_lib_src += ./Proc/HT/Features/htFeatRouting.c -agesa_lib_src += ./Proc/HT/Features/htFeatSets.c -agesa_lib_src += ./Proc/HT/Features/htFeatSublinks.c -agesa_lib_src += ./Proc/HT/Features/htFeatTrafficDistribution.c -agesa_lib_src += ./Proc/HT/Features/htIds.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph1.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph2.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph3Line.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph3Triangle.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph4Degenerate.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph4FullyConnected.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph4Kite.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph4Line.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph4Square.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph4Star.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph5FullyConnected.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph5TwistedLadder.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph6DoubloonLower.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph6DoubloonUpper.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph6FullyConnected.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph6TwinTriangles.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph6TwistedLadder.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph7FullyConnected.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph7TwistedLadder.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph8DoubloonM.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph8FullyConnected.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph8Ladder.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph8TwinFullyFourWays.c -agesa_lib_src += ./Proc/HT/htGraph/htGraph8TwistedLadder.c -agesa_lib_src += ./Proc/HT/NbCommon/htNbCoherent.c -agesa_lib_src += ./Proc/HT/NbCommon/htNbNonCoherent.c -agesa_lib_src += ./Proc/HT/NbCommon/htNbOptimization.c -agesa_lib_src += ./Proc/HT/NbCommon/htNbUtilities.c -agesa_lib_src += ./Proc/Mem/Ardk/ma.c -agesa_lib_src += ./Proc/Mem/Ardk/C32/marc32_3.c -agesa_lib_src += ./Proc/Mem/Ardk/C32/mauc32_3.c -agesa_lib_src += ./Proc/Mem/Ardk/HY/marhy3.c -agesa_lib_src += ./Proc/Mem/Ardk/HY/mauhy3.c -agesa_lib_src += ./Proc/Mem/Ardk/OR/maror3.c -agesa_lib_src += ./Proc/Mem/Ardk/OR/mauor3.c -agesa_lib_src += ./Proc/Mem/Feat/CHINTLV/mfchi.c -agesa_lib_src += ./Proc/Mem/Feat/CSINTLV/mfcsi.c -agesa_lib_src += ./Proc/Mem/Feat/DMI/mfDMI.c -agesa_lib_src += ./Proc/Mem/Feat/ECC/mfecc.c -agesa_lib_src += ./Proc/Mem/Feat/ECC/mfemp.c -agesa_lib_src += ./Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c -agesa_lib_src += ./Proc/Mem/Feat/IDENDIMM/mfidendimm.c -agesa_lib_src += ./Proc/Mem/Feat/INTLVRN/mfintlvrn.c -agesa_lib_src += ./Proc/Mem/Feat/LVDDR3/mflvddr3.c -agesa_lib_src += ./Proc/Mem/Feat/MEMCLR/mfmemclr.c -agesa_lib_src += ./Proc/Mem/Feat/NDINTLV/mfndi.c -agesa_lib_src += ./Proc/Mem/Feat/ODTHERMAL/mfodthermal.c -agesa_lib_src += ./Proc/Mem/Feat/OLSPARE/mfspr.c -agesa_lib_src += ./Proc/Mem/Feat/PARTRN/mfParallelTraining.c -agesa_lib_src += ./Proc/Mem/Feat/PARTRN/mfStandardTraining.c -agesa_lib_src += ./Proc/Mem/Feat/S3/mfs3.c -agesa_lib_src += ./Proc/Mem/Feat/TABLE/mftds.c -agesa_lib_src += ./Proc/Mem/Main/mdef.c -agesa_lib_src += ./Proc/Mem/Main/merrhdl.c -agesa_lib_src += ./Proc/Mem/Main/minit.c -agesa_lib_src += ./Proc/Mem/Main/mm.c -agesa_lib_src += ./Proc/Mem/Main/mmConditionalPso.c -agesa_lib_src += ./Proc/Mem/Main/mmEcc.c -agesa_lib_src += ./Proc/Mem/Main/mmExcludeDimm.c -agesa_lib_src += ./Proc/Mem/Main/mmLvDdr3.c -agesa_lib_src += ./Proc/Mem/Main/mmMemClr.c -agesa_lib_src += ./Proc/Mem/Main/mmMemRestore.c -agesa_lib_src += ./Proc/Mem/Main/mmNodeInterleave.c -agesa_lib_src += ./Proc/Mem/Main/mmOnlineSpare.c -agesa_lib_src += ./Proc/Mem/Main/mmParallelTraining.c -agesa_lib_src += ./Proc/Mem/Main/mmStandardTraining.c -agesa_lib_src += ./Proc/Mem/Main/mmUmaAlloc.c -agesa_lib_src += ./Proc/Mem/Main/mu.c -agesa_lib_src += ./Proc/Mem/Main/muc.c -agesa_lib_src += ./Proc/Mem/NB/mn.c -agesa_lib_src += ./Proc/Mem/NB/mndct.c -agesa_lib_src += ./Proc/Mem/NB/mnfeat.c -agesa_lib_src += ./Proc/Mem/NB/mnflow.c -agesa_lib_src += ./Proc/Mem/NB/mnmct.c -agesa_lib_src += ./Proc/Mem/NB/mnphy.c -agesa_lib_src += ./Proc/Mem/NB/mnreg.c -agesa_lib_src += ./Proc/Mem/NB/mnS3.c -agesa_lib_src += ./Proc/Mem/NB/mntrain3.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mndctc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnflowc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnidendimmc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnmctc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnotc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnParTrainc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnphyc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnprotoc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnregc32.c -agesa_lib_src += ./Proc/Mem/NB/C32/mnS3c32.c -agesa_lib_src += ./Proc/Mem/NB/HY/mndcthy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnflowhy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnhy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnidendimmhy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnmcthy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnothy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnParTrainHy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnphyhy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnprotohy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnreghy.c -agesa_lib_src += ./Proc/Mem/NB/HY/mnS3hy.c -agesa_lib_src += ./Proc/Mem/NB/OR/mndctor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnflowor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnidendimmor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnmctor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnotor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnpartrainor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnphyor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnprotoor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mnregor.c -agesa_lib_src += ./Proc/Mem/NB/OR/mns3or.c -agesa_lib_src += ./Proc/Mem/Ps/mp.c -agesa_lib_src += ./Proc/Mem/Ps/mplribt.c -agesa_lib_src += ./Proc/Mem/Ps/mplrnlr.c -agesa_lib_src += ./Proc/Mem/Ps/mplrnpr.c -agesa_lib_src += ./Proc/Mem/Ps/mpmaxfreq.c -agesa_lib_src += ./Proc/Mem/Ps/mpmr0.c -agesa_lib_src += ./Proc/Mem/Ps/mpodtpat.c -agesa_lib_src += ./Proc/Mem/Ps/mprc10opspd.c -agesa_lib_src += ./Proc/Mem/Ps/mprc2ibt.c -agesa_lib_src += ./Proc/Mem/Ps/mprtt.c -agesa_lib_src += ./Proc/Mem/Ps/mps2d.c -agesa_lib_src += ./Proc/Mem/Ps/mpsao.c -agesa_lib_src += ./Proc/Mem/Ps/mpseeds.c -agesa_lib_src += ./Proc/Mem/Ps/C32/mprc32_3.c -agesa_lib_src += ./Proc/Mem/Ps/C32/mpuc32_3.c -agesa_lib_src += ./Proc/Mem/Ps/HY/mprhy3.c -agesa_lib_src += ./Proc/Mem/Ps/HY/mpshy3.c -agesa_lib_src += ./Proc/Mem/Ps/HY/mpuhy3.c -agesa_lib_src += ./Proc/Mem/Tech/mt.c -agesa_lib_src += ./Proc/Mem/Tech/mthdi.c -agesa_lib_src += ./Proc/Mem/Tech/mttdimbt.c -agesa_lib_src += ./Proc/Mem/Tech/mttecc.c -agesa_lib_src += ./Proc/Mem/Tech/mttEdgeDetect.c -agesa_lib_src += ./Proc/Mem/Tech/mtthrc.c -agesa_lib_src += ./Proc/Mem/Tech/mtthrcSeedTrain.c -agesa_lib_src += ./Proc/Mem/Tech/mttml.c -agesa_lib_src += ./Proc/Mem/Tech/mttoptsrc.c -agesa_lib_src += ./Proc/Mem/Tech/mttsrc.c -agesa_lib_src += ./Proc/Mem/Tech/DDR3/mt3.c -agesa_lib_src += ./Proc/Mem/Tech/DDR3/mtlrdimm3.c -agesa_lib_src += ./Proc/Mem/Tech/DDR3/mtot3.c -agesa_lib_src += ./Proc/Mem/Tech/DDR3/mtrci3.c -agesa_lib_src += ./Proc/Mem/Tech/DDR3/mtsdi3.c -agesa_lib_src += ./Proc/Mem/Tech/DDR3/mtspd3.c -agesa_lib_src += ./Proc/Mem/Tech/DDR3/mttecc3.c -agesa_lib_src += ./Proc/Mem/Tech/DDR3/mttwl3.c -agesa_lib_src += ./Proc/Recovery/HT/htInitRecovery.c -agesa_lib_src += ./Proc/Recovery/HT/htInitReset.c +libagesa-y += Legacy/Proc/agesaCallouts.c +libagesa-y += Legacy/Proc/Dispatcher.c +libagesa-y += Legacy/Proc/hobTransfer.c +libagesa-y += Lib/amdlib.c +libagesa-y += Proc/Common/AmdInitEarly.c +libagesa-y += Proc/Common/AmdInitEnv.c +libagesa-y += Proc/Common/AmdInitLate.c +libagesa-y += Proc/Common/AmdInitMid.c +libagesa-y += Proc/Common/AmdInitPost.c +libagesa-y += Proc/Common/AmdInitReset.c +libagesa-y += Proc/Common/AmdInitResume.c +libagesa-y += Proc/Common/AmdLateRunApTask.c +libagesa-y += Proc/Common/AmdS3LateRestore.c +libagesa-y += Proc/Common/AmdS3Save.c +libagesa-y += Proc/Common/CommonInits.c +libagesa-y += Proc/Common/CommonReturns.c +libagesa-y += Proc/Common/CreateStruct.c +libagesa-y += Proc/Common/S3RestoreState.c +libagesa-y += Proc/Common/S3SaveState.c +libagesa-y += Proc/CPU/cahaltasm.S +libagesa-y += Proc/CPU/cahalt.c +libagesa-y += Proc/CPU/cpuApicUtilities.c +libagesa-y += Proc/CPU/cpuBist.c +libagesa-y += Proc/CPU/cpuBrandId.c +libagesa-y += Proc/CPU/cpuEarlyInit.c +libagesa-y += Proc/CPU/cpuEventLog.c +libagesa-y += Proc/CPU/cpuFamilyTranslation.c +libagesa-y += Proc/CPU/cpuGeneralServices.c +libagesa-y += Proc/CPU/cpuInitEarlyTable.c +libagesa-y += Proc/CPU/cpuLateInit.c +libagesa-y += Proc/CPU/cpuMicrocodePatch.c +libagesa-y += Proc/CPU/cpuPostInit.c +libagesa-y += Proc/CPU/cpuPowerMgmt.c +libagesa-y += Proc/CPU/cpuPowerMgmtMultiSocket.c +libagesa-y += Proc/CPU/cpuPowerMgmtSingleSocket.c +libagesa-y += Proc/CPU/cpuWarmReset.c +libagesa-y += Proc/CPU/heapManager.c +libagesa-y += Proc/CPU/S3.c +libagesa-y += Proc/CPU/Table.c +libagesa-y += Proc/CPU/Family/0x10/cpuCommonF10Utilities.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandId.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdC32.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdG34.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10CacheDefaults.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10Cpb.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10Dmi.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10EarlyInit.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10HtPhyTables.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10MsrTables.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10PciTables.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10PowerCheck.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10PowerPlane.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10Pstate.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10Utilities.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +libagesa-y += Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c +libagesa-y += Proc/CPU/Family/0x10/F10InitEarlyTable.c +libagesa-y += Proc/CPU/Family/0x10/F10IoCstate.c +libagesa-y += Proc/CPU/Family/0x10/F10MultiLinkPciTables.c +libagesa-y += Proc/CPU/Family/0x10/F10PmAsymBoostInit.c +libagesa-y += Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c +libagesa-y += Proc/CPU/Family/0x10/F10PmNbCofVidInit.c +libagesa-y += Proc/CPU/Family/0x10/F10PmNbPstateInit.c +libagesa-y += Proc/CPU/Family/0x10/F10SingleLinkPciTables.c +libagesa-y += Proc/CPU/Family/0x15/cpuCommonF15Utilities.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15Apm.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15BrandId.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15CacheDefaults.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15Dmi.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15MsrTables.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15PciTables.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15PowerCheck.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15Utilities.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +libagesa-y += Proc/CPU/Family/0x15/F15PstateHpcMode.c +libagesa-y += Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c +libagesa-y += Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c +libagesa-y += Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c +libagesa-y += Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c +libagesa-y += Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c +libagesa-y += Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrC6State.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrCpb.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrIoCstate.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrL3Features.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrMsrTables.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrPciTables.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrUtilities.c +libagesa-y += Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c +libagesa-y += Proc/CPU/Feature/cpuApm.c +libagesa-y += Proc/CPU/Feature/cpuC6State.c +libagesa-y += Proc/CPU/Feature/cpuCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Feature/cpuCacheInit.c +libagesa-y += Proc/CPU/Feature/cpuCoreLeveling.c +libagesa-y += Proc/CPU/Feature/cpuCpb.c +libagesa-y += Proc/CPU/Feature/cpuDmi.c +libagesa-y += Proc/CPU/Feature/cpuFeatureLeveling.c +libagesa-y += Proc/CPU/Feature/cpuFeatures.c +libagesa-y += Proc/CPU/Feature/cpuHwC1e.c +libagesa-y += Proc/CPU/Feature/cpuIoCstate.c +libagesa-y += Proc/CPU/Feature/cpuL3Features.c +libagesa-y += Proc/CPU/Feature/cpuLowPwrPstate.c +libagesa-y += Proc/CPU/Feature/cpuMsgBasedC1e.c +libagesa-y += Proc/CPU/Feature/cpuPstateGather.c +libagesa-y += Proc/CPU/Feature/cpuPstateHpcMode.c +libagesa-y += Proc/CPU/Feature/cpuPstateLeveling.c +libagesa-y += Proc/CPU/Feature/cpuPstateTables.c +libagesa-y += Proc/CPU/Feature/cpuSlit.c +libagesa-y += Proc/CPU/Feature/cpuSrat.c +libagesa-y += Proc/CPU/Feature/cpuSwC1e.c +libagesa-y += Proc/CPU/Feature/cpuWhea.c +libagesa-y += Proc/CPU/Feature/PreserveMailbox.c +libagesa-y += Proc/HT/htFeat.c +libagesa-y += Proc/HT/htInterface.c +libagesa-y += Proc/HT/htInterfaceCoherent.c +libagesa-y += Proc/HT/htInterfaceGeneral.c +libagesa-y += Proc/HT/htInterfaceNonCoherent.c +libagesa-y += Proc/HT/htMain.c +libagesa-y += Proc/HT/htNb.c +libagesa-y += Proc/HT/htNotify.c +libagesa-y += Proc/HT/Fam10/htNbCoherentFam10.c +libagesa-y += Proc/HT/Fam10/htNbFam10.c +libagesa-y += Proc/HT/Fam10/htNbNonCoherentFam10.c +libagesa-y += Proc/HT/Fam10/htNbOptimizationFam10.c +libagesa-y += Proc/HT/Fam10/htNbSystemFam10.c +libagesa-y += Proc/HT/Fam10/htNbUtilitiesFam10.c +libagesa-y += Proc/HT/Fam15/htNbCoherentFam15.c +libagesa-y += Proc/HT/Fam15/htNbFam15.c +libagesa-y += Proc/HT/Fam15/htNbNonCoherentFam15.c +libagesa-y += Proc/HT/Fam15/htNbOptimizationFam15.c +libagesa-y += Proc/HT/Fam15/htNbSystemFam15.c +libagesa-y += Proc/HT/Fam15/htNbUtilitiesFam15.c +libagesa-y += Proc/HT/Features/htFeatDynamicDiscovery.c +libagesa-y += Proc/HT/Features/htFeatGanging.c +libagesa-y += Proc/HT/Features/htFeatNoncoherent.c +libagesa-y += Proc/HT/Features/htFeatOptimization.c +libagesa-y += Proc/HT/Features/htFeatRouting.c +libagesa-y += Proc/HT/Features/htFeatSets.c +libagesa-y += Proc/HT/Features/htFeatSublinks.c +libagesa-y += Proc/HT/Features/htFeatTrafficDistribution.c +libagesa-y += Proc/HT/Features/htIds.c +libagesa-y += Proc/HT/htGraph/htGraph.c +libagesa-y += Proc/HT/htGraph/htGraph1.c +libagesa-y += Proc/HT/htGraph/htGraph2.c +libagesa-y += Proc/HT/htGraph/htGraph3Line.c +libagesa-y += Proc/HT/htGraph/htGraph3Triangle.c +libagesa-y += Proc/HT/htGraph/htGraph4Degenerate.c +libagesa-y += Proc/HT/htGraph/htGraph4FullyConnected.c +libagesa-y += Proc/HT/htGraph/htGraph4Kite.c +libagesa-y += Proc/HT/htGraph/htGraph4Line.c +libagesa-y += Proc/HT/htGraph/htGraph4Square.c +libagesa-y += Proc/HT/htGraph/htGraph4Star.c +libagesa-y += Proc/HT/htGraph/htGraph5FullyConnected.c +libagesa-y += Proc/HT/htGraph/htGraph5TwistedLadder.c +libagesa-y += Proc/HT/htGraph/htGraph6DoubloonLower.c +libagesa-y += Proc/HT/htGraph/htGraph6DoubloonUpper.c +libagesa-y += Proc/HT/htGraph/htGraph6FullyConnected.c +libagesa-y += Proc/HT/htGraph/htGraph6TwinTriangles.c +libagesa-y += Proc/HT/htGraph/htGraph6TwistedLadder.c +libagesa-y += Proc/HT/htGraph/htGraph7FullyConnected.c +libagesa-y += Proc/HT/htGraph/htGraph7TwistedLadder.c +libagesa-y += Proc/HT/htGraph/htGraph8DoubloonM.c +libagesa-y += Proc/HT/htGraph/htGraph8FullyConnected.c +libagesa-y += Proc/HT/htGraph/htGraph8Ladder.c +libagesa-y += Proc/HT/htGraph/htGraph8TwinFullyFourWays.c +libagesa-y += Proc/HT/htGraph/htGraph8TwistedLadder.c +libagesa-y += Proc/HT/NbCommon/htNbCoherent.c +libagesa-y += Proc/HT/NbCommon/htNbNonCoherent.c +libagesa-y += Proc/HT/NbCommon/htNbOptimization.c +libagesa-y += Proc/HT/NbCommon/htNbUtilities.c +libagesa-y += Proc/Mem/Ardk/ma.c +libagesa-y += Proc/Mem/Ardk/C32/marc32_3.c +libagesa-y += Proc/Mem/Ardk/C32/mauc32_3.c +libagesa-y += Proc/Mem/Ardk/HY/marhy3.c +libagesa-y += Proc/Mem/Ardk/HY/mauhy3.c +libagesa-y += Proc/Mem/Ardk/OR/maror3.c +libagesa-y += Proc/Mem/Ardk/OR/mauor3.c +libagesa-y += Proc/Mem/Feat/CHINTLV/mfchi.c +libagesa-y += Proc/Mem/Feat/CSINTLV/mfcsi.c +libagesa-y += Proc/Mem/Feat/DMI/mfDMI.c +libagesa-y += Proc/Mem/Feat/ECC/mfecc.c +libagesa-y += Proc/Mem/Feat/ECC/mfemp.c +libagesa-y += Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +libagesa-y += Proc/Mem/Feat/IDENDIMM/mfidendimm.c +libagesa-y += Proc/Mem/Feat/INTLVRN/mfintlvrn.c +libagesa-y += Proc/Mem/Feat/LVDDR3/mflvddr3.c +libagesa-y += Proc/Mem/Feat/MEMCLR/mfmemclr.c +libagesa-y += Proc/Mem/Feat/NDINTLV/mfndi.c +libagesa-y += Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +libagesa-y += Proc/Mem/Feat/OLSPARE/mfspr.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfParallelTraining.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfStandardTraining.c +libagesa-y += Proc/Mem/Feat/S3/mfs3.c +libagesa-y += Proc/Mem/Feat/TABLE/mftds.c +libagesa-y += Proc/Mem/Main/mdef.c +libagesa-y += Proc/Mem/Main/merrhdl.c +libagesa-y += Proc/Mem/Main/minit.c +libagesa-y += Proc/Mem/Main/mm.c +libagesa-y += Proc/Mem/Main/mmConditionalPso.c +libagesa-y += Proc/Mem/Main/mmEcc.c +libagesa-y += Proc/Mem/Main/mmExcludeDimm.c +libagesa-y += Proc/Mem/Main/mmLvDdr3.c +libagesa-y += Proc/Mem/Main/mmMemClr.c +libagesa-y += Proc/Mem/Main/mmMemRestore.c +libagesa-y += Proc/Mem/Main/mmNodeInterleave.c +libagesa-y += Proc/Mem/Main/mmOnlineSpare.c +libagesa-y += Proc/Mem/Main/mmParallelTraining.c +libagesa-y += Proc/Mem/Main/mmStandardTraining.c +libagesa-y += Proc/Mem/Main/mmUmaAlloc.c +libagesa-y += Proc/Mem/Main/mu.c +libagesa-y += Proc/Mem/Main/muc.c +libagesa-y += Proc/Mem/NB/mn.c +libagesa-y += Proc/Mem/NB/mndct.c +libagesa-y += Proc/Mem/NB/mnfeat.c +libagesa-y += Proc/Mem/NB/mnflow.c +libagesa-y += Proc/Mem/NB/mnmct.c +libagesa-y += Proc/Mem/NB/mnphy.c +libagesa-y += Proc/Mem/NB/mnreg.c +libagesa-y += Proc/Mem/NB/mnS3.c +libagesa-y += Proc/Mem/NB/mntrain3.c +libagesa-y += Proc/Mem/NB/C32/mnc32.c +libagesa-y += Proc/Mem/NB/C32/mndctc32.c +libagesa-y += Proc/Mem/NB/C32/mnflowc32.c +libagesa-y += Proc/Mem/NB/C32/mnidendimmc32.c +libagesa-y += Proc/Mem/NB/C32/mnmctc32.c +libagesa-y += Proc/Mem/NB/C32/mnotc32.c +libagesa-y += Proc/Mem/NB/C32/mnParTrainc32.c +libagesa-y += Proc/Mem/NB/C32/mnphyc32.c +libagesa-y += Proc/Mem/NB/C32/mnprotoc32.c +libagesa-y += Proc/Mem/NB/C32/mnregc32.c +libagesa-y += Proc/Mem/NB/C32/mnS3c32.c +libagesa-y += Proc/Mem/NB/HY/mndcthy.c +libagesa-y += Proc/Mem/NB/HY/mnflowhy.c +libagesa-y += Proc/Mem/NB/HY/mnhy.c +libagesa-y += Proc/Mem/NB/HY/mnidendimmhy.c +libagesa-y += Proc/Mem/NB/HY/mnmcthy.c +libagesa-y += Proc/Mem/NB/HY/mnothy.c +libagesa-y += Proc/Mem/NB/HY/mnParTrainHy.c +libagesa-y += Proc/Mem/NB/HY/mnphyhy.c +libagesa-y += Proc/Mem/NB/HY/mnprotohy.c +libagesa-y += Proc/Mem/NB/HY/mnreghy.c +libagesa-y += Proc/Mem/NB/HY/mnS3hy.c +libagesa-y += Proc/Mem/NB/OR/mndctor.c +libagesa-y += Proc/Mem/NB/OR/mnflowor.c +libagesa-y += Proc/Mem/NB/OR/mnidendimmor.c +libagesa-y += Proc/Mem/NB/OR/mnmctor.c +libagesa-y += Proc/Mem/NB/OR/mnor.c +libagesa-y += Proc/Mem/NB/OR/mnotor.c +libagesa-y += Proc/Mem/NB/OR/mnpartrainor.c +libagesa-y += Proc/Mem/NB/OR/mnphyor.c +libagesa-y += Proc/Mem/NB/OR/mnprotoor.c +libagesa-y += Proc/Mem/NB/OR/mnregor.c +libagesa-y += Proc/Mem/NB/OR/mns3or.c +libagesa-y += Proc/Mem/Ps/mp.c +libagesa-y += Proc/Mem/Ps/mplribt.c +libagesa-y += Proc/Mem/Ps/mplrnlr.c +libagesa-y += Proc/Mem/Ps/mplrnpr.c +libagesa-y += Proc/Mem/Ps/mpmaxfreq.c +libagesa-y += Proc/Mem/Ps/mpmr0.c +libagesa-y += Proc/Mem/Ps/mpodtpat.c +libagesa-y += Proc/Mem/Ps/mprc10opspd.c +libagesa-y += Proc/Mem/Ps/mprc2ibt.c +libagesa-y += Proc/Mem/Ps/mprtt.c +libagesa-y += Proc/Mem/Ps/mps2d.c +libagesa-y += Proc/Mem/Ps/mpsao.c +libagesa-y += Proc/Mem/Ps/mpseeds.c +libagesa-y += Proc/Mem/Ps/C32/mprc32_3.c +libagesa-y += Proc/Mem/Ps/C32/mpuc32_3.c +libagesa-y += Proc/Mem/Ps/HY/mprhy3.c +libagesa-y += Proc/Mem/Ps/HY/mpshy3.c +libagesa-y += Proc/Mem/Ps/HY/mpuhy3.c +libagesa-y += Proc/Mem/Tech/mt.c +libagesa-y += Proc/Mem/Tech/mthdi.c +libagesa-y += Proc/Mem/Tech/mttdimbt.c +libagesa-y += Proc/Mem/Tech/mttecc.c +libagesa-y += Proc/Mem/Tech/mttEdgeDetect.c +libagesa-y += Proc/Mem/Tech/mtthrc.c +libagesa-y += Proc/Mem/Tech/mtthrcSeedTrain.c +libagesa-y += Proc/Mem/Tech/mttml.c +libagesa-y += Proc/Mem/Tech/mttoptsrc.c +libagesa-y += Proc/Mem/Tech/mttsrc.c +libagesa-y += Proc/Mem/Tech/DDR3/mt3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtlrdimm3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtot3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtrci3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtsdi3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtspd3.c +libagesa-y += Proc/Mem/Tech/DDR3/mttecc3.c +libagesa-y += Proc/Mem/Tech/DDR3/mttwl3.c +libagesa-y += Proc/Recovery/HT/htInitRecovery.c +libagesa-y += Proc/Recovery/HT/htInitReset.c + +libagesa-y += Proc/Mem/Main/mmflow.c +libagesa-y += Proc/Mem/Main/OR/mmflowor.c +libagesa-y += Proc/Mem/Ps/OR/mpor3.c -agesa_lib_src += ./Proc/Mem/Main/mmflow.c -agesa_lib_src += ./Proc/Mem/Main/OR/mmflowor.c -agesa_lib_src += ./Proc/Mem/Ps/OR/mpor3.c ifeq ($(CONFIG_CPU_AMD_SOCKET_C32), y) - agesa_lib_src += ./Proc/Mem/Main/C32/mmflowC32.c - agesa_lib_src += ./Proc/Mem/Ps/OR/C32/mpLorC3.c - agesa_lib_src += ./Proc/Mem/Ps/OR/C32/mpRorC3.c - agesa_lib_src += ./Proc/Mem/Ps/OR/C32/mpUorC3.c + libagesa-y += Proc/Mem/Main/C32/mmflowC32.c + libagesa-y += Proc/Mem/Ps/OR/C32/mpLorC3.c + libagesa-y += Proc/Mem/Ps/OR/C32/mpRorC3.c + libagesa-y += Proc/Mem/Ps/OR/C32/mpUorC3.c -# agesa_lib_src += ./Proc/Mem/Main/HY/mmflowhy.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c +# libagesa-y += Proc/Mem/Main/HY/mmflowhy.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c endif + ifeq ($(CONFIG_CPU_AMD_SOCKET_G34), y) - agesa_lib_src += ./Proc/Mem/Main/HY/mmflowhy.c - agesa_lib_src += ./Proc/Mem/Ps/OR/G34/mpLorG3.c - agesa_lib_src += ./Proc/Mem/Ps/OR/G34/mpRorG3.c - agesa_lib_src += ./Proc/Mem/Ps/OR/G34/mpUorG3.c + libagesa-y += Proc/Mem/Main/HY/mmflowhy.c + libagesa-y += Proc/Mem/Ps/OR/G34/mpLorG3.c + libagesa-y += Proc/Mem/Ps/OR/G34/mpRorG3.c + libagesa-y += Proc/Mem/Ps/OR/G34/mpUorG3.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c + libagesa-y += Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c + libagesa-y += Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c endif ifeq ($(CONFIG_CPU_AMD_SOCKET_AM3R2), y) - agesa_lib_src += ./Proc/Mem/Main/DA/mmflowda.c - agesa_lib_src += ./Proc/Mem/Main/RB/mmflowRb.c - agesa_lib_src += ./Proc/Mem/Main/PH/mmflowPh.c + libagesa-y += Proc/Mem/Main/DA/mmflowda.c + libagesa-y += Proc/Mem/Main/RB/mmflowRb.c + libagesa-y += Proc/Mem/Main/PH/mmflowPh.c - agesa_lib_src += ./Proc/Mem/Ps/OR/AM3/mpUorA3.c - agesa_lib_src += ./Proc/Mem/Ps/OR/AM3/mpSorA3.c + libagesa-y += Proc/Mem/Ps/OR/AM3/mpUorA3.c + libagesa-y += Proc/Mem/Ps/OR/AM3/mpSorA3.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c + libagesa-y += Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c + libagesa-y += Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c + libagesa-y += Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c + libagesa-y += Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c + libagesa-y += Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c + libagesa-y += Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c + libagesa-y += Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c + libagesa-y += Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c - agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c + libagesa-y += Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c + libagesa-y += Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c + libagesa-y += Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c + libagesa-y += Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c + libagesa-y += Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c + libagesa-y += Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c + libagesa-y += Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c + libagesa-y += Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c + libagesa-y += Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnidendimmda.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnregda.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnS3da.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnprotoda.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnda.c - agesa_lib_src += ./Proc/Mem/NB/DA/mndctda.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnmctda.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnflowda.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnParTrainDa.c - agesa_lib_src += ./Proc/Mem/NB/DA/mnotda.c - agesa_lib_src += ./Proc/Mem/NB/PH/mnS3Ph.c - agesa_lib_src += ./Proc/Mem/NB/PH/mnflowPh.c - agesa_lib_src += ./Proc/Mem/NB/PH/mnidendimmPh.c - agesa_lib_src += ./Proc/Mem/NB/PH/mnmctPh.c - agesa_lib_src += ./Proc/Mem/NB/PH/mnPh.c - agesa_lib_src += ./Proc/Mem/NB/PH/mnmctPh.c - agesa_lib_src += ./Proc/Mem/NB/PH/mnflowPh.c - agesa_lib_src += ./Proc/Mem/NB/PH/mnidendimmPh.c - agesa_lib_src += ./Proc/Mem/NB/RB/mnidendimmRb.c - agesa_lib_src += ./Proc/Mem/NB/RB/mnRb.c - agesa_lib_src += ./Proc/Mem/NB/RB/mnflowRb.c - agesa_lib_src += ./Proc/Mem/NB/RB/mnS3Rb.c + libagesa-y += Proc/Mem/NB/DA/mnidendimmda.c + libagesa-y += Proc/Mem/NB/DA/mnregda.c + libagesa-y += Proc/Mem/NB/DA/mnS3da.c + libagesa-y += Proc/Mem/NB/DA/mnprotoda.c + libagesa-y += Proc/Mem/NB/DA/mnda.c + libagesa-y += Proc/Mem/NB/DA/mndctda.c + libagesa-y += Proc/Mem/NB/DA/mnmctda.c + libagesa-y += Proc/Mem/NB/DA/mnflowda.c + libagesa-y += Proc/Mem/NB/DA/mnParTrainDa.c + libagesa-y += Proc/Mem/NB/DA/mnotda.c + libagesa-y += Proc/Mem/NB/PH/mnS3Ph.c + libagesa-y += Proc/Mem/NB/PH/mnflowPh.c + libagesa-y += Proc/Mem/NB/PH/mnidendimmPh.c + libagesa-y += Proc/Mem/NB/PH/mnmctPh.c + libagesa-y += Proc/Mem/NB/PH/mnPh.c + libagesa-y += Proc/Mem/NB/PH/mnmctPh.c + libagesa-y += Proc/Mem/NB/PH/mnflowPh.c + libagesa-y += Proc/Mem/NB/PH/mnidendimmPh.c + libagesa-y += Proc/Mem/NB/RB/mnidendimmRb.c + libagesa-y += Proc/Mem/NB/RB/mnRb.c + libagesa-y += Proc/Mem/NB/RB/mnflowRb.c + libagesa-y += Proc/Mem/NB/RB/mnS3Rb.c - agesa_lib_src += ./Proc/Mem/Ardk/DA/masda2.c - agesa_lib_src += ./Proc/Mem/Ardk/DA/masda3.c - agesa_lib_src += ./Proc/Mem/Ardk/DA/mauda3.c - agesa_lib_src += ./Proc/Mem/Ardk/PH/mauPh3.c - agesa_lib_src += ./Proc/Mem/Ardk/PH/masph3.c - agesa_lib_src += ./Proc/Mem/Ardk/RB/mauRb3.c - agesa_lib_src += ./Proc/Mem/Ardk/RB/masRb3.c + libagesa-y += Proc/Mem/Ardk/DA/masda2.c + libagesa-y += Proc/Mem/Ardk/DA/masda3.c + libagesa-y += Proc/Mem/Ardk/DA/mauda3.c + libagesa-y += Proc/Mem/Ardk/PH/mauPh3.c + libagesa-y += Proc/Mem/Ardk/PH/masph3.c + libagesa-y += Proc/Mem/Ardk/RB/mauRb3.c + libagesa-y += Proc/Mem/Ardk/RB/masRb3.c - agesa_lib_src += ./Proc/Mem/Ps/DA/mpuda3.c - agesa_lib_src += ./Proc/Mem/Ps/DA/mpsda3.c - agesa_lib_src += ./Proc/Mem/Ps/DA/mpsda2.c - agesa_lib_src += ./Proc/Mem/Ps/PH/mpuph3.c - agesa_lib_src += ./Proc/Mem/Ps/PH/mpsph3.c - agesa_lib_src += ./Proc/Mem/Ps/RB/mpuRb3.c - agesa_lib_src += ./Proc/Mem/Ps/RB/mpsRb3.c + libagesa-y += Proc/Mem/Ps/DA/mpuda3.c + libagesa-y += Proc/Mem/Ps/DA/mpsda3.c + libagesa-y += Proc/Mem/Ps/DA/mpsda2.c + libagesa-y += Proc/Mem/Ps/PH/mpuph3.c + libagesa-y += Proc/Mem/Ps/PH/mpsph3.c + libagesa-y += Proc/Mem/Ps/RB/mpuRb3.c + libagesa-y += Proc/Mem/Ps/RB/mpsRb3.c endif -romstage-y += $(agesa_lib_src) -ramstage-y += $(agesa_lib_src) - -## AGESA need sse feature ## -CFLAGS_x86_32 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +$(obj)/libagesa.fam15.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + ar rcs $@ $+ -export AGESA_ROOT -export AGESA_INC -CPPFLAGS_x86_32 += $(AGESA_INC) +romstage-libs += $(obj)/libagesa.fam15.a +ramstage-libs += $(obj)/libagesa.fam15.a

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New patch to review for coreboot: 9aaa108 southbridge/intel/fsp_rangeley: Fix missing entry-point prototype
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7697 -gerrit commit 9aaa10850750bc43a42ace601bbf82a8fb64fd44 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 05:45:05 2014 +1100 southbridge/intel/fsp_rangeley: Fix missing entry-point prototype In '-ffreestanding' main() is just as any other function and so it needs a type-signature. Fixes a clang warning. Change-Id: I59eff28d77bd2a7f0c598c5846240344b7cec4d4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/intel/fsp_rangeley/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fd8b3b2..2174a60 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -39,6 +39,7 @@ #include <cpu/x86/msr.h> #include "gpio.h" +void main(FSP_INFO_HEADER *fsp_info_header); // XXX: find a better place void main(FSP_INFO_HEADER *fsp_info_header) { uint32_t fd_mask = 0;

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Patch set updated for coreboot: bd2defa TEST clang warn as error
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7672 -gerrit commit bd2defad7a4924c31e0315fd1cfc6b4c3c7f0cde Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Dec 7 02:46:07 2014 +1100 TEST clang warn as error Change-Id: Iac4efa59f63437fd6c7678368f4c62ba005d2103 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- src/Kconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eaba3e4..e0246ff 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -Wno-unused-variable -Wno-unused-function -Wno-tautological-compare CC_x86_32:=clang HOSTCC := clang diff --git a/src/Kconfig b/src/Kconfig index 533bc5c..7f033a2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1131,8 +1131,7 @@ config ENABLE_APIC_EXT_ID # the whole treee. config WARNINGS_ARE_ERRORS bool - default y if !COMPILER_LLVM_CLANG - default n if COMPILER_LLVM_CLANG + default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

1 0

New patch to review for coreboot: fd924fb southbridge/dmp/vortex86ex/southbridge.c: Silence bitwise op warns
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7696 -gerrit commit fd924fbce3beddb76a3ec36858e3656392a4d845 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 04:41:39 2014 +1100 southbridge/dmp/vortex86ex/southbridge.c: Silence bitwise op warns Silence some useless Clang warns in this case. Change-Id: I202a85f7dec52c65d80e2bc56f7d9e4eb3e61d48 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/dmp/vortex86ex/southbridge.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..2fe1bc2 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -227,11 +227,11 @@ static void pci_routing_fixup(struct device *dev) unsigned char irqs[4] = { MAC_IRQ, 0, 0, 0 }; pci_assign_irqs(0, 0x8, irqs); } - if (OHCII_IRQ && EHCII_IRQ) { + if ((OHCII_IRQ != 0) && (EHCII_IRQ != 0)) { unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 }; pci_assign_irqs(0, 0xa, irqs); } - if (CONFIG_IDE_NATIVE_MODE && PIDE_IRQ) { + if ((CONFIG_IDE_NATIVE_MODE != 0) && (PIDE_IRQ != 0)) { /* IDE in native mode, setup PCI IRQ. */ unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 }; pci_assign_irqs(0, 0xc, irqs); @@ -572,7 +572,7 @@ static void southbridge_init_func1(struct device *dev) pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2); /* Assign in-chip PCI device IRQs. */ - if (SPI1_IRQ || MOTOR_IRQ) { + if ((SPI1_IRQ != 0) || (MOTOR_IRQ != 0)) { unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 }; pci_assign_irqs(0, 0x10, irqs); }

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Patch set updated for coreboot: f70b126 TEST clang warn as error
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7672 -gerrit commit f70b1266395d45927ce03ef770a9e6ec627f3e7c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Dec 7 02:46:07 2014 +1100 TEST clang warn as error Change-Id: Iac4efa59f63437fd6c7678368f4c62ba005d2103 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- src/Kconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eaba3e4..e0246ff 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -Wno-unused-variable -Wno-unused-function -Wno-tautological-compare CC_x86_32:=clang HOSTCC := clang diff --git a/src/Kconfig b/src/Kconfig index 533bc5c..7f033a2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1131,8 +1131,7 @@ config ENABLE_APIC_EXT_ID # the whole treee. config WARNINGS_ARE_ERRORS bool - default y if !COMPILER_LLVM_CLANG - default n if COMPILER_LLVM_CLANG + default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

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New patch to review for coreboot: 4feb213 include/cpu/amd/{gx2, lx}def.h: Treat magic const as 'ull' type
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7695 -gerrit commit 4feb2132433fc239c5dba0fa8b346de57cc37da7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 04:34:08 2014 +1100 include/cpu/amd/{gx2,lx}def.h: Treat magic const as 'ull' type Avoids clang warn. Change-Id: Icc4a3b62095a57ae77bb9f90369279608019e6aa Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/cpu/amd/gx2def.h | 2 +- src/include/cpu/amd/lxdef.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index beb4c65..587cce1 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -483,7 +483,7 @@ #define GLIU1_IOD_SC_5 (MSR_GLIU1 + 0xE8) /* definitions that are "once you are mostly up, start VSA" type things */ -#define SMM_OFFSET 0x40400000 +#define SMM_OFFSET 0x40400000ull #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ #define DMM_OFFSET 0x0C0000000 #define DMM_SIZE 128 diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index da26895..821dae8 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -620,7 +620,7 @@ /* ------------------------ */ -#define SMM_OFFSET 0x80400000 /* above 2GB */ +#define SMM_OFFSET 0x80400000ull /* above 2GB */ #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ /* DRAM_TERMINATED affects how the DELAY register is set. */

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Patch set updated for coreboot: 9b63ff8 TEST clang warn as error
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7672 -gerrit commit 9b63ff81c89ad77d88084dc3b3d1df4d131ae904 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Dec 7 02:46:07 2014 +1100 TEST clang warn as error Change-Id: Iac4efa59f63437fd6c7678368f4c62ba005d2103 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- src/Kconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eaba3e4..e0246ff 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -Wno-unused-variable -Wno-unused-function -Wno-tautological-compare CC_x86_32:=clang HOSTCC := clang diff --git a/src/Kconfig b/src/Kconfig index 533bc5c..7f033a2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1131,8 +1131,7 @@ config ENABLE_APIC_EXT_ID # the whole treee. config WARNINGS_ARE_ERRORS bool - default y if !COMPILER_LLVM_CLANG - default n if COMPILER_LLVM_CLANG + default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

1 0

New patch to review for coreboot: 5ee717f drivers/intel/fsp/fsp_util.c: Probably breaks things
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7694 -gerrit commit 5ee717f4b272717413f962541145ea3790d414f0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 03:47:20 2014 +1100 drivers/intel/fsp/fsp_util.c: Probably breaks things NOTFORMERGE: test clang to zero warn day?? Change-Id: I06e71876c3a3a15101013623797c2ebbf449756d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/intel/fsp/fsp_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index e15c82e..3e3f727 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -103,7 +103,7 @@ void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr) } #endif /* __PRE_RAM__ */ -volatile u8 * __attribute__((optimize("O0"))) find_fsp () +volatile u8 * find_fsp () { #ifdef __PRE_RAM__

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Patch set updated for coreboot: c665023 TEST clang warn as error
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7672 -gerrit commit c665023bcf63033940b4c26e76be6e090da61de5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Dec 7 02:46:07 2014 +1100 TEST clang warn as error Change-Id: Iac4efa59f63437fd6c7678368f4c62ba005d2103 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- src/Kconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eaba3e4..5a7e687 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -Wno-unused-variable -Wno-unused-function CC_x86_32:=clang HOSTCC := clang diff --git a/src/Kconfig b/src/Kconfig index 533bc5c..7f033a2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1131,8 +1131,7 @@ config ENABLE_APIC_EXT_ID # the whole treee. config WARNINGS_ARE_ERRORS bool - default y if !COMPILER_LLVM_CLANG - default n if COMPILER_LLVM_CLANG + default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

1 0

New patch to review for coreboot: c6fe522 mainboard/{iwill, amd/serenget_*}: Cast ptr as we discard const qualifier
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7693 -gerrit commit c6fe52220b6fb0df04d0f61df7b32d50edd228c1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 03:43:44 2014 +1100 mainboard/{iwill,amd/serenget_*}: Cast ptr as we discard const qualifier This silences a useless Clang warn in this case. Change-Id: I22e55eb2b7fe06c416e5e4fd322045bc7031ed63 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 6 +++--- src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c | 8 ++++---- src/mainboard/iwill/dk8_htx/acpi_tables.c | 8 ++++---- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 65b8fc5..e171db5 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -154,13 +154,13 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: //8132 - p = &AmlCode_ssdt2; + p = (void *) &AmlCode_ssdt2; break; case 2: //8151 - p = &AmlCode_ssdt3; + p = (void *) &AmlCode_ssdt3; break; case 3: //8131 - p = &AmlCode_ssdt4; + p = (void *) &AmlCode_ssdt4; break; default: continue; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index ea3ec6c..5a1b0d1 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -162,17 +162,17 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: - p = &AmlCode_ssdt2; + p = (void *) &AmlCode_ssdt2; break; case 2: - p = &AmlCode_ssdt3; + p = (void *) &AmlCode_ssdt3; break; case 3: //8131 - p = &AmlCode_ssdt4; + p = (void *) &AmlCode_ssdt4; break; default: //HTX no io apic - p = &AmlCode_ssdt5; + p = (void *) &AmlCode_ssdt5; } memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index 53e79b0..85d9862 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -159,17 +159,17 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: //8132 - p = &AmlCode_ssdt2; + p = (void *) &AmlCode_ssdt2; break; case 2: //8151 - p = &AmlCode_ssdt3; + p = (void *) &AmlCode_ssdt3; break; case 3: //8131 - p = &AmlCode_ssdt4; + p = (void *) &AmlCode_ssdt4; break; default: //HTX no io apic - p = &AmlCode_ssdt5; + p = (void *) &AmlCode_ssdt5; break; } memcpy(ssdtx, p, sizeof(acpi_header_t));

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coreboot-gerrit December 2014