coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: dd6f4f0 TEST clang warn as error
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7672 -gerrit commit dd6f4f0d002889056358f423afe072e557f48bee Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Dec 7 02:46:07 2014 +1100 TEST clang warn as error Change-Id: Iac4efa59f63437fd6c7678368f4c62ba005d2103 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- src/Kconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eaba3e4..5a7e687 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -Wno-unused-variable -Wno-unused-function CC_x86_32:=clang HOSTCC := clang diff --git a/src/Kconfig b/src/Kconfig index 533bc5c..7f033a2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1131,8 +1131,7 @@ config ENABLE_APIC_EXT_ID # the whole treee. config WARNINGS_ARE_ERRORS bool - default y if !COMPILER_LLVM_CLANG - default n if COMPILER_LLVM_CLANG + default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

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Patch merged into coreboot/master: dc3d5ed ga-b75m-d3h: Remove duplicate sata_port_map
by gerrit＠coreboot.org 07 Dec '14

07 Dec '14

the following patch was just integrated into master: commit dc3d5ed3cb12fcae4ed5746d21b3f87169eb0416 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Dec 7 16:48:47 2014 +0100 ga-b75m-d3h: Remove duplicate sata_port_map Change-Id: I128f1dfea013a4f94c5b006a90c10aa32563d81c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7691 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7691 for details. -gerrit

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Patch set updated for coreboot: 02d002d TEST clang warn as error
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7672 -gerrit commit 02d002d6f6bd1a508208f964ca496bff7922e87b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Dec 7 02:46:07 2014 +1100 TEST clang warn as error Change-Id: Iac4efa59f63437fd6c7678368f4c62ba005d2103 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- src/Kconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eaba3e4..5a7e687 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -Wno-unused-variable -Wno-unused-function CC_x86_32:=clang HOSTCC := clang diff --git a/src/Kconfig b/src/Kconfig index 533bc5c..7f033a2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1131,8 +1131,7 @@ config ENABLE_APIC_EXT_ID # the whole treee. config WARNINGS_ARE_ERRORS bool - default y if !COMPILER_LLVM_CLANG - default n if COMPILER_LLVM_CLANG + default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

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Patch set updated for coreboot: 421e65e southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7692 -gerrit commit 421e65e66fee369aefdeb7c59fc431dd4b7a8077 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 03:00:26 2014 +1100 southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. Be sure to write back out the data on the retrain. Change-Id: I95d1799514157b7849f3e473837aaf2fd9bd59b9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/sr5650/sr5650.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 7fdecf1..2a2d558 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -238,13 +238,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); + tmp = (reg >> 4) & 0x7; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8; + nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); count++; /* CIM said "keep in loop"? */ } else { res = 1;

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New patch to review for coreboot: 06bae68 southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7692 -gerrit commit 06bae6883bc4993c62c1e656cd8705c104af2d82 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 03:00:26 2014 +1100 southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. Be sure to write back out the data on the retrain. Change-Id: I95d1799514157b7849f3e473837aaf2fd9bd59b9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/sr5650/sr5650.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 7fdecf1..2a2d558 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -238,13 +238,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); + tmp = (reg >> 4) & 0x7; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8; + nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); count++; /* CIM said "keep in loop"? */ } else { res = 1;

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New patch to review for coreboot: 521bc06 ga-b75m-d3h: Remove duplicate sata_port_map
by Vladimir Serbinenko 07 Dec '14

07 Dec '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7691 -gerrit commit 521bc06de724516c5cd67c0436bf82f1fc9effe3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Dec 7 16:48:47 2014 +0100 ga-b75m-d3h: Remove duplicate sata_port_map Change-Id: I128f1dfea013a4f94c5b006a90c10aa32563d81c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 20f88cb..3c7641a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "0" register "p_cnt_throttling_supported" = "0" register "docking_supported" = "0" - register "sata_port_map" = "0x3f" register "c2_latency" = "0x0065" device pci 14.0 on # USB 3.0 Controller

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New patch to review for coreboot: e27c166 mainboard/google/samus: Fix usage of GNU field designator ext
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7690 -gerrit commit e27c1668436d9107ce4adde37c466471b97c3604 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 02:28:39 2014 +1100 mainboard/google/samus: Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Id3b16872f62660393d938d6f95977a4e3842d0d1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/samus/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index abd93c4..bdf0e70 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -146,7 +146,7 @@ void mainboard_romstage_entry(unsigned long bist) { 0x0040, 1, USB_OC_PIN_SKIP, /* P7: BT */ USB_PORT_INTERNAL }, }, - usb3_ports: { + .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, /* P1: HOST PORT */ { 1, 1 }, /* P2: HOST PORT */

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Patch set updated for coreboot: 5a83249 TEST clang warn as error
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7672 -gerrit commit 5a832499bf9d574143288fcf6f88add6a0e16df9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Dec 7 02:46:07 2014 +1100 TEST clang warn as error Change-Id: Iac4efa59f63437fd6c7678368f4c62ba005d2103 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- src/Kconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eaba3e4..5a7e687 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -Wno-unused-variable -Wno-unused-function CC_x86_32:=clang HOSTCC := clang diff --git a/src/Kconfig b/src/Kconfig index 533bc5c..7f033a2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1131,8 +1131,7 @@ config ENABLE_APIC_EXT_ID # the whole treee. config WARNINGS_ARE_ERRORS bool - default y if !COMPILER_LLVM_CLANG - default n if COMPILER_LLVM_CLANG + default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

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New patch to review for coreboot: 5b0a078 vendorcode/amd/pi/00730F01/Lib/amdlib.c: Remove optimize attribute
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7689 -gerrit commit 5b0a0789f0059b0ee2c0b4187ac4073eb67f6cd7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Dec 8 02:17:12 2014 +1100 vendorcode/amd/pi/00730F01/Lib/amdlib.c: Remove optimize attribute Remove '__attribute__((optimize("Os")))' as it is unlikely to be necessary as it is not used in other families that have the same code and only hides deeper issues. Change-Id: Ica890812ebc2fb659b9c3e46b40cf3f6534b3cf2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/pi/00730F01/Lib/amdlib.c | 31 ----------------------------- 1 file changed, 31 deletions(-) diff --git a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c index f2e6b91..fa4fa0b 100644 --- a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c +++ b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c @@ -89,7 +89,6 @@ ReadNumberOfCpuCores( void ); -__attribute__((optimize("Os"))) UINT8 ReadIo8 ( IN UINT16 Address @@ -98,7 +97,6 @@ ReadIo8 ( return __inbyte (Address); } -__attribute__((optimize("Os"))) UINT16 ReadIo16 ( IN UINT16 Address @@ -107,7 +105,6 @@ ReadIo16 ( return __inword (Address); } -__attribute__((optimize("Os"))) UINT32 ReadIo32 ( IN UINT16 Address @@ -116,7 +113,6 @@ ReadIo32 ( return __indword (Address); } -__attribute__((optimize("Os"))) VOID WriteIo8 ( IN UINT16 Address, @@ -126,7 +122,6 @@ WriteIo8 ( __outbyte (Address, Data); } -__attribute__((optimize("Os"))) VOID WriteIo16 ( IN UINT16 Address, @@ -136,7 +131,6 @@ WriteIo16 ( __outword (Address, Data); } -__attribute__((optimize("Os"))) VOID WriteIo32 ( IN UINT16 Address, @@ -146,7 +140,6 @@ WriteIo32 ( __outdword (Address, Data); } -__attribute__((optimize("Os"))) STATIC UINT64 SetFsBase ( UINT64 address @@ -159,7 +152,6 @@ UINT64 SetFsBase ( return hwcr; } -__attribute__((optimize("Os"))) STATIC VOID RestoreHwcr ( @@ -170,7 +162,6 @@ RestoreHwcr ( __writemsr (0xC0010015, value); } -__attribute__((optimize("Os"))) UINT8 Read64Mem8 ( IN UINT64 Address @@ -187,7 +178,6 @@ Read64Mem8 ( return dataRead; } -__attribute__((optimize("Os"))) UINT16 Read64Mem16 ( IN UINT64 Address @@ -204,7 +194,6 @@ Read64Mem16 ( return dataRead; } -__attribute__((optimize("Os"))) UINT32 Read64Mem32 ( IN UINT64 Address @@ -221,7 +210,6 @@ Read64Mem32 ( return dataRead; } -__attribute__((optimize("Os"))) VOID Write64Mem8 ( IN UINT64 Address, @@ -239,7 +227,6 @@ Write64Mem8 ( } } -__attribute__((optimize("Os"))) VOID Write64Mem16 ( IN UINT64 Address, @@ -257,7 +244,6 @@ Write64Mem16 ( } } -__attribute__((optimize("Os"))) VOID Write64Mem32 ( IN UINT64 Address, @@ -275,7 +261,6 @@ Write64Mem32 ( } } -__attribute__((optimize("Os"))) VOID LibAmdReadCpuReg ( IN UINT8 RegNum, @@ -308,7 +293,6 @@ LibAmdReadCpuReg ( } } -__attribute__((optimize("Os"))) VOID LibAmdWriteCpuReg ( IN UINT8 RegNum, @@ -339,7 +323,6 @@ LibAmdWriteCpuReg ( } } -__attribute__((optimize("Os"))) VOID LibAmdWriteBackInvalidateCache ( void @@ -348,7 +331,6 @@ LibAmdWriteBackInvalidateCache ( __wbinvd (); } -__attribute__((optimize("Os"))) VOID LibAmdHDTBreakPoint ( void @@ -358,7 +340,6 @@ LibAmdHDTBreakPoint ( __debugbreak (); // do you really need icebp? If so, go back to asm code } -__attribute__((optimize("Os"))) UINT8 LibAmdBitScanForward ( IN UINT32 value @@ -371,7 +352,6 @@ LibAmdBitScanForward ( return (UINT8) Index; } -__attribute__((optimize("Os"))) UINT8 LibAmdBitScanReverse ( IN UINT32 value @@ -384,7 +364,6 @@ LibAmdBitScanReverse ( return (UINT8) Index; } -__attribute__((optimize("Os"))) VOID LibAmdMsrRead ( IN UINT32 MsrAddress, @@ -398,7 +377,6 @@ LibAmdMsrRead ( *Value = __readmsr (MsrAddress); } -__attribute__((optimize("Os"))) VOID LibAmdMsrWrite ( IN UINT32 MsrAddress, @@ -409,7 +387,6 @@ LibAmdMsrWrite ( __writemsr (MsrAddress, *Value); } -__attribute__((optimize("Os"))) void LibAmdCpuidRead ( IN UINT32 CpuidFcnAddress, OUT CPUID_DATA* Value, @@ -419,7 +396,6 @@ void LibAmdCpuidRead ( __cpuid ((int *)Value, CpuidFcnAddress); } -__attribute__((optimize("Os"))) UINT64 ReadTSC ( void @@ -428,7 +404,6 @@ ReadTSC ( return __rdtsc (); } -__attribute__((optimize("Os"))) VOID LibAmdSimNowEnterDebugger ( void @@ -444,7 +419,6 @@ LibAmdSimNowEnterDebugger ( ((VOID (*)(VOID)) (size_t) opcode) (); // call the function } -__attribute__((optimize("Os"))) VOID IdsOutPort ( IN UINT32 Addr, @@ -455,7 +429,6 @@ IdsOutPort ( __outdword ((UINT16) Addr, Value); } -__attribute__((optimize("Os"))) VOID StopHere ( void @@ -465,7 +438,6 @@ StopHere ( while (x); } -__attribute__((optimize("Os"))) VOID LibAmdCLFlush ( IN UINT64 Address, @@ -485,7 +457,6 @@ LibAmdCLFlush ( } -__attribute__((optimize("Os"))) VOID LibAmdFinit( void @@ -1367,7 +1338,6 @@ LibAmdAccessWidth ( return Width; } -__attribute__((optimize("Os"))) VOID CpuidRead ( IN UINT32 CpuidFcnAddress, @@ -1377,7 +1347,6 @@ CpuidRead ( __cpuid ((int *)Value, CpuidFcnAddress); } -__attribute__((optimize("Os"))) UINT8 ReadNumberOfCpuCores( void

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Patch set updated for coreboot: 76e1954 TEST clang warn as error
by Edward O'Callaghan 07 Dec '14

07 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7672 -gerrit commit 76e19549d3896952b39e90470f6dc03f374a90f6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Dec 7 02:46:07 2014 +1100 TEST clang warn as error Change-Id: Iac4efa59f63437fd6c7678368f4c62ba005d2103 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- src/Kconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eaba3e4..5a7e687 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 -Wno-unused-variable -Wno-unused-function CC_x86_32:=clang HOSTCC := clang diff --git a/src/Kconfig b/src/Kconfig index 533bc5c..7f033a2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1131,8 +1131,7 @@ config ENABLE_APIC_EXT_ID # the whole treee. config WARNINGS_ARE_ERRORS bool - default y if !COMPILER_LLVM_CLANG - default n if COMPILER_LLVM_CLANG + default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are

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coreboot-gerrit December 2014