coreboot-gerrit November 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 8ae16ef AMD boards: constify romstage variables
by Patrick Georgi 01 Nov '14

01 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7313 -gerrit commit 8ae16ef5c9887e409290363413aad6b4a223477d Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Nov 1 10:34:23 2014 +0100 AMD boards: constify romstage variables That takes them out of .data Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 6 +++--- src/mainboard/amd/torpedo/PlatformGnbPcie.c | 6 +++--- src/mainboard/amd/torpedo/gpio.h | 4 ++-- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 6 +++--- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index ec5d68d..4072112 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -71,7 +71,7 @@ * 38 DP2_TX[P,N]6 */ -PCIe_PORT_DESCRIPTOR PortList [] = { +static const PCIe_PORT_DESCRIPTOR PortList [] = { /* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */ { 0, /* Descriptor flags */ @@ -121,7 +121,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }, }; -PCIe_DDI_DESCRIPTOR DdiList [] = { +static const PCIe_DDI_DESCRIPTOR DdiList [] = { // DP0 to HDMI0/DP0 { 0, @@ -142,7 +142,7 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { }, }; -PCIe_COMPLEX_DESCRIPTOR Trinity = { +static const PCIe_COMPLEX_DESCRIPTOR Trinity = { DESCRIPTOR_TERMINATE_LIST, 0, &PortList[0], diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index b0b5dd6..a17a7ed 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -24,7 +24,7 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE -PCIe_PORT_DESCRIPTOR PortList [] = { +static const PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) { 0, //Descriptor flags @@ -69,7 +69,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { // } }; -PCIe_DDI_DESCRIPTOR DdiList [] = { +static const PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) { 0, //Descriptor flags @@ -84,7 +84,7 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { } }; -PCIe_COMPLEX_DESCRIPTOR Llano = { +static const PCIe_COMPLEX_DESCRIPTOR Llano = { DESCRIPTOR_TERMINATE_LIST, 0, &PortList[0], diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index f8516a2..f8281f8 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -1995,7 +1995,7 @@ typedef struct _GPIO_SETTINGS u8 NonGpioGevent; } GPIO_SETTINGS; -GPIO_SETTINGS gpio_table[]= +const GPIO_SETTINGS gpio_table[]= { {GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT}, {GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT}, @@ -2269,7 +2269,7 @@ typedef struct _GEVENT_SETTINGS u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 } GEVENT_SETTINGS; -GEVENT_SETTINGS gevent_table[] = +const GEVENT_SETTINGS gevent_table[] = { {GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL}, {GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL}, diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index ee5b5ff..3a8be41 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -68,7 +68,7 @@ * 38 DP2_TX[P,N]6 */ -PCIe_PORT_DESCRIPTOR PortList [] = { +static const PCIe_PORT_DESCRIPTOR PortList [] = { /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ { 0, /* Descriptor flags */ @@ -95,7 +95,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { * Tested and works: VGA/DVI * Untested: HDMI */ -PCIe_DDI_DESCRIPTOR DdiList [] = { +static const PCIe_DDI_DESCRIPTOR DdiList [] = { // DP0 to HDMI0/DP { 0, @@ -116,7 +116,7 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { }, }; -PCIe_COMPLEX_DESCRIPTOR Trinity = { +static const PCIe_COMPLEX_DESCRIPTOR Trinity = { DESCRIPTOR_TERMINATE_LIST, 0, &PortList[0],

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New patch to review for coreboot: 2f7defd AGESA f12: Add "const" modifiers
by Patrick Georgi 01 Nov '14

01 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7312 -gerrit commit 2f7defda9f9a8e95a3a84236766f7eac961a79dc Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Nov 1 10:23:03 2014 +0100 AGESA f12: Add "const" modifiers Apply commit 283ba78415 to f12 (literally, plus one adaptation). Change-Id: Ied7891806e269320caf968cae3de3dc792c5f8fd Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/vendorcode/amd/agesa/f12/AGESA.h | 4 +- .../amd/agesa/f12/Legacy/Proc/Dispatcher.c | 2 +- src/vendorcode/amd/agesa/f12/Lib/amdlib.c | 60 +++++++++++----------- src/vendorcode/amd/agesa/f12/Lib/amdlib.h | 44 ++++++++-------- .../GNB/Modules/GnbPcieConfig/PcieInputParser.c | 14 ++--- .../GNB/Modules/GnbPcieConfig/PcieInputParser.h | 6 +-- 6 files changed, 65 insertions(+), 65 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h index 9f61807..9660f35 100644 --- a/src/vendorcode/amd/agesa/f12/AGESA.h +++ b/src/vendorcode/amd/agesa/f12/AGESA.h @@ -825,8 +825,8 @@ typedef struct { * @li @b Bit31 - last descriptor in topology */ IN UINT32 SocketId; ///< Socket Id - IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). - IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + IN CONST PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + IN CONST PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). IN VOID *Reserved; ///< Reserved for future use } PCIe_COMPLEX_DESCRIPTOR; diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c index 865c84f..cbbd491 100644 --- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c +++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c @@ -84,7 +84,7 @@ AmdAgesaDispatcher ( DISPATCH_TABLE *Entry; UINT32 ImageStart; UINT32 ImageEnd; - AMD_IMAGE_HEADER* AltImagePtr; + CONST AMD_IMAGE_HEADER* AltImagePtr; Status = AGESA_UNSUPPORTED; ImageEntry = NULL; diff --git a/src/vendorcode/amd/agesa/f12/Lib/amdlib.c b/src/vendorcode/amd/agesa/f12/Lib/amdlib.c index f88eb98..1ca9b55 100644 --- a/src/vendorcode/amd/agesa/f12/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f12/Lib/amdlib.c @@ -90,8 +90,8 @@ VOID STATIC LibAmdGetDataFromPtr ( IN ACCESS_WIDTH AccessWidth, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, OUT UINT32 *TemData, OUT UINT32 *TempDataMask ); @@ -504,7 +504,7 @@ VOID LibAmdIoWrite ( IN ACCESS_WIDTH AccessWidth, IN UINT16 IoAddress, - IN VOID *Value, + IN CONST VOID *Value, IN OUT AMD_CONFIG_PARAMS *StdHeader ) { @@ -542,8 +542,8 @@ VOID LibAmdIoRMW ( IN ACCESS_WIDTH AccessWidth, IN UINT16 IoAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN OUT AMD_CONFIG_PARAMS *StdHeader ) { @@ -574,8 +574,8 @@ VOID LibAmdIoPoll ( IN ACCESS_WIDTH AccessWidth, IN UINT16 IoAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN UINT64 Delay, IN OUT AMD_CONFIG_PARAMS *StdHeader ) @@ -641,7 +641,7 @@ VOID LibAmdMemWrite ( IN ACCESS_WIDTH AccessWidth, IN UINT64 MemAddress, - IN VOID *Value, + IN CONST VOID *Value, IN OUT AMD_CONFIG_PARAMS *StdHeader ) { @@ -679,8 +679,8 @@ VOID LibAmdMemRMW ( IN ACCESS_WIDTH AccessWidth, IN UINT64 MemAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN OUT AMD_CONFIG_PARAMS *StdHeader ) { @@ -711,8 +711,8 @@ VOID LibAmdMemPoll ( IN ACCESS_WIDTH AccessWidth, IN UINT64 MemAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN UINT64 Delay, IN OUT AMD_CONFIG_PARAMS *StdHeader ) @@ -792,7 +792,7 @@ VOID LibAmdPciWrite ( IN ACCESS_WIDTH AccessWidth, IN PCI_ADDR PciAddress, - IN VOID *Value, + IN CONST VOID *Value, IN OUT AMD_CONFIG_PARAMS *StdHeader ) { @@ -844,8 +844,8 @@ VOID LibAmdPciRMW ( IN ACCESS_WIDTH AccessWidth, IN PCI_ADDR PciAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN OUT AMD_CONFIG_PARAMS *StdHeader ) { @@ -876,8 +876,8 @@ VOID LibAmdPciPoll ( IN ACCESS_WIDTH AccessWidth, IN PCI_ADDR PciAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN UINT64 Delay, IN OUT AMD_CONFIG_PARAMS *StdHeader ) @@ -976,7 +976,7 @@ LibAmdPciWriteBits ( IN PCI_ADDR Address, IN UINT8 Highbit, IN UINT8 Lowbit, - IN UINT32 *Value, + IN CONST UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { @@ -1112,13 +1112,13 @@ LibAmdMemFill ( VOID LibAmdMemCopy ( IN VOID *Destination, - IN VOID *Source, + IN CONST VOID *Source, IN UINTN CopyLength, IN OUT AMD_CONFIG_PARAMS *StdHeader ) { UINT8 *Dest; - UINT8 *SourcePtr; + CONST UINT8 *SourcePtr; ASSERT (StdHeader != NULL); Dest = Destination; SourcePtr = Source; @@ -1138,7 +1138,7 @@ LibAmdMemCopy ( */ BOOLEAN LibAmdVerifyImageChecksum ( - IN VOID *ImagePtr + IN CONST VOID *ImagePtr ) { // Assume ImagePtr points to the binary start ($AMD) @@ -1175,19 +1175,19 @@ LibAmdVerifyImageChecksum ( * @retval NULL if image not found * @retval pointer to image header */ -VOID * +CONST VOID * LibAmdLocateImage ( - IN VOID *StartAddress, - IN VOID *EndAddress, + IN CONST VOID *StartAddress, + IN CONST VOID *EndAddress, IN UINT32 Alignment, - IN CHAR8 ModuleSignature[8] + IN CONST CHAR8 ModuleSignature[8] ) { - UINT8 *CurrentPtr; + CONST UINT8 *CurrentPtr; AMD_MODULE_HEADER *ModuleHeaderPtr; - UINT64 *SearchStr; - UINT64 *InputStr; + CONST UINT64 *SearchStr; + CONST UINT64 *InputStr; CurrentPtr = StartAddress; InputStr = (UINT64 *)ModuleSignature; @@ -1252,8 +1252,8 @@ VOID STATIC LibAmdGetDataFromPtr ( IN ACCESS_WIDTH AccessWidth, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, OUT UINT32 *TemData, OUT UINT32 *TempDataMask ) diff --git a/src/vendorcode/amd/agesa/f12/Lib/amdlib.h b/src/vendorcode/amd/agesa/f12/Lib/amdlib.h index 63cd659..5225dce 100644 --- a/src/vendorcode/amd/agesa/f12/Lib/amdlib.h +++ b/src/vendorcode/amd/agesa/f12/Lib/amdlib.h @@ -185,7 +185,7 @@ VOID LibAmdIoWrite ( IN ACCESS_WIDTH AccessWidth, IN UINT16 IoAddress, - IN VOID *Value, + IN CONST VOID *Value, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -193,8 +193,8 @@ VOID LibAmdIoRMW ( IN ACCESS_WIDTH AccessWidth, IN UINT16 IoAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -202,8 +202,8 @@ VOID LibAmdIoPoll ( IN ACCESS_WIDTH AccessWidth, IN UINT16 IoAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN UINT64 Delay, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -221,7 +221,7 @@ VOID LibAmdMemWrite ( IN ACCESS_WIDTH AccessWidth, IN UINT64 MemAddress, - IN VOID *Value, + IN CONST VOID *Value, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -229,8 +229,8 @@ VOID LibAmdMemRMW ( IN ACCESS_WIDTH AccessWidth, IN UINT64 MemAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -238,8 +238,8 @@ VOID LibAmdMemPoll ( IN ACCESS_WIDTH AccessWidth, IN UINT64 MemAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN UINT64 Delay, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -257,7 +257,7 @@ VOID LibAmdPciWrite ( IN ACCESS_WIDTH AccessWidth, IN PCI_ADDR PciAddress, - IN VOID *Value, + IN CONST VOID *Value, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -265,8 +265,8 @@ VOID LibAmdPciRMW ( IN ACCESS_WIDTH AccessWidth, IN PCI_ADDR PciAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -274,8 +274,8 @@ VOID LibAmdPciPoll ( IN ACCESS_WIDTH AccessWidth, IN PCI_ADDR PciAddress, - IN VOID *Data, - IN VOID *DataMask, + IN CONST VOID *Data, + IN CONST VOID *DataMask, IN UINT64 Delay, IN OUT AMD_CONFIG_PARAMS *StdHeader ); @@ -294,7 +294,7 @@ LibAmdPciWriteBits ( IN PCI_ADDR Address, IN UINT8 Highbit, IN UINT8 Lowbit, - IN UINT32 *Value, + IN CONST UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader ); @@ -324,17 +324,17 @@ LibAmdMemFill ( VOID LibAmdMemCopy ( IN VOID *Destination, - IN VOID *Source, + IN CONST VOID *Source, IN UINTN CopyLength, IN OUT AMD_CONFIG_PARAMS *StdHeader ); -VOID * +CONST VOID * LibAmdLocateImage ( - IN VOID *StartAddress, - IN VOID *EndAddress, + IN CONST VOID *StartAddress, + IN CONST VOID *EndAddress, IN UINT32 Alignment, - IN CHAR8 ModuleSignature[8] + IN CONST CHAR8 ModuleSignature[8] ); UINT32 @@ -344,7 +344,7 @@ LibAmdGetPackageType ( BOOLEAN LibAmdVerifyImageChecksum ( - IN VOID *ImagePtr + IN CONST VOID *ImagePtr ); UINT8 diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c index c6d9d47..5398ca1 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c @@ -73,7 +73,7 @@ */ UINTN PcieInputParserGetLengthOfDdiEnginesList ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex + IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex ); /*----------------------------------------------------------------------------------------*/ @@ -88,7 +88,7 @@ PcieInputParserGetLengthOfDdiEnginesList ( */ UINTN PcieInputParserGetNumberOfComplexes ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList + IN CONST PCIe_COMPLEX_DESCRIPTOR *ComplexList ) { UINTN Result; @@ -113,11 +113,11 @@ PcieInputParserGetNumberOfComplexes ( */ UINTN PcieInputParserGetLengthOfPcieEnginesList ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex + IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex ) { UINTN Result; - PCIe_PORT_DESCRIPTOR *PciePortList; + CONST PCIe_PORT_DESCRIPTOR *PciePortList; Result = 0; if (Complex != NULL) { PciePortList = Complex->PciePortList; @@ -140,11 +140,11 @@ PcieInputParserGetLengthOfPcieEnginesList ( */ UINTN PcieInputParserGetLengthOfDdiEnginesList ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex + IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex ) { UINTN Result; - PCIe_DDI_DESCRIPTOR *DdiLinkList; + CONST PCIe_DDI_DESCRIPTOR *DdiLinkList; Result = 0; if (Complex != NULL) { DdiLinkList = Complex->DdiLinkList; @@ -168,7 +168,7 @@ PcieInputParserGetLengthOfDdiEnginesList ( */ UINTN PcieInputParserGetNumberOfEngines ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex + IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex ) { UINTN Result; diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h index d10c383..ed2e33a 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h @@ -48,12 +48,12 @@ UINTN PcieInputParserGetNumberOfComplexes ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList + IN CONST PCIe_COMPLEX_DESCRIPTOR *ComplexList ); UINTN PcieInputParserGetNumberOfEngines ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex + IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex ); @@ -77,7 +77,7 @@ PcieInputParserGetComplexDescriptorOfSocket ( UINTN PcieInputParserGetLengthOfPcieEnginesList ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex + IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex ); #endif

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Patch set updated for coreboot: 103975f x86: Update the check for Forbidden global variables
by Patrick Georgi 01 Nov '14

01 Nov '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7306 -gerrit commit 103975f8b3f7a09ebf8b7683b45dc2285b637d59 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 30 11:53:38 2014 -0700 x86: Update the check for Forbidden global variables Add a section .illegal_globals to romstage and check that the section does not contain any variables while creating romstage. [pg: Handle individual AGESA special cases in the linker script instead of whitelisting everything remotely AGESA related in the Makefile.] Change-Id: I866681f51a44bc21770d32995c281b556a90c153 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/arch/x86/Makefile.inc | 5 +++-- src/arch/x86/init/romstage.ld | 15 +++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f99ea15..55266f6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -214,9 +214,10 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif - $(NM_romstage) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ + $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders && \ + $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ - $(NM_romstage) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ + $(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \ else true; fi $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index d6eb511..99bcc8e 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -65,5 +65,20 @@ SECTIONS preram_cbmem_console = .; } + /* Global variables are not allowed in romstage + * This section is checked during stage creation to ensure + * that there are no global variables present + */ + + . = 0xffffff00; + .illegal_globals . : { + *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */cpu/amd/agesa/*.romstage.o */vendorcode/amd/agesa/* */vendorcode/amd/cimx/*) .data) + *(.data.*) + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } + _bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); }

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Patch set updated for coreboot: 2c263cd include/*: Clarify correct typing of 'struct device *'
by Edward O'Callaghan 01 Nov '14

01 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7311 -gerrit commit 2c263cd15ac2684a12c08120065a25cb7465260f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 13:55:04 2014 +1100 include/*: Clarify correct typing of 'struct device *' Disambiguate 'device_t' into 'struct device *', 'pci_devfn_t' and 'pnp_devfn_t' component types where appropriate. Change-Id: I114341d745b8852217ca335a2c957917507de8f9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/cpu/amd/model_fxx_rev.h | 6 ++-- src/include/device/agp.h | 2 +- src/include/device/cardbus.h | 4 +-- src/include/device/device.h | 69 ++++++++++++++++++------------------- src/include/device/pci.h | 30 ++++++++-------- src/include/device/pci_ops.h | 24 ++++++------- src/include/device/pciexp.h | 2 +- src/include/device/pcix.h | 2 +- src/include/device/pnp.h | 38 ++++++++++---------- src/include/device/smbus.h | 54 ++++++++++++++--------------- src/include/reg_script.h | 6 ++-- 11 files changed, 118 insertions(+), 119 deletions(-) diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 1e85596..1044abc 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -59,7 +59,7 @@ static int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + pci_devnfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,2); val_old = pci_read_config32(dev, 0x80); val = val_old; @@ -101,7 +101,7 @@ static inline int is_cpu_pre_f2(void) static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; @@ -109,7 +109,7 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff0f) < 0x40f02; diff --git a/src/include/device/agp.h b/src/include/device/agp.h index be2b833..b3791fe 100644 --- a/src/include/device/agp.h +++ b/src/include/device/agp.h @@ -7,7 +7,7 @@ unsigned int agp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); -unsigned int agp_scan_bridge(device_t dev, unsigned int max); +unsigned int agp_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_agp_ops_bus; diff --git a/src/include/device/cardbus.h b/src/include/device/cardbus.h index 45ae24f..4443c15 100644 --- a/src/include/device/cardbus.h +++ b/src/include/device/cardbus.h @@ -5,8 +5,8 @@ #include <device/device.h> -void cardbus_read_resources(device_t dev); -void cardbus_enable_resources(device_t dev); +void cardbus_read_resources(struct device *dev); +void cardbus_enable_resources(struct device *dev); extern struct device_operations default_cardbus_ops_bus; diff --git a/src/include/device/device.h b/src/include/device/device.h index 3810716..750621e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -41,19 +41,19 @@ struct smbios_type11; struct acpi_rsdp; struct device_operations { - void (*read_resources)(device_t dev); - void (*set_resources)(device_t dev); - void (*enable_resources)(device_t dev); - void (*init)(device_t dev); - void (*final)(device_t dev); - unsigned int (*scan_bus)(device_t bus, unsigned int _max); - void (*enable)(device_t dev); - void (*disable)(device_t dev); - void (*set_link)(device_t dev, unsigned int link); + void (*read_resources)(struct device *dev); + void (*set_resources)(struct device *dev); + void (*enable_resources)(struct device *dev); + void (*init)(struct device *dev); + void (*final)(struct device *dev); + unsigned int (*scan_bus)(struct device *bus, unsigned int _max); + void (*enable)(struct device *dev); + void (*disable)(struct device *dev); + void (*set_link)(struct device *dev, unsigned int link); void (*reset_bus)(struct bus *bus); #if CONFIG_GENERATE_SMBIOS_TABLES - int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); - void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); + int (*get_smbios_data)(struct device *dev, int *handle, unsigned long *current); + void (*get_smbios_strings)(struct device *dev, struct smbios_type11 *t); #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); @@ -62,7 +62,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); + const struct pci_bus_operations * (*ops_pci_bus)(struct device *dev); const struct pnp_mode_ops *ops_pnp_mode; }; @@ -70,9 +70,8 @@ struct device_operations { struct bus { - - ROMSTAGE_CONST struct device * dev; /* This bridge device */ - ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct device *dev; /* This bridge device */ + ROMSTAGE_CONST struct device *children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ @@ -92,7 +91,7 @@ struct pci_irq_info { unsigned int ioapic_irq_pin; unsigned int ioapic_src_pin; unsigned int ioapic_dst_id; - unsigned int ioapic_flags; + unsigned int ioapic_flags; }; struct device { @@ -153,7 +152,7 @@ extern uint64_t uma_memory_size; #endif /* Generic device interface functions */ -device_t alloc_dev(struct bus *parent, struct device_path *path); +struct device *alloc_dev(struct bus *parent, struct device_path *path); void dev_initialize_chips(void); void dev_enumerate(void); void dev_configure(void); @@ -169,30 +168,30 @@ unsigned int scan_bus(struct device *bus, unsigned int _max); void assign_resources(struct bus *bus); void enumerate_static_device(void); void enumerate_static_devices(void); -const char *dev_name(device_t dev); -const char *dev_path(device_t dev); -u32 dev_path_encode(device_t dev); +const char *dev_name(struct device *dev); +const char *dev_path(struct device *dev); +u32 dev_path_encode(struct device *dev); const char *bus_path(struct bus *bus); -void dev_set_enabled(device_t dev, int enable); +void dev_set_enabled(struct device *dev, int enable); void disable_children(struct bus *bus); /* Option ROM helper functions */ void run_bios(struct device *dev, unsigned long addr); /* Helper functions */ -device_t find_dev_path(struct bus *parent, struct device_path *path); -device_t alloc_find_dev(struct bus *parent, struct device_path *path); -device_t dev_find_device (u16 vendor, u16 device, device_t from); -device_t dev_find_class (unsigned int class, device_t from); -device_t dev_find_slot (unsigned int bus, unsigned int devfn); -device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); -device_t dev_find_slot_pnp(u16 port, u16 device); -device_t dev_find_lapic(unsigned apic_id); +struct device *find_dev_path(struct bus *parent, struct device_path *path); +struct device *alloc_find_dev(struct bus *parent, struct device_path *path); +struct device *dev_find_device (u16 vendor, u16 device, struct device *from); +struct device *dev_find_class (unsigned int class, struct device *from); +struct device *dev_find_slot (unsigned int bus, unsigned int devfn); +struct device *dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +struct device *dev_find_slot_pnp(u16 port, u16 device); +struct device *dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); void remap_bsp_lapic(struct bus *cpu_bus); -device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); -void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread); +struct device *add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); +void set_cpu_topology(struct device *cpu, unsigned node, unsigned package, unsigned core, unsigned thread); #define amd_cpu_topology(cpu, node, core) \ set_cpu_topology(cpu, node, 0, core, 0) @@ -201,7 +200,7 @@ void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned co set_cpu_topology(cpu, 0, package, core, thread) /* Debug functions */ -void print_resource_tree(struct device * root, int debug_level, +void print_resource_tree(struct device *root, int debug_level, const char *msg); void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum); void show_devs_subtree(struct device *root, int debug_level, const char *msg); @@ -220,9 +219,9 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); -unsigned int scan_static_bus(device_t bus, unsigned int _max); +unsigned int scan_static_bus(struct device *bus, unsigned int _max); -void fixed_mem_resource(device_t dev, unsigned long index, +void fixed_mem_resource(struct device *dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); @@ -251,7 +250,7 @@ u32 find_pci_tolm(struct bus *bus); ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); -ROMSTAGE_CONST struct device *dev_find_next_pci_device( +ROMSTAGE_CONST struct device * dev_find_next_pci_device( ROMSTAGE_CONST struct device *previous_dev); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 0670da4..3688322 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -32,7 +32,7 @@ /* Common pci operations without a standard interface */ struct pci_operations { /* set the Subsystem IDs for the PCI device */ - void (*set_subsystem)(device_t dev, unsigned vendor, unsigned device); + void (*set_subsystem)(struct device *dev, unsigned vendor, unsigned device); }; /* Common pci bus operations */ @@ -62,35 +62,35 @@ extern struct pci_driver epci_drivers[]; extern struct device_operations default_pci_ops_dev; extern struct device_operations default_pci_ops_bus; -void pci_dev_read_resources(device_t dev); -void pci_bus_read_resources(device_t dev); -void pci_dev_set_resources(device_t dev); -void pci_dev_enable_resources(device_t dev); -void pci_bus_enable_resources(device_t dev); +void pci_dev_read_resources(struct device *dev); +void pci_bus_read_resources(struct device *dev); +void pci_dev_set_resources(struct device *dev); +void pci_dev_enable_resources(struct device *dev); +void pci_bus_enable_resources(struct device *dev); void pci_bus_reset(struct bus *bus); -device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); -unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, +struct device *pci_probe_dev(struct device *dev, struct bus *bus, unsigned devfn); +unsigned int do_pci_scan_bridge(struct device *bus, unsigned int max, unsigned int (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max)); -unsigned int pci_scan_bridge(device_t bus, unsigned int max); +unsigned int pci_scan_bridge(struct device *bus, unsigned int max); unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); uint8_t pci_moving_config8(struct device *dev, unsigned reg); uint16_t pci_moving_config16(struct device *dev, unsigned reg); uint32_t pci_moving_config32(struct device *dev, unsigned reg); struct resource *pci_get_resource(struct device *dev, unsigned long index); -void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); +void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); -unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev); +unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev); const char * pin_to_str(int pin); -int get_pci_irq_pins(device_t dev, device_t *parent_bdg); +int get_pci_irq_pins(struct device *dev, struct device **parent_bdg); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -static inline const struct pci_operations *ops_pci(device_t dev) +static inline const struct pci_operations *ops_pci(struct device *dev) { const struct pci_operations *pops; pops = 0; @@ -106,8 +106,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); #else /* !__PRE_RAM__ */ -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); -unsigned pci_find_capability(device_t dev, unsigned cap); +unsigned pci_find_next_capability(struct device *dev, unsigned cap, unsigned last); +unsigned pci_find_capability(struct device *dev, unsigned cap); #endif /* __PRE_RAM__ */ void pci_early_bridge_init(void); diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index ae58a01..920475a 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -6,20 +6,20 @@ #include <arch/pci_ops.h> #ifndef __SIMPLE_DEVICE__ -u8 pci_read_config8(device_t dev, unsigned int where); -u16 pci_read_config16(device_t dev, unsigned int where); -u32 pci_read_config32(device_t dev, unsigned int where); -void pci_write_config8(device_t dev, unsigned int where, u8 val); -void pci_write_config16(device_t dev, unsigned int where, u16 val); -void pci_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_read_config8(struct device *dev, unsigned int where); +u16 pci_read_config16(struct device *dev, unsigned int where); +u32 pci_read_config32(struct device *dev, unsigned int where); +void pci_write_config8(struct device *dev, unsigned int where, u8 val); +void pci_write_config16(struct device *dev, unsigned int where, u16 val); +void pci_write_config32(struct device *dev, unsigned int where, u32 val); #if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(device_t dev, unsigned int where); -u16 pci_mmio_read_config16(device_t dev, unsigned int where); -u32 pci_mmio_read_config32(device_t dev, unsigned int where); -void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val); -void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val); -void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_mmio_read_config8(struct device *dev, unsigned int where); +u16 pci_mmio_read_config16(struct device *dev, unsigned int where); +u32 pci_mmio_read_config32(struct device *dev, unsigned int where); +void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val); +void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val); +void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val); #endif #endif diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 87a5002..c7ff4f5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -11,7 +11,7 @@ enum aspm_type { unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); +unsigned int pciexp_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 4ffab5b..8cc83df 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -4,7 +4,7 @@ unsigned int pcix_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); -unsigned int pcix_scan_bridge(device_t dev, unsigned int max); +unsigned int pcix_scan_bridge(struct device *dev, unsigned int max); const char *pcix_speed(u16 sstatus); extern struct device_operations default_pcix_ops_bus; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index d0d6fa3..9290056 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -9,21 +9,21 @@ #ifndef __SIMPLE_DEVICE__ /* Primitive PNP resource manipulation */ -void pnp_write_config(device_t dev, u8 reg, u8 value); -u8 pnp_read_config(device_t dev, u8 reg); -void pnp_set_logical_device(device_t dev); -void pnp_set_enable(device_t dev, int enable); -int pnp_read_enable(device_t dev); -void pnp_set_iobase(device_t dev, u8 index, u16 iobase); -void pnp_set_irq(device_t dev, u8 index, u8 irq); -void pnp_set_drq(device_t dev, u8 index, u8 drq); +void pnp_write_config(struct device *dev, u8 reg, u8 value); +u8 pnp_read_config(struct device *dev, u8 reg); +void pnp_set_logical_device(struct device *dev); +void pnp_set_enable(struct device *dev, int enable); +int pnp_read_enable(struct device *dev); +void pnp_set_iobase(struct device *dev, u8 index, u16 iobase); +void pnp_set_irq(struct device *dev, u8 index, u8 irq); +void pnp_set_drq(struct device *dev, u8 index, u8 drq); /* PNP device operations */ -void pnp_read_resources(device_t dev); -void pnp_set_resources(device_t dev); -void pnp_enable_resources(device_t dev); -void pnp_enable(device_t dev); -void pnp_alt_enable(device_t dev); +void pnp_read_resources(struct device *dev); +void pnp_set_resources(struct device *dev); +void pnp_enable_resources(struct device *dev); +void pnp_enable(struct device *dev); +void pnp_alt_enable(struct device *dev); extern struct device_operations pnp_ops; @@ -52,16 +52,16 @@ struct pnp_info { #define PNP_MSC10 0x1000 struct io_info io0, io1, io2, io3; }; -struct resource *pnp_get_resource(device_t dev, unsigned index); +struct resource *pnp_get_resource(struct device *dev, unsigned index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); struct pnp_mode_ops { - void (*enter_conf_mode)(device_t dev); - void (*exit_conf_mode)(device_t dev); + void (*enter_conf_mode)(struct device *dev); + void (*exit_conf_mode)(struct device *dev); }; -void pnp_enter_conf_mode(device_t dev); -void pnp_exit_conf_mode(device_t dev); +void pnp_enter_conf_mode(struct device *dev); +void pnp_exit_conf_mode(struct device *dev); #endif /* ! __SIMPLE_DEVICE__ */ -#endif /* DEVICE_PNP_H */ +#endif /*devICE_PNP_H */ diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 073d7e2..7002459 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -8,17 +8,17 @@ /* Common SMBus bus operations */ struct smbus_bus_operations { - int (*quick_read) (device_t dev); - int (*quick_write) (device_t dev); - int (*recv_byte) (device_t dev); - int (*send_byte) (device_t dev, u8 value); - int (*read_byte) (device_t dev, u8 addr); - int (*write_byte) (device_t dev, u8 addr, u8 value); - int (*read_word) (device_t dev, u8 addr); - int (*write_word) (device_t dev, u8 addr, u16 value); - int (*process_call)(device_t dev, u8 cmd, u16 data); - int (*block_read) (device_t dev, u8 cmd, u8 bytes, u8 *buffer); - int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer); + int (*quick_read) (struct device *dev); + int (*quick_write) (struct device *dev); + int (*recv_byte) (struct device *dev); + int (*send_byte) (struct device *dev, u8 value); + int (*read_byte) (struct device *dev, u8 addr); + int (*write_byte) (struct device *dev, u8 addr, u8 value); + int (*read_word) (struct device *dev, u8 addr); + int (*write_word) (struct device *dev, u8 addr, u16 value); + int (*process_call)(struct device *dev, u8 cmd, u16 data); + int (*block_read) (struct device *dev, u8 cmd, u8 bytes, u8 *buffer); + int (*block_write) (struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); }; static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) @@ -32,19 +32,19 @@ static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) return bops; } -struct bus *get_pbus_smbus(device_t dev); -int smbus_set_link(device_t dev); - -int smbus_quick_read(device_t dev); -int smbus_quick_write(device_t dev); -int smbus_recv_byte(device_t dev); -int smbus_send_byte(device_t dev, u8 byte); -int smbus_read_byte(device_t dev, u8 addr); -int smbus_write_byte(device_t dev, u8 addr, u8 val); -int smbus_read_word(device_t dev, u8 addr); -int smbus_write_word(device_t dev, u8 addr, u16 val); -int smbus_process_call(device_t dev, u8 cmd, u16 data); -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); -int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); - -#endif /* DEVICE_SMBUS_H */ +struct bus *get_pbus_smbus(struct device *dev); +int smbus_set_link(struct device *dev); + +int smbus_quick_read(struct device *dev); +int smbus_quick_write(struct device *dev); +int smbus_recv_byte(struct device *dev); +int smbus_send_byte(struct device *dev, u8 byte); +int smbus_read_byte(struct device *dev, u8 addr); +int smbus_write_byte(struct device *dev, u8 addr, u8 val); +int smbus_read_word(struct device *dev, u8 addr); +int smbus_write_word(struct device *dev, u8 addr, u16 val); +int smbus_process_call(struct device *dev, u8 cmd, u16 data); +int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); + +#endif /*devICE_SMBUS_H */ diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 97b4fb0..71be7c2 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -34,7 +34,7 @@ * are employed: * - Chaining of tables that allow runtime tables to chain to compile-time * tables. - * - Notion of current device (device_t) being worked on. This allows for + * - Notion of current device (struct device *) being worked on. This allows for * PCI config, io, and mmio on a particular device's resources. * * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push @@ -80,7 +80,7 @@ struct reg_script { union { uint32_t id; const struct reg_script *next; - device_t dev; + struct device *dev; unsigned int res_index; }; }; @@ -334,6 +334,6 @@ struct reg_script { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) void reg_script_run(const struct reg_script *script); -void reg_script_run_on_dev(device_t dev, const struct reg_script *step); +void reg_script_run_on_dev(struct device *dev, const struct reg_script *step); #endif /* REG_SCRIPT_H */

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Patch set updated for coreboot: c16cb11 superio/ite: Use common dispatch for pnp entry/exit functions
by Edward O'Callaghan 01 Nov '14

01 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7310 -gerrit commit c16cb11e4ce143a6743d00fd81176b27312bf890 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 12:11:58 2014 +1100 superio/ite: Use common dispatch for pnp entry/exit functions We already have these implemented under superio/common, use those instead of this copy-paste syndrom. Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8712f/superio.c | 24 +++--------------------- src/superio/ite/it8716f/superio.c | 24 +++--------------------- src/superio/ite/it8772f/superio.c | 24 +++--------------------- 3 files changed, 9 insertions(+), 63 deletions(-) diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 9dd9f85..02a51fb 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -24,22 +24,9 @@ #include <pc80/keyboard.h> #include <arch/io.h> #include <stdlib.h> -#include "it8712f.h" - -static void pnp_enter_ext_func_mode(struct device *dev) -{ - u16 port = dev->path.pnp.port; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} +#include <superio/conf_mode.h> -static void pnp_exit_ext_func_mode(struct device *dev) -{ - pnp_write_config(dev, 0x02, 0x02); -} +#include "it8712f.h" static void it8712f_init(struct device *dev) { @@ -69,18 +56,13 @@ static void it8712f_init(struct device *dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = it8712f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 874061f..56747ba 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -27,22 +27,9 @@ #include <pc80/keyboard.h> #include <arch/io.h> #include <stdlib.h> -#include "it8716f.h" - -static void pnp_enter_ext_func_mode(struct device *dev) -{ - u16 port = dev->path.pnp.port; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} +#include <superio/conf_mode.h> -static void pnp_exit_ext_func_mode(struct device *dev) -{ - pnp_write_config(dev, 0x02, 0x02); -} +#include "it8716f.h" #if !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL static void pnp_write_index(u16 port_base, u8 reg, u8 value) @@ -93,18 +80,13 @@ static void it8716f_init(struct device *dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = it8716f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 143cc30..ca10351 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -23,24 +23,11 @@ #include <pc80/keyboard.h> #include <arch/io.h> #include <stdlib.h> +#include <superio/conf_mode.h> + #include "chip.h" /* FIXME */ #include "it8772f.h" -static void pnp_enter_ext_func_mode(struct device *dev) -{ - u16 port = dev->path.pnp.port; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void pnp_exit_ext_func_mode(struct device *dev) -{ - pnp_write_config(dev, 0x02, 0x02); -} - static inline u8 it8772f_envc_read(struct resource *res, u8 addr) { outb(addr, res->base + 5); @@ -187,18 +174,13 @@ static void it8772f_init(struct device *dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = it8772f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, }; static struct pnp_info pnp_dev_info[] = {

1 0

Patch set updated for coreboot: 351c05c superio/fintek/f81216h: Implement device support
by Edward O'Callaghan 01 Nov '14

01 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7309 -gerrit commit 351c05c8a5fba536f2900362ed7964ec8ddc31b9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 10:19:58 2014 +1100 superio/fintek/f81216h: Implement device support Change-Id: I20a34b569f109dd12af29e9e0cee8f7f6b8ebb80 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/Kconfig | 4 + src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f81216h/Makefile.inc | 22 ++++++ src/superio/fintek/f81216h/chip.h | 40 ++++++++++ src/superio/fintek/f81216h/early_serial.c | 68 +++++++++++++++++ src/superio/fintek/f81216h/f81216h.h | 46 ++++++++++++ src/superio/fintek/f81216h/superio.c | 119 ++++++++++++++++++++++++++++++ 7 files changed, 300 insertions(+) diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index f577898..e9cbe74 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -47,6 +47,10 @@ config SUPERIO_FINTEK_F71889 bool select SUPERIO_FINTEK_COMMON_ROMSTAGE +config SUPERIO_FINTEK_F81216H + bool +# N.B. 'special romstage' + config SUPERIO_FINTEK_F81865F bool select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 1b11336..5756393 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -26,4 +26,5 @@ subdirs-y += f71863fg subdirs-y += f71869ad subdirs-y += f71872 subdirs-y += f71889 +subdirs-y += f81216h subdirs-y += f81865f diff --git a/src/superio/fintek/f81216h/Makefile.inc b/src/superio/fintek/f81216h/Makefile.inc new file mode 100644 index 0000000..f473ef2 --- /dev/null +++ b/src/superio/fintek/f81216h/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += superio.c diff --git a/src/superio/fintek/f81216h/chip.h b/src/superio/fintek/f81216h/chip.h new file mode 100644 index 0000000..9b54ce1 --- /dev/null +++ b/src/superio/fintek/f81216h/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81216H_CHIP_H +#define SUPERIO_FINTEK_F81216H_CHIP_H + +#include <stdint.h> + +/* Member variables are defined in devicetree.cb. */ +struct superio_fintek_f81216h_config { + /** + * KEY1 KEY0 Enter key + * 0 0 0x77 (default) + * 0 1 0xA0 + * 1 0 0x87 + * 1 1 0x67 + * + * See page 17 of data sheet. + */ + uint8_t conf_key_mode; +}; + +#endif /* SUPERIO_FINTEK_F81216H_CHIP_H */ diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c new file mode 100644 index 0000000..6b667df --- /dev/null +++ b/src/superio/fintek/f81216h/early_serial.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "fintek.h" + +static u8 f81216h_entry_key; +#define FINTEK_EXIT_KEY 0xAA + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(f81216h_entry_key, port); + outb(f81216h_entry_key, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, enum mode_key k) +{ + switch(k) { + MODE_6767: + f81216h_entry_key = 0x67; + break; + MODE_7777: + f81216h_entry_key = 0x77; + break; + MODE_8787: + f81216h_entry_key = 0x87; + break; + MODE_A0A0: + f81216h_entry_key = 0xa0; + break; + default: + f81216h_entry_key = 0x77; /* (safe to be hw default) */ + } + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h new file mode 100644 index 0000000..37e7753 --- /dev/null +++ b/src/superio/fintek/f81216h/f81216h.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81216H_H +#define SUPERIO_FINTEK_F81216H_H + +/* Logical Device Numbers (LDN). */ +#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */ +#define F81216H_SP2 0x01 /* UART2 */ +#define F81216H_SP3 0x02 /* UART3 */ +#define F81216H_SP4 0x03 /* UART4 */ +#define F81216H_WDT 0x08 /* WDT */ + +/** + * The PNP config entry key is parameterised + * by two bits on this Super I/O with 0x77 as + * the default key. + * See page 17 of data sheet for details. + */ +enum { + MODE_6767, + MODE_7777, + MODE_8787, + MODE_A0A0, +} mode_key; + +void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, enum mode_key k); + +#endif /* SUPERIO_FINTEK_F81216H_H */ diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c new file mode 100644 index 0000000..eed165a --- /dev/null +++ b/src/superio/fintek/f81216h/superio.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> + +#include "chip.h" +#include "f81216h.h" + + +static void pnp_enter_ext_func_mode(struct device *dev) +{ + const struct superio_fintek_f81216h_config *conf = dev->chip_info; + + u8 key; + + /** + * KEY1 KEY0 Enter key + * 0 0 0x77 (default) + * 0 1 0xA0 + * 1 0 0x87 + * 1 1 0x67 + * + * See page 17 of data sheet. + */ + switch(conf->conf_key_mode) { + case 0: + key = 0x77; /* (default) */ + break; + case 1: + key = 0xa0; + break; + case 2: + key = 0x87; + break; + case 3: + key = 0x67; + break; + default: + key = 0x77; /* safe to be hw default */ + } + + outb(key, dev->path.pnp.port); + outb(key, dev->path.pnp.port); +} + +static void pnp_exit_ext_func_mode(struct device *dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + + +static void f81216h_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case F81216H_SP1: + case F81216H_SP2: + case F81216H_SP3: + case F81216H_SP4: + case F81216H_WDT: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81216h_init, + .ops_pnp_mode = &pnp_conf_mode_ops, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, F81216H_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_WDT, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81216h_ops = { + CHIP_NAME("Fintek F81216H/D/DG/F/FG Super I/O") + .enable_dev = enable_dev +};

1 0

Patch set updated for coreboot: fa2a4ba superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO's
by Edward O'Callaghan 01 Nov '14

01 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7308 -gerrit commit fa2a4ba7a5cdaafe2e5f4048f28ecbeb965bc171 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 09:14:58 2014 +1100 superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO's Super I/O manufactures have found new and innovative ways to enter and exit out of LDN config in PNP config space. Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/superio/conf_mode.h | 6 ++++++ src/superio/common/conf_mode.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index 9f7e3e6..2aca8c1 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -25,13 +25,19 @@ /* Common enter/exit implementations */ void pnp_enter_conf_mode_55(struct device *dev); +void pnp_enter_conf_mode_6767(struct device *dev); +void pnp_enter_conf_mode_7777(struct device *dev); void pnp_enter_conf_mode_8787(struct device *dev); +void pnp_enter_conf_mode_a0a0(struct device *dev); void pnp_exit_conf_mode_aa(struct device *dev); void pnp_enter_conf_mode_870155aa(struct device *dev); void pnp_exit_conf_mode_0202(struct device *dev); extern const struct pnp_mode_ops pnp_conf_mode_55_aa; +extern const struct pnp_mode_ops pnp_conf_mode_6767_aa; +extern const struct pnp_mode_ops pnp_conf_mode_7777_aa; extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; +extern const struct pnp_mode_ops pnp_conf_mode_a0a0_aa; extern const struct pnp_mode_ops pnp_conf_mode_870155_aa; #endif /* DEVICE_PNP_CONF_MODE_H */ diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index 271d4ef..92bd7a3 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -28,12 +28,30 @@ void pnp_enter_conf_mode_55(struct device *dev) outb(0x55, dev->path.pnp.port); } +void pnp_enter_conf_mode_6767(struct device *dev) +{ + outb(0x67, dev->path.pnp.port); + outb(0x67, dev->path.pnp.port); +} + +void pnp_enter_conf_mode_7777(struct device *dev) +{ + outb(0x77, dev->path.pnp.port); + outb(0x77, dev->path.pnp.port); +} + void pnp_enter_conf_mode_8787(struct device *dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } +void pnp_enter_conf_mode_a0a0(struct device *dev) +{ + outb(0xa0, dev->path.pnp.port); + outb(0xa0, dev->path.pnp.port); +} + void pnp_exit_conf_mode_aa(struct device *dev) { outb(0xaa, dev->path.pnp.port); @@ -63,11 +81,26 @@ const struct pnp_mode_ops pnp_conf_mode_55_aa = { .exit_conf_mode = pnp_exit_conf_mode_aa, }; +const struct pnp_mode_ops pnp_conf_mode_6767_aa = { + .enter_conf_mode = pnp_enter_conf_mode_6767, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + +const struct pnp_mode_ops pnp_conf_mode_7777_aa = { + .enter_conf_mode = pnp_enter_conf_mode_7777, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + const struct pnp_mode_ops pnp_conf_mode_8787_aa = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; +const struct pnp_mode_ops pnp_conf_mode_a0a0_aa = { + .enter_conf_mode = pnp_enter_conf_mode_a0a0, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + const struct pnp_mode_ops pnp_conf_mode_870155_aa = { .enter_conf_mode = pnp_enter_conf_mode_870155aa, .exit_conf_mode = pnp_exit_conf_mode_0202,

1 0

New patch to review for coreboot: e7c7d40 include/*: Clarify correct typing of 'struct device *'
by Edward O'Callaghan 01 Nov '14

01 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7311 -gerrit commit e7c7d40212388a8d8694c48c266ce55b48deb01b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 13:55:04 2014 +1100 include/*: Clarify correct typing of 'struct device *' Disambiguate 'device_t' into 'struct device *', 'pci_devfn_t' and 'pnp_devfn_t' component types where appropriate. Change-Id: I114341d745b8852217ca335a2c957917507de8f9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/cpu/amd/model_fxx_rev.h | 6 ++-- src/include/device/agp.h | 2 +- src/include/device/cardbus.h | 4 +-- src/include/device/device.h | 69 ++++++++++++++++++------------------- src/include/device/pci.h | 30 ++++++++-------- src/include/device/pci_ops.h | 24 ++++++------- src/include/device/pciexp.h | 2 +- src/include/device/pcix.h | 2 +- src/include/device/pnp.h | 38 ++++++++++---------- src/include/device/smbus.h | 54 ++++++++++++++--------------- src/include/reg_script.h | 6 ++-- 11 files changed, 118 insertions(+), 119 deletions(-) diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 1e85596..1044abc 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -59,7 +59,7 @@ static int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + pci_devnfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,2); val_old = pci_read_config32(dev, 0x80); val = val_old; @@ -101,7 +101,7 @@ static inline int is_cpu_pre_f2(void) static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; @@ -109,7 +109,7 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff0f) < 0x40f02; diff --git a/src/include/device/agp.h b/src/include/device/agp.h index be2b833..b3791fe 100644 --- a/src/include/device/agp.h +++ b/src/include/device/agp.h @@ -7,7 +7,7 @@ unsigned int agp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); -unsigned int agp_scan_bridge(device_t dev, unsigned int max); +unsigned int agp_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_agp_ops_bus; diff --git a/src/include/device/cardbus.h b/src/include/device/cardbus.h index 45ae24f..4443c15 100644 --- a/src/include/device/cardbus.h +++ b/src/include/device/cardbus.h @@ -5,8 +5,8 @@ #include <device/device.h> -void cardbus_read_resources(device_t dev); -void cardbus_enable_resources(device_t dev); +void cardbus_read_resources(struct device *dev); +void cardbus_enable_resources(struct device *dev); extern struct device_operations default_cardbus_ops_bus; diff --git a/src/include/device/device.h b/src/include/device/device.h index 3810716..750621e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -41,19 +41,19 @@ struct smbios_type11; struct acpi_rsdp; struct device_operations { - void (*read_resources)(device_t dev); - void (*set_resources)(device_t dev); - void (*enable_resources)(device_t dev); - void (*init)(device_t dev); - void (*final)(device_t dev); - unsigned int (*scan_bus)(device_t bus, unsigned int _max); - void (*enable)(device_t dev); - void (*disable)(device_t dev); - void (*set_link)(device_t dev, unsigned int link); + void (*read_resources)(struct device *dev); + void (*set_resources)(struct device *dev); + void (*enable_resources)(struct device *dev); + void (*init)(struct device *dev); + void (*final)(struct device *dev); + unsigned int (*scan_bus)(struct device *bus, unsigned int _max); + void (*enable)(struct device *dev); + void (*disable)(struct device *dev); + void (*set_link)(struct device *dev, unsigned int link); void (*reset_bus)(struct bus *bus); #if CONFIG_GENERATE_SMBIOS_TABLES - int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); - void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); + int (*get_smbios_data)(struct device *dev, int *handle, unsigned long *current); + void (*get_smbios_strings)(struct device *dev, struct smbios_type11 *t); #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); @@ -62,7 +62,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); + const struct pci_bus_operations * (*ops_pci_bus)(struct device *dev); const struct pnp_mode_ops *ops_pnp_mode; }; @@ -70,9 +70,8 @@ struct device_operations { struct bus { - - ROMSTAGE_CONST struct device * dev; /* This bridge device */ - ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct device *dev; /* This bridge device */ + ROMSTAGE_CONST struct device *children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ @@ -92,7 +91,7 @@ struct pci_irq_info { unsigned int ioapic_irq_pin; unsigned int ioapic_src_pin; unsigned int ioapic_dst_id; - unsigned int ioapic_flags; + unsigned int ioapic_flags; }; struct device { @@ -153,7 +152,7 @@ extern uint64_t uma_memory_size; #endif /* Generic device interface functions */ -device_t alloc_dev(struct bus *parent, struct device_path *path); +struct device *alloc_dev(struct bus *parent, struct device_path *path); void dev_initialize_chips(void); void dev_enumerate(void); void dev_configure(void); @@ -169,30 +168,30 @@ unsigned int scan_bus(struct device *bus, unsigned int _max); void assign_resources(struct bus *bus); void enumerate_static_device(void); void enumerate_static_devices(void); -const char *dev_name(device_t dev); -const char *dev_path(device_t dev); -u32 dev_path_encode(device_t dev); +const char *dev_name(struct device *dev); +const char *dev_path(struct device *dev); +u32 dev_path_encode(struct device *dev); const char *bus_path(struct bus *bus); -void dev_set_enabled(device_t dev, int enable); +void dev_set_enabled(struct device *dev, int enable); void disable_children(struct bus *bus); /* Option ROM helper functions */ void run_bios(struct device *dev, unsigned long addr); /* Helper functions */ -device_t find_dev_path(struct bus *parent, struct device_path *path); -device_t alloc_find_dev(struct bus *parent, struct device_path *path); -device_t dev_find_device (u16 vendor, u16 device, device_t from); -device_t dev_find_class (unsigned int class, device_t from); -device_t dev_find_slot (unsigned int bus, unsigned int devfn); -device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); -device_t dev_find_slot_pnp(u16 port, u16 device); -device_t dev_find_lapic(unsigned apic_id); +struct device *find_dev_path(struct bus *parent, struct device_path *path); +struct device *alloc_find_dev(struct bus *parent, struct device_path *path); +struct device *dev_find_device (u16 vendor, u16 device, struct device *from); +struct device *dev_find_class (unsigned int class, struct device *from); +struct device *dev_find_slot (unsigned int bus, unsigned int devfn); +struct device *dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +struct device *dev_find_slot_pnp(u16 port, u16 device); +struct device *dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); void remap_bsp_lapic(struct bus *cpu_bus); -device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); -void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread); +struct device *add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); +void set_cpu_topology(struct device *cpu, unsigned node, unsigned package, unsigned core, unsigned thread); #define amd_cpu_topology(cpu, node, core) \ set_cpu_topology(cpu, node, 0, core, 0) @@ -201,7 +200,7 @@ void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned co set_cpu_topology(cpu, 0, package, core, thread) /* Debug functions */ -void print_resource_tree(struct device * root, int debug_level, +void print_resource_tree(struct device *root, int debug_level, const char *msg); void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum); void show_devs_subtree(struct device *root, int debug_level, const char *msg); @@ -220,9 +219,9 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); -unsigned int scan_static_bus(device_t bus, unsigned int _max); +unsigned int scan_static_bus(struct device *bus, unsigned int _max); -void fixed_mem_resource(device_t dev, unsigned long index, +void fixed_mem_resource(struct device *dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); @@ -251,7 +250,7 @@ u32 find_pci_tolm(struct bus *bus); ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); -ROMSTAGE_CONST struct device *dev_find_next_pci_device( +ROMSTAGE_CONST struct device * dev_find_next_pci_device( ROMSTAGE_CONST struct device *previous_dev); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 0670da4..3688322 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -32,7 +32,7 @@ /* Common pci operations without a standard interface */ struct pci_operations { /* set the Subsystem IDs for the PCI device */ - void (*set_subsystem)(device_t dev, unsigned vendor, unsigned device); + void (*set_subsystem)(struct device *dev, unsigned vendor, unsigned device); }; /* Common pci bus operations */ @@ -62,35 +62,35 @@ extern struct pci_driver epci_drivers[]; extern struct device_operations default_pci_ops_dev; extern struct device_operations default_pci_ops_bus; -void pci_dev_read_resources(device_t dev); -void pci_bus_read_resources(device_t dev); -void pci_dev_set_resources(device_t dev); -void pci_dev_enable_resources(device_t dev); -void pci_bus_enable_resources(device_t dev); +void pci_dev_read_resources(struct device *dev); +void pci_bus_read_resources(struct device *dev); +void pci_dev_set_resources(struct device *dev); +void pci_dev_enable_resources(struct device *dev); +void pci_bus_enable_resources(struct device *dev); void pci_bus_reset(struct bus *bus); -device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); -unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, +struct device *pci_probe_dev(struct device *dev, struct bus *bus, unsigned devfn); +unsigned int do_pci_scan_bridge(struct device *bus, unsigned int max, unsigned int (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max)); -unsigned int pci_scan_bridge(device_t bus, unsigned int max); +unsigned int pci_scan_bridge(struct device *bus, unsigned int max); unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); uint8_t pci_moving_config8(struct device *dev, unsigned reg); uint16_t pci_moving_config16(struct device *dev, unsigned reg); uint32_t pci_moving_config32(struct device *dev, unsigned reg); struct resource *pci_get_resource(struct device *dev, unsigned long index); -void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); +void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); -unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev); +unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev); const char * pin_to_str(int pin); -int get_pci_irq_pins(device_t dev, device_t *parent_bdg); +int get_pci_irq_pins(struct device *dev, struct device **parent_bdg); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -static inline const struct pci_operations *ops_pci(device_t dev) +static inline const struct pci_operations *ops_pci(struct device *dev) { const struct pci_operations *pops; pops = 0; @@ -106,8 +106,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); #else /* !__PRE_RAM__ */ -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); -unsigned pci_find_capability(device_t dev, unsigned cap); +unsigned pci_find_next_capability(struct device *dev, unsigned cap, unsigned last); +unsigned pci_find_capability(struct device *dev, unsigned cap); #endif /* __PRE_RAM__ */ void pci_early_bridge_init(void); diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index ae58a01..920475a 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -6,20 +6,20 @@ #include <arch/pci_ops.h> #ifndef __SIMPLE_DEVICE__ -u8 pci_read_config8(device_t dev, unsigned int where); -u16 pci_read_config16(device_t dev, unsigned int where); -u32 pci_read_config32(device_t dev, unsigned int where); -void pci_write_config8(device_t dev, unsigned int where, u8 val); -void pci_write_config16(device_t dev, unsigned int where, u16 val); -void pci_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_read_config8(struct device *dev, unsigned int where); +u16 pci_read_config16(struct device *dev, unsigned int where); +u32 pci_read_config32(struct device *dev, unsigned int where); +void pci_write_config8(struct device *dev, unsigned int where, u8 val); +void pci_write_config16(struct device *dev, unsigned int where, u16 val); +void pci_write_config32(struct device *dev, unsigned int where, u32 val); #if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(device_t dev, unsigned int where); -u16 pci_mmio_read_config16(device_t dev, unsigned int where); -u32 pci_mmio_read_config32(device_t dev, unsigned int where); -void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val); -void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val); -void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_mmio_read_config8(struct device *dev, unsigned int where); +u16 pci_mmio_read_config16(struct device *dev, unsigned int where); +u32 pci_mmio_read_config32(struct device *dev, unsigned int where); +void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val); +void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val); +void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val); #endif #endif diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 87a5002..c7ff4f5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -11,7 +11,7 @@ enum aspm_type { unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); +unsigned int pciexp_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 4ffab5b..8cc83df 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -4,7 +4,7 @@ unsigned int pcix_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); -unsigned int pcix_scan_bridge(device_t dev, unsigned int max); +unsigned int pcix_scan_bridge(struct device *dev, unsigned int max); const char *pcix_speed(u16 sstatus); extern struct device_operations default_pcix_ops_bus; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index d0d6fa3..9290056 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -9,21 +9,21 @@ #ifndef __SIMPLE_DEVICE__ /* Primitive PNP resource manipulation */ -void pnp_write_config(device_t dev, u8 reg, u8 value); -u8 pnp_read_config(device_t dev, u8 reg); -void pnp_set_logical_device(device_t dev); -void pnp_set_enable(device_t dev, int enable); -int pnp_read_enable(device_t dev); -void pnp_set_iobase(device_t dev, u8 index, u16 iobase); -void pnp_set_irq(device_t dev, u8 index, u8 irq); -void pnp_set_drq(device_t dev, u8 index, u8 drq); +void pnp_write_config(struct device *dev, u8 reg, u8 value); +u8 pnp_read_config(struct device *dev, u8 reg); +void pnp_set_logical_device(struct device *dev); +void pnp_set_enable(struct device *dev, int enable); +int pnp_read_enable(struct device *dev); +void pnp_set_iobase(struct device *dev, u8 index, u16 iobase); +void pnp_set_irq(struct device *dev, u8 index, u8 irq); +void pnp_set_drq(struct device *dev, u8 index, u8 drq); /* PNP device operations */ -void pnp_read_resources(device_t dev); -void pnp_set_resources(device_t dev); -void pnp_enable_resources(device_t dev); -void pnp_enable(device_t dev); -void pnp_alt_enable(device_t dev); +void pnp_read_resources(struct device *dev); +void pnp_set_resources(struct device *dev); +void pnp_enable_resources(struct device *dev); +void pnp_enable(struct device *dev); +void pnp_alt_enable(struct device *dev); extern struct device_operations pnp_ops; @@ -52,16 +52,16 @@ struct pnp_info { #define PNP_MSC10 0x1000 struct io_info io0, io1, io2, io3; }; -struct resource *pnp_get_resource(device_t dev, unsigned index); +struct resource *pnp_get_resource(struct device *dev, unsigned index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); struct pnp_mode_ops { - void (*enter_conf_mode)(device_t dev); - void (*exit_conf_mode)(device_t dev); + void (*enter_conf_mode)(struct device *dev); + void (*exit_conf_mode)(struct device *dev); }; -void pnp_enter_conf_mode(device_t dev); -void pnp_exit_conf_mode(device_t dev); +void pnp_enter_conf_mode(struct device *dev); +void pnp_exit_conf_mode(struct device *dev); #endif /* ! __SIMPLE_DEVICE__ */ -#endif /* DEVICE_PNP_H */ +#endif /*devICE_PNP_H */ diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 073d7e2..7002459 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -8,17 +8,17 @@ /* Common SMBus bus operations */ struct smbus_bus_operations { - int (*quick_read) (device_t dev); - int (*quick_write) (device_t dev); - int (*recv_byte) (device_t dev); - int (*send_byte) (device_t dev, u8 value); - int (*read_byte) (device_t dev, u8 addr); - int (*write_byte) (device_t dev, u8 addr, u8 value); - int (*read_word) (device_t dev, u8 addr); - int (*write_word) (device_t dev, u8 addr, u16 value); - int (*process_call)(device_t dev, u8 cmd, u16 data); - int (*block_read) (device_t dev, u8 cmd, u8 bytes, u8 *buffer); - int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer); + int (*quick_read) (struct device *dev); + int (*quick_write) (struct device *dev); + int (*recv_byte) (struct device *dev); + int (*send_byte) (struct device *dev, u8 value); + int (*read_byte) (struct device *dev, u8 addr); + int (*write_byte) (struct device *dev, u8 addr, u8 value); + int (*read_word) (struct device *dev, u8 addr); + int (*write_word) (struct device *dev, u8 addr, u16 value); + int (*process_call)(struct device *dev, u8 cmd, u16 data); + int (*block_read) (struct device *dev, u8 cmd, u8 bytes, u8 *buffer); + int (*block_write) (struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); }; static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) @@ -32,19 +32,19 @@ static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) return bops; } -struct bus *get_pbus_smbus(device_t dev); -int smbus_set_link(device_t dev); - -int smbus_quick_read(device_t dev); -int smbus_quick_write(device_t dev); -int smbus_recv_byte(device_t dev); -int smbus_send_byte(device_t dev, u8 byte); -int smbus_read_byte(device_t dev, u8 addr); -int smbus_write_byte(device_t dev, u8 addr, u8 val); -int smbus_read_word(device_t dev, u8 addr); -int smbus_write_word(device_t dev, u8 addr, u16 val); -int smbus_process_call(device_t dev, u8 cmd, u16 data); -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); -int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); - -#endif /* DEVICE_SMBUS_H */ +struct bus *get_pbus_smbus(struct device *dev); +int smbus_set_link(struct device *dev); + +int smbus_quick_read(struct device *dev); +int smbus_quick_write(struct device *dev); +int smbus_recv_byte(struct device *dev); +int smbus_send_byte(struct device *dev, u8 byte); +int smbus_read_byte(struct device *dev, u8 addr); +int smbus_write_byte(struct device *dev, u8 addr, u8 val); +int smbus_read_word(struct device *dev, u8 addr); +int smbus_write_word(struct device *dev, u8 addr, u16 val); +int smbus_process_call(struct device *dev, u8 cmd, u16 data); +int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); + +#endif /*devICE_SMBUS_H */ diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 97b4fb0..71be7c2 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -34,7 +34,7 @@ * are employed: * - Chaining of tables that allow runtime tables to chain to compile-time * tables. - * - Notion of current device (device_t) being worked on. This allows for + * - Notion of current device (struct device *) being worked on. This allows for * PCI config, io, and mmio on a particular device's resources. * * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push @@ -80,7 +80,7 @@ struct reg_script { union { uint32_t id; const struct reg_script *next; - device_t dev; + struct device *dev; unsigned int res_index; }; }; @@ -334,6 +334,6 @@ struct reg_script { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) void reg_script_run(const struct reg_script *script); -void reg_script_run_on_dev(device_t dev, const struct reg_script *step); +void reg_script_run_on_dev(struct device *dev, const struct reg_script *step); #endif /* REG_SCRIPT_H */

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New patch to review for coreboot: f23c58c superio/ite: Use common dispatch for pnp entry/exit functions
by Edward O'Callaghan 01 Nov '14

01 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7310 -gerrit commit f23c58c06af6fe06facb01857e060c87859a6401 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 12:11:58 2014 +1100 superio/ite: Use common dispatch for pnp entry/exit functions We already have these implemented under superio/common, use those instead of this copy-paste syndrom. Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8712f/superio.c | 22 +--------------------- src/superio/ite/it8716f/superio.c | 22 +--------------------- src/superio/ite/it8772f/superio.c | 22 +--------------------- 3 files changed, 3 insertions(+), 63 deletions(-) diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 9dd9f85..7a881fa 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -26,21 +26,6 @@ #include <stdlib.h> #include "it8712f.h" -static void pnp_enter_ext_func_mode(struct device *dev) -{ - u16 port = dev->path.pnp.port; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void pnp_exit_ext_func_mode(struct device *dev) -{ - pnp_write_config(dev, 0x02, 0x02); -} - static void it8712f_init(struct device *dev) { @@ -69,18 +54,13 @@ static void it8712f_init(struct device *dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = it8712f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 874061f..25ddd24 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -29,21 +29,6 @@ #include <stdlib.h> #include "it8716f.h" -static void pnp_enter_ext_func_mode(struct device *dev) -{ - u16 port = dev->path.pnp.port; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void pnp_exit_ext_func_mode(struct device *dev) -{ - pnp_write_config(dev, 0x02, 0x02); -} - #if !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL static void pnp_write_index(u16 port_base, u8 reg, u8 value) { @@ -93,18 +78,13 @@ static void it8716f_init(struct device *dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = it8716f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 143cc30..6a1d3fa 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -26,21 +26,6 @@ #include "chip.h" /* FIXME */ #include "it8772f.h" -static void pnp_enter_ext_func_mode(struct device *dev) -{ - u16 port = dev->path.pnp.port; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void pnp_exit_ext_func_mode(struct device *dev) -{ - pnp_write_config(dev, 0x02, 0x02); -} - static inline u8 it8772f_envc_read(struct resource *res, u8 addr) { outb(addr, res->base + 5); @@ -187,18 +172,13 @@ static void it8772f_init(struct device *dev) } } -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = it8772f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, }; static struct pnp_info pnp_dev_info[] = {

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Patch set updated for coreboot: 8385c82 superio/fintek/f81216h: Implement device support
by Edward O'Callaghan 01 Nov '14

01 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7309 -gerrit commit 8385c82a9b7d3d8732dbe4dae60ce36ea751d49c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 10:19:58 2014 +1100 superio/fintek/f81216h: Implement device support Change-Id: I20a34b569f109dd12af29e9e0cee8f7f6b8ebb80 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/Kconfig | 4 + src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f81216h/Makefile.inc | 22 ++++++ src/superio/fintek/f81216h/chip.h | 40 ++++++++++ src/superio/fintek/f81216h/early_serial.c | 68 +++++++++++++++++ src/superio/fintek/f81216h/f81216h.h | 46 ++++++++++++ src/superio/fintek/f81216h/superio.c | 119 ++++++++++++++++++++++++++++++ 7 files changed, 300 insertions(+) diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index f577898..e9cbe74 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -47,6 +47,10 @@ config SUPERIO_FINTEK_F71889 bool select SUPERIO_FINTEK_COMMON_ROMSTAGE +config SUPERIO_FINTEK_F81216H + bool +# N.B. 'special romstage' + config SUPERIO_FINTEK_F81865F bool select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 1b11336..5756393 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -26,4 +26,5 @@ subdirs-y += f71863fg subdirs-y += f71869ad subdirs-y += f71872 subdirs-y += f71889 +subdirs-y += f81216h subdirs-y += f81865f diff --git a/src/superio/fintek/f81216h/Makefile.inc b/src/superio/fintek/f81216h/Makefile.inc new file mode 100644 index 0000000..f473ef2 --- /dev/null +++ b/src/superio/fintek/f81216h/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += superio.c diff --git a/src/superio/fintek/f81216h/chip.h b/src/superio/fintek/f81216h/chip.h new file mode 100644 index 0000000..9b54ce1 --- /dev/null +++ b/src/superio/fintek/f81216h/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81216H_CHIP_H +#define SUPERIO_FINTEK_F81216H_CHIP_H + +#include <stdint.h> + +/* Member variables are defined in devicetree.cb. */ +struct superio_fintek_f81216h_config { + /** + * KEY1 KEY0 Enter key + * 0 0 0x77 (default) + * 0 1 0xA0 + * 1 0 0x87 + * 1 1 0x67 + * + * See page 17 of data sheet. + */ + uint8_t conf_key_mode; +}; + +#endif /* SUPERIO_FINTEK_F81216H_CHIP_H */ diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c new file mode 100644 index 0000000..6b667df --- /dev/null +++ b/src/superio/fintek/f81216h/early_serial.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "fintek.h" + +static u8 f81216h_entry_key; +#define FINTEK_EXIT_KEY 0xAA + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(f81216h_entry_key, port); + outb(f81216h_entry_key, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, enum mode_key k) +{ + switch(k) { + MODE_6767: + f81216h_entry_key = 0x67; + break; + MODE_7777: + f81216h_entry_key = 0x77; + break; + MODE_8787: + f81216h_entry_key = 0x87; + break; + MODE_A0A0: + f81216h_entry_key = 0xa0; + break; + default: + f81216h_entry_key = 0x77; /* (safe to be hw default) */ + } + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h new file mode 100644 index 0000000..37e7753 --- /dev/null +++ b/src/superio/fintek/f81216h/f81216h.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81216H_H +#define SUPERIO_FINTEK_F81216H_H + +/* Logical Device Numbers (LDN). */ +#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */ +#define F81216H_SP2 0x01 /* UART2 */ +#define F81216H_SP3 0x02 /* UART3 */ +#define F81216H_SP4 0x03 /* UART4 */ +#define F81216H_WDT 0x08 /* WDT */ + +/** + * The PNP config entry key is parameterised + * by two bits on this Super I/O with 0x77 as + * the default key. + * See page 17 of data sheet for details. + */ +enum { + MODE_6767, + MODE_7777, + MODE_8787, + MODE_A0A0, +} mode_key; + +void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, enum mode_key k); + +#endif /* SUPERIO_FINTEK_F81216H_H */ diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c new file mode 100644 index 0000000..eed165a --- /dev/null +++ b/src/superio/fintek/f81216h/superio.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> + +#include "chip.h" +#include "f81216h.h" + + +static void pnp_enter_ext_func_mode(struct device *dev) +{ + const struct superio_fintek_f81216h_config *conf = dev->chip_info; + + u8 key; + + /** + * KEY1 KEY0 Enter key + * 0 0 0x77 (default) + * 0 1 0xA0 + * 1 0 0x87 + * 1 1 0x67 + * + * See page 17 of data sheet. + */ + switch(conf->conf_key_mode) { + case 0: + key = 0x77; /* (default) */ + break; + case 1: + key = 0xa0; + break; + case 2: + key = 0x87; + break; + case 3: + key = 0x67; + break; + default: + key = 0x77; /* safe to be hw default */ + } + + outb(key, dev->path.pnp.port); + outb(key, dev->path.pnp.port); +} + +static void pnp_exit_ext_func_mode(struct device *dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = pnp_enter_ext_func_mode, + .exit_conf_mode = pnp_exit_ext_func_mode, +}; + + +static void f81216h_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case F81216H_SP1: + case F81216H_SP2: + case F81216H_SP3: + case F81216H_SP4: + case F81216H_WDT: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81216h_init, + .ops_pnp_mode = &pnp_conf_mode_ops, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, F81216H_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F81216H_WDT, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81216h_ops = { + CHIP_NAME("Fintek F81216H/D/DG/F/FG Super I/O") + .enable_dev = enable_dev +};

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coreboot-gerrit November 2014