coreboot-gerrit November 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: b14bf88 superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO's
by gerrit＠coreboot.org 01 Nov '14

01 Nov '14

the following patch was just integrated into master: commit b14bf88697950c63fa786cbd70dab3070e464807 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 09:14:58 2014 +1100 superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO's Super I/O manufactures have found new and innovative ways to enter and exit out of LDN config in PNP config space. Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/7308 for details. -gerrit

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Patch set updated for coreboot: 38f3ba9 include/*: Clarify correct typing of 'struct device *'
by Edward O'Callaghan 01 Nov '14

01 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7311 -gerrit commit 38f3ba9e6339a04288d9a7b552cebf8c7f0bb842 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 1 13:55:04 2014 +1100 include/*: Clarify correct typing of 'struct device *' Disambiguate 'device_t' into 'struct device *', 'pci_devfn_t' and 'pnp_devfn_t' component types where appropriate. Change-Id: I114341d745b8852217ca335a2c957917507de8f9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/cpu/amd/model_fxx_rev.h | 7 ++-- src/include/device/agp.h | 2 +- src/include/device/cardbus.h | 4 +-- src/include/device/device.h | 69 ++++++++++++++++++------------------- src/include/device/pci.h | 30 ++++++++-------- src/include/device/pci_ops.h | 24 ++++++------- src/include/device/pciexp.h | 2 +- src/include/device/pcix.h | 2 +- src/include/device/pnp.h | 38 ++++++++++---------- src/include/device/smbus.h | 54 ++++++++++++++--------------- src/include/reg_script.h | 6 ++-- 11 files changed, 119 insertions(+), 119 deletions(-) diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 1e85596..f3d7f5e 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -1,4 +1,5 @@ #include <arch/cpu.h> +#include <arch/io.h> int init_processor_name(void); @@ -59,7 +60,7 @@ static int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + pci_devnfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,2); val_old = pci_read_config32(dev, 0x80); val = val_old; @@ -101,7 +102,7 @@ static inline int is_cpu_pre_f2(void) static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; @@ -109,7 +110,7 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff0f) < 0x40f02; diff --git a/src/include/device/agp.h b/src/include/device/agp.h index be2b833..b3791fe 100644 --- a/src/include/device/agp.h +++ b/src/include/device/agp.h @@ -7,7 +7,7 @@ unsigned int agp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); -unsigned int agp_scan_bridge(device_t dev, unsigned int max); +unsigned int agp_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_agp_ops_bus; diff --git a/src/include/device/cardbus.h b/src/include/device/cardbus.h index 45ae24f..4443c15 100644 --- a/src/include/device/cardbus.h +++ b/src/include/device/cardbus.h @@ -5,8 +5,8 @@ #include <device/device.h> -void cardbus_read_resources(device_t dev); -void cardbus_enable_resources(device_t dev); +void cardbus_read_resources(struct device *dev); +void cardbus_enable_resources(struct device *dev); extern struct device_operations default_cardbus_ops_bus; diff --git a/src/include/device/device.h b/src/include/device/device.h index c67205c..fe8dbed 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -41,19 +41,19 @@ struct smbios_type11; struct acpi_rsdp; struct device_operations { - void (*read_resources)(device_t dev); - void (*set_resources)(device_t dev); - void (*enable_resources)(device_t dev); - void (*init)(device_t dev); - void (*final)(device_t dev); - unsigned int (*scan_bus)(device_t bus, unsigned int _max); - void (*enable)(device_t dev); - void (*disable)(device_t dev); - void (*set_link)(device_t dev, unsigned int link); + void (*read_resources)(struct device *dev); + void (*set_resources)(struct device *dev); + void (*enable_resources)(struct device *dev); + void (*init)(struct device *dev); + void (*final)(struct device *dev); + unsigned int (*scan_bus)(struct device *bus, unsigned int _max); + void (*enable)(struct device *dev); + void (*disable)(struct device *dev); + void (*set_link)(struct device *dev, unsigned int link); void (*reset_bus)(struct bus *bus); #if CONFIG_GENERATE_SMBIOS_TABLES - int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); - void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); + int (*get_smbios_data)(struct device *dev, int *handle, unsigned long *current); + void (*get_smbios_strings)(struct device *dev, struct smbios_type11 *t); #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); @@ -62,7 +62,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; - const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); + const struct pci_bus_operations * (*ops_pci_bus)(struct device *dev); const struct pnp_mode_ops *ops_pnp_mode; }; @@ -76,9 +76,8 @@ static inline void device_noop(struct device *dev) {} struct bus { - - ROMSTAGE_CONST struct device * dev; /* This bridge device */ - ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct device *dev; /* This bridge device */ + ROMSTAGE_CONST struct device *children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ unsigned char link_num; /* The index of this link */ @@ -98,7 +97,7 @@ struct pci_irq_info { unsigned int ioapic_irq_pin; unsigned int ioapic_src_pin; unsigned int ioapic_dst_id; - unsigned int ioapic_flags; + unsigned int ioapic_flags; }; struct device { @@ -159,7 +158,7 @@ extern uint64_t uma_memory_size; #endif /* Generic device interface functions */ -device_t alloc_dev(struct bus *parent, struct device_path *path); +struct device *alloc_dev(struct bus *parent, struct device_path *path); void dev_initialize_chips(void); void dev_enumerate(void); void dev_configure(void); @@ -175,30 +174,30 @@ unsigned int scan_bus(struct device *bus, unsigned int _max); void assign_resources(struct bus *bus); void enumerate_static_device(void); void enumerate_static_devices(void); -const char *dev_name(device_t dev); -const char *dev_path(device_t dev); -u32 dev_path_encode(device_t dev); +const char *dev_name(struct device *dev); +const char *dev_path(struct device *dev); +u32 dev_path_encode(struct device *dev); const char *bus_path(struct bus *bus); -void dev_set_enabled(device_t dev, int enable); +void dev_set_enabled(struct device *dev, int enable); void disable_children(struct bus *bus); /* Option ROM helper functions */ void run_bios(struct device *dev, unsigned long addr); /* Helper functions */ -device_t find_dev_path(struct bus *parent, struct device_path *path); -device_t alloc_find_dev(struct bus *parent, struct device_path *path); -device_t dev_find_device (u16 vendor, u16 device, device_t from); -device_t dev_find_class (unsigned int class, device_t from); -device_t dev_find_slot (unsigned int bus, unsigned int devfn); -device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); -device_t dev_find_slot_pnp(u16 port, u16 device); -device_t dev_find_lapic(unsigned apic_id); +struct device *find_dev_path(struct bus *parent, struct device_path *path); +struct device *alloc_find_dev(struct bus *parent, struct device_path *path); +struct device *dev_find_device (u16 vendor, u16 device, struct device *from); +struct device *dev_find_class (unsigned int class, struct device *from); +struct device *dev_find_slot (unsigned int bus, unsigned int devfn); +struct device *dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +struct device *dev_find_slot_pnp(u16 port, u16 device); +struct device *dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); void remap_bsp_lapic(struct bus *cpu_bus); -device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); -void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread); +struct device *add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); +void set_cpu_topology(struct device *cpu, unsigned node, unsigned package, unsigned core, unsigned thread); #define amd_cpu_topology(cpu, node, core) \ set_cpu_topology(cpu, node, 0, core, 0) @@ -207,7 +206,7 @@ void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned co set_cpu_topology(cpu, 0, package, core, thread) /* Debug functions */ -void print_resource_tree(struct device * root, int debug_level, +void print_resource_tree(struct device *root, int debug_level, const char *msg); void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum); void show_devs_subtree(struct device *root, int debug_level, const char *msg); @@ -226,9 +225,9 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); -unsigned int scan_static_bus(device_t bus, unsigned int _max); +unsigned int scan_static_bus(struct device *bus, unsigned int _max); -void fixed_mem_resource(device_t dev, unsigned long index, +void fixed_mem_resource(struct device *dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); @@ -257,7 +256,7 @@ u32 find_pci_tolm(struct bus *bus); ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); -ROMSTAGE_CONST struct device *dev_find_next_pci_device( +ROMSTAGE_CONST struct device * dev_find_next_pci_device( ROMSTAGE_CONST struct device *previous_dev); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 0670da4..3688322 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -32,7 +32,7 @@ /* Common pci operations without a standard interface */ struct pci_operations { /* set the Subsystem IDs for the PCI device */ - void (*set_subsystem)(device_t dev, unsigned vendor, unsigned device); + void (*set_subsystem)(struct device *dev, unsigned vendor, unsigned device); }; /* Common pci bus operations */ @@ -62,35 +62,35 @@ extern struct pci_driver epci_drivers[]; extern struct device_operations default_pci_ops_dev; extern struct device_operations default_pci_ops_bus; -void pci_dev_read_resources(device_t dev); -void pci_bus_read_resources(device_t dev); -void pci_dev_set_resources(device_t dev); -void pci_dev_enable_resources(device_t dev); -void pci_bus_enable_resources(device_t dev); +void pci_dev_read_resources(struct device *dev); +void pci_bus_read_resources(struct device *dev); +void pci_dev_set_resources(struct device *dev); +void pci_dev_enable_resources(struct device *dev); +void pci_bus_enable_resources(struct device *dev); void pci_bus_reset(struct bus *bus); -device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); -unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, +struct device *pci_probe_dev(struct device *dev, struct bus *bus, unsigned devfn); +unsigned int do_pci_scan_bridge(struct device *bus, unsigned int max, unsigned int (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max)); -unsigned int pci_scan_bridge(device_t bus, unsigned int max); +unsigned int pci_scan_bridge(struct device *bus, unsigned int max); unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); uint8_t pci_moving_config8(struct device *dev, unsigned reg); uint16_t pci_moving_config16(struct device *dev, unsigned reg); uint32_t pci_moving_config32(struct device *dev, unsigned reg); struct resource *pci_get_resource(struct device *dev, unsigned long index); -void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); +void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); -unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev); +unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev); const char * pin_to_str(int pin); -int get_pci_irq_pins(device_t dev, device_t *parent_bdg); +int get_pci_irq_pins(struct device *dev, struct device **parent_bdg); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -static inline const struct pci_operations *ops_pci(device_t dev) +static inline const struct pci_operations *ops_pci(struct device *dev) { const struct pci_operations *pops; pops = 0; @@ -106,8 +106,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); #else /* !__PRE_RAM__ */ -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); -unsigned pci_find_capability(device_t dev, unsigned cap); +unsigned pci_find_next_capability(struct device *dev, unsigned cap, unsigned last); +unsigned pci_find_capability(struct device *dev, unsigned cap); #endif /* __PRE_RAM__ */ void pci_early_bridge_init(void); diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index ae58a01..920475a 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -6,20 +6,20 @@ #include <arch/pci_ops.h> #ifndef __SIMPLE_DEVICE__ -u8 pci_read_config8(device_t dev, unsigned int where); -u16 pci_read_config16(device_t dev, unsigned int where); -u32 pci_read_config32(device_t dev, unsigned int where); -void pci_write_config8(device_t dev, unsigned int where, u8 val); -void pci_write_config16(device_t dev, unsigned int where, u16 val); -void pci_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_read_config8(struct device *dev, unsigned int where); +u16 pci_read_config16(struct device *dev, unsigned int where); +u32 pci_read_config32(struct device *dev, unsigned int where); +void pci_write_config8(struct device *dev, unsigned int where, u8 val); +void pci_write_config16(struct device *dev, unsigned int where, u16 val); +void pci_write_config32(struct device *dev, unsigned int where, u32 val); #if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(device_t dev, unsigned int where); -u16 pci_mmio_read_config16(device_t dev, unsigned int where); -u32 pci_mmio_read_config32(device_t dev, unsigned int where); -void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val); -void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val); -void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_mmio_read_config8(struct device *dev, unsigned int where); +u16 pci_mmio_read_config16(struct device *dev, unsigned int where); +u32 pci_mmio_read_config32(struct device *dev, unsigned int where); +void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val); +void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val); +void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val); #endif #endif diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 87a5002..c7ff4f5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -11,7 +11,7 @@ enum aspm_type { unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); +unsigned int pciexp_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 4ffab5b..8cc83df 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -4,7 +4,7 @@ unsigned int pcix_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); -unsigned int pcix_scan_bridge(device_t dev, unsigned int max); +unsigned int pcix_scan_bridge(struct device *dev, unsigned int max); const char *pcix_speed(u16 sstatus); extern struct device_operations default_pcix_ops_bus; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index d0d6fa3..9290056 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -9,21 +9,21 @@ #ifndef __SIMPLE_DEVICE__ /* Primitive PNP resource manipulation */ -void pnp_write_config(device_t dev, u8 reg, u8 value); -u8 pnp_read_config(device_t dev, u8 reg); -void pnp_set_logical_device(device_t dev); -void pnp_set_enable(device_t dev, int enable); -int pnp_read_enable(device_t dev); -void pnp_set_iobase(device_t dev, u8 index, u16 iobase); -void pnp_set_irq(device_t dev, u8 index, u8 irq); -void pnp_set_drq(device_t dev, u8 index, u8 drq); +void pnp_write_config(struct device *dev, u8 reg, u8 value); +u8 pnp_read_config(struct device *dev, u8 reg); +void pnp_set_logical_device(struct device *dev); +void pnp_set_enable(struct device *dev, int enable); +int pnp_read_enable(struct device *dev); +void pnp_set_iobase(struct device *dev, u8 index, u16 iobase); +void pnp_set_irq(struct device *dev, u8 index, u8 irq); +void pnp_set_drq(struct device *dev, u8 index, u8 drq); /* PNP device operations */ -void pnp_read_resources(device_t dev); -void pnp_set_resources(device_t dev); -void pnp_enable_resources(device_t dev); -void pnp_enable(device_t dev); -void pnp_alt_enable(device_t dev); +void pnp_read_resources(struct device *dev); +void pnp_set_resources(struct device *dev); +void pnp_enable_resources(struct device *dev); +void pnp_enable(struct device *dev); +void pnp_alt_enable(struct device *dev); extern struct device_operations pnp_ops; @@ -52,16 +52,16 @@ struct pnp_info { #define PNP_MSC10 0x1000 struct io_info io0, io1, io2, io3; }; -struct resource *pnp_get_resource(device_t dev, unsigned index); +struct resource *pnp_get_resource(struct device *dev, unsigned index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); struct pnp_mode_ops { - void (*enter_conf_mode)(device_t dev); - void (*exit_conf_mode)(device_t dev); + void (*enter_conf_mode)(struct device *dev); + void (*exit_conf_mode)(struct device *dev); }; -void pnp_enter_conf_mode(device_t dev); -void pnp_exit_conf_mode(device_t dev); +void pnp_enter_conf_mode(struct device *dev); +void pnp_exit_conf_mode(struct device *dev); #endif /* ! __SIMPLE_DEVICE__ */ -#endif /* DEVICE_PNP_H */ +#endif /*devICE_PNP_H */ diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 073d7e2..7002459 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -8,17 +8,17 @@ /* Common SMBus bus operations */ struct smbus_bus_operations { - int (*quick_read) (device_t dev); - int (*quick_write) (device_t dev); - int (*recv_byte) (device_t dev); - int (*send_byte) (device_t dev, u8 value); - int (*read_byte) (device_t dev, u8 addr); - int (*write_byte) (device_t dev, u8 addr, u8 value); - int (*read_word) (device_t dev, u8 addr); - int (*write_word) (device_t dev, u8 addr, u16 value); - int (*process_call)(device_t dev, u8 cmd, u16 data); - int (*block_read) (device_t dev, u8 cmd, u8 bytes, u8 *buffer); - int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer); + int (*quick_read) (struct device *dev); + int (*quick_write) (struct device *dev); + int (*recv_byte) (struct device *dev); + int (*send_byte) (struct device *dev, u8 value); + int (*read_byte) (struct device *dev, u8 addr); + int (*write_byte) (struct device *dev, u8 addr, u8 value); + int (*read_word) (struct device *dev, u8 addr); + int (*write_word) (struct device *dev, u8 addr, u16 value); + int (*process_call)(struct device *dev, u8 cmd, u16 data); + int (*block_read) (struct device *dev, u8 cmd, u8 bytes, u8 *buffer); + int (*block_write) (struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); }; static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) @@ -32,19 +32,19 @@ static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) return bops; } -struct bus *get_pbus_smbus(device_t dev); -int smbus_set_link(device_t dev); - -int smbus_quick_read(device_t dev); -int smbus_quick_write(device_t dev); -int smbus_recv_byte(device_t dev); -int smbus_send_byte(device_t dev, u8 byte); -int smbus_read_byte(device_t dev, u8 addr); -int smbus_write_byte(device_t dev, u8 addr, u8 val); -int smbus_read_word(device_t dev, u8 addr); -int smbus_write_word(device_t dev, u8 addr, u16 val); -int smbus_process_call(device_t dev, u8 cmd, u16 data); -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); -int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); - -#endif /* DEVICE_SMBUS_H */ +struct bus *get_pbus_smbus(struct device *dev); +int smbus_set_link(struct device *dev); + +int smbus_quick_read(struct device *dev); +int smbus_quick_write(struct device *dev); +int smbus_recv_byte(struct device *dev); +int smbus_send_byte(struct device *dev, u8 byte); +int smbus_read_byte(struct device *dev, u8 addr); +int smbus_write_byte(struct device *dev, u8 addr, u8 val); +int smbus_read_word(struct device *dev, u8 addr); +int smbus_write_word(struct device *dev, u8 addr, u16 val); +int smbus_process_call(struct device *dev, u8 cmd, u16 data); +int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); + +#endif /*devICE_SMBUS_H */ diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 97b4fb0..71be7c2 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -34,7 +34,7 @@ * are employed: * - Chaining of tables that allow runtime tables to chain to compile-time * tables. - * - Notion of current device (device_t) being worked on. This allows for + * - Notion of current device (struct device *) being worked on. This allows for * PCI config, io, and mmio on a particular device's resources. * * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push @@ -80,7 +80,7 @@ struct reg_script { union { uint32_t id; const struct reg_script *next; - device_t dev; + struct device *dev; unsigned int res_index; }; }; @@ -334,6 +334,6 @@ struct reg_script { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) void reg_script_run(const struct reg_script *script); -void reg_script_run_on_dev(device_t dev, const struct reg_script *step); +void reg_script_run_on_dev(struct device *dev, const struct reg_script *step); #endif /* REG_SCRIPT_H */

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Patch merged into coreboot/master: d204073 northbridge/via: Use DEVICE_NOOP macro over dummy symbol
by gerrit＠coreboot.org 01 Nov '14

01 Nov '14

the following patch was just integrated into master: commit d2040737a9c3e07fee5392079dea88988ad8c56c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 08:26:21 2014 +1100 northbridge/via: Use DEVICE_NOOP macro over dummy symbol Change-Id: Ib9d0fae363c5c1fbed3a63cb8aa86716cf1f9ee1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7289 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/7289 for details. -gerrit

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Patch merged into coreboot/master: 812d2a4 northbridge/amd: Use DEVICE_NOOP macro over dummy symbol
by gerrit＠coreboot.org 01 Nov '14

01 Nov '14

the following patch was just integrated into master: commit 812d2a47d4cdc0475dd06c14623881ca9d543c99 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 08:17:23 2014 +1100 northbridge/amd: Use DEVICE_NOOP macro over dummy symbol Change-Id: I3fdd2a9f981592112998d74ce4cfe4850d8fab31 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7288 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/7288 for details. -gerrit

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Patch merged into coreboot/master: 9f74462 northbridge/intel: Use DEVICE_NOOP macro over dummy symbol
by gerrit＠coreboot.org 01 Nov '14

01 Nov '14

the following patch was just integrated into master: commit 9f74462790bab4d8bcb0dbe6791313bf7a3db73b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 08:12:34 2014 +1100 northbridge/intel: Use DEVICE_NOOP macro over dummy symbol Change-Id: I9aeed70f72d4df260312df6e53379f1741415b65 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7287 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/7287 for details. -gerrit

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Patch merged into coreboot/master: c3f38cd mainboard: Use DEVICE_NOOP macro over dummy symbol
by gerrit＠coreboot.org 01 Nov '14

01 Nov '14

the following patch was just integrated into master: commit c3f38cd423158ff21017c8d75b3d987aed08286f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 08:04:30 2014 +1100 mainboard: Use DEVICE_NOOP macro over dummy symbol Change-Id: I37c302c7a17645f55d568c1a5f7bb791319ddbb4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7286 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/7286 for details. -gerrit

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Patch merged into coreboot/master: 0625a8b {cpu, soc}: Use DEVICE_NOOP macro over dummy symbol
by gerrit＠coreboot.org 01 Nov '14

01 Nov '14

the following patch was just integrated into master: commit 0625a8bcfb90ae8d68c07147cc5cb3172424f601 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 08:03:16 2014 +1100 {cpu,soc}: Use DEVICE_NOOP macro over dummy symbol Change-Id: Iaf2b2873bd1c52d7f936bd9b483e194a0872a626 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7285 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/7285 for details. -gerrit

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Patch merged into coreboot/master: 524625d drivers: Use DEVICE_NOOP macro over dummy symbol
by gerrit＠coreboot.org 01 Nov '14

01 Nov '14

the following patch was just integrated into master: commit 524625d4e0a6ee07b01960437a3f918c0f04a1bb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 07:55:45 2014 +1100 drivers: Use DEVICE_NOOP macro over dummy symbol Change-Id: I931bd9c89bce6ac8f8e9e482a7876e2004abfb38 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7284 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/7284 for details. -gerrit

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Patch merged into coreboot/master: 530355d include/device/device.h: Provide DEVICE_NOOP macro shim
by gerrit＠coreboot.org 01 Nov '14

01 Nov '14

the following patch was just integrated into master: commit 530355d41bf10fa4f0ee215e0e71fc68e80053ea Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 08:31:44 2014 +1100 include/device/device.h: Provide DEVICE_NOOP macro shim Rather than everyone writing their own adhoc device operation NOP shim, we provide some formalism. We later make use of this to reduce the loc count down trivially. Change-Id: I2d04bfb50e76f367a0ee258dab97d7caa12ec99e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7283 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/7283 for details. -gerrit

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Patch set updated for coreboot: a3bf2d8 inteltool: refine GPIO and PMBASE/TCO printing on Ibex Peak/5 Series
by Stefan Tauner 01 Nov '14

01 Nov '14

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7239 -gerrit commit a3bf2d8689e6b110ead9c23c1aef8497f46d87a6 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Nov 1 17:12:37 2014 +0100 inteltool: refine GPIO and PMBASE/TCO printing on Ibex Peak/5 Series Nicolas Reinecke was noticing that in my Lenovo T410s logs the GPIO*3 settings were missing. This led to some investigation and this patch, thanks! Change-Id: I7ba28aa00d10f988a7fe81e61d2e216b54a11006 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/gpio.c | 90 ++++++++++++++++++++++++++++++++++------------ util/inteltool/powermgt.c | 39 +++++++++----------- util/inteltool/rootcmplx.c | 20 +++++------ 3 files changed, 94 insertions(+), 55 deletions(-) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 49c1325..93c5d14 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -258,6 +258,44 @@ static const io_register_t pch_gpio_registers[] = { { 0x78, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" }, }; +/* Default values for Ibex Peak desktop chipsets */ +static const gpio_default_t ip_pch_desktop_defaults[] = { + { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */ + { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */ + { 0x0c, 0x02fe0100 }, /* GP_LVL */ + { 0x18, 0x00040000 }, /* GPO_BLINK */ + { 0x1c, 0x00000000 }, /* GP_SER_BLINK */ + { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */ + { 0x2c, 0x00000000 }, /* GP_INV */ + { 0x30, 0x020300ff }, /* GPIO_USE_SEL2 */ + { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */ + { 0x38, 0xa4aa0003 }, /* GP_LVL2 */ + { 0x40, 0x00000100 }, /* GPIO_USE_SEL3 */ + { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */ + { 0x48, 0x00000000 }, /* GP_LVL3 */ + { 0x60, 0x01000000 }, /* GP_RST_SEL1 */ + { 0x64, 0x00000000 }, /* GP_RST_SEL2 */ + { 0x68, 0x00000000 }, /* GP_RST_SEL3 */ +}; +/* Default values for Ibex Peak mobile chipsets */ +static const gpio_default_t ip_pch_mobile_defaults[] = { + { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */ + { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */ + { 0x0c, 0x02fe0100 }, /* GP_LVL */ + { 0x18, 0x00040000 }, /* GPO_BLINK */ + { 0x1c, 0x00000000 }, /* GP_SER_BLINK */ + { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */ + { 0x2c, 0x00000000 }, /* GP_INV */ + { 0x30, 0x020300fe }, /* GPIO_USE_SEL2 */ + { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */ + { 0x38, 0xa4aa0003 }, /* GP_LVL2 */ + { 0x40, 0x00000000 }, /* GPIO_USE_SEL3 */ + { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */ + { 0x48, 0x00000000 }, /* GP_LVL3 */ + { 0x60, 0x01000000 }, /* GP_RST_SEL1 */ + { 0x64, 0x00000000 }, /* GP_RST_SEL2 */ + { 0x68, 0x00000000 }, /* GP_RST_SEL3 */ +}; /* Default values for Cougar Point desktop chipsets */ static const gpio_default_t cp_pch_desktop_defaults[] = { { 0x00, 0xb96ba1ff }, @@ -406,6 +444,35 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: + case PCI_DEVICE_ID_INTEL_3400_DESKTOP: + case PCI_DEVICE_ID_INTEL_B55_A: + case PCI_DEVICE_ID_INTEL_B55_B: + case PCI_DEVICE_ID_INTEL_H55: + case PCI_DEVICE_ID_INTEL_H57: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_Q57: + gpiobase = pci_read_word(sb, 0x48) & 0xff80; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = ip_pch_desktop_defaults; + defaults_size = ARRAY_SIZE(ip_pch_desktop_defaults); + break; + case PCI_DEVICE_ID_INTEL_3400_MOBILE: + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_HM55: + case PCI_DEVICE_ID_INTEL_HM57: + case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_QM57: + case PCI_DEVICE_ID_INTEL_QS57: + gpiobase = pci_read_word(sb, 0x48) & 0xff80; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = ip_pch_mobile_defaults; + defaults_size = ARRAY_SIZE(ip_pch_mobile_defaults); + break; case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: case PCI_DEVICE_ID_INTEL_H67: @@ -522,29 +589,6 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpio_registers = i631x_gpio_registers; size = ARRAY_SIZE(i631x_gpio_registers); break; - - case PCI_DEVICE_ID_INTEL_3400_DESKTOP: - case PCI_DEVICE_ID_INTEL_3400_MOBILE: - case PCI_DEVICE_ID_INTEL_P55: - case PCI_DEVICE_ID_INTEL_PM55: - case PCI_DEVICE_ID_INTEL_H55: - case PCI_DEVICE_ID_INTEL_QM57: - case PCI_DEVICE_ID_INTEL_H57: - case PCI_DEVICE_ID_INTEL_HM55: - case PCI_DEVICE_ID_INTEL_Q57: - case PCI_DEVICE_ID_INTEL_HM57: - case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: - case PCI_DEVICE_ID_INTEL_B55_A: - case PCI_DEVICE_ID_INTEL_QS57: - case PCI_DEVICE_ID_INTEL_3400: - case PCI_DEVICE_ID_INTEL_3420: - case PCI_DEVICE_ID_INTEL_3450: - case PCI_DEVICE_ID_INTEL_B55_B: - gpiobase = pci_read_word(sb, 0x48) & 0xfffc; - gpio_registers = i631x_gpio_registers; - size = ARRAY_SIZE(i631x_gpio_registers); - break; - case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); return 1; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 3bc4efc..8908835 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -656,6 +656,23 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: + case PCI_DEVICE_ID_INTEL_3400_DESKTOP: + case PCI_DEVICE_ID_INTEL_3400_MOBILE: + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_B55_A: + case PCI_DEVICE_ID_INTEL_B55_B: + case PCI_DEVICE_ID_INTEL_H55: + case PCI_DEVICE_ID_INTEL_H57: + case PCI_DEVICE_ID_INTEL_HM55: + case PCI_DEVICE_ID_INTEL_HM57: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_Q57: + case PCI_DEVICE_ID_INTEL_QM57: + case PCI_DEVICE_ID_INTEL_QS57: case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: case PCI_DEVICE_ID_INTEL_UM67: @@ -761,28 +778,6 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) size = ARRAY_SIZE(i63xx_pm_registers); break; - case PCI_DEVICE_ID_INTEL_3400_DESKTOP: - case PCI_DEVICE_ID_INTEL_3400_MOBILE: - case PCI_DEVICE_ID_INTEL_P55: - case PCI_DEVICE_ID_INTEL_PM55: - case PCI_DEVICE_ID_INTEL_H55: - case PCI_DEVICE_ID_INTEL_QM57: - case PCI_DEVICE_ID_INTEL_H57: - case PCI_DEVICE_ID_INTEL_HM55: - case PCI_DEVICE_ID_INTEL_Q57: - case PCI_DEVICE_ID_INTEL_HM57: - case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: - case PCI_DEVICE_ID_INTEL_B55_A: - case PCI_DEVICE_ID_INTEL_QS57: - case PCI_DEVICE_ID_INTEL_3400: - case PCI_DEVICE_ID_INTEL_3420: - case PCI_DEVICE_ID_INTEL_3450: - case PCI_DEVICE_ID_INTEL_B55_B: - pmbase = pci_read_word(sb, 0x40) & 0xfffc; - pm_registers = i63xx_pm_registers; - size = ARRAY_SIZE(i63xx_pm_registers); - break; - case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have PMBASE.\n"); return 1; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index f1e902d..392b7a9 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -47,23 +47,23 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: case PCI_DEVICE_ID_INTEL_I63XX: + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: case PCI_DEVICE_ID_INTEL_3400_DESKTOP: case PCI_DEVICE_ID_INTEL_3400_MOBILE: - case PCI_DEVICE_ID_INTEL_P55: - case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_B55_A: + case PCI_DEVICE_ID_INTEL_B55_B: case PCI_DEVICE_ID_INTEL_H55: - case PCI_DEVICE_ID_INTEL_QM57: case PCI_DEVICE_ID_INTEL_H57: case PCI_DEVICE_ID_INTEL_HM55: - case PCI_DEVICE_ID_INTEL_Q57: case PCI_DEVICE_ID_INTEL_HM57: - case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: - case PCI_DEVICE_ID_INTEL_B55_A: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_Q57: + case PCI_DEVICE_ID_INTEL_QM57: case PCI_DEVICE_ID_INTEL_QS57: - case PCI_DEVICE_ID_INTEL_3400: - case PCI_DEVICE_ID_INTEL_3420: - case PCI_DEVICE_ID_INTEL_3450: - case PCI_DEVICE_ID_INTEL_B55_B: case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: case PCI_DEVICE_ID_INTEL_UM67:

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coreboot-gerrit November 2014