coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

1 participants
1026 discussions

Patch set updated for coreboot: edee704 AMD Trinity and Kabini: fix fan control
by WANG Siyuan 10 Oct '14

10 Oct '14

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6981 -gerrit commit edee7047dd07d62a0534f691eff71a264c56f140 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Fri Oct 10 14:37:02 2014 +0800 AMD Trinity and Kabini: fix fan control The fan can stop but can't run again. This patch can resolve this problem. Change-Id: I1b5bf3f6f7a66c60743f78918dc5442cdfc8b6e4 Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index c7927dc..37d36b1 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -58,11 +58,6 @@ static void agesawrapper_post_device(void *unused) pci_write_config32(dev, 0x60, value); #endif -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - /* AMD AGESA does not enable thermal zone, so we enable it here. */ - enable_imc_thermal_zone(); -#endif - #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif @@ -70,6 +65,12 @@ static void agesawrapper_post_device(void *unused) return; AGESAWRAPPER(amdS3Save); + +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* AMD AGESA does not enable thermal zone, so we enable it here. */ + printk(BIOS_DEBUG, "enable_imc_thermal_zone\n"); + enable_imc_thermal_zone(); +#endif } BOOT_STATE_INIT_ENTRIES(agesa_bscb) = {

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Patch set updated for coreboot: dc39a02 util/inteltool: add ibex peak default gpio registers
by Alexander Couzens 09 Oct '14

09 Oct '14

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7030 -gerrit commit dc39a02bc1fe6db395b8f2eca766d6d26f84a399 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Oct 8 03:53:53 2014 +0200 util/inteltool: add ibex peak default gpio registers Change-Id: I41688e29fcd6e53c863ba908b2b5b27287fb1dc0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/inteltool/gpio.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index dfb0819..7454fb2 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -258,6 +258,44 @@ static const io_register_t pch_gpio_registers[] = { { 0x78, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" }, }; +/* Default values for Ibex Peak mobile chipsets */ +static const gpio_default_t ib_pch_mobile_defaults[] = { + { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */ + { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */ + { 0x0c, 0x02fe0100 }, /* GP_LVL */ + { 0x18, 0x00040000 }, /* GPO_BLINK */ + { 0x1c, 0x00000000 }, /* GP_SER_BLINK */ + { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */ + { 0x2c, 0x00000000 }, /* GP_INV */ + { 0x30, 0x020300fe }, /* GPIO_USE_SEL2 */ + { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */ + { 0x38, 0xa4aa0003 }, /* GP_LVL2 */ + { 0x40, 0x00000000 }, /* GPIO_USE_SEL3 */ + { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */ + { 0x48, 0x00000000 }, /* GP_LVL3 */ + { 0x60, 0x01000000 }, /* GP_RST_SEL1 */ + { 0x64, 0x00000000 }, /* GP_RST_SEL2 */ + { 0x68, 0x00000000 }, /* GP_RST_SEL3 */ +}; +/* Default values for Ibex Peak desktop chipsets */ +static const gpio_default_t ib_pch_desktop_defaults[] = { + { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */ + { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */ + { 0x0c, 0x02fe0100 }, /* GP_LVL */ + { 0x18, 0x00040000 }, /* GPO_BLINK */ + { 0x1c, 0x00000000 }, /* GP_SER_BLINK */ + { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */ + { 0x2c, 0x00000000 }, /* GP_INV */ + { 0x30, 0x020300ff }, /* GPIO_USE_SEL2 */ + { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */ + { 0x38, 0xa4aa0003 }, /* GP_LVL2 */ + { 0x40, 0x00000100 }, /* GPIO_USE_SEL3 */ + { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */ + { 0x48, 0x00000000 }, /* GP_LVL3 */ + { 0x60, 0x01000000 }, /* GP_RST_SEL1 */ + { 0x64, 0x00000000 }, /* GP_RST_SEL2 */ + { 0x68, 0x00000000 }, /* GP_RST_SEL3 */ +}; /* Default values for Cougar Point desktop chipsets */ static const gpio_default_t cp_pch_desktop_defaults[] = { { 0x00, 0xb96ba1ff }, @@ -417,6 +455,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = ib_pch_desktop_defaults; + defaults_size = ARRAY_SIZE(ib_pch_desktop_defaults); break; case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: case PCI_DEVICE_ID_INTEL_3400_MOBILE: @@ -428,6 +468,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = ib_pch_mobile_defaults; + defaults_size = ARRAY_SIZE(ib_pch_mobile_defaults); break; case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67:

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Patch set updated for coreboot: 102497e util/inteltool: fix ibex peak register definition
by Alexander Couzens 09 Oct '14

09 Oct '14

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7029 -gerrit commit 102497e40215c9bd45b7306ccc16a9e3dfdf2763 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Oct 8 03:52:49 2014 +0200 util/inteltool: fix ibex peak register definition ibex peak is the first pch chipset Change-Id: Ic506bd8d4a6a6eabeb990f9a09ad7805b32b51f7 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/inteltool/gpio.c | 38 +++++++++++++++++++++++--------------- util/inteltool/powermgt.c | 30 +++++++++++++++--------------- 2 files changed, 38 insertions(+), 30 deletions(-) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 49c1325..dfb0819 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -406,6 +406,29 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_3400_DESKTOP: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_H55: + case PCI_DEVICE_ID_INTEL_H57: + case PCI_DEVICE_ID_INTEL_Q57: + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + break; + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_3400_MOBILE: + case PCI_DEVICE_ID_INTEL_HM57: + case PCI_DEVICE_ID_INTEL_HM55: + case PCI_DEVICE_ID_INTEL_QM57: + case PCI_DEVICE_ID_INTEL_QS57: + case PCI_DEVICE_ID_INTEL_PM55: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: case PCI_DEVICE_ID_INTEL_H67: @@ -523,22 +546,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) size = ARRAY_SIZE(i631x_gpio_registers); break; - case PCI_DEVICE_ID_INTEL_3400_DESKTOP: - case PCI_DEVICE_ID_INTEL_3400_MOBILE: - case PCI_DEVICE_ID_INTEL_P55: - case PCI_DEVICE_ID_INTEL_PM55: - case PCI_DEVICE_ID_INTEL_H55: - case PCI_DEVICE_ID_INTEL_QM57: - case PCI_DEVICE_ID_INTEL_H57: - case PCI_DEVICE_ID_INTEL_HM55: - case PCI_DEVICE_ID_INTEL_Q57: - case PCI_DEVICE_ID_INTEL_HM57: - case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: case PCI_DEVICE_ID_INTEL_B55_A: - case PCI_DEVICE_ID_INTEL_QS57: - case PCI_DEVICE_ID_INTEL_3400: - case PCI_DEVICE_ID_INTEL_3420: - case PCI_DEVICE_ID_INTEL_3450: case PCI_DEVICE_ID_INTEL_B55_B: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = i631x_gpio_registers; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 3bc4efc..4829301 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -656,6 +656,21 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3400_DESKTOP: + case PCI_DEVICE_ID_INTEL_3400_MOBILE: + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: + case PCI_DEVICE_ID_INTEL_H55: + case PCI_DEVICE_ID_INTEL_H57: + case PCI_DEVICE_ID_INTEL_HM55: + case PCI_DEVICE_ID_INTEL_HM57: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_Q57: + case PCI_DEVICE_ID_INTEL_QM57: + case PCI_DEVICE_ID_INTEL_QS57: case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: case PCI_DEVICE_ID_INTEL_UM67: @@ -761,22 +776,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) size = ARRAY_SIZE(i63xx_pm_registers); break; - case PCI_DEVICE_ID_INTEL_3400_DESKTOP: - case PCI_DEVICE_ID_INTEL_3400_MOBILE: - case PCI_DEVICE_ID_INTEL_P55: - case PCI_DEVICE_ID_INTEL_PM55: - case PCI_DEVICE_ID_INTEL_H55: - case PCI_DEVICE_ID_INTEL_QM57: - case PCI_DEVICE_ID_INTEL_H57: - case PCI_DEVICE_ID_INTEL_HM55: - case PCI_DEVICE_ID_INTEL_Q57: - case PCI_DEVICE_ID_INTEL_HM57: - case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: case PCI_DEVICE_ID_INTEL_B55_A: - case PCI_DEVICE_ID_INTEL_QS57: - case PCI_DEVICE_ID_INTEL_3400: - case PCI_DEVICE_ID_INTEL_3420: - case PCI_DEVICE_ID_INTEL_3450: case PCI_DEVICE_ID_INTEL_B55_B: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = i63xx_pm_registers;

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Patch merged into coreboot/master: 762d53d intel/fsp_baytrail: Include header for "southcluster_smm_save_gpio_route"
by gerrit＠coreboot.org 09 Oct '14

09 Oct '14

the following patch was just integrated into master: commit 762d53d41897b3b2b13e47623c50cc94b5113333 Author: Kayalvizhi Dhandapani <kayalvizhid(a)ami.com> Date: Tue Oct 7 12:21:31 2014 -0400 intel/fsp_baytrail: Include header for "southcluster_smm_save_gpio_route" Fix the error 'implicit declaration of function "southcluster_smm_save_gpio_route"', when SMM module is added. Change-Id: Ia050ab7e2b036541537b645d3fe4dc747cd1dff8 Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid(a)ami.com> Reviewed-on: http://review.coreboot.org/7024 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> See http://review.coreboot.org/7024 for details. -gerrit

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Patch merged into coreboot/master: a16055a intel/fsp_baytrail: fix error "unknown type device_t", when SMM Module added
by gerrit＠coreboot.org 09 Oct '14

09 Oct '14

the following patch was just integrated into master: commit a16055ae8ad2a04a7577aae351def4482d7bbab8 Author: Kayalvizhi Dhandapani <kayalvizhid(a)ami.com> Date: Tue Oct 7 14:11:20 2014 -0400 intel/fsp_baytrail: fix error "unknown type device_t", when SMM Module added Change-Id: I6d8622c7f343619b915442d8056aa6672dfc4f6e Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid(a)ami.com> Reviewed-on: http://review.coreboot.org/7025 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <gaumless(a)gmail.com> See http://review.coreboot.org/7025 for details. -gerrit

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Patch merged into coreboot/master: 454625c intel/fsp_baytrail: Fix SMM/SMI
by gerrit＠coreboot.org 09 Oct '14

09 Oct '14

the following patch was just integrated into master: commit 454625c5cf4adecb5b80777503bc600c8b139004 Author: Kayalvizhi Dhandapani <kayalvizhid(a)ami.com> Date: Tue Oct 7 14:34:01 2014 -0400 intel/fsp_baytrail: Fix SMM/SMI With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485 Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid(a)ami.com> Reviewed-on: http://review.coreboot.org/7026 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7026 for details. -gerrit

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Patch set updated for coreboot: 6c90c66 intel/fsp_baytrail: Fix SMM/SMI
by Marc Jones 09 Oct '14

09 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7026 -gerrit commit 6c90c66aa10eb01c95dbb0d4c13a0e5a1bc4021d Author: Kayalvizhi Dhandapani <kayalvizhid(a)ami.com> Date: Tue Oct 7 14:34:01 2014 -0400 intel/fsp_baytrail: Fix SMM/SMI With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485 Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid(a)ami.com> --- src/mainboard/intel/bayleybay_fsp/devicetree.cb | 2 +- src/soc/intel/fsp_baytrail/Kconfig | 4 ++++ src/soc/intel/fsp_baytrail/cpu.c | 10 ++++++++-- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb index befd3dc..356c8df 100644 --- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb +++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb @@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail register "SataMode" = "SATA_MODE_AHCI" register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" + register "MrcInitTsegSize" = "TSEG_SIZE_8_MB" register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index cb4757b..e9391c3 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -31,12 +31,16 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DYNAMIC_CBMEM + select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP select REG_SCRIPT + select SMM_MODULES + select SMM_TSEG + select BAYTRAIL_SMM select SMP select SPI_FLASH select SSE2 diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index f260880..6f1e9c4 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -148,14 +148,20 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params) runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); } -static void asmlinkage -cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime) +static void asmlinkage cpu_smm_do_relocation(void *arg) { #ifndef CONFIG_MAX_CPUS #error CONFIG_MAX_CPUS must be set. #endif msr_t smrr; em64t100_smm_state_save_area_t *smm_state; + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + + p = arg; + runtime = p->runtime; + cpu = p->cpu; if (cpu >= CONFIG_MAX_CPUS) { printk(BIOS_CRIT,

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Patch merged into coreboot/master: 2c0f46a AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.inc
by gerrit＠coreboot.org 09 Oct '14

09 Oct '14

the following patch was just integrated into master: commit 2c0f46afbbee078881ad9e9a99f5c219c2ed528e Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Thu Sep 25 16:45:45 2014 -0600 AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.inc The static library builder for the stub that interfaces to the AGESA binary does not include config.h and kconfig.h, so any header file changes that depend on Kconfig variables fail. Force these two system headers to be included in the build of any AGESA stub files. Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Change-Id: I2e8d38fa5aa21cc31b995ee3abe68ab3c3c55a68 Reviewed-on: http://review.coreboot.org/6979 Reviewed-by: Martin Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6979 for details. -gerrit

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Patch set updated for coreboot: 31fc1db NOTFORMERGE: build-check to see which mobos are still monolithic ACPI
by Vladimir Serbinenko 09 Oct '14

09 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7028 -gerrit commit 31fc1db0570a3c4c588da0a7454fe94cf27151cd Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 8 00:26:42 2014 +0200 NOTFORMERGE: build-check to see which mobos are still monolithic ACPI Change-Id: I37fab85eabac79b8596031fa4efb9ef630ae5664 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index afcaab6..f474a19 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -470,7 +470,7 @@ config MAX_PIRQ_LINKS config PER_DEVICE_ACPI_TABLES bool - default n + default y #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu.

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Patch set updated for coreboot: ce9674f baytrail: Switch to per-device ACPI
by Vladimir Serbinenko 09 Oct '14

09 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7037 -gerrit commit ce9674fb8897a3434da08983215a3eb330eaa908 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 8 22:56:27 2014 +0200 baytrail: Switch to per-device ACPI Change-Id: I6a1b1daa291298c85e14f89aa47a0693837cec6f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/rambi/acpi_tables.c | 159 +------------------- src/mainboard/intel/minnowmax/acpi_tables.c | 223 +--------------------------- src/mainboard/intel/minnowmax/mainboard.c | 25 ++++ src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/acpi/globalnvs.asl | 3 +- src/soc/intel/baytrail/baytrail/nvs.h | 1 + src/soc/intel/baytrail/northcluster.c | 14 ++ src/soc/intel/baytrail/southcluster.c | 32 ++++ 8 files changed, 77 insertions(+), 381 deletions(-) diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 890e1df..d94b2de 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -34,9 +34,7 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -68,158 +66,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "current = %lx\n", current); - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c index 881c143..8e31da2 100644 --- a/src/mainboard/intel/minnowmax/acpi_tables.c +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -36,10 +36,7 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> - -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -62,221 +59,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *ssdt2; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, - facs->length); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - ALIGN_CURRENT; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, - dsdt->length); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, - fadt->header.length); - - /* - * We explicitly add these tables later on: - */ - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, - hpet->header.length); - - /* If we want to use HPET Timers Linux wants an MADT */ - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, - madt->header.length); - - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, - mcfg->header.length); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ -#if CONFIG_HAVE_SMI_HANDLER - smm_setup_structures(gnvs, NULL, NULL); -#endif - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - ssdt = (acpi_header_t *)current; - memset(ssdt, 0, sizeof(acpi_header_t)); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length) { - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, - ssdt->length); - ALIGN_CURRENT; - } else { - ssdt = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); - } - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - ALIGN_CURRENT; - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - -#if IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) - printk(BIOS_DEBUG, "rsdp\n"); - hexdump(BIOS_DEBUG, rsdp, sizeof(acpi_rsdp_t)); - - printk(BIOS_DEBUG, "rsdt\n"); - hexdump(BIOS_DEBUG, rsdt, sizeof(acpi_rsdt_t)); - - printk(BIOS_DEBUG, "hpet\n"); - hexdump(BIOS_DEBUG, hpet, hpet->header.length); - - printk(BIOS_DEBUG, "madt\n"); - hexdump(BIOS_DEBUG, madt, madt->header.length); - - printk(BIOS_DEBUG, "mcfg\n"); - hexdump(BIOS_DEBUG, mcfg, mcfg->header.length); - - printk(BIOS_DEBUG, "dsdt\n"); - hexdump(BIOS_DEBUG, dsdt, dsdt->length); - - if (ssdt != NULL) { - printk(BIOS_DEBUG, "ssdt\n"); - hexdump(BIOS_DEBUG, ssdt, ssdt->length); - } - - if (ssdt2 != NULL) { - printk(BIOS_DEBUG, "ssdt2\n"); - hexdump(BIOS_DEBUG, ssdt2, ssdt2->length); - } - - printk(BIOS_DEBUG, "fadt\n"); - hexdump(BIOS_DEBUG, fadt, fadt->header.length); - - printk(BIOS_DEBUG, "facs\n"); - hexdump(BIOS_DEBUG, facs, facs->length); - -#endif /* IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) */ - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c index 3da1e23..fa9dfc5 100644 --- a/src/mainboard/intel/minnowmax/mainboard.c +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -39,7 +39,32 @@ static void mainboard_final(void *chip_info) { } +static unsigned long mainboard_write_acpi_tables(unsigned long start) +{ + acpi_header_t *ssdt2; + + ssdt2 = (acpi_header_t *)current; + memset(ssdt2, 0, sizeof(acpi_header_t)); + acpi_create_serialio_ssdt(ssdt2); + if (ssdt2->length) { + current += ssdt2->length; + acpi_add_table(rsdp, ssdt2); + printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, + ssdt2->length); + ALIGN_CURRENT; + } else { + ssdt2 = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); + } + + printk(BIOS_DEBUG, "current = %lx\n", current); + + return current; +} + + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .write_acpi_tables = mainboard_write_acpi_tables, .final = mainboard_final, }; diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index f36394e..d5f84cb 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC + select PER_DEVICE_ACPI_TABLES config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index a201c03..946f123 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -30,7 +30,8 @@ Name(\PICM, 0) // IOAPIC/8259 */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index c5defac..c204042 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -70,6 +70,7 @@ typedef struct { device_nvs_t dev; } __attribute__((packed)) global_nvs_t; +void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index e90c030..f592673 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <arch/acpi.h> #include <baytrail/iomap.h> #include <baytrail/iosf.h> @@ -139,8 +140,21 @@ static void nc_read_resources(device_t dev) #endif } +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + static struct device_operations nc_ops = { .read_resources = nc_read_resources, + .acpi_fill_ssdt_generator = generate_cpu_entries, .set_resources = NULL, .enable_resources = NULL, .init = NULL, diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 49e4c91..a021088 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -39,6 +39,9 @@ #include <baytrail/ramstage.h> #include <baytrail/spi.h> #include "chip.h" +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> static inline void add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) @@ -470,9 +473,38 @@ void southcluster_enable_dev(device_t dev) } } +static void southcluster_inject_dsdt(void) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + int scopelen; + memset(gnvs, 0, sizeof(*gnvs)); + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + scopelen = acpigen_write_scope("\\"); + scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_patch_len(scopelen - 1); + } +} + + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .write_acpi_tables = acpi_write_hpet, .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev,

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coreboot-gerrit October 2014