coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: b1fda43 lenovo/x60: Enable text mode native gfx init
by Francis Rowe 10 Oct '14

10 Oct '14

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6725 -gerrit commit b1fda435b5f549750fe76b306f069f7d1fcaf0a4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Aug 21 02:25:59 2014 +0200 lenovo/x60: Enable text mode native gfx init Change-Id: I3aad96a7034c73e447cf8995473a45ffd3893f3f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/northbridge/intel/i945/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index c27cad8..5d5962a 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select INTEL_EDID diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 360b2ab..a4da1a5 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -29,6 +29,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select DYNAMIC_CBMEM select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER + select VGA config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n

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New patch to review for coreboot: c6779c0 Revert "cbmem console: Locate the preram console with a symbol instead of a section."
by Francis Rowe 10 Oct '14

10 Oct '14

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7041 -gerrit commit c6779c02bcc1d77e90f07fefb063c8ee727c3f18 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Fri Oct 10 21:46:36 2014 +0100 Revert "cbmem console: Locate the preram console with a symbol instead of a section." This reverts commit 35382a6eeb6634c291ffb67a3c4fa7a4601a7328. X60/X201 were found not to boot at all with this commit. Reverting it fixes boot issue. Change-Id: Idfe7bd5323e4936441f112f3bb65287f3ec6cd1f Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/arch/arm/include/arch/early_variables.h | 1 + src/arch/x86/include/arch/early_variables.h | 2 ++ src/arch/x86/init/romstage.ld | 14 +++++++------- src/console/Kconfig | 10 +++++----- src/lib/cbmem_console.c | 5 ++--- 5 files changed, 17 insertions(+), 15 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 5b58baa..041d0ae 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -21,6 +21,7 @@ #define ARCH_EARLY_VARIABLES_H #define CAR_GLOBAL +#define CAR_CBMEM #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 80e82d6..ea1a133 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -26,8 +26,10 @@ asm(".previous"); asm(".section .car.cbmem_console,\"w\",@nobits"); asm(".previous"); #define CAR_GLOBAL __attribute__((section(".car.global_data"))) +#define CAR_CBMEM __attribute__((section(".car.cbmem_console"))) #else #define CAR_GLOBAL +#define CAR_CBMEM #endif #if defined(__PRE_RAM__) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index d6eb511..5458cfc 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -55,15 +55,15 @@ SECTIONS .car.data . (NOLOAD) : { _car_data_start = .; *(.car.global_data); - _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents that - * grows to a bound of CONFIG_CONSOLE_PRERAM_BUFFER_SIZE. - * However, collisions within the cache-as-ram region cannot be + /* The cbmem_console section comes last to take advantage of + * a zero-sized array to hold the memconsole contents that + * grows to a bound of CONFIG_CONSOLE_CAR_BUFFER_SIZE. However, + * collisions within the cache-as-ram region cannot be * statically checked because the cache-as-ram region usage is * cpu/chipset dependent. */ - preram_cbmem_console = .; + *(.car.cbmem_console); + _car_data_end = .; } - _bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); + _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); } diff --git a/src/console/Kconfig b/src/console/Kconfig index 619af56..472ac5c 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -184,15 +184,15 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. -config CONSOLE_PRERAM_BUFFER_SIZE +config CONSOLE_CAR_BUFFER_SIZE depends on CONSOLE_CBMEM - hex "Room allocated for console output before RAM is initialized" + hex "Room allocated for console output in Cache as RAM" default 0xc00 help Console is used before RAM is initialized. This is the room reserved - in the DCACHE based RAM, SRAM, etc. to keep console output before it - can be saved in a CBMEM buffer. 3K bytes should be enough even for - the BIOS_SPEW level. + in the DCACHE based RAM to keep console output before it can be + saved in a CBMEM buffer. 3K bytes should be enough even for the + BIOS_SPEW level. config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index b5b75f3..9d5419a 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -44,7 +44,7 @@ static struct cbmem_console *cbmem_console_p CAR_GLOBAL; * the area are defined in the config. */ -extern struct cbmem_console preram_cbmem_console; +static struct cbmem_console car_cbmem_console CAR_CBMEM; #else @@ -86,8 +86,7 @@ static inline void init_console_ptr(void *storage, u32 total_space) void cbmemc_init(void) { #ifdef __PRE_RAM__ - init_console_ptr(&preram_cbmem_console, - CONFIG_CONSOLE_PRERAM_BUFFER_SIZE); + init_console_ptr(&car_cbmem_console, CONFIG_CONSOLE_CAR_BUFFER_SIZE); #else /* * Initializing before CBMEM is available, use static buffer to store

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New patch to review for coreboot: c8f5fe7 intel/fsp_baytrail: Clear the GNVS area prior to filling
by Scott Radcliffe 10 Oct '14

10 Oct '14

Scott Radcliffe (sradcliffe(a)microind.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7040 -gerrit commit c8f5fe75046b576d1de74ce3c548a79733efd682 Author: Scott Radcliffe <sradcliffe(a)microind.com> Date: Fri Oct 10 16:26:05 2014 -0400 intel/fsp_baytrail: Clear the GNVS area prior to filling Zero out the GNVS area so that uninitialized portions are defined. Change-Id: I2b575c65bfaab58ae6206ac6f457c259c27a7d97 Signed-off-by: Scott Radcliffe <sradcliffe(a)microind.com> --- src/soc/intel/fsp_baytrail/acpi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index dece178..fb0dc87 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -88,6 +88,9 @@ static acpi_cstate_t cstate_map[] = { void acpi_init_gnvs(global_nvs_t *gnvs) { + /* Clear gnvs area so uninitialized portions are defined */ + memset(gnvs, 0, sizeof(*gnvs)); + /* CPU core count */ gnvs->pcnt = dev_count_cpu();

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New patch to review for coreboot: 3062a56 baytrail: Add padding to the end of device_nvs to match ACPI
by Scott Radcliffe 10 Oct '14

10 Oct '14

Scott Radcliffe (sradcliffe(a)microind.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7039 -gerrit commit 3062a5611721d53e4a2f0f7490d4158b2bfdd210 Author: Scott Radcliffe <sradcliffe(a)microind.com> Date: Fri Oct 10 16:15:01 2014 -0400 baytrail: Add padding to the end of device_nvs to match ACPI ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000. To reserve the full 0x2000 bytes for gnvs usage, padding must be added to the device_nvs struct. Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac Signed-off-by: Scott Radcliffe <sradcliffe(a)microind.com> --- src/soc/intel/baytrail/baytrail/device_nvs.h | 3 ++- src/soc/intel/fsp_baytrail/baytrail/device_nvs.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h index f8f831b..4e175a0 100644 --- a/src/soc/intel/baytrail/baytrail/device_nvs.h +++ b/src/soc/intel/baytrail/baytrail/device_nvs.h @@ -55,13 +55,14 @@ typedef struct { u32 scc_bar0[3]; u32 lpe_bar0; - /* BAR 0 */ + /* BAR 1 */ u32 lpss_bar1[14]; u32 scc_bar1[3]; u32 lpe_bar1; /* Extra */ u32 lpe_fw; /* LPE Firmware */ + u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t; #endif diff --git a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h index a06ca70..4e175a0 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h +++ b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h @@ -62,6 +62,7 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ + u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t; #endif

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New patch to review for coreboot: 37e1a67 intel/fsp_baytrail: Add padding so device_nvs location matches ACPI
by Scott Radcliffe 10 Oct '14

10 Oct '14

Scott Radcliffe (sradcliffe(a)microind.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7038 -gerrit commit 37e1a6729a300c122d7bd5acf8d9920bf932c7d5 Author: Scott Radcliffe <sradcliffe(a)microind.com> Date: Fri Oct 10 16:09:52 2014 -0400 intel/fsp_baytrail: Add padding so device_nvs location matches ACPI The offset of the device_nvs in the gnvs struct is expected to be 0x1000. It is actually 0x100 so padding is needed to move device_nvs to the expected location. ACPI references to device_nvs objects will be correct with the padding. Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61 Signed-off-by: Scott Radcliffe <sradcliffe(a)microind.com> --- src/soc/intel/fsp_baytrail/baytrail/nvs.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/baytrail/nvs.h b/src/soc/intel/fsp_baytrail/baytrail/nvs.h index 53c4a64..242f6d3 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/nvs.h +++ b/src/soc/intel/fsp_baytrail/baytrail/nvs.h @@ -61,6 +61,9 @@ typedef struct { u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[196]; + /* Pad 0x0100-0x0fff */ + u8 rsvd4[3840]; + /* Baytrail LPSS (0x1000) */ device_nvs_t dev; } __attribute__((packed)) global_nvs_t;

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Patch merged into coreboot/master: 9215a89 via/epia-m: Switch to per-device ACPI
by gerrit＠coreboot.org 10 Oct '14

10 Oct '14

the following patch was just integrated into master: commit 9215a89f1cf8dfdb62a6b8a55a2e89e4e322a2d3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Sep 1 22:52:02 2014 +0200 via/epia-m: Switch to per-device ACPI Change-Id: Ic63fc1f933fff5cd58adcd4299c4ac2a62c4bb68 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6941 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6941 for details. -gerrit

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Patch set updated for coreboot: c15f405 bd82x6x, ibexpeak, lynxpoint: Declare NVSA before its use.
by Vladimir Serbinenko 10 Oct '14

10 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7017 -gerrit commit c15f405967a19060c50b9329d6ee029d9bd3ac2e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 5 11:10:35 2014 +0200 bd82x6x, ibexpeak, lynxpoint: Declare NVSA before its use. Windows chokes if it's not the case. Change-Id: I3df15228ed00c3124b8d42fc01d7d63ff3fe07ba Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 21 +++++++++++++++++++-- src/include/device/device.h | 1 + src/southbridge/intel/bd82x6x/lpc.c | 8 +++----- src/southbridge/intel/ibexpeak/lpc.c | 6 ++---- src/southbridge/intel/lynxpoint/lpc.c | 8 +++----- 5 files changed, 28 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 3a30d31..c4f5fca 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -707,8 +707,25 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT\n"); dsdt = (acpi_header_t *) current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); + if (dsdt->length >= sizeof(acpi_header_t)) { + current += sizeof(acpi_header_t); + + acpigen_set_current((char *) current); + for (dev = all_devices; dev; dev = dev->next) + if (dev->ops && dev->ops->acpi_inject_dsdt_generator) { + dev->ops->acpi_inject_dsdt_generator(); + } + current = (unsigned long) acpigen_get_current(); + memcpy((char *)current, + (char *)&AmlCode + sizeof(acpi_header_t), + dsdt->length - sizeof(acpi_header_t)); + current += dsdt->length - sizeof(acpi_header_t); + + /* (Re)calculate length and checksum. */ + dsdt->length = current - (unsigned long)dsdt; + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + } ALIGN_CURRENT; diff --git a/src/include/device/device.h b/src/include/device/device.h index 256afd4..7ae49f5 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -61,6 +61,7 @@ struct device_operations { unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); unsigned long (*acpi_fill_ssdt_generator)(unsigned long current, const char *oem_table_id); + void (*acpi_inject_dsdt_generator)(void); #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index a1c7c2a..6218874 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -671,7 +671,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oem_table_id) +static void southbridge_inject_dsdt(void) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); void *opregion; @@ -690,13 +690,11 @@ static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oe /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); - /* Add it to SSDT. */ + /* Add it to DSDT. */ scopelen = acpigen_write_scope("\\"); scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); acpigen_patch_len(scopelen - 1); } - - return (unsigned long) (acpigen_get_current()); } static struct pci_operations pci_ops = { @@ -708,7 +706,7 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pch_lpc_enable_resources, .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = lpc_init, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 27ece63..31bb4e7 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -665,7 +665,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oem_table_id) +static void southbridge_inject_dsdt(void) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); void *opregion; @@ -689,8 +689,6 @@ static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oe scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); acpigen_patch_len(scopelen - 1); } - - return (unsigned long) (acpigen_get_current()); } static struct pci_operations pci_ops = { @@ -701,7 +699,7 @@ static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pch_lpc_enable_resources, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .enable = pch_lpc_enable, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 451aeab..9e860d0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -743,7 +743,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oem_table_id) +static void southbridge_inject_dsdt(void) { global_nvs_t *gnvs; @@ -761,13 +761,11 @@ static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oe /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); - /* Add it to SSDT. */ + /* Add it to DSDT. */ scopelen = acpigen_write_scope("\\"); scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); acpigen_patch_len(scopelen - 1); } - - return (unsigned long) (acpigen_get_current()); } #define ALIGN_CURRENT current = (ALIGN(current, 16)) @@ -815,7 +813,7 @@ static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .enable = pch_lpc_enable,

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Patch merged into coreboot/master: 6b330f2 lynxpoint: Change OEM table ID for serialio.
by gerrit＠coreboot.org 10 Oct '14

10 Oct '14

the following patch was just integrated into master: commit 6b330f2a2462a72c2d10940b5e06b99f02b20297 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 5 11:08:40 2014 +0200 lynxpoint: Change OEM table ID for serialio. According to ACPI spec all SSDTs should have distinct OEM table ID. We end up with 2 SSDTs named "COREBOOT". Fix this. Change-Id: I01bccb72758baf51c6b4263778716f4bb9d438c9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/7016 for details. -gerrit

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Patch merged into coreboot/master: 7309c64 bd82x6x, ibexpeak, lynxpoint: Ensure 0-filling of uninited GNVS vars.
by gerrit＠coreboot.org 10 Oct '14

10 Oct '14

the following patch was just integrated into master: commit 7309c64d483abb4bf4ebe12901109320d88124ba Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 5 11:07:33 2014 +0200 bd82x6x, ibexpeak, lynxpoint: Ensure 0-filling of uninited GNVS vars. Change-Id: I672c3ca9e7f30a21330cf1920a25b1ab38b3f282 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7015 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/7015 for details. -gerrit

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Patch merged into coreboot/master: 60fccdc acpi_create_mcfg_mmconfig: Zero-out the structure before filling.
by gerrit＠coreboot.org 10 Oct '14

10 Oct '14

the following patch was just integrated into master: commit 60fccdc3d2ab5a3b0265f1a411d02b8504407e1c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 5 11:05:16 2014 +0200 acpi_create_mcfg_mmconfig: Zero-out the structure before filling. Otherwise "reserved" fields end up with a garbage instead of predictable value. Change-Id: I8a036769a8f86f1d6752651601de2800f4f1bd00 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7014 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/7014 for details. -gerrit

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coreboot-gerrit October 2014