coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: f5877f0 siemens/sitemp_g1p1: Fix serial output for simo board
by Dennis Wassenberg 15 Oct '14

15 Oct '14

Dennis Wassenberg (dennis.wassenberg(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7060 -gerrit commit f5877f053505b250b47df41ea43f7a6bc6144d27 Author: Dennis Wassenberg <dennis.wassenberg(a)secunet.com> Date: Tue Oct 14 17:29:36 2014 +0200 siemens/sitemp_g1p1: Fix serial output for simo board The simo board with console output at UART port 1 (COM2) will not produce any output if CONFIG_UART_FOR_CONSOLE=1 is set correctly. Commit f29200240e428761827ab8d179fa23068bfa9d59 (superio/ite/*: Factor out generic romstage component) will only and always activate UART port 0 unregarded to CONFIG_UART_FOR_CONSOLE value. Now the UART port which was selected by CONFIG_UART_FOR_CONSOLE will be enabled and used for console output Change-Id: Ibbd2b5115b1ed4763962ba32fc9c19431a906c78 Signed-off-by: Dennis Wassenberg <dennis.wassenberg(a)secunet.com> --- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 3332999..4beb8c9 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -46,7 +46,7 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, CONFIG_UART_FOR_CONSOLE == 1 ? IT8712F_SP2 : IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/

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New patch to review for coreboot: c2d3ee2 libpayload: Don't use default path for kconfig
by Nico Huber 14 Oct '14

14 Oct '14

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7061 -gerrit commit c2d3ee2593a3129ef774c850041d1c52120403d9 Author: Nico Huber <nico.h(a)gmx.de> Date: Tue Oct 14 23:27:50 2014 +0200 libpayload: Don't use default path for kconfig libpayload's kconfig is totally incompatible with other kconfig versions, today. Using other versions just doesn't work any more, so don't use the overridable $(obj)/util/kconfig path. Choose a path that reflects the incompatibility: $(obj)/util/lp_kconfig, instead. This whole every-(sub)project-has-it's-own-patched-kconfig-version makes me really, really sad :'-( Change-Id: I964772f3323dc20aa7c1cc26a384a2fbca1dbb5e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- payloads/libpayload/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index d84b63b..0b2f109 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -48,7 +48,7 @@ export src := src export srck := $(top)/util/kconfig export obj ?= build export objutil ?= $(obj)/util -export objk := $(objutil)/kconfig +export objk := $(objutil)/lp_kconfig export KCONFIG_AUTOHEADER := $(obj)/config.h @@ -272,7 +272,7 @@ printall: endif -$(shell mkdir -p $(obj) $(objutil)/kconfig/lxdialog $(additional-dirs) $(alldirs)) +$(shell mkdir -p $(obj) $(objk)/lxdialog $(additional-dirs) $(alldirs)) cscope: cscope -bR

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Patch merged into coreboot/master: 8ffc085 intel/fsp_baytrail: Add padding so device_nvs location matches ACPI
by gerrit＠coreboot.org 14 Oct '14

14 Oct '14

the following patch was just integrated into master: commit 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e Author: Scott Radcliffe <sradcliffe(a)microind.com> Date: Fri Oct 10 16:09:52 2014 -0400 intel/fsp_baytrail: Add padding so device_nvs location matches ACPI The offset of the device_nvs in the gnvs struct is expected to be 0x1000. It is actually 0x100 so padding is needed to move device_nvs to the expected location. ACPI references to device_nvs objects will be correct with the padding. This was tested using a Micro Industries customized Baytrail-I board based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's a Google customized structure located at 0x0100-0x0FFF that is removed from the fsp_baytrail/nvs.h which explains the mismatch here. Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61 Signed-off-by: Scott Radcliffe <sradcliffe(a)microind.com> Reviewed-on: http://review.coreboot.org/7038 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7038 for details. -gerrit

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Patch merged into coreboot/master: bf9d6a8 baytrail: Add padding to the end of device_nvs to match ACPI
by gerrit＠coreboot.org 14 Oct '14

14 Oct '14

the following patch was just integrated into master: commit bf9d6a856788f7bae7c3732b1761adb99ac3914f Author: Scott Radcliffe <sradcliffe(a)microind.com> Date: Fri Oct 10 16:15:01 2014 -0400 baytrail: Add padding to the end of device_nvs to match ACPI ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000. Padding has been added to device_nvs struct to reserve the full 0x2000 bytes for gnvs usage. No known issues are caused by having the GNVS area shorter than what ACPI thinks. Since there's nothing defined in this area, O/S shouldn't try to access it. Only problem might be if O/S notices the SSDT is located within the GNVS defined area. I verified that the next table written to memory (SSDT) is 0x2000 past GNVS start using a custom-designed Baytrail-I motherboard based on the Intel Bayley Bay CRB. Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac Signed-off-by: Scott Radcliffe <sradcliffe(a)microind.com> Reviewed-on: http://review.coreboot.org/7039 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7039 for details. -gerrit

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Patch merged into coreboot/master: 375e6ce intel/fsp_baytrail: Clear the GNVS area prior to filling
by gerrit＠coreboot.org 14 Oct '14

14 Oct '14

the following patch was just integrated into master: commit 375e6ce4aeee449c34a6d3efb6374c5684f7b32f Author: Scott Radcliffe <sradcliffe(a)microind.com> Date: Fri Oct 10 16:26:05 2014 -0400 intel/fsp_baytrail: Clear the GNVS area prior to filling Zero out the GNVS area so that uninitialized portions are defined. Tests using Microsoft Windows (XP/7/8) gave a bluescreen bugcheck: A5 (ACPI_BIOS_ERROR) with the first parameter (0x00001000) (ACPI_BIOS_USING_OS_MEMORY). Some ACPI enumerated devices use the GNVS area to define whether they're enabled and their MMIO regions. On my custom baytrail-based board and build, these devices were disabled but GNVS had uninitialized data indicating the devices were enabled with improper MMIO regions. Should investigate further to see where the GNVS device values are set if enabled and make sure they're set to valid values even when the devices are disabled via the mainboard/devicetree.cb. Change-Id: I2b575c65bfaab58ae6206ac6f457c259c27a7d97 Signed-off-by: Scott Radcliffe <sradcliffe(a)microind.com> Reviewed-on: http://review.coreboot.org/7040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7040 for details. -gerrit

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New patch to review for coreboot: fa8737d sitemp_g1p1: fixed serial output for simo-board
by Dennis Wassenberg 14 Oct '14

14 Oct '14

Dennis Wassenberg (dennis.wassenberg(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7060 -gerrit commit fa8737db2efd999c684a7a1d297386c25b55a31d Author: Dennis Wassenberg <dennis.wassenberg(a)secunet.com> Date: Tue Oct 14 17:29:36 2014 +0200 sitemp_g1p1: fixed serial output for simo-board The Simo-board with console output at UART port 1 (COM2) will not produce any output if CONFIG_UART_FOR_CONSOLE=1 is set correctly. Commit f29200240e428761827ab8d179fa23068bfa9d59 will only and always activate UART port 0 unregarded to CONFIG_UART_FOR_CONSOLE value. Now the UART port which was selected by CONFIG_UART_FOR_CONSOLE will be enabled and used for console output Change-Id: Ibbd2b5115b1ed4763962ba32fc9c19431a906c78 Signed-off-by: Dennis Wassenberg <dennis.wassenberg(a)secunet.com> --- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 3332999..4beb8c9 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -46,7 +46,7 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, CONFIG_UART_FOR_CONSOLE == 1 ? IT8712F_SP2 : IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/

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Patch set updated for coreboot: 6e9a396 AMD (K8/fam10): Rewrite CAR migration in post_cache_as_ram
by Kyösti Mälkki 14 Oct '14

14 Oct '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4583 -gerrit commit 6e9a396640b6c84458a1db8f70a5370fb0a4e362 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 29 12:07:54 2013 +0200 AMD (K8/fam10): Rewrite CAR migration in post_cache_as_ram Old routine copied all of CAR region as-is right below CONFIG_RAMTOP. Most of this region was reserved to interleave AP CPU address spaces and unused on BSP CPU. The only part of CAR region requiring a copy in RAM is the sysinfo structure. Improved routine changes this as follows: A region of size 'backup_size' below CONFIG_RAMTOP is cleared. In case of S3 resume, OS context from this region is first copied to high memory (CBMEM_ID_RESUME). At stack switch, CAR stack is discarded. Top of the stack for BSP is located at 'CONFIG_RAMTOP - car_size' for the remaining part of the romstage. This region is part of 'backup_size' and was zeroed before the switch took place. Before CAR is torn down the region of CAR_GLOBALS (and CAR_CBMEM), including the relevant sysinfo data for AP nodes memory training, is copied at 'CONFIG_RAMTOP - car_size'. Change-Id: Ie45b576aec6a2e006bfcb26b52fdb77c24f72e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/cache_as_ram.inc | 5 +- src/cpu/amd/car/post_cache_as_ram.c | 176 ++++++++++++++++++------------------ src/include/cpu/amd/car.h | 4 +- 3 files changed, 92 insertions(+), 93 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index dd02f6c..dadf8f7 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -424,10 +424,9 @@ CAR_FAM10_ap_out: cache_as_ram_switch_stack: /* Return address. */ popl %eax - /* Resume memory. */ + /* New stack. */ popl %eax - subl $(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp - pushl %eax + movl %eax, %esp call cache_as_ram_new_stack all_mtrr_msrs: diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 3a0763a..c27d485 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -10,58 +10,78 @@ #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" -static inline void print_debug_pcar(const char *strval, uint32_t val) -{ - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -} +#if CONFIG_RAMTOP <= 0x100000 + #error "You need to set CONFIG_RAMTOP greater than 1M" +#endif -/* from linux kernel 2.6.32 asm/string_32.h */ +#define PRINTK_IN_CAR 1 -static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes) -{ - int d0, d1, d2; - asm volatile("cld ; rep ; movsl\n\t" - "movl %4,%%ecx\n\t" - "andl $3,%%ecx\n\t" - "jz 1f\n\t" - "rep ; movsb\n\t" - "1:" - : "=&c" (d0), "=&D" (d1), "=&S" (d2) - : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src) - : "memory", "cc"); -} - -#if CONFIG_HAVE_ACPI_RESUME +#if PRINTK_IN_CAR +#define print_car_debug(x) print_debug(x) +#else +#define print_car_debug(x) +#endif -static inline void *backup_resume(void) { - void *resume_backup_memory; - int suspend = acpi_is_wakeup_early(); +extern char _car_data_start[]; +extern char _car_data_end[]; - if (!suspend) - return NULL; +static size_t car_data_size(void) +{ + size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + return ALIGN(car_size, 64); +} - if (cbmem_recovery(1)) - return NULL; +static size_t backup_size(void) +{ + size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + return ALIGN(car_size + 1024, 1024); +} - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); +static void memcpy_(void *d, const void *s, size_t len) +{ +#if PRINTK_IN_CAR + printk(BIOS_SPEW, " Copy [%08x-%08x] to [%08x - %08x] ... ", + (u32) s, (u32) (s + len - 1), (u32) d, (u32) (d + len - 1)); +#endif + memcpy(d, s, len); +} - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ +static void memset_(void *d, int val, size_t len) +{ +#if PRINTK_IN_CAR + printk(BIOS_SPEW, " Fill [%08x-%08x] ... ", (u32) d, (u32) (d + len - 1)); +#endif + memset(d, val, len); +} +static void prepare_romstage_ramstack(void *resume_backup_memory) +{ + size_t backup_top = backup_size(); + print_car_debug("Prepare CAR migration and stack regions..."); +#if CONFIG_HAVE_ACPI_RESUME if (resume_backup_memory) { - print_debug_pcar("Will copy coreboot region to: ", (uint32_t) resume_backup_memory); - /* copy only backup only memory used for CAR */ - memcopy(resume_backup_memory+HIGH_MEMORY_SAVE-CONFIG_DCACHE_RAM_SIZE, - (void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), - CONFIG_DCACHE_RAM_SIZE); //inline + memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, + (void *)(CONFIG_RAMTOP - backup_top), backup_top); } - - return resume_backup_memory; +#endif + memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); + print_car_debug("Done\n"); } + +static void prepare_ramstage_region(void *resume_backup_memory) +{ + size_t backup_top = backup_size(); + print_car_debug("Prepare ramstage memory region... "); +#if CONFIG_HAVE_ACPI_RESUME + if (resume_backup_memory) { + memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); + memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE - backup_top); + } #endif + if (!resume_backup_memory) + memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); + print_car_debug("Done\n"); +} /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */ @@ -80,48 +100,41 @@ static void vErrata343(void) void post_cache_as_ram(void) { void *resume_backup_memory = NULL; -#if 1 - { - /* Check value of esp to verify if we have enough room for stack in Cache as RAM */ - unsigned v_esp; - __asm__ volatile ( - "movl %%esp, %0\n\t" - : "=a" (v_esp) - ); - print_debug_pcar("v_esp=", v_esp); - } -#endif - - /* copy data from cache as ram to - ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. - */ -#if CONFIG_RAMTOP <= 0x100000 - #error "You need to set CONFIG_RAMTOP greater than 1M" -#endif #if CONFIG_HAVE_ACPI_RESUME - resume_backup_memory = backup_resume(); + int s3resume = acpi_is_wakeup_early(); + if (s3resume) { + cbmem_recovery(s3resume); + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + } #endif - - print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); + prepare_romstage_ramstack(resume_backup_memory); /* from here don't store more data in CAR */ vErrata343(); - memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline - cache_as_ram_switch_stack(resume_backup_memory); -} + size_t car_size = car_data_size(); + void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); -void -cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) -{ - /* We can put data to stack again */ + print_car_debug("Copying data from cache to RAM... "); + memcpy_(migrated_car, &_car_data_start[0], car_size); + print_car_debug("Done\n"); - /* only global variable sysinfo in cache need to be offset */ - print_debug("Done\n"); + /* New stack grows right below migrated_car. */ + print_car_debug("Switching to use RAM as stack... "); + cache_as_ram_switch_stack(migrated_car); - print_debug("Disabling cache as ram now \n"); + /* We do not come back. */ +} +void cache_as_ram_new_stack (void) +{ + void *resume_backup_memory = NULL; + +#if PRINTK_IN_CAR + printk(BIOS_DEBUG, "Top about %08x ... Done\n", (u32) &resume_backup_memory); +#endif + print_car_debug("Disabling cache as ram now\n"); disable_cache_as_ram_bsp(); disable_cache(); @@ -129,24 +142,11 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) enable_cache(); #if CONFIG_HAVE_ACPI_RESUME - /* now copy the rest of the area, using the WB method because we already - run normal RAM */ - if (resume_backup_memory) { - memcopy(resume_backup_memory, - (void *)(CONFIG_RAMBASE), - (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); + if (acpi_is_wakeup_early()) { + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); } #endif - - print_debug("Clearing initial memory region: "); - -#if CONFIG_HAVE_ACPI_RESUME - /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); -#else - memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); -#endif - print_debug("Done\n"); + prepare_ramstage_region(resume_backup_memory); set_sysinfo_in_ram(1); // So other core0 could start to train mem @@ -154,5 +154,5 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) copy_and_run(); /* We will not return */ - print_debug("should not be here -\n"); + print_car_debug("should not be here -\n"); } diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index a001c93..c00310a 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -5,8 +5,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void done_cache_as_ram_main(void); void post_cache_as_ram(void); -void cache_as_ram_switch_stack(void *resume_backup_memory); -void cache_as_ram_new_stack(void *resume_backup_memory); +void cache_as_ram_switch_stack(void *stacktop); +void cache_as_ram_new_stack(void); #if CONFIG_CPU_AMD_AGESA void disable_cache_as_ram(void);

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Patch set updated for coreboot: 39d3e71 AMD Trinity and Kabini: fix fan control
by WANG Siyuan 14 Oct '14

14 Oct '14

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6981 -gerrit commit 39d3e71637bcb2cfc0f7bb06ec24f7b4893d81e9 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Fri Oct 10 14:37:02 2014 +0800 AMD Trinity and Kabini: fix fan control The fan can stop but can't run again. "AGESA: Call get_bus_conf() just once" (commit ef40ca57) results to this problem. This patch can resolve this problem. Change-Id: I1b5bf3f6f7a66c60743f78918dc5442cdfc8b6e4 Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index c7927dc..9f30c2b 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -58,18 +58,16 @@ static void agesawrapper_post_device(void *unused) pci_write_config32(dev, 0x60, value); #endif -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - /* AMD AGESA does not enable thermal zone, so we enable it here. */ - enable_imc_thermal_zone(); -#endif - #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif - if (!acpi_s3_resume_allowed()) - return; + if (acpi_s3_resume_allowed()) + AGESAWRAPPER(amdS3Save); - AGESAWRAPPER(amdS3Save); +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* AMD AGESA does not enable thermal zone, so we enable it here. */ + enable_imc_thermal_zone(); +#endif } BOOT_STATE_INIT_ENTRIES(agesa_bscb) = {

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New patch to review for coreboot: 55207e1 AMD mainboards: fix system hang
by WANG Siyuan 14 Oct '14

14 Oct '14

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7059 -gerrit commit 55207e1b4cbf6750b6185488a11d232d4f4d7f69 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Oct 14 16:36:19 2014 +0800 AMD mainboards: fix system hang AMD mainboards with "AGESAWRAPPER(amdinitmmio);" maybe hang during boot. Sometimes system stops for about 10 seconds and go on, sometimes system can't boot. This is because do_agesawrapper() use printk: printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); The serial outpt is not ready, so system maybe hang. Change-Id: I3ab4e5378db44aece9046c8636cde1053ce5390d Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/dinar/romstage.c | 2 +- src/mainboard/amd/inagua/romstage.c | 2 +- src/mainboard/amd/olivehill/romstage.c | 2 +- src/mainboard/amd/parmer/romstage.c | 2 +- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/amd/torpedo/romstage.c | 2 +- src/mainboard/amd/union_station/romstage.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 1b32e30..f93bacf 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -64,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x32); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); /* Halt if there was a built in self test failure */ post_code(0x33); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 468f896..d7bc836 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -75,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 326a41a..c01c2d9 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -51,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 7c143f4..97fef18 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -42,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5d530b7..07d94af 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -80,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 98a042a..b202a9f 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -75,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 8ee42bd..f679765 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -47,7 +47,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 byte; device_t dev; - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); //__asm__ volatile ("1: jmp 1b"); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 7ed520a..222fd94 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -45,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 168b57f..b4a91ef 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -69,7 +69,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); AGESAWRAPPER(amdinitreset);

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Patch set updated for coreboot: 1c47099 baytrail: Add padding to the end of device_nvs to match ACPI
by Scott Radcliffe 13 Oct '14

13 Oct '14

Scott Radcliffe (sradcliffe(a)microind.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7039 -gerrit commit 1c47099de331e46ef0f628aa6846e9e9dbf400da Author: Scott Radcliffe <sradcliffe(a)microind.com> Date: Fri Oct 10 16:15:01 2014 -0400 baytrail: Add padding to the end of device_nvs to match ACPI ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000. Padding has been added to device_nvs struct to reserve the full 0x2000 bytes for gnvs usage. No known issues are caused by having the GNVS area shorter than what ACPI thinks. Since there's nothing defined in this area, O/S shouldn't try to access it. Only problem might be if O/S notices the SSDT is located within the GNVS defined area. I verified that the next table written to memory (SSDT) is 0x2000 past GNVS start using a custom-designed Baytrail-I motherboard based on the Intel Bayley Bay CRB. Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac Signed-off-by: Scott Radcliffe <sradcliffe(a)microind.com> --- src/soc/intel/baytrail/baytrail/device_nvs.h | 1 + src/soc/intel/fsp_baytrail/baytrail/device_nvs.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h index f8f831b..1ed897f 100644 --- a/src/soc/intel/baytrail/baytrail/device_nvs.h +++ b/src/soc/intel/baytrail/baytrail/device_nvs.h @@ -62,6 +62,7 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ + u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t; #endif diff --git a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h index a06ca70..c7fbc45 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h +++ b/src/soc/intel/fsp_baytrail/baytrail/device_nvs.h @@ -62,6 +62,7 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ + u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t; #endif

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coreboot-gerrit October 2014