coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

1 participants
1026 discussions

New patch to review for coreboot: a2af793 macbook21: Kill empty mainboard.asl
by Vladimir Serbinenko 15 Oct '14

15 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7063 -gerrit commit a2af793a9273534d2e7e410d8551bd6c3960b8d6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 20:24:12 2014 +0200 macbook21: Kill empty mainboard.asl Change-Id: I29c7d367df7d1ce911f6cd7ed5e5c56865b41dcc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/acpi/mainboard.asl | 0 src/mainboard/apple/macbook21/dsdt.asl | 3 --- 2 files changed, 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi/mainboard.asl b/src/mainboard/apple/macbook21/acpi/mainboard.asl deleted file mode 100644 index e69de29..0000000 diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 5ba7b09..c5456d7 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -41,9 +41,6 @@ DefinitionBlock( // General Purpose Events #include "acpi/gpe.asl" - // mainboard specific devices - #include "acpi/mainboard.asl" - Scope (\_SB) { Device (PCI0) {

1 0

New patch to review for coreboot: 6ef95e4 i945: consolidate sb & nb early inits
by Vladimir Serbinenko 15 Oct '14

15 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7062 -gerrit commit 6ef95e489885bc74a78323fd24b089daf41174b1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 20:17:51 2014 +0200 i945: consolidate sb & nb early inits Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/romstage.c | 69 ++---------------------------- src/mainboard/getac/p470/romstage.c | 48 ++------------------- src/mainboard/ibase/mb899/romstage.c | 51 ++-------------------- src/mainboard/intel/d945gclf/romstage.c | 48 ++------------------- src/mainboard/kontron/986lcd-m/romstage.c | 50 ++-------------------- src/mainboard/lenovo/t60/romstage.c | 50 +++------------------- src/mainboard/lenovo/x60/romstage.c | 50 ++-------------------- src/northbridge/intel/i945/early_init.c | 52 +++++++++++++++++++++- src/northbridge/intel/i945/i945.h | 2 +- src/southbridge/intel/i82801gx/early_lpc.c | 26 +++++++++++ src/southbridge/intel/i82801gx/i82801gx.h | 1 + 11 files changed, 108 insertions(+), 339 deletions(-) diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index e7ff902..7bec26b 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -286,12 +286,9 @@ static void early_ich7_init(void) void main(unsigned long bist) { - u32 reg32; - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); @@ -324,22 +321,7 @@ void main(unsigned long bist) */ i945_early_initialization(); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif - } + s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); @@ -349,7 +331,7 @@ void main(unsigned long bist) #endif timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(boot_mode, spd_addrmap); + sdram_initialize(s3resume ? 2 : 0, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ @@ -364,50 +346,7 @@ void main(unsigned long bist) fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(); - -#if !CONFIG_HAVE_ACPI_RESUME -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG_DEBUG_RAM_SETUP - sdram_dump_mchbar_registers(); - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); - } -#endif -#endif -#endif - - MCHBAR16(SSKPD) = 0xCAFE; - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, - SKPAD_ACPI_S3_MAGIC); - } -#endif + i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 3dab527..ccfb076 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -268,9 +268,7 @@ static void early_ich7_init(void) #include <cpu/intel/romstage.h> void main(unsigned long bist) { - u32 reg32; - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; if (bist == 0) enable_lapic(); @@ -302,21 +300,7 @@ void main(unsigned long bist) */ i945_early_initialization(); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); @@ -325,7 +309,7 @@ void main(unsigned long bist) dump_spd_registers(); #endif - sdram_initialize(boot_mode, NULL); + sdram_initialize(s3resume ? 2 : 0, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); @@ -339,29 +323,5 @@ void main(unsigned long bist) fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(); - - MCHBAR16(SSKPD) = 0xCAFE; - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); - } -#endif + i945_late_initialization(s3resume); } diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 322907b..2a81921 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -226,9 +226,7 @@ static void early_ich7_init(void) #include <cpu/intel/romstage.h> void main(unsigned long bist) { - u32 reg32; - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; if (bist == 0) enable_lapic(); @@ -253,21 +251,7 @@ void main(unsigned long bist) */ i945_early_initialization(); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); @@ -276,7 +260,7 @@ void main(unsigned long bist) dump_spd_registers(); #endif - sdram_initialize(boot_mode, NULL); + sdram_initialize(s3resume ? 2 : 0, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); @@ -290,32 +274,5 @@ void main(unsigned long bist) fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(); - - - quick_ram_check(); - - MCHBAR16(SSKPD) = 0xCAFE; - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); - } -#endif + i945_late_initialization(s3resume); } diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 0c48247..a0fb1c1 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -159,9 +159,7 @@ static void early_ich7_init(void) #include <cpu/intel/romstage.h> void main(unsigned long bist) { - u32 reg32; - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; if (bist == 0) enable_lapic(); @@ -187,21 +185,7 @@ void main(unsigned long bist) */ i945_early_initialization(); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); @@ -210,7 +194,7 @@ void main(unsigned long bist) dump_spd_registers(); #endif - sdram_initialize(boot_mode, NULL); + sdram_initialize(s3resume ? 2 : 0, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); @@ -224,29 +208,5 @@ void main(unsigned long bist) fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(); - - MCHBAR16(SSKPD) = 0xCAFE; - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); - } -#endif + i945_late_initialization(s3resume); } diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 2c12c5d..2c89e6c 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -332,9 +332,7 @@ static void early_ich7_init(void) #include <cpu/intel/romstage.h> void main(unsigned long bist) { - u32 reg32; - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; if (bist == 0) enable_lapic(); @@ -364,21 +362,7 @@ void main(unsigned long bist) */ i945_early_initialization(); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); @@ -387,7 +371,7 @@ void main(unsigned long bist) dump_spd_registers(); #endif - sdram_initialize(boot_mode, NULL); + sdram_initialize(s3resume ? 2 : 0, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); @@ -401,31 +385,5 @@ void main(unsigned long bist) fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(); - - quick_ram_check(); - - MCHBAR16(SSKPD) = 0xCAFE; - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); - } -#endif + i945_late_initialization(s3resume); } diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index f11b33e..f0ebcbc 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -209,9 +209,8 @@ static void early_ich7_init(void) #include <cpu/intel/romstage.h> void main(unsigned long bist) { - u32 reg32; - int boot_mode = 0, dock_err; - int cbmem_was_initted; + int s3resume = 0; + int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; @@ -262,21 +261,7 @@ void main(unsigned long bist) */ i945_early_initialization(); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); @@ -286,7 +271,7 @@ void main(unsigned long bist) #endif timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(boot_mode, spd_addrmap); + sdram_initialize(s3resume ? 2 : 0, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ @@ -301,32 +286,7 @@ void main(unsigned long bist) fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(); - - MCHBAR16(SSKPD) = 0xCAFE; - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); - } -#endif + i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); - } diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 943143a..1310b33 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -216,9 +216,7 @@ static void early_ich7_init(void) #include <cpu/intel/romstage.h> void main(unsigned long bist) { - u32 reg32; - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; @@ -264,21 +262,7 @@ void main(unsigned long bist) */ i945_early_initialization(); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); @@ -288,7 +272,7 @@ void main(unsigned long bist) #endif timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(boot_mode, spd_addrmap); + sdram_initialize(s3resume ? 2 : 0, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ @@ -303,33 +287,7 @@ void main(unsigned long bist) fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(); - - MCHBAR16(SSKPD) = 0xCAFE; - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, - SKPAD_ACPI_S3_MAGIC); - } -#endif + i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 24054bd..1715c47 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -22,6 +22,8 @@ #include <console/console.h> #include <arch/io.h> #include <device/pci_def.h> +#include <cbmem.h> +#include <string.h> #include "i945.h" int i945_silicon_revision(void) @@ -887,7 +889,34 @@ void i945_early_initialization(void) RCBA32(0x2010) |= (1 << 10); } -void i945_late_initialization(void) +static void i945_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if (s3resume && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, + HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, + SKPAD_ACPI_S3_MAGIC); + } +} + +void i945_late_initialization(int s3resume) { i945_setup_egress_port(); @@ -902,4 +931,25 @@ void i945_late_initialization(void) i945_setup_pci_express_x16(); i945_setup_root_complex_topology(); + +#if !CONFIG_HAVE_ACPI_RESUME +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEBUG_RAM_SETUP + sdram_dump_mchbar_registers(); + + { + /* This will not work if TSEG is in place! */ + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); + + printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); + ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, tom); + } +#endif +#endif +#endif + + MCHBAR16(SSKPD) = 0xCAFE; + + i945_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 9be9379..8573b0c 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -350,7 +350,7 @@ static inline void barrier(void) { asm("" ::: "memory"); } int i945_silicon_revision(void); void i945_early_initialization(void); -void i945_late_initialization(void); +void i945_late_initialization(int s3resume); /* provided by mainboard code */ void setup_ich7_gpios(void); diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c index 9f80d41..69bbfb2 100644 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -20,6 +20,9 @@ #include <arch/io.h> #include <timestamp.h> +#include <console/console.h> +#include <arch/acpi.h> +#include "i82801gx.h" #if CONFIG_COLLECT_TIMESTAMPS tsc_t get_initial_timestamp(void) @@ -31,3 +34,26 @@ tsc_t get_initial_timestamp(void) return base_time; } #endif + +int southbridge_detect_s3_resume(void) +{ + u32 reg32; + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + return 1; + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } + } + + return 0; +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1064dde..ee13b7d 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -44,6 +44,7 @@ extern void i82801gx_enable(device_t dev); #else void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); +int southbridge_detect_s3_resume(void); #endif #endif

1 0

Patch set updated for coreboot: 61b13f7 sandybridge: Move common northbridge finalize to northbridge code.
by Vladimir Serbinenko 15 Oct '14

15 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6920 -gerrit commit 61b13f7456828922cce9d1864e1618a9e56165d8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Sep 5 03:37:44 2014 +0200 sandybridge: Move common northbridge finalize to northbridge code. Change-Id: I6d4178e5aaffc1330b0953b0601bf6b448250a8e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/romstage.c | 24 +++------------------- src/mainboard/google/link/romstage.c | 24 +++------------------- src/mainboard/google/parrot/romstage.c | 24 +++------------------- src/mainboard/google/stout/romstage.c | 24 +++------------------- src/mainboard/intel/emeraldlake2/romstage.c | 24 +++------------------- src/mainboard/kontron/ktqm77/romstage.c | 24 +++------------------- src/mainboard/lenovo/t520/romstage.c | 24 +++------------------- src/mainboard/lenovo/t530/romstage.c | 22 +------------------- src/mainboard/lenovo/x220/romstage.c | 22 +------------------- src/mainboard/lenovo/x230/romstage.c | 22 +------------------- src/mainboard/samsung/lumpy/romstage.c | 24 ++-------------------- src/mainboard/samsung/stumpy/romstage.c | 24 +++------------------- src/northbridge/intel/sandybridge/early_init.c | 27 +++++++++++++++++++++++++ src/northbridge/intel/sandybridge/sandybridge.h | 1 + 14 files changed, 57 insertions(+), 253 deletions(-) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 083abe1..03d499d 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -245,35 +245,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 6d819b4..ca58262 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -289,35 +289,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 6c3ec79..667d639 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -245,35 +245,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 05caa3e..7ac5297 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -299,35 +299,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index e10e7b6..c9c2b1d 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -297,35 +297,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 211bfb5..5053530 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -305,35 +305,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 8aef922..8fc0f5f 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -252,36 +252,18 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode == 2); if (boot_mode != 2) { save_mrc_data(&pei_data); } -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index c9ad90d..d95f10a 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -240,28 +240,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d); - MCHBAR16(SSKPD) = 0xCAFE; + northbridge_romstage_finalize(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 04d577b..59563f9 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -238,28 +238,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d); - MCHBAR16(SSKPD) = 0xCAFE; + northbridge_romstage_finalize(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 94fa5cf..1a96ab2 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -229,28 +229,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d); - MCHBAR16(SSKPD) = 0xCAFE; + northbridge_romstage_finalize(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 32f1ec5..20fcaee 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -316,36 +316,16 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode == 2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index a3905ab..2166d6e 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -327,35 +327,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index d1d35db..8bf44c1 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <elog.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include "sandybridge.h" @@ -174,3 +175,29 @@ void sandybridge_early_initialization(int chipset_type) sandybridge_setup_graphics(); } + +void northbridge_romstage_finalize(int s3resume) +{ + MCHBAR16(SSKPD) = 0xCAFE; + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if (s3resume) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = 2; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif +} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 291ea46..d38bf0b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -209,6 +209,7 @@ void intel_sandybridge_finalize_smm(void); int bridge_silicon_revision(void); void sandybridge_early_initialization(int chipset_type); void sandybridge_late_initialization(void); +void northbridge_romstage_finalize(int s3resume); /* debugging functions */ void print_pci_devices(void);

1 0

Patch set updated for coreboot: 869df7d bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.
by Vladimir Serbinenko 15 Oct '14

15 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6921 -gerrit commit 869df7de69095a8a276c1598eba00ed02ba0a54a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Sep 5 16:29:41 2014 +0200 bd82x6x: Move common bd82x6x S3 detect to bd82x6x code. Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/romstage.c | 21 +------------------ src/mainboard/google/link/romstage.c | 22 ++------------------ src/mainboard/google/parrot/romstage.c | 21 +------------------ src/mainboard/google/stout/romstage.c | 21 +------------------ src/mainboard/intel/emeraldlake2/romstage.c | 21 +------------------ src/mainboard/kontron/ktqm77/romstage.c | 21 +------------------ src/mainboard/lenovo/t520/romstage.c | 21 +------------------ src/mainboard/lenovo/t530/romstage.c | 21 +------------------ src/mainboard/lenovo/x220/romstage.c | 21 +------------------ src/mainboard/lenovo/x230/romstage.c | 21 +------------------ src/mainboard/samsung/lumpy/romstage.c | 21 +------------------ src/mainboard/samsung/stumpy/romstage.c | 21 +------------------ src/southbridge/intel/bd82x6x/early_pch.c | 31 +++++++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/pch.h | 1 + 14 files changed, 45 insertions(+), 240 deletions(-) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 03d499d..908b6d8 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -117,8 +117,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { pei_version: PEI_VERSION, @@ -202,24 +200,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index ca58262..8236e20 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -155,8 +155,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -239,24 +237,8 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } else { + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; + if (boot_mode == 0) { /* This is the fastest way to let users know * the Intel CPU is now alive. */ diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 667d639..ce42b41 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -118,8 +118,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -202,24 +200,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 7ac5297..bfa4af7 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -159,8 +159,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { pei_version: PEI_VERSION, @@ -249,24 +247,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; /* Do ec reset as early as possible, but skip it on S3 resume */ if (boot_mode < 2) diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index c9c2b1d..220b1d7 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -167,8 +167,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -250,24 +248,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 5053530..401314c 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -164,8 +164,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -262,24 +260,7 @@ void main(unsigned long bist) pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_PEG10); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 8fc0f5f..a0cbad5 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -114,8 +114,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); @@ -196,24 +194,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index d95f10a..c2f0a4b 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -152,8 +152,6 @@ static void init_usb(void) void main(unsigned long bist) { int s3resume = 0; - u32 pm1_cnt; - u16 pm1_sts; spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { @@ -200,24 +198,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 59563f9..b989ecb 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -151,8 +151,6 @@ init_usb (void) void main(unsigned long bist) { int s3resume = 0; - u32 pm1_cnt; - u16 pm1_sts; spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { @@ -198,24 +196,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1a96ab2..16a17c2 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -152,8 +152,6 @@ init_usb (void) void main(unsigned long bist) { int s3resume = 0; - u32 pm1_cnt; - u16 pm1_sts; spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { @@ -189,24 +187,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + s3resume = southbridge_detect_s3_resume(); post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 20fcaee..dc4161d 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -137,8 +137,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { pei_version: PEI_VERSION, @@ -225,24 +223,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 2166d6e..625903d 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -177,8 +177,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -265,24 +263,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 9f80d41..3438a0a 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -20,6 +20,9 @@ #include <arch/io.h> #include <timestamp.h> +#include "pch.h" +#include <arch/acpi.h> +#include <console/console.h> #if CONFIG_COLLECT_TIMESTAMPS tsc_t get_initial_timestamp(void) @@ -31,3 +34,31 @@ tsc_t get_initial_timestamp(void) return base_time; } #endif + + +int southbridge_detect_s3_resume(void) +{ + u32 pm1_cnt; + u16 pm1_sts; + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + return 1; + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } + } + + return 0; +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 83128e2..aabf617 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,6 +76,7 @@ int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void early_pch_init_native(void); +int southbridge_detect_s3_resume(void); #endif #endif

1 0

Patch set updated for coreboot: 27a13d9 x220, x230: Remove unused headers.
by Vladimir Serbinenko 15 Oct '14

15 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6922 -gerrit commit 27a13d9a25e1f69c26939bfa43dd65c04bbc2f9c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Sep 6 01:38:55 2014 +0300 x220, x230: Remove unused headers. Change-Id: Ia85e3b588c0e255e5c0f77114f051130596ce8d5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x220/mainboard.c | 7 ------- src/mainboard/lenovo/x220/romstage.c | 3 --- src/mainboard/lenovo/x230/mainboard.c | 6 ------ 3 files changed, 16 deletions(-) diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 87fedfe..00e7991 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -26,15 +26,10 @@ #include <device/pci_ops.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> -#include <cbfs.h> #include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> #include <build.h> @@ -54,8 +49,6 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } - - static void mainboard_init(device_t dev) { RCBA32(0x38c8) = 0x00002005; diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 7d97f12..33d9b5e 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -28,9 +28,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit_native.h" @@ -39,7 +37,6 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> -#include <cbfs.h> static void pch_enable_lpc(void) { diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 7d9c456..a060015 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -26,15 +26,11 @@ #include <device/pci_ops.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> -#include <cbfs.h> #include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> #include <build.h> @@ -54,8 +50,6 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } - - static void mainboard_init(device_t dev) { RCBA32(0x38c8) = 0x00002005;

1 0

Patch set updated for coreboot: 2cf6420 bd82x6x: Consolidate early native USB init
by Vladimir Serbinenko 15 Oct '14

15 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6923 -gerrit commit 2cf64206668ea25ce9fb7e82f15944ab71efc26b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Sep 17 02:38:51 2014 +0200 bd82x6x: Consolidate early native USB init Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t530/romstage.c | 56 +++++------------ src/mainboard/lenovo/x220/romstage.c | 56 +++++------------ src/mainboard/lenovo/x230/romstage.c | 56 +++++------------ src/southbridge/intel/bd82x6x/Makefile.inc | 10 +-- src/southbridge/intel/bd82x6x/early_usb_native.c | 77 ++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/pch.h | 11 ++++ 6 files changed, 141 insertions(+), 125 deletions(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index c2f0a4b..89a5cb4 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -110,45 +110,6 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -static void init_usb(void) -{ - const u32 rcba_dump[64] = { - /* 3500 */ 0x20000f57, 0x20000f57, 0x2000055b, 0x20000f57, - /* 3510 */ 0x20000f57, 0x20000153, 0x20000153, 0x2000055b, - /* 3520 */ 0x20000153, 0x20000f57, 0x20000153, 0x20000153, - /* 3530 */ 0x20000f51, 0x20000f57, 0x00000000, 0x00000000, - /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, - /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, - /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00001448, - /* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000, - /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - }; - int i; - /* Activate PMBAR. */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ - - /* Unlock registers. */ - outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); - - for (i = 0; i < 64; i++) - write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); - - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); - - /* Relock registers. */ - outw (0x0000, DEFAULT_PMBASE | 0x003c); -} - - void main(unsigned long bist) { int s3resume = 0; @@ -184,7 +145,22 @@ void main(unsigned long bist) outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); - init_usb(); + early_usb_init((struct southbridge_usb_port []) { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 2, 3 }, + { 1, 1, -1 }, + { 1, 1, -1 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 1, 2, -1 }, + { 1, 0, -1 }, + { 1, 1, 5 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 3, -1 }, + { 1, 1, -1 }, + }); /* Initialize console device(s) */ console_init(); diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index b989ecb..7d97f12 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -108,45 +108,6 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -static void -init_usb (void) -{ - const u32 rcba_dump[64] = { - /* 3500 */ 0x20000153, 0x20000f57, 0x20000f57, 0x20000f57, - /* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x20000153, - /* 3520 */ 0x20000f57, 0x20000f57, 0x20000f57, 0x20000f57, - /* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000, - /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3560 */ 0x020c0001, 0x000024a3, 0x00040002, 0x01000050, - /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, - /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3590 */ 0x00000003, 0x000000c0, 0x00000000, 0x00000000, - /* 35a0 */ 0x0fc00201, 0x102d0200, 0x00000000, 0x00000000, - /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - }; - int i; - /* Activate PMBAR. */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ - - /* Unlock registers. */ - outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); - - for (i = 0; i < 64; i++) - write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); - - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); - - /* Relock registers. */ - outw (0x0000, DEFAULT_PMBASE | 0x003c); -} - #include <cpu/intel/romstage.h> void main(unsigned long bist) { @@ -182,7 +143,22 @@ void main(unsigned long bist) outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44); outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48); - init_usb(); + early_usb_init((struct southbridge_usb_port []) { + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 1, -1 }, + { 1, 1, -1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 1, 6 }, + { 1, 1, 5 }, + { 1, 1, 6 }, + { 1, 1, 6 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + }); /* Initialize console device(s) */ console_init(); diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 16a17c2..c2a0ae7 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -109,45 +109,6 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -static void -init_usb (void) -{ - const u32 rcba_dump[64] = { - /* 3500 */ 0x20000153, 0x20000153, 0x20000f57, 0x20000f57, - /* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x2000055b, - /* 3520 */ 0x20000153, 0x2000055b, 0x20000f57, 0x20000f57, - /* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000, - /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, - /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, - /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000040, - /* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000, - /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - }; - int i; - /* Activate PMBAR. */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ - - /* Unlock registers. */ - outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); - - for (i = 0; i < 64; i++) - write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); - - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); - - /* Relock registers. */ - outw (0x0000, DEFAULT_PMBASE | 0x003c); -} - #include <cpu/intel/romstage.h> void main(unsigned long bist) { @@ -173,7 +134,22 @@ void main(unsigned long bist) setup_pch_gpios(&x230_gpio_map); - init_usb(); + early_usb_init((struct southbridge_usb_port []) { + { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ + { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ + { 1, 1, 3 }, /* P2: dock, OC 3 */ + { 1, 1, -1 }, /* P3: wwan, no OC */ + { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */ + { 1, 1, -1 }, /* P5: Expresscard, no OC */ + { 0, 0, -1 }, /* P6: Empty */ + { 1, 2, -1 }, /* P7: dock, no OC */ + { 1, 0, -1 }, + { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */ + { 1, 1, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: wlan, no OC */ + { 1, 1, -1 }, /* P13: webcam, no OC */ + }); /* Initialize console device(s) */ console_init(); diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b79b85a..3d33edc 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -47,14 +47,14 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c -romstage-y += early_usb.c early_smbus.c me_status.c gpio.c +romstage-y += early_smbus.c me_status.c gpio.c romstage-y += reset.c romstage-y += early_spi.c early_pch.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c new file mode 100644 index 0000000..2afe8d3 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */ +#include "pch.h" + +void +early_usb_init (const struct southbridge_usb_port *portmap) +{ + u32 reg32; + const u32 rcba_dump[8] = { + /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, + /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, + }; + const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 }; + int i; + /* Activate PMBAR. */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + /* Unlock registers. */ + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + for (i = 0; i < 14; i++) + write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), + currents[portmap[i].current]); + for (i = 0; i < 10; i++) + write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0); + + for (i = 0; i < 8; i++) + write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]); + for (i = 0; i < 8; i++) + write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0); + reg32 = 0; + for (i = 0; i < 14; i++) + if (!portmap[i].enabled) + reg32 |= (1 << i); + write32 (DEFAULT_RCBABASE | 0x359c, reg32); + reg32 = 0; + for (i = 0; i < 8; i++) + if (portmap[i].enabled && portmap[i].oc_pin >= 0) + reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); + write32 (DEFAULT_RCBABASE | 0x35a0, reg32); + reg32 = 0; + for (i = 8; i < 14; i++) + if (portmap[i].enabled && portmap[i].oc_pin >= 4) + reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); + write32 (DEFAULT_RCBABASE | 0x35a4, reg32); + for (i = 0; i < 22; i++) + write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0); + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + /* Relock registers. */ + outw (0x0000, DEFAULT_PMBASE | 0x003c); +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index aabf617..7a796df 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -77,6 +77,17 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void early_pch_init_native(void); int southbridge_detect_s3_resume(void); + +struct southbridge_usb_port +{ + int enabled; + int current; + int oc_pin; +}; + +void +early_usb_init (const struct southbridge_usb_port *portmap); + #endif #endif

1 0

Patch set updated for coreboot: 72096de lenovo/{x2, t5}{2, 3}0: Remove butterfly DSP init.
by Vladimir Serbinenko 15 Oct '14

15 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6841 -gerrit commit 72096deb12d6eb03d560b70416974b466a055be5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Sep 5 02:56:24 2014 +0200 lenovo/{x2,t5}{2,3}0: Remove butterfly DSP init. It's specific to butterfly. Doesn't do anything on lenovos. Change-Id: I7b607196733225eace0f5e70b4cc02651488aa74 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t530/hda_verb.c | 128 +---------------------------------- src/mainboard/lenovo/x220/hda_verb.c | 123 +-------------------------------- src/mainboard/lenovo/x230/hda_verb.c | 128 +---------------------------------- 3 files changed, 9 insertions(+), 370 deletions(-) diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index 29f8a45..bd176c1 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -31,7 +31,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x0000007d, // Number of 4 dword sets + 0x00000012, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -81,135 +81,13 @@ const u32 cim_verb_data[] = { 0x01470740, 0x00970600, - 0x00370600, - 0x00270600, - 0x00270600, - 0x00270600, - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), - /* - * Hardware EQ Parameters - * Sample Rate 88200 - */ - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, - 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, - 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, - 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, - 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, - 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, - 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, - 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, - 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, - 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, - 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, - 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, - 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, - 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, - 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, - 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, - 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, - 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, - 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, - 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, - 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, - 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, - 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, - 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, - 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, - 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, - 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, - 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, - 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, - 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, - 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, - 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, - 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, - 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, - 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, - 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, - 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, - 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, - 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, - 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, - 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, - 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, - 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, - 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, - 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, - 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, - 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, - - /* - * Hardware EQ Parameters - * Sample Rate 96000 - */ - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, - 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, - 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, - 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, - 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, - 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, - 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, - 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, - 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, - 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, - 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, - 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, - 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, - 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, - 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, - 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, - 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, - 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, - 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, - 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, - 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, - 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, - 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, - 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, - 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, - 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, - 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, - 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, - 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, - 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, - 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, - 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, - 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, - 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, - 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, - 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, - 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, - 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, - 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, - 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, - 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, - 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, - 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, - 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, - 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, - 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, - 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, - - /* SAFEDSP Parameters */ - 0x022782C1, 0x02277127, 0x02277227, 0x02278801, - 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, - 0x02278B0F, 0x0017B008, - /* Misc entries */ + 0x00370600, + 0x00270600, 0x00B707C0, /* Enable PortB as Output with HP amp */ 0x00D70740, /* Enable PortD as Output */ 0x0017A200, /* Disable ClkEn of PortSenseTst */ diff --git a/src/mainboard/lenovo/x220/hda_verb.c b/src/mainboard/lenovo/x220/hda_verb.c index c3d1372..6495fd6 100644 --- a/src/mainboard/lenovo/x220/hda_verb.c +++ b/src/mainboard/lenovo/x220/hda_verb.c @@ -31,7 +31,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 0x17aa21db, // Subsystem ID - 0x00000077, // Number of 4 dword sets + 0x0000000d , // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -52,125 +52,6 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), AZALIA_PIN_CFG(0x0, 0x23, 0x90A60170), - /* - * Hardware EQ Parameters - * Sample Rate 88200 - */ - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, - 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, - 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, - 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, - 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, - 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, - 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, - 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, - 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, - 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, - 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, - 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, - 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, - 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, - 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, - 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, - 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, - 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, - 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, - 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, - 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, - 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, - 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, - 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, - 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, - 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, - 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, - 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, - 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, - 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, - 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, - 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, - 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, - 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, - 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, - 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, - 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, - 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, - 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, - 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, - 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, - 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, - 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, - 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, - 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, - 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, - 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, - - /* - * Hardware EQ Parameters - * Sample Rate 96000 - */ - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, - 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, - 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, - 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, - 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, - 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, - 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, - 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, - 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, - 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, - 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, - 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, - 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, - 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, - 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, - 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, - 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, - 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, - 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, - 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, - 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, - 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, - 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, - 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, - 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, - 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, - 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, - 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, - 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, - 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, - 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, - 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, - 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, - 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, - 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, - 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, - 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, - 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, - 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, - 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, - 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, - 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, - 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, - 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, - 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, - 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, - 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, - - /* SAFEDSP Parameters */ - 0x022782C1, 0x02277127, 0x02277227, 0x02278801, - 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, - 0x02278B0F, 0x0017B008, - /* Misc entries */ 0x00B707C0, /* Enable PortB as Output with HP amp */ 0x00D70740, /* Enable PortD as Output */ @@ -181,6 +62,8 @@ const u32 cim_verb_data[] = { Enable Combo Jack Detection */ 0x0017A208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */ + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ /* --- Next Codec --- */ diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index 29f8a45..bd176c1 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -31,7 +31,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x0000007d, // Number of 4 dword sets + 0x00000012, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -81,135 +81,13 @@ const u32 cim_verb_data[] = { 0x01470740, 0x00970600, - 0x00370600, - 0x00270600, - 0x00270600, - 0x00270600, - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), - /* - * Hardware EQ Parameters - * Sample Rate 88200 - */ - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, - 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, - 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, - 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, - 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, - 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, - 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, - 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, - 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, - 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, - 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, - 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, - 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, - 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, - 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, - 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, - 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, - 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, - 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, - 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, - 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, - 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, - 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, - 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, - 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, - 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, - 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, - 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, - 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, - 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, - 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, - 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, - 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, - 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, - 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, - 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, - 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, - 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, - 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, - 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, - 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, - 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, - 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, - 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, - 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, - 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, - 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, - - /* - * Hardware EQ Parameters - * Sample Rate 96000 - */ - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, - 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, - 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, - 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, - 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, - 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, - 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, - 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, - 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, - 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, - 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, - 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, - 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, - 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, - 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, - 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, - 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, - 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, - 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, - 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, - 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, - 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, - 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, - 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, - 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, - 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, - 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, - 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, - 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, - 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, - 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, - 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, - 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, - 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, - 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, - 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, - 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, - 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, - 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, - 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, - 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, - 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, - 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, - 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, - 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, - 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, - 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, - - /* SAFEDSP Parameters */ - 0x022782C1, 0x02277127, 0x02277227, 0x02278801, - 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, - 0x02278B0F, 0x0017B008, - /* Misc entries */ + 0x00370600, + 0x00270600, 0x00B707C0, /* Enable PortB as Output with HP amp */ 0x00D70740, /* Enable PortD as Output */ 0x0017A200, /* Disable ClkEn of PortSenseTst */

1 0

Patch merged into coreboot/master: 0e64617 i945: Convert to per-device ACPI
by gerrit＠coreboot.org 15 Oct '14

15 Oct '14

the following patch was just integrated into master: commit 0e64617d7d8adcd4d3db16eed7a34604691c2ee6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 31 00:27:05 2014 +0200 i945: Convert to per-device ACPI Change-Id: Iee3ee33ca58b8c722d2d38aae31e7130032512ad Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/6804 for details. -gerrit

1 0

Patch merged into coreboot/master: 33769a5 gm45: Convert to per-device ACPI
by gerrit＠coreboot.org 15 Oct '14

15 Oct '14

the following patch was just integrated into master: commit 33769a5caadca0ff82267ab5021bc85315e1d7f5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 30 22:39:20 2014 +0200 gm45: Convert to per-device ACPI Change-Id: Ib04b03b2dc2ad3bfa886b43df9dd6518bbb46e3f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/6803 for details. -gerrit

1 0

Patch set updated for coreboot: 428d5d5 AMD Parmer and OliveHill: regress agesawrapper_amdinitmmio
by WANG Siyuan 15 Oct '14

15 Oct '14

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7059 -gerrit commit 428d5d5fb686583cea442135cb8e9a79d4a7fc9e Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed Oct 15 15:11:27 2014 +0800 AMD Parmer and OliveHill: regress agesawrapper_amdinitmmio "AGESAWRAPPER(amdinitmmio);" can't print anything on Parmer and OliveHill, because it is previous console init. Parmer and OliveHill don't have superio. We use a FPGA card to decode serial output. System maybe hang if the FPGA card is connected. This is because the card try to decode print message in "AGESAWRAPPER(amdinitmmio);". Change-Id: I3ab4e5378db44aece9046c8636cde1053ce5390d Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/olivehill/romstage.c | 2 +- src/mainboard/amd/parmer/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 326a41a..c01c2d9 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -51,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 7c143f4..97fef18 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -42,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80();

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2014