the following patch was just integrated into master:
commit b640fd39062194819cfb0ed4ff40b75fc383cac6
Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Date: Wed Oct 22 13:47:18 2014 +0800
AMD Hudson: enable IMC fan control using ACPI code
IMC fan control should be enabled after OS launched.
I have tested on OliveHill and Parmer with Windows 7 and Ubuntu 13.10.
Change-Id: I16d6ff6b1272d16b840e803e0a95f6e363c79704
Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Reviewed-on: http://review.coreboot.org/7165
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/7165 for details.
-gerrit
the following patch was just integrated into master:
commit 29d9c5675865e902cfd46df4b2f948c195de8884
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Oct 16 21:35:48 2014 +0300
AMD Trinity and Kabini: fix fan control
The fan can stop but can't run again. "AGESA: Call get_bus_conf() just
once" (commit ef40ca57) results to this problem.
This patch can resolve this problem.
Change-Id: I1b5bf3f6f7a66c60743f78918dc5442cdfc8b6e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6981
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6981 for details.
-gerrit
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7175
-gerrit
commit d98f537f490bf779fef0ec1fa9484060e8166e62
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Fri Oct 24 01:34:25 2014 +1100
bd82x6x/sata: Fix AHCI mode bits for max port split between controllers
According to the Intel datasheet under 'MAP - Address Map Register (SATA-D31:F2)',
2 flags, SATA Mode Select (SMS) and SATA Port-to-Controller Configuration (SC),
must be set when in AHCI mode.
Other bits [4:0], [15:8] and under the special condition of '0b11' in [7:6]
within this register are marked as reserved and so do a read and mask before
writing over them.
Make 'devicetree' configurable the alternative possible six port map
splitting possible between the first and second controllers via the boolean
'sata_port_split' as configurable in bit 5. Possible splits are 2/4 and 6/0
with a default of 6/0.
Note that bit 5 should be '1' while in AHCI/RAID mode.
Change-Id: I7872f0d4d4ffacbf4f80bb0157389ed8593d42e9
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Co-Author: Damien Zammit <damien(a)zamaudio.com>
---
src/southbridge/intel/bd82x6x/chip.h | 1 +
src/southbridge/intel/bd82x6x/sata.c | 12 +++++++++++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 0f2f0e9..e8d1da9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -65,6 +65,7 @@ struct southbridge_intel_bd82x6x_config {
/* IDE configuration */
uint8_t sata_port_map;
+ uint8_t sata_port_split;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..b577ba2 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -224,15 +224,25 @@ static void sata_enable(device_t dev)
if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
sata_mode = 0;
+ /* Take care with map as 0x90 has reserved bits */
+ map = pci_read_config16(dev, 0x90);
+
/*
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
if (sata_mode == 0)
- map = 0x0060;
+ map |= 0x0060;
map |= (config->sata_port_map ^ 0x3f) << 8;
+ /* Toggle between 6/0 or 2/4 split first/second respective
+ * controllers where:
+ * 2/4 is configured by sata_port_split = 0
+ * 6/0 is configured by sata_port_split = 1
+ */
+ map |= (config->sata_port_split << 5) & 0x20;
+
pci_write_config16(dev, 0x90, map);
}
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7175
-gerrit
commit 492afc0f639c70532834a537d073c26acaed683f
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Thu Oct 23 13:21:45 2014 +1100
bd82x6x/sata: Fix AHCI mode setting for max 6 ports on first controller
According to the Intel datasheet, 2 flags must be set when in AHCI mode.
This is now fixed. There is an alternative setting to enable max 2 ports
on first controller and 4 on the second controller, but this patch hardcodes
max 6 sata ports on the first controller.
Tested and working on new Intel desktop mainboard port.
Change-Id: I7872f0d4d4ffacbf4f80bb0157389ed8593d42e9
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Co-Author: Damien Zammit <damien(a)zamaudio.com>
---
src/southbridge/intel/bd82x6x/chip.h | 1 +
src/southbridge/intel/bd82x6x/sata.c | 8 +++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 0f2f0e9..e8d1da9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -65,6 +65,7 @@ struct southbridge_intel_bd82x6x_config {
/* IDE configuration */
uint8_t sata_port_map;
+ uint8_t sata_port_split;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..702dabc 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -224,15 +224,21 @@ static void sata_enable(device_t dev)
if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
sata_mode = 0;
+ /* Take care as 0x90 has reserved bits */
+ map = pci_read_config16(dev, 0x90);
+
/*
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
if (sata_mode == 0)
- map = 0x0060;
+ map |= 0x0060;
map |= (config->sata_port_map ^ 0x3f) << 8;
+ /* Toggle between 6/0 or 2/4 on split first/second respectively controllers */
+ map |= (config->sata_port_split << 5) & 0x20;
+
pci_write_config16(dev, 0x90, map);
}
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7175
-gerrit
commit d47856663fb909c147a54f07cfe6484630302199
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Thu Oct 23 13:21:45 2014 +1100
bd82x6x/sata: Fix AHCI mode setting for max 6 ports on first controller
According to the Intel datasheet, 2 flags must be set when in AHCI mode.
This is now fixed. There is an alternative setting to enable max 2 ports
on first controller and 4 on the second controller, but this patch hardcodes
max 6 sata ports on the first controller.
Tested and working on new Intel desktop mainboard port.
Change-Id: I7872f0d4d4ffacbf4f80bb0157389ed8593d42e9
Co-Author: Damien Zammit <damien(a)zamaudio.com>
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/southbridge/intel/bd82x6x/chip.h | 1 +
src/southbridge/intel/bd82x6x/sata.c | 8 +++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 0f2f0e9..e8d1da9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -65,6 +65,7 @@ struct southbridge_intel_bd82x6x_config {
/* IDE configuration */
uint8_t sata_port_map;
+ uint8_t sata_port_split;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..702dabc 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -224,15 +224,21 @@ static void sata_enable(device_t dev)
if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
sata_mode = 0;
+ /* Take care as 0x90 has reserved bits */
+ map = pci_read_config16(dev, 0x90);
+
/*
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
if (sata_mode == 0)
- map = 0x0060;
+ map |= 0x0060;
map |= (config->sata_port_map ^ 0x3f) << 8;
+ /* Toggle between 6/0 or 2/4 on split first/second respectively controllers */
+ map |= (config->sata_port_split << 5) & 0x20;
+
pci_write_config16(dev, 0x90, map);
}
the following patch was just integrated into master:
commit a10bde9048952c7a9a2f63d8450da35bbeda08c0
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Thu Oct 23 13:29:32 2014 +1100
intel/sandybridge: Add VGA pci device ID 0x0162
for Ivy Bridge. Tested on Gigabyte ga-b75m-d3h.
Change-Id: I7a1b1e8bac38789321960ebbe8c97d68a5aebfe2
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
Reviewed-on: http://review.coreboot.org/7173
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/7173 for details.
-gerrit
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7172
-gerrit
commit 39c4711f75e16a07b45205c36e7085ad8680a9b6
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Thu Oct 23 13:21:45 2014 +1100
bd82x6x/sata: Fix AHCI mode setting and allow split mode
According to the Intel PCH 7 series datasheet,
a flag must be set when in AHCI mode. This is now fixed.
A second flag has been implemented to allow user selection
of 6/0 or 2/4 split controller mode of ports on SATA when in IDE mode.
This is a new configurable parameter called sata_port_split
in the devicetree and takes the value 0 or 1.
Change-Id: I825c15d329b2d5960534b1f01843e0df3ace5317
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/southbridge/intel/bd82x6x/chip.h | 1 +
src/southbridge/intel/bd82x6x/sata.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 0f2f0e9..e8d1da9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -65,6 +65,7 @@ struct southbridge_intel_bd82x6x_config {
/* IDE configuration */
uint8_t sata_port_map;
+ uint8_t sata_port_split;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..7ec33c0 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -89,6 +89,10 @@ static void sata_init(struct device *dev)
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
+ /* Set AHCI mode (SMS + SC) */
+ reg16 = 0x0060;
+ pci_write_config16(dev, 0x90, reg16);
+
/* for AHCI, Port Enable is managed in memory mapped space */
reg16 = pci_read_config16(dev, 0x92);
reg16 &= ~0x3f; /* 6 ports SKU + ORM */
@@ -163,6 +167,10 @@ static void sata_init(struct device *dev)
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
+ /* Toggle between 6/0 or 2/4 on split controllers */
+ reg16 |= (config->sata_port_split << 5) & 0x20;
+ pci_write_config16(dev, 0x90, reg16);
+
/* Port enable */
reg16 = pci_read_config16(dev, 0x92);
reg16 &= ~0x3f;