coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 4060060 reg_script: include in romstage
by Isaac Christensen 01 Oct '14

01 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7003 -gerrit commit 4060060228fe6c4dd267febabbacbacb20d300da Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Wed Oct 1 11:50:20 2014 -0600 reg_script: include in romstage The new broadwell support uses the reg_script functions in romstage. Change-Id: Ic040bf947d35854711f4c1547858b0e4378ef759 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/lib/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8de4fb7..c104ce3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -86,6 +86,7 @@ ramstage-y += cbmem_info.c ramstage-y += hexdump.c romstage-y += hexdump.c +romstage-$(CONFIG_REG_SCRIPT) += reg_script.c ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c

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Patch merged into coreboot/master: 3cb86de intel/i945: Another magic number
by gerrit＠coreboot.org 01 Oct '14

01 Oct '14

the following patch was just integrated into master: commit 3cb86de4747593253a3b2d8d383784669b3e660b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Sep 29 20:42:33 2014 +0200 intel/i945: Another magic number Replace it with the existing #define Change-Id: I6e67ed1a455cd4f9eeed1865b9ef981e7ef0a874 Found-by: Idwer Vollering Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6992 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/6992 for details. -gerrit

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Patch merged into coreboot/master: a341a77 intel/i945: Fix "always false" statement
by gerrit＠coreboot.org 01 Oct '14

01 Oct '14

the following patch was just integrated into master: commit a341a77177c3e4b6c8de16b368f457d3d23c549a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Sep 29 19:51:21 2014 +0200 intel/i945: Fix "always false" statement Also replace magic number with already existing #define Change-Id: I64d22aca185bf43ff0ac126584b41920182a1112 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6990 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/6990 for details. -gerrit

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New patch to review for coreboot: 00d2245 Provide a way to compile some files with -O0 option
by Isaac Christensen 01 Oct '14

01 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7005 -gerrit commit 00d2245275d18a2ed12c93df6f774d95bcf4957b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Apr 22 17:06:43 2014 -0700 Provide a way to compile some files with -O0 option When preparing an image for source level debugging, it is convenient to be able to compile some modules with -O0, which makes it much easier to follow the execution flow. This patch allows to do it by defining GDB_DEBUG=1 in the environment before invoking make. Adding this feature as a common config flag is problematic, because we don't want to compile the entire image with -O0. Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196359 (cherry picked from commit dde4928c045d12e502cb109015a710cd9fdf2a04) Changed from CFLAGS to CFLAGS_common. Change-Id: Ie0be653509509eeb64ea3a7229f54c0c812840a9 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- Makefile.inc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 382eead..fe04a7a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -218,7 +218,7 @@ CPPFLAGS_common := -Isrc -Isrc/include -I$(obj) CPPFLAGS_common += -Isrc/device/oprom/include CPPFLAGS_common += -include $(src)/include/kconfig.h -CFLAGS_common += -Os -pipe -g -nostdinc +CFLAGS_common += -pipe -g -nostdinc CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS_common += -Wstrict-aliasing -Wshadow @@ -226,6 +226,12 @@ ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror endif CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer +ifneq ($(GDB_DEBUG),) +CFLAGS_common += -O0 +else +CFLAGS_common += -Os +endif + additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(objutil)/ifdfake $(objutil)/options $(objutil)/fletcher \

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Patch set updated for coreboot: 7c3e3f4 elog: Add event type for CPU thermal trip
by Isaac Christensen 01 Oct '14

01 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7004 -gerrit commit 7c3e3f4fac6bf677b07e8eaf7ea5ac957475a059 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon May 12 10:20:45 2014 -0700 elog: Add event type for CPU thermal trip There is a status bit for this event in most intel chipsets that we can read and report. Start by adding the new event type. Change-Id: Ib06411e3b87a1d069fb469943dd445bee6c1291f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199370 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 386a06170ec5afb31d0fe93ace3afbaab897a598) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/include/elog.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index eb8352d..648ce42 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -145,6 +145,9 @@ struct elog_event_data_me_extended { /* EC Shutdown Reason */ #define ELOG_TYPE_EC_SHUTDOWN 0xa5 +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xa7 + extern int elog_init(void); extern int elog_clear(void); extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size);

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New patch to review for coreboot: 8ca3b47 elog: Add event type for CPU thermal trip
by Isaac Christensen 01 Oct '14

01 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7004 -gerrit commit 8ca3b470d76136dd14cb4f43db7f9df3187b377a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon May 12 10:20:45 2014 -0700 elog: Add event type for CPU thermal trip There is a status bit for this event in most intel chipsets that we can read and report. Start by adding the new event type. BUG=chrome-os-partner:28234 TEST=build and boot on wtm2 Change-Id: Ib06411e3b87a1d069fb469943dd445bee6c1291f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199370 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 386a06170ec5afb31d0fe93ace3afbaab897a598) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/include/elog.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index eb8352d..648ce42 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -145,6 +145,9 @@ struct elog_event_data_me_extended { /* EC Shutdown Reason */ #define ELOG_TYPE_EC_SHUTDOWN 0xa5 +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xa7 + extern int elog_init(void); extern int elog_clear(void); extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size);

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New patch to review for coreboot: 8e16a40 reg_script: include in romstage
by Isaac Christensen 01 Oct '14

01 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7003 -gerrit commit 8e16a40014a67c3b0b3f0200ad46befa240e4764 Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Wed Oct 1 11:50:20 2014 -0600 reg_script: include in romstage The new broadwell support uses the reg_script functions in romstage. Change-Id: Ic040bf947d35854711f4c1547858b0e4378ef759 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/lib/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8de4fb7..c104ce3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -86,6 +86,7 @@ ramstage-y += cbmem_info.c ramstage-y += hexdump.c romstage-y += hexdump.c +romstage-$(CONFIG_REG_SCRIPT) += reg_script.c ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c

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New patch to review for coreboot: 5485aca libpayload: usb: xhci: Treat port reset as a port status change
by Isaac Christensen 01 Oct '14

01 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7002 -gerrit commit 5485acaf048932aacc5da9dafb50f01df1d2bec7 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Mar 10 14:46:06 2014 -0700 libpayload: usb: xhci: Treat port reset as a port status change If a port is connected before and after an xhci controller reset, the PORTSC CSC bit may not be asserted. Add an additional check in xhci_rh_port_status_changed for the PRC bit so we can correctly handle ports in such a state. Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Change-Id: I2d623aae647ab13711badd7211ab467afdc69548 Reviewed-on: https://chromium-review.googlesource.com/189394 Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit ee7c3ea182b35bb6ce3c62f301c4515714f6e654) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/drivers/usb/xhci_rh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index 26bb4f9..fa118fe 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -51,7 +51,7 @@ xhci_rh_port_status_changed(usbdev_t *const dev, const int port) xhci_t *const xhci = XHCI_INST(dev->controller); volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc; - const int changed = !!(*portsc & PORTSC_CSC); + const int changed = !!(*portsc & (PORTSC_CSC | PORTSC_PRC)); /* always clear all the status change bits */ *portsc = (*portsc & PORTSC_RW_MASK) | 0x00ef0000; return changed;

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Patch merged into coreboot/master: 21fd2f4 reg_script: Fix bug in IO macros
by gerrit＠coreboot.org 01 Oct '14

01 Oct '14

the following patch was just integrated into master: commit 21fd2f4801bc7761981e509d135663f1a76f98fe Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 22 11:14:12 2014 -0700 reg_script: Fix bug in IO macros These have apparently never been used because they are incorrect. Change-Id: I3624cb2548a0ee3da56a2cca62ed50b0dfbf7817 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196266 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit bc0187702061fe326422c070c592a18cd93de723) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6999 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6999 for details. -gerrit

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Patch merged into coreboot/master: 08f6c80 edid: Support EDID 1.4.
by gerrit＠coreboot.org 01 Oct '14

01 Oct '14

the following patch was just integrated into master: commit 08f6c80d34db90124e7937ac92e930958fb47ca3 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 3 21:13:11 2014 +0800 edid: Support EDID 1.4. EDID v1.4 has changed some fields (0xfc - Monitor Name, 0xfd - Monitor Range Limits) to optional so we need to list the requirements explicitly instead of sharing v1.3 requirements. Change-Id: I5c7ca06893bd20e178bc35164c4ca639c881e00b Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193013 (cherry picked from commit 2ad598b8bd620117e70e13347365d74a7c6b87ef) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6998 for details. -gerrit

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coreboot-gerrit October 2014