coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 99bd783 edid: Relax EDID 1.3 requirements.
by Isaac Christensen 02 Oct '14

02 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7009 -gerrit commit 99bd783772519e2cfca674c99753fce30106b7e9 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 3 21:13:11 2014 +0800 edid: Relax EDID 1.3 requirements. In E-EDID(EDID v1.3), Monitor Name (0xfc) and Monitor Range Limits (0xfd) are always required. However, some panels do not really have these fields. As a workaround (and since we don't really use these fields), we only print warning messages for that case. Change-Id: I81b1db7d7f6c6f9320a862608dec4c7be298d7db Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193742 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit c633215ef8342664d9a4478e821fc8aad368b7f3) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/lib/edid.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 6efe6a9..c8e3203 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1272,12 +1272,22 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (nonconformant_digital_display || !has_valid_string_termination || !has_valid_descriptor_pad || - !has_name_descriptor || - !has_preferred_timing || - !has_range_descriptor) + !has_preferred_timing) { conformant = 0; + } + /** + * According to E-EDID (EDIDv1.3), has_name_descriptor and + * has_range_descriptor are both required. These fields are + * optional in v1.4. However some v1.3 panels (Ex, B133XTN01.3) + * don't have them. As a workaround, we only print warning + * messages. + */ if (!conformant) printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.3!\n"); + else if (!has_name_descriptor || !has_range_descriptor) + printk(BIOS_WARNING, "WARNING: EDID block does NOT " + "fully conform to EDID 1.3.\n"); + if (nonconformant_digital_display) printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n", nonconformant_digital_display);

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New patch to review for coreboot: c8587c6 spi: Remove unused constants from spi-generic.h.
by Isaac Christensen 02 Oct '14

02 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7008 -gerrit commit c8587c6ffbccfdf7ee8b83c58ef22f907fd6b9f2 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Mar 27 20:50:25 2014 -0700 spi: Remove unused constants from spi-generic.h. These constants aren't used anywhere. Change-Id: Ifdad9b088a281909892edb34dcb58419e0e123ba Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/192047 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 3cdaf9dd7de6ae71efc9e74335d876ec55f9ca0a) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/include/spi-generic.h | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 3b10ae9..6c1bc1e 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -28,22 +28,6 @@ /* Controller-specific definitions: */ -/* SPI mode flags */ -#define SPI_CPHA 0x01 /* clock phase */ -#define SPI_CPOL 0x02 /* clock polarity */ -#define SPI_MODE_0 (0|0) /* (original MicroWire) */ -#define SPI_MODE_1 (0|SPI_CPHA) -#define SPI_MODE_2 (SPI_CPOL|0) -#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) -#define SPI_CS_HIGH 0x04 /* CS active high */ -#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ -#define SPI_3WIRE 0x10 /* SI/SO signals shared */ -#define SPI_LOOP 0x20 /* loopback mode */ - -/* SPI transfer flags */ -#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ -#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ - /* SPI opcodes */ #define SPI_OPCODE_WREN 0x06 #define SPI_OPCODE_FAST_READ 0x0b

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Patch merged into coreboot/master: 55cdc16 Provide a way to compile some files with -O0 option
by gerrit＠coreboot.org 02 Oct '14

02 Oct '14

the following patch was just integrated into master: commit 55cdc160bbe1827e8ab1a2370ab1ebb0162e9768 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Apr 22 17:06:43 2014 -0700 Provide a way to compile some files with -O0 option When preparing an image for source level debugging, it is convenient to be able to compile some modules with -O0, which makes it much easier to follow the execution flow. This patch allows to do it by defining GDB_DEBUG=1 in the environment before invoking make. Adding this feature as a common config flag is problematic, because we don't want to compile the entire image with -O0. Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196359 (cherry picked from commit dde4928c045d12e502cb109015a710cd9fdf2a04) Changed from CFLAGS to CFLAGS_common. Change-Id: Ie0be653509509eeb64ea3a7229f54c0c812840a9 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7005 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/7005 for details. -gerrit

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New patch to review for coreboot: 76c6cf6 tpm: i2c: When probing the TPM, write a 0 into the TPM access register.
by Isaac Christensen 02 Oct '14

02 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7007 -gerrit commit 76c6cf6052a22283b71d5abffe120bb34acfc163 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Mar 26 21:51:41 2014 -0700 tpm: i2c: When probing the TPM, write a 0 into the TPM access register. Not doing so makes it fail when run at high frequency. Change-Id: I1cfb69c55f03cb90f66f437289803d897a1aad5c Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/191812 Reviewed-by: Tom Warren <twarren(a)nvidia.com> Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: Tom Warren <twarren(a)nvidia.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 04452441d2bfe2cacd3e0b6990c0e9261b5350d1) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/drivers/i2c/tpm/tis.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 3a5f519..e8d69ac 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -79,10 +79,10 @@ int tis_init(void) * Probe TPM twice; the first probing might fail because TPM is asleep, * and the probing can wake up TPM. */ - uint8_t tmp; + uint8_t tmp = 0; - if (i2c_read(bus, chip, 0, 0, &tmp, sizeof(tmp)) && - i2c_read(bus, chip, 0, 0, &tmp, sizeof(tmp))) + if (i2c_write(bus, chip, 0, 1, &tmp, sizeof(tmp)) && + i2c_write(bus, chip, 0, 1, &tmp, sizeof(tmp))) return -1; return 0;

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Patch merged into coreboot/master: daecc44 elog: Add event type for CPU thermal trip
by gerrit＠coreboot.org 02 Oct '14

02 Oct '14

the following patch was just integrated into master: commit daecc449ca1708a2412df6cd394e299ede36bfe2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon May 12 10:20:45 2014 -0700 elog: Add event type for CPU thermal trip There is a status bit for this event in most intel chipsets that we can read and report. Start by adding the new event type. Change-Id: Ib06411e3b87a1d069fb469943dd445bee6c1291f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199370 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 386a06170ec5afb31d0fe93ace3afbaab897a598) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7004 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/7004 for details. -gerrit

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Patch merged into coreboot/master: e1dad0c libpayload: usb: xhci: Treat port reset as a port status change
by gerrit＠coreboot.org 02 Oct '14

02 Oct '14

the following patch was just integrated into master: commit e1dad0c0b9f3aaf7a5f09a48f44fa8d2d9ef1b72 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Mar 10 14:46:06 2014 -0700 libpayload: usb: xhci: Treat port reset as a port status change If a port is connected before and after an xhci controller reset, the PORTSC CSC bit may not be asserted. Add an additional check in xhci_rh_port_status_changed for the PRC bit so we can correctly handle ports in such a state. Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Change-Id: I2d623aae647ab13711badd7211ab467afdc69548 Reviewed-on: https://chromium-review.googlesource.com/189394 Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit ee7c3ea182b35bb6ce3c62f301c4515714f6e654) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7002 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/7002 for details. -gerrit

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Patch merged into coreboot/master: a16029a libpayload: usb: Remove generic roothub reset port function
by gerrit＠coreboot.org 02 Oct '14

02 Oct '14

the following patch was just integrated into master: commit a16029a93d06dc73f7ee2796db7c90b2211ee776 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Mar 10 14:12:29 2014 -0700 libpayload: usb: Remove generic roothub reset port function The generic roothub reset port function is overly broad and does some things which may be undesirable, such as issuing multiple resets to a port if the reset is deemed to have finished too quickly. Remove the generic function and replace it with a controller-specific function, currently only implemented for xhci. Change-Id: Id46f73ea3341d4d01d2b517c6bf687402022d272 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189495 Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 54e1da075b0106b0a1f736641fa52c39401d349d) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/7001 for details. -gerrit

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Patch merged into coreboot/master: 758f26a nvidia/cbootimage: avoid upstream's build system
by gerrit＠coreboot.org 02 Oct '14

02 Oct '14

the following patch was just integrated into master: commit 758f26aa2dd7447267ac7e08b32ef157fc55a755 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Sep 27 11:37:46 2014 +0200 nvidia/cbootimage: avoid upstream's build system It brings in useless dependencies, a weird autotools configuration, and tons of pain everywhere. Instead just build things ourselves. Change-Id: I67f06e711cb9dcd594363bc1a4f99d3273074549 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6986 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6986 for details. -gerrit

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Patch merged into coreboot/master: e87ee14 baytrail: update C0 microcode
by gerrit＠coreboot.org 01 Oct '14

01 Oct '14

the following patch was just integrated into master: commit e87ee14449fb549be09d6a5de10185f182efdc79 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Mar 26 11:17:58 2014 -0700 baytrail: update C0 microcode baytrail: Add 811 microcode for C0 parts Incorporate 811 microcode version for C0 stepping parts. Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Old-Change-Id: Ic34c233df28fa2c94db3a886faad8239a05f475d Reviewed-on: https://chromium-review.googlesource.com/191693 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 57c9cbdb9e4bb1cf721849ace8958eb6ec032594) baytrail: Add 813 microcode for C0 parts Incorporate 813 microcode version for C0 stepping parts. Old-Change-Id: I513ce5cc1470fa0154bee088547c5cb8a5902fb5 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195200 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit bf15a48c6bd71c2b0ab91530713afb26e139ad9c) baytrail: Update microcode to version 816 Version 816 of microcode. Old-Change-Id: I868702ec94a265013bb5e378a2345ff1cf0dc364 Original-Change-Id: I9a9cacf2d16bdabdb7ec84607bf6c96e4ac3f3c4 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197692 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 16512b09e399c05cf42694854277aa7f1753e49e) Squashed 3 successive updates for baytrail C0 microcode. Change-Id: I76714ae636b119348e6bb9f8a4639c68be32ba3a Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7000 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/7000 for details. -gerrit

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New patch to review for coreboot: ce086d7 reg_script: default to n for ARCH_X86
by Isaac Christensen 01 Oct '14

01 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7006 -gerrit commit ce086d76578026eb4ac1b34bf9488c4f5632f2ac Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Wed Oct 1 13:37:36 2014 -0600 reg_script: default to n for ARCH_X86 The reg_script functionality is only used by specific chipsets so have it selected instead of defaulting to y for ARCH_X86. Change-Id: I8fb9466e148eed7896ca8ed80755c77ba1190583 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index afcaab6..00d5b80 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1120,7 +1120,6 @@ config POWER_BUTTON_IS_OPTIONAL config REG_SCRIPT bool - default y if ARCH_X86 default n help Internal option that controls whether we compile in register scripts. diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index f36394e..b387295 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK + select REG_SCRIPT select SMM_MODULES select SMM_TSEG select SMP

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coreboot-gerrit October 2014