coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: aa5f445 bd82x6x, ibexpeak, lynxpoint: Ensure 0-filling of uninited GNVS vars.
by Vladimir Serbinenko 05 Oct '14

05 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7015 -gerrit commit aa5f445b76c29c95cbf86fd08b9fefa829f20d02 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 5 11:07:33 2014 +0200 bd82x6x, ibexpeak, lynxpoint: Ensure 0-filling of uninited GNVS vars. Change-Id: I672c3ca9e7f30a21330cf1920a25b1ab38b3f282 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/lpc.c | 4 ++++ src/southbridge/intel/ibexpeak/lpc.c | 3 +++ src/southbridge/intel/lynxpoint/lpc.c | 9 ++++++++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index fa05d54..a1c7c2a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -33,6 +33,7 @@ #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> #include <cbmem.h> +#include <string.h> #include "pch.h" #include "nvs.h" @@ -680,6 +681,9 @@ static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oe if (gnvs) { int scopelen; + + memset(gnvs, 0, sizeof (*gnvs)); + acpi_create_gnvs(gnvs); /* IGD OpRegion Base Address */ gnvs->aslb = (u32)opregion; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 7580aa9..1d893e9 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -674,6 +674,9 @@ static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oe if (gnvs) { int scopelen; + + memset(gnvs, 0, sizeof (*gnvs)); + acpi_create_gnvs(gnvs); /* IGD OpRegion Base Address */ gnvs->aslb = (u32)opregion; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d1a7203..451aeab 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -745,7 +745,14 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oem_table_id) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } if (gnvs) { int scopelen;

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New patch to review for coreboot: ca46fae acpi_create_mcfg_mmconfig: Zero-out the structure before filling.
by Vladimir Serbinenko 05 Oct '14

05 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7014 -gerrit commit ca46faeca4454bb6fbf49a8f33ca2ff964f7afef Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 5 11:05:16 2014 +0200 acpi_create_mcfg_mmconfig: Zero-out the structure before filling. Otherwise "reserved" fields end up with a garbage instead of predictable value. Change-Id: I8a036769a8f86f1d6752651601de2800f4f1bd00 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 3bfa3bd..3a30d31 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -118,6 +118,7 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end) { + memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address = base; mmconfig->base_reserved = 0; mmconfig->pci_segment_group_number = seg_nr;

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Patch merged into coreboot/master: a296f9e Kconfig: Allow native vga init to be selectable for SeaBIOS payload
by gerrit＠coreboot.org 04 Oct '14

04 Oct '14

the following patch was just integrated into master: commit a296f9e3d385d2d310aae1cdfd4a20c592de1d20 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 03:43:49 2014 +1000 Kconfig: Allow native vga init to be selectable for SeaBIOS payload Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6891 Tested-by: build bot (Jenkins) Reviewed-by: Kevin O'Connor <kevin(a)koconnor.net> Reviewed-by: Martin Roth <gaumless(a)gmail.com> See http://review.coreboot.org/6891 for details. -gerrit

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Patch merged into coreboot/master: d63b97f mainboard/amd: Sanitise headers in PlatformGnbPcie.c
by gerrit＠coreboot.org 04 Oct '14

04 Oct '14

the following patch was just integrated into master: commit d63b97f9ab5bda1b696a53c66a3b802316762bfe Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jun 12 16:12:43 2014 +1000 mainboard/amd: Sanitise headers in PlatformGnbPcie.c It is hard to see where things are coming from without correct headers. Change-Id: I8e2195b101501ffd25464196283fb2bddb5b8f51 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5980 Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5980 for details. -gerrit

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New patch to review for coreboot: 31004ca cbmem console: Locate the preram console with a symbol instead of a section.
by Isaac Christensen 03 Oct '14

03 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7013 -gerrit commit 31004ca3bd259f400bbeb1a9b3d866e9c09f5623 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 2 17:57:05 2014 -0700 cbmem console: Locate the preram console with a symbol instead of a section. On non-x86 systems, the location of the preram CBMEM console may not be in a predictable place relative to other things in the linker script. That makes it difficult to work with as its own section because the linker will complain if you try to move backwards as it lays out memory. If the console header is treated as an actual blob of memory which has to be put in the image, we'd have to predict where to put it so that it isn't before something with a lower address or after something with a higher address. Symbols, on the other hand, can be defined arbitrarily. Change-Id: I3257b981eee0c15bb997a9f2c55a03494c6ec6f0 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/193164 Reviewed-by: Tom Warren <twarren(a)nvidia.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit a492761c27076bcac080013d509ae4aafd6dc3e3) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/x86/include/arch/early_variables.h | 2 -- src/arch/x86/init/romstage.ld | 14 +++++++------- src/console/Kconfig | 10 +++++----- src/lib/cbmem_console.c | 5 +++-- 5 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 041d0ae..5b58baa 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -21,7 +21,6 @@ #define ARCH_EARLY_VARIABLES_H #define CAR_GLOBAL -#define CAR_CBMEM #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index ea1a133..80e82d6 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -26,10 +26,8 @@ asm(".previous"); asm(".section .car.cbmem_console,\"w\",@nobits"); asm(".previous"); #define CAR_GLOBAL __attribute__((section(".car.global_data"))) -#define CAR_CBMEM __attribute__((section(".car.cbmem_console"))) #else #define CAR_GLOBAL -#define CAR_CBMEM #endif #if defined(__PRE_RAM__) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 5458cfc..d6eb511 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -55,15 +55,15 @@ SECTIONS .car.data . (NOLOAD) : { _car_data_start = .; *(.car.global_data); - /* The cbmem_console section comes last to take advantage of - * a zero-sized array to hold the memconsole contents that - * grows to a bound of CONFIG_CONSOLE_CAR_BUFFER_SIZE. However, - * collisions within the cache-as-ram region cannot be + _car_data_end = .; + /* The preram cbmem console area comes last to take advantage + * of a zero-sized array to hold the memconsole contents that + * grows to a bound of CONFIG_CONSOLE_PRERAM_BUFFER_SIZE. + * However, collisions within the cache-as-ram region cannot be * statically checked because the cache-as-ram region usage is * cpu/chipset dependent. */ - *(.car.cbmem_console); - _car_data_end = .; + preram_cbmem_console = .; } - _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); + _bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); } diff --git a/src/console/Kconfig b/src/console/Kconfig index 472ac5c..619af56 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -184,15 +184,15 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. -config CONSOLE_CAR_BUFFER_SIZE +config CONSOLE_PRERAM_BUFFER_SIZE depends on CONSOLE_CBMEM - hex "Room allocated for console output in Cache as RAM" + hex "Room allocated for console output before RAM is initialized" default 0xc00 help Console is used before RAM is initialized. This is the room reserved - in the DCACHE based RAM to keep console output before it can be - saved in a CBMEM buffer. 3K bytes should be enough even for the - BIOS_SPEW level. + in the DCACHE based RAM, SRAM, etc. to keep console output before it + can be saved in a CBMEM buffer. 3K bytes should be enough even for + the BIOS_SPEW level. config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 9d5419a..b5b75f3 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -44,7 +44,7 @@ static struct cbmem_console *cbmem_console_p CAR_GLOBAL; * the area are defined in the config. */ -static struct cbmem_console car_cbmem_console CAR_CBMEM; +extern struct cbmem_console preram_cbmem_console; #else @@ -86,7 +86,8 @@ static inline void init_console_ptr(void *storage, u32 total_space) void cbmemc_init(void) { #ifdef __PRE_RAM__ - init_console_ptr(&car_cbmem_console, CONFIG_CONSOLE_CAR_BUFFER_SIZE); + init_console_ptr(&preram_cbmem_console, + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE); #else /* * Initializing before CBMEM is available, use static buffer to store

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Patch set updated for coreboot: c2bdb33 edid: Relax EDID 1.3 requirements.
by Paul Menzel 03 Oct '14

03 Oct '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7009 -gerrit commit c2bdb33b6dae2d3ad149204f67bea8cd81879384 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 3 21:13:11 2014 +0800 edid: Relax EDID 1.3 requirements. In E-EDID (EDID v1.3), Monitor Name (0xfc) and Monitor Range Limits (0xfd) are always required. However, some panels do not really have these fields. As a workaround (and since we don't really use these fields), we only print warning messages for that case. Change-Id: I81b1db7d7f6c6f9320a862608dec4c7be298d7db Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193742 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit c633215ef8342664d9a4478e821fc8aad368b7f3) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/lib/edid.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/lib/edid.c b/src/lib/edid.c index 6efe6a9..c8e3203 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1272,12 +1272,22 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (nonconformant_digital_display || !has_valid_string_termination || !has_valid_descriptor_pad || - !has_name_descriptor || - !has_preferred_timing || - !has_range_descriptor) + !has_preferred_timing) { conformant = 0; + } + /** + * According to E-EDID (EDIDv1.3), has_name_descriptor and + * has_range_descriptor are both required. These fields are + * optional in v1.4. However some v1.3 panels (Ex, B133XTN01.3) + * don't have them. As a workaround, we only print warning + * messages. + */ if (!conformant) printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.3!\n"); + else if (!has_name_descriptor || !has_range_descriptor) + printk(BIOS_WARNING, "WARNING: EDID block does NOT " + "fully conform to EDID 1.3.\n"); + if (nonconformant_digital_display) printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n", nonconformant_digital_display);

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New patch to review for coreboot: 2474e4d acpi_add_ssdt_pstates: Remove function.
by Vladimir Serbinenko 03 Oct '14

03 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7012 -gerrit commit 2474e4ddfd6da56919189786580729f1f8149450 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Oct 3 09:39:31 2014 +0200 acpi_add_ssdt_pstates: Remove function. Nowhere in database p_state_num is set. So this whole function ends up being a noop. Moreover the offsets used by it are wrong with any optimizing iasl. Remove it in preparation of move to per-device ACPI. Change-Id: I1f1f9743565aa8f0b8fca472ad4cb6d7542fcecb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/include/arch/acpi.h | 3 - src/include/cpu/amd/amdfam10_sysconf.h | 2 - src/mainboard/advansus/a785e-i/acpi_tables.c | 3 - src/mainboard/amd/bimini_fam10/acpi_tables.c | 3 - .../amd/serengeti_cheetah_fam10/acpi_tables.c | 3 - src/mainboard/amd/tilapia_fam10/acpi_tables.c | 3 - src/mainboard/asus/m4a78-em/acpi_tables.c | 3 - src/mainboard/asus/m5a88-v/acpi_tables.c | 3 - src/mainboard/avalue/eax-785e/acpi_tables.c | 3 - src/mainboard/gigabyte/ma785gm/acpi_tables.c | 3 - src/mainboard/gigabyte/ma785gmt/acpi_tables.c | 3 - src/mainboard/gigabyte/ma78gm/acpi_tables.c | 3 - src/mainboard/jetway/pa78vm5/acpi_tables.c | 3 - src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 3 - src/northbridge/amd/amdfam10/Makefile.inc | 5 -- src/northbridge/amd/amdfam10/acpi.c | 87 ---------------------- 16 files changed, 133 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 4adf89e..aec698a 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -575,9 +575,6 @@ void acpi_jump_to_wakeup(void *wakeup_addr); int __attribute__((weak)) acpi_get_sleep_type(void); #endif /* IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) */ -/* northbridge/amd/amdfam10/amdfam10_acpi.c */ -unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current); - /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(void); diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h index baba6ce..261c2db 100644 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ b/src/include/cpu/amd/amdfam10_sysconf.h @@ -56,8 +56,6 @@ struct amdfam10_sysconf_t { msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5 unsigned needs_update_pstate_msrs; - struct p_state_t p_state[NODE_NUMS * 5]; - unsigned p_state_num; unsigned bsp_apicid; int enabled_apic_ext_id; diff --git a/src/mainboard/advansus/a785e-i/acpi_tables.c b/src/mainboard/advansus/a785e-i/acpi_tables.c index 7853bd1..3f9bd60 100644 --- a/src/mainboard/advansus/a785e-i/acpi_tables.c +++ b/src/mainboard/advansus/a785e-i/acpi_tables.c @@ -157,9 +157,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/amd/bimini_fam10/acpi_tables.c b/src/mainboard/amd/bimini_fam10/acpi_tables.c index 2ec11bb..84abaaa 100644 --- a/src/mainboard/amd/bimini_fam10/acpi_tables.c +++ b/src/mainboard/amd/bimini_fam10/acpi_tables.c @@ -182,9 +182,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index f624424..32649ba 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -252,9 +252,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt, ssdt->length); acpi_add_table(rsdp, ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different possition? We may have to copy, diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c index 898a955..4e56e8b 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ b/src/mainboard/amd/tilapia_fam10/acpi_tables.c @@ -182,9 +182,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/asus/m4a78-em/acpi_tables.c b/src/mainboard/asus/m4a78-em/acpi_tables.c index 2398c01..65f94d5 100644 --- a/src/mainboard/asus/m4a78-em/acpi_tables.c +++ b/src/mainboard/asus/m4a78-em/acpi_tables.c @@ -156,9 +156,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c index 7853bd1..3f9bd60 100644 --- a/src/mainboard/asus/m5a88-v/acpi_tables.c +++ b/src/mainboard/asus/m5a88-v/acpi_tables.c @@ -157,9 +157,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c index 7853bd1..3f9bd60 100644 --- a/src/mainboard/avalue/eax-785e/acpi_tables.c +++ b/src/mainboard/avalue/eax-785e/acpi_tables.c @@ -157,9 +157,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c index 7a5df88..d97a75e 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c @@ -157,9 +157,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c index 07b174c..60e0312 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c @@ -155,9 +155,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/gigabyte/ma78gm/acpi_tables.c b/src/mainboard/gigabyte/ma78gm/acpi_tables.c index 07b174c..60e0312 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma78gm/acpi_tables.c @@ -155,9 +155,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/jetway/pa78vm5/acpi_tables.c b/src/mainboard/jetway/pa78vm5/acpi_tables.c index fc6f186..007d536 100644 --- a/src/mainboard/jetway/pa78vm5/acpi_tables.c +++ b/src/mainboard/jetway/pa78vm5/acpi_tables.c @@ -156,9 +156,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index ae9cca9..660ea6f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -170,9 +170,6 @@ unsigned long write_acpi_tables(unsigned long start) ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - #if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index a24783b..7dc74df 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -3,11 +3,6 @@ ramstage-y += misc_control.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr1.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr2.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr3.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr4.asl -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sspr5.asl ramstage-y += get_pci1234.c diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index abba0ce..513fa58 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -290,90 +290,3 @@ void update_ssdtx(void *ssdtx, int i) } -static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex) -{ - u8 *CPU; - u8 *CPUIN; - u8 *COREFREQ; - u8 *POWER; - u8 *TRANSITION_LAT; - u8 *BUSMASTER_LAT; - u8 *CONTROL; - u8 *STATUS; - unsigned offset = 0x94 - 0x7f; - int i; - - CPU = sspr + 0x38; - CPUIN = sspr + 0x3a; - - COREFREQ = sspr + 0x7f; //2 byte - POWER = sspr + 0x82; //3 bytes - TRANSITION_LAT = sspr + 0x87; //two bytes - BUSMASTER_LAT = sspr + 0x8a; //two bytes - CONTROL = sspr + 0x8d; - STATUS = sspr + 0x8f; - - snprintf((char*)CPU, 3, "%02x", (char)cpuindex); - *CPUIN = (u8) cpuindex; - - for(i=0;i<sysconf.p_state_num;i++) { - struct p_state_t *p_state = &sysconf.p_state[nodeid * 5 + i]; - intx_to_stream(p_state->corefreq, 2, COREFREQ + i*offset); - intx_to_stream(p_state->power, 3, POWER + i*offset); - intx_to_stream(p_state->transition_lat, 2, TRANSITION_LAT + i*offset); - intx_to_stream(p_state->busmaster_lat, 2, BUSMASTER_LAT + i*offset); - *((u8 *)(CONTROL + i*offset)) =(u8) p_state->control; - *((u8 *)(STATUS + i*offset)) =(u8) p_state->status; - } -} - -extern const unsigned char AmlCode_sspr5[]; -extern const unsigned char AmlCode_sspr4[]; -extern const unsigned char AmlCode_sspr3[]; -extern const unsigned char AmlCode_sspr2[]; -extern const unsigned char AmlCode_sspr1[]; - -/* fixme: find one good way for different p_state_num */ -unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current) -{ - device_t cpu; - int cpu_index = 0; - - acpi_header_t *ssdt; - - if(!sysconf.p_state_num) return current; - - void *AmlCode_sspr; - switch(sysconf.p_state_num) { - case 1: AmlCode_sspr = &AmlCode_sspr1; break; - case 2: AmlCode_sspr = &AmlCode_sspr2; break; - case 3: AmlCode_sspr = &AmlCode_sspr3; break; - case 4: AmlCode_sspr = &AmlCode_sspr4; break; - default: AmlCode_sspr = &AmlCode_sspr5; break; - } - - for(cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) { - continue; - } - printk(BIOS_DEBUG, "ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id); - - current = ALIGN(current, 16); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, AmlCode_sspr, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, AmlCode_sspr, ssdt->length); - update_sspr((void*)ssdt,cpu->path.apic.node_id, cpu_index); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - acpi_add_table(rsdp, ssdt); - - cpu_index++; - } - return current; -}

1 0

Patch set updated for coreboot: cd919de mainboard/amd: Sanitise headers in PlatformGnbPcie.c
by Bruce Griffith 03 Oct '14

03 Oct '14

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5980 -gerrit commit cd919de4014891649d68ae3a394b0df5d4e268e8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jun 12 16:12:43 2014 +1000 mainboard/amd: Sanitise headers in PlatformGnbPcie.c It is hard to see where things are coming from without correct headers. Change-Id: I8e2195b101501ffd25464196283fb2bddb5b8f51 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 7 ++----- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 6 +----- src/mainboard/amd/south_station/PlatformGnbPcie.c | 7 ++----- src/mainboard/amd/torpedo/PlatformGnbPcie.c | 9 ++++----- 4 files changed, 9 insertions(+), 20 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index 6c1a3f9..2b0122d 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -17,14 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" +#include "BiosCallOuts.h" #include <string.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 112a8e4..078f3cb 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -17,15 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include "BiosCallOuts.h" #include <string.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index 5c0aba6..a0b8d3d 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -17,14 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" +#include "BiosCallOuts.h" #include <string.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index 3978786..922aa8b 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -17,12 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" +#include "BiosCallOuts.h" + +#include <string.h> +#include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE

1 0

New patch to review for coreboot: 6ee027a libpayload: usb: xhci: Fix STALL endpoint handling
by Isaac Christensen 03 Oct '14

03 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7011 -gerrit commit 6ee027a4acd145172411f14dbd3b2a88d1238f4a Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Apr 2 09:14:32 2014 -0700 libpayload: usb: xhci: Fix STALL endpoint handling - Remove the call to clear_stall in xhci_reset_endpoint because we will call clear_stall from the mass-storage driver. - Remove the xhci_reset_endpoint call from xhci_bulk on STALL since we will reset on the next transfer anyway. - Remove the clear_halt parameter from xhci_bulk since it's now unused. Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Change-Id: I852b87621861109e596ec24b78a8f036d796ff14 Reviewed-on: https://chromium-review.googlesource.com/192866 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit e67e4f0545cbdc074328c83c7edccf9e712cd7be) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/drivers/usb/xhci.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 5b30d0c..2331485 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -461,8 +461,7 @@ xhci_stop (hci_t *controller) } static int -xhci_reset_endpoint(usbdev_t *const dev, endpoint_t *const ep, - const int clear_halt) +xhci_reset_endpoint(usbdev_t *const dev, endpoint_t *const ep) { xhci_t *const xhci = XHCI_INST(dev->controller); const int slot_id = dev->address; @@ -487,10 +486,6 @@ xhci_reset_endpoint(usbdev_t *const dev, endpoint_t *const ep, dev->controller->devices[hub]->speed == HIGH_SPEED) /* TODO */; - /* Try clearing the device' halt condition on non-control endpoints */ - if (clear_halt && ep) - clear_stall(ep); - /* Reset transfer ring if the endpoint is in the right state */ const unsigned ep_state = EC_GET(STATE, epctx); if (ep_state == 3 || ep_state == 4) { @@ -602,7 +597,7 @@ xhci_control(usbdev_t *const dev, const direction_t dir, /* Reset endpoint if it's not running */ const unsigned ep_state = EC_GET(STATE, epctx); if (ep_state > 1) { - if (xhci_reset_endpoint(dev, NULL, 0)) + if (xhci_reset_endpoint(dev, NULL)) return -1; } @@ -713,7 +708,7 @@ xhci_bulk(endpoint_t *const ep, const int size, u8 *const src, /* Reset endpoint if it's not running */ const unsigned ep_state = EC_GET(STATE, epctx); if (ep_state > 1) { - if (xhci_reset_endpoint(ep->dev, ep, 0)) + if (xhci_reset_endpoint(ep->dev, ep)) return -1; } @@ -730,8 +725,6 @@ xhci_bulk(endpoint_t *const ep, const int size, u8 *const src, xhci_debug("Stopping ID %d EP %d\n", ep->dev->address, ep_id); xhci_cmd_stop_endpoint(xhci, ep->dev->address, ep_id); - } else if (ret == -CC_STALL_ERROR) { - xhci_reset_endpoint(ep->dev, ep, 1); } xhci_debug("Bulk transfer failed: %d\n" " ep state: %d -> %d\n"

1 0

New patch to review for coreboot: cf72933 libpayload: usb: Make OHCI work with ARM systems
by Isaac Christensen 03 Oct '14

03 Oct '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7010 -gerrit commit cf72933c426c557cfb7cfa0cc6d29ed0fda604b0 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Apr 8 13:34:11 2014 -0700 libpayload: usb: Make OHCI work with ARM systems This patch enables the OHCI driver to use DMA memory, which is necessary for ARM systems where DMA devices are not cache coherent. I really only need this to test some later OHCI changes, but it was easy enough... copied almost verbatim from ehci.c. Change-Id: Ia717eef28340bd6182a6782e83bfdd0693cf0db1 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193730 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit e46b6ebc439e86a00e13bf656d60cf6c186a3777) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/drivers/usb/ohci.c | 83 +++++++++++++++++++------- payloads/libpayload/drivers/usb/ohci_private.h | 2 + 2 files changed, 62 insertions(+), 23 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 723b0db..e1664cc 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -221,12 +221,18 @@ ohci_init (unsigned long physical_bar) OHCI_INST (controller)->opreg->HcCommandStatus = HostControllerReset; udelay (10); /* at most 10us for reset to complete. State must be set to Operational within 2ms (5.1.1.4) */ OHCI_INST (controller)->opreg->HcFmInterval = interval; - OHCI_INST (controller)->hcca = memalign(256, 256); + OHCI_INST (controller)->hcca = dma_memalign(256, 256); memset((void*)OHCI_INST (controller)->hcca, 0, 256); + if (dma_initialized()) { + OHCI_INST(controller)->dma_buffer = dma_memalign(4096, DMA_SIZE); + if (!OHCI_INST(controller)->dma_buffer) + fatal("Not enough DMA memory for OHCI bounce buffer.\n"); + } + /* Initialize interrupt table. */ u32 *const intr_table = OHCI_INST(controller)->hcca->HccaInterruptTable; - ed_t *const periodic_ed = memalign(sizeof(ed_t), sizeof(ed_t)); + ed_t *const periodic_ed = dma_memalign(sizeof(ed_t), sizeof(ed_t)); memset((void *)periodic_ed, 0, sizeof(*periodic_ed)); for (i = 0; i < 32; ++i) intr_table[i] = virt_to_phys(periodic_ed); @@ -352,12 +358,28 @@ ohci_free_ed (ed_t *const head) } static int -ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen, - unsigned char *data) +ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen, + unsigned char *src) { + u8 *data = src; + u8 *devreq = setup; int remaining = dalen; td_t *cur; + if (!dma_coherent(devreq)) { + devreq = OHCI_INST(dev->controller)->dma_buffer; + memcpy(devreq, setup, drlen); + } + if (dalen > 0 && !dma_coherent(src)) { + data = OHCI_INST(dev->controller)->dma_buffer + drlen; + if (drlen + dalen > DMA_SIZE) { + usb_debug("OHCI control transfer too large for DMA buffer: %d\n", drlen + dalen); + return -1; + } + if (dir == OUT) + memcpy(data, src, dalen); + } + // pages are specified as 4K in OHCI, so don't use getpagesize() int first_page = (unsigned long)data / 4096; int last_page = (unsigned long)(data+dalen-1)/4096; @@ -365,7 +387,7 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen int pages = (dalen==0)?0:(last_page - first_page + 1); /* First TD. */ - td_t *const first_td = (td_t *)memalign(sizeof(td_t), sizeof(td_t)); + td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); memset((void *)first_td, 0, sizeof(*first_td)); cur = first_td; @@ -379,7 +401,7 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen while (pages > 0) { /* One more TD. */ - td_t *const next = (td_t *)memalign(sizeof(td_t), sizeof(td_t)); + td_t *const next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); memset((void *)next, 0, sizeof(*next)); /* Linked to the previous. */ cur->next_td = virt_to_phys(next); @@ -413,7 +435,7 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen } /* One more TD. */ - td_t *const next_td = (td_t *)memalign(sizeof(td_t), sizeof(td_t)); + td_t *const next_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); memset((void *)next_td, 0, sizeof(*next_td)); /* Linked to the previous. */ cur->next_td = virt_to_phys(next_td); @@ -428,13 +450,13 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen cur->buffer_end = 0; /* Final dummy TD. */ - td_t *const final_td = (td_t *)memalign(sizeof(td_t), sizeof(td_t)); + td_t *const final_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); memset((void *)final_td, 0, sizeof(*final_td)); /* Linked to the previous. */ cur->next_td = virt_to_phys(final_td); /* Data structures */ - ed_t *head = memalign(sizeof(ed_t), sizeof(ed_t)); + ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t)); memset((void*)head, 0, sizeof(*head)); head->config = (dev->address << ED_FUNC_SHIFT) | (0 << ED_EP_SHIFT) | @@ -465,21 +487,34 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen /* free memory */ ohci_free_ed(head); - if (result >= 0) + if (result >= 0) { result = dalen - result; + if (dir == IN && data != src) + memcpy(src, data, result); + } return result; } /* finalize == 1: if data is of packet aligned size, add a zero length packet */ static int -ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize) +ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize) { int i; - int remaining = dalen; - usb_debug("bulk: %x bytes from %x, finalize: %x, maxpacketsize: %x\n", dalen, data, finalize, ep->maxpacketsize); - td_t *cur, *next; + int remaining = dalen; + u8 *data = src; + usb_debug("bulk: %x bytes from %x, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize); + + if (!dma_coherent(src)) { + data = OHCI_INST(ep->dev->controller)->dma_buffer; + if (dalen > DMA_SIZE) { + usb_debug("OHCI bulk transfer too large for DMA buffer: %d\n", dalen); + return -1; + } + if (ep->direction == OUT) + memcpy(data, src, dalen); + } // pages are specified as 4K in OHCI, so don't use getpagesize() int first_page = (unsigned long)data / 4096; @@ -493,7 +528,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize) } /* First TD. */ - td_t *const first_td = (td_t *)memalign(sizeof(td_t), sizeof(td_t)); + td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); memset((void *)first_td, 0, sizeof(*first_td)); cur = next = first_td; @@ -531,7 +566,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize) data += second_page_size; } /* One more TD. */ - next = (td_t *)memalign(sizeof(td_t), sizeof(td_t)); + next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); memset((void *)next, 0, sizeof(*next)); /* Linked to the previous. */ cur->next_td = virt_to_phys(next); @@ -543,7 +578,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize) cur = next; /* Data structures */ - ed_t *head = memalign(sizeof(ed_t), sizeof(ed_t)); + ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t)); memset((void*)head, 0, sizeof(*head)); head->config = (ep->dev->address << ED_FUNC_SHIFT) | ((ep->endpoint & 0xf) << ED_EP_SHIFT) | @@ -575,9 +610,11 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize) /* free memory */ ohci_free_ed(head); - if (result >= 0) + if (result >= 0) { result = dalen - result; - else + if (ep->direction == IN && data != src) + memcpy(src, data, result); + } else clear_stall(ep); return result; @@ -638,16 +675,16 @@ ohci_create_intr_queue(endpoint_t *const ep, const int reqsize, return NULL; intr_queue_t *const intrq = - (intr_queue_t *)memalign(sizeof(intrq->ed), sizeof(*intrq)); + (intr_queue_t *)dma_memalign(sizeof(intrq->ed), sizeof(*intrq)); memset(intrq, 0, sizeof(*intrq)); - intrq->data = (u8 *)malloc(reqcount * reqsize); + intrq->data = (u8 *)dma_malloc(reqcount * reqsize); intrq->reqsize = reqsize; intrq->endp = ep; /* Create #reqcount TDs. */ u8 *cur_data = intrq->data; for (i = 0; i < reqcount; ++i) { - intrq_td_t *const td = memalign(sizeof(td->td), sizeof(*td)); + intrq_td_t *const td = dma_memalign(sizeof(td->td), sizeof(*td)); ++intrq->remaining_tds; ohci_fill_intrq_td(td, intrq, cur_data); cur_data += reqsize; @@ -659,7 +696,7 @@ ohci_create_intr_queue(endpoint_t *const ep, const int reqsize, } /* Create last, dummy TD. */ - intrq_td_t *dummy_td = memalign(sizeof(dummy_td->td), sizeof(*dummy_td)); + intrq_td_t *dummy_td = dma_memalign(sizeof(dummy_td->td), sizeof(*dummy_td)); memset(dummy_td, 0, sizeof(*dummy_td)); dummy_td->intrq = intrq; if (last_td) diff --git a/payloads/libpayload/drivers/usb/ohci_private.h b/payloads/libpayload/drivers/usb/ohci_private.h index b6eaf6b..e912837 100644 --- a/payloads/libpayload/drivers/usb/ohci_private.h +++ b/payloads/libpayload/drivers/usb/ohci_private.h @@ -257,6 +257,8 @@ hcca_t *hcca; usbdev_t *roothub; ed_t *periodic_ed; +#define DMA_SIZE (64 * 1024) + void *dma_buffer; } ohci_t; typedef enum { OHCI_SETUP=0, OHCI_OUT=1, OHCI_IN=2, OHCI_FROM_TD=3 } ohci_pid_t;

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coreboot-gerrit October 2014