coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ee16872 libpayload/lpgcc: Add curses include path.
by Vladimir Serbinenko 19 Jan '14

19 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4689 -gerrit commit ee16872921876c9fe0d295a96843c61e71caa942 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Jan 15 22:04:12 2014 +0100 libpayload/lpgcc: Add curses include path. Without it payloads that need curses fail to build. Change-Id: I4533238b547e4c2d9e0778fb7d314db35a9559df Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- payloads/libpayload/bin/lpgcc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 43eb016..4eca091 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -135,6 +135,14 @@ done _CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$BASE/../build -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" +if [ "$CONFIG_PDCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses-3.4" +fi + +if [ "$CONFIG_TINYCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses" +fi + # Check for the -fno-stack-protector silliness trygccoption -fno-stack-protector

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New patch to review for coreboot: a5f5a31 board_info.txt: Add mentions of thinclient names.
by Vladimir Serbinenko 19 Jan '14

19 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4746 -gerrit commit a5f5a31ac0108be1033769c71f415164e309f4d6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 19 12:47:20 2014 +0100 board_info.txt: Add mentions of thinclient names. Based on info from old page Change-Id: Ibd07b5904569e510de249e4216875438a855ff57 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/asi/mb_5blgp/board_info.txt | 1 + src/mainboard/asi/mb_5blmp/board_info.txt | 1 + src/mainboard/bcom/winnet100/board_info.txt | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/asi/mb_5blgp/board_info.txt b/src/mainboard/asi/mb_5blgp/board_info.txt index 0ba2657..2367ec2 100644 --- a/src/mainboard/asi/mb_5blgp/board_info.txt +++ b/src/mainboard/asi/mb_5blgp/board_info.txt @@ -1 +1,2 @@ +Board name: MB-5BLGP (Neoware Eon 4000s thin client) Category: settop diff --git a/src/mainboard/asi/mb_5blmp/board_info.txt b/src/mainboard/asi/mb_5blmp/board_info.txt index f97f123..67e1eb6 100644 --- a/src/mainboard/asi/mb_5blmp/board_info.txt +++ b/src/mainboard/asi/mb_5blmp/board_info.txt @@ -1,3 +1,4 @@ +Board name: MB-5BLMP (IGEL WinNET III thin client) Category: settop Board URL: http://www.hojerteknik.com/winnet.htm Flashrom support: y diff --git a/src/mainboard/bcom/winnet100/board_info.txt b/src/mainboard/bcom/winnet100/board_info.txt index 517b5e8..37afe6c 100644 --- a/src/mainboard/bcom/winnet100/board_info.txt +++ b/src/mainboard/bcom/winnet100/board_info.txt @@ -1,3 +1,4 @@ Category: settop +Board name: WinNET100 (IGEL-316 thin client) Board URL: http://web.archive.org/web/20031207003521/http://www.igel.co.za/igel_316_co… Flashrom support: y

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Patch set updated for coreboot: a00676c boardstatus: Add useful info from old page header to foreword.
by Vladimir Serbinenko 19 Jan '14

19 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4743 -gerrit commit a00676c1f005f45782254c0f19f7c943da8d45c2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 19 03:50:06 2014 +0100 boardstatus: Add useful info from old page header to foreword. Change-Id: Ie3d1be1e51df458cd8b55230c888f032ab705ef8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/board_status/to-wiki/foreword.wiki | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/util/board_status/to-wiki/foreword.wiki b/util/board_status/to-wiki/foreword.wiki index ef64daf..be05c8c 100644 --- a/util/board_status/to-wiki/foreword.wiki +++ b/util/board_status/to-wiki/foreword.wiki @@ -1,12 +1,25 @@ = coreboot status by mainboard = -This list contains reports of successful coreboot execution, ordered by date. It's shows which boards can actually run with current coreboot versions. -Using the precise commit id and config.txt, it's possible to reproduce working coreboot builds (assuming no compiler bugs). +* This list contains reports of successful coreboot execution, ordered by date. It's shows which boards can actually run with current coreboot versions. -By sorting it by date, we encourage developers and users to keep ports current and well-tested. +* Using the precise commit id and config.txt, it's possible to reproduce working coreboot builds (assuming no compiler bugs). -Status data comes from the [http://review.coreboot.org/gitweb?p=board-status.git board status repository]. -The coreboot tree [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=util/board_status… contains a tool] to generate and push suitable data +* By sorting it by date, we encourage developers and users to keep ports current and well-tested. + +* Status data comes from the [http://review.coreboot.org/gitweb?p=board-status.git board status repository]. + +* The coreboot tree [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=util/board_status… contains a tool] to generate and push suitable data as well as the scripts that present the data in wiki format. -An account on review.coreboot.org is required for sending data. +* Board info is automatically generated from Kconfig and board_info.txt files. All boards present in the tree will appear here with varying amount of details. + +* An account on review.coreboot.org is required for sending data. + +* Sometimes the same board is sold under different names, we've tried to list all known names but some names might be missing. + +* Some boards have been removed for various reasons, may be brought back if someone works on them. Consult [[Graveyard]] for details. + +* If the board is not found in the corebootv4's source code, there might be some form of support that is not ready yet for inclusion in coreboot, usually people willing to send their patches to coreboot goes trough [http://review.coreboot.org gerrit], so looking there could find some code for boards that are not yet merged. +* some vendors have their own coreboot trees/fork, like for instance: +** [http://git.xivo.fr/?p=official/xioh/coreboot.git;a=summary xivo's tree] +** [http://git.chromium.org/gitweb/?p=chromiumos/third_party/coreboot.git;a=sum… chrome/chromium's tree]

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Patch set updated for coreboot: 0382b73 adlink/lippert: Add Adlink names for devices with both names.
by Vladimir Serbinenko 19 Jan '14

19 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4744 -gerrit commit 0382b7371b04578e9989d8805680d6622f950544 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 19 05:34:14 2014 +0100 adlink/lippert: Add Adlink names for devices with both names. Change-Id: I6a3f089309a2610986545e4e45e35569ea2772ed Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/adlink/Kconfig | 10 ++++++++++ src/mainboard/adlink/cexpress-gfr/board_info.txt | 8 ++++++++ src/mainboard/adlink/coremodule2-gf/board_info.txt | 8 ++++++++ src/mainboard/lippert/Kconfig | 9 +++++++-- 4 files changed, 33 insertions(+), 2 deletions(-) diff --git a/src/mainboard/adlink/Kconfig b/src/mainboard/adlink/Kconfig index f71d6a9..d61b52a 100644 --- a/src/mainboard/adlink/Kconfig +++ b/src/mainboard/adlink/Kconfig @@ -3,6 +3,16 @@ if VENDOR_ADLINK comment "see under vendor LiPPERT" # any further boards will then be ADLINK +choice + prompt "Mainboard model" + +config BOARD_LIPPERT_FRONTRUNNER_AF + bool "CoreModule2-GF aka LiPPPERT FrontRunner-AF" +config BOARD_LIPPERT_TOUCAN_AF + bool "cExpress-GFR (+W83627DHG SIO) aka LiPPERT Toucan-AF" + +endchoice + config MAINBOARD_VENDOR string default "ADLINK" diff --git a/src/mainboard/adlink/cexpress-gfr/board_info.txt b/src/mainboard/adlink/cexpress-gfr/board_info.txt new file mode 100644 index 0000000..5b59df9 --- /dev/null +++ b/src/mainboard/adlink/cexpress-gfr/board_info.txt @@ -0,0 +1,8 @@ +Category: half +Board name: cExpress-GFR (+W83627DHG SIO) +Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lippert/toucan-af diff --git a/src/mainboard/adlink/coremodule2-gf/board_info.txt b/src/mainboard/adlink/coremodule2-gf/board_info.txt new file mode 100644 index 0000000..251192f --- /dev/null +++ b/src/mainboard/adlink/coremodule2-gf/board_info.txt @@ -0,0 +1,8 @@ +Board name: CoreModule2-GF +Category: half +Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1283 +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lippert/frontrunner-af diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 5d69aae..afb2370 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -23,15 +23,20 @@ config BOARD_LIPPERT_TOUCAN_AF endchoice source "src/mainboard/lippert/frontrunner/Kconfig" -source "src/mainboard/lippert/frontrunner-af/Kconfig" source "src/mainboard/lippert/hurricane-lx/Kconfig" source "src/mainboard/lippert/literunner-lx/Kconfig" source "src/mainboard/lippert/roadrunner-lx/Kconfig" source "src/mainboard/lippert/spacerunner-lx/Kconfig" -source "src/mainboard/lippert/toucan-af/Kconfig" config MAINBOARD_VENDOR string default "LiPPERT" endif # VENDOR_LIPPERT + +if VENDOR_LIPPERT || VENDOR_ADLINK + +source "src/mainboard/lippert/frontrunner-af/Kconfig" +source "src/mainboard/lippert/toucan-af/Kconfig" + +endif

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Patch merged into coreboot/master: 5f88b31 boardstatus: Drop v4 mention of coreboot version.
by gerrit＠coreboot.org 19 Jan '14

19 Jan '14

the following patch was just integrated into master: commit 5f88b318a2240550f9c074af40c8fb00c6da5ef5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 19 03:49:30 2014 +0100 boardstatus: Drop v4 mention of coreboot version. Change-Id: I5cf34e14f6e11c03822a6ce6226365c76e0f6875 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4742 for details. -gerrit

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Patch merged into coreboot/master: b4fc4fd libpayload/options: Fix out of array read.
by gerrit＠coreboot.org 19 Jan '14

19 Jan '14

the following patch was just integrated into master: commit b4fc4fdbc1047201e70bae82b6491fa0b2d2d9d6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Jan 15 22:06:56 2014 +0100 libpayload/options: Fix out of array read. It resulted in garbage in upper bytes of numeric options. Change-Id: I5e5d8b770ed93c7e8a1756a5ce32444b6a045bac Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4691 for details. -gerrit

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Patch merged into coreboot/master: 4a7aa66 libpayload: Bring keyboard_wait_write() back
by gerrit＠coreboot.org 19 Jan '14

19 Jan '14

the following patch was just integrated into master: commit 4a7aa6610e08b3dbac7b5018ec08cd9192be83f6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jan 10 20:40:59 2014 +0100 libpayload: Bring keyboard_wait_write() back Code is using it... Change-Id: I6894b45cbbf70c8e7ce37ce18d93cadf0ea9fbfc Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/4649 for details. -gerrit

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New patch to review for coreboot: 1210c52 cubieboard: Enable the SD controller and mux SD pins
by Alexandru Gagniuc 19 Jan '14

19 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4745 -gerrit commit 1210c529e1063e35f4584fe77e9d72fd5f26e81e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Dec 28 15:10:28 2013 -0500 cubieboard: Enable the SD controller and mux SD pins This step needs to be done before calling any MMC functionality. Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/clock.h | 10 ++++++++++ src/mainboard/cubietech/cubieboard/bootblock.c | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index 0be736c..0a9cfd6 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -66,6 +66,16 @@ /* DRAM_CLK values*/ #define DRAM_CTRL_DCLK_OUT (1 << 15) +/* SDx_CLK values */ +#define SDx_CLK_GATE (1 << 31) +#define SDx_CLK_SRC_MASK (3 << 24) +#define SDx_CLK_SRC_OSC24M (0 << 24) +#define SDx_CLK_SRC_PLL6 (1 << 24) +#define SDx_CLK_SRC_PLL5 (2 << 24) +#define SDx_RAT_EXP_N_MASK (3 << 16) +#define SDx_RAT_EXP_N(n) (((n) << 16) & SDx_RAT_EXP_N_MASK) +#define SDx_RAT_M_MASK (0xf << 0) +#define SDx_RAT_M(m) ((((m) - 1) << 0) & SDx_RAT_M_MASK) /** * \brief Clock gating definitions * diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 2e5929c..c994c57 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -27,6 +27,10 @@ #define GPB_UART0_FUNC 2 #define GPB_UART0_PINS ((1 << 22) | (1 << 23)) +#define GPF_SD0_FUNC 2 +#define GPF_SD0_PINS 0x3f /* PF0 thru PF5 */ +#define GPH1_SD0_DET_FUNC 5 + static void cubieboard_set_sys_clock(void) { u32 reg32; @@ -60,6 +64,13 @@ static void cubieboard_setup_clocks(void) write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0), &ccm->apb1_clk_div_cfg); + /* Configure the clock for SD0 */ + write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) + | SDx_RAT_M(1), &ccm->sd0_clk_cfg); + + /* Enable clock to SD0 */ + a1x_periph_clock_enable(A1X_CLKEN_MMC0); + } static void cubieboard_setup_gpios(void) @@ -71,6 +82,10 @@ static void cubieboard_setup_gpios(void) /* Mux UART pins */ gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); + + /* Mux SD pins */ + gpio_set_multipin_func(GPF, GPF_SD0_PINS, GPF_SD0_FUNC); + gpio_set_pin_func(GPH, 1, GPH1_SD0_DET_FUNC); } static void cubieboard_enable_uart(void)

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Patch set updated for coreboot: b8fee81 cpu/allwinner/a10: Add minimal ramstage driver
by Alexandru Gagniuc 19 Jan '14

19 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4698 -gerrit commit b8fee817d859d7828359b66afbba11330e042cf6 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 3 04:24:35 2014 -0500 cpu/allwinner/a10: Add minimal ramstage driver Change-Id: I857755976b17b0e492c086162f395a77933eeed8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 3 +++ src/cpu/allwinner/a10/cbmem.c | 26 +++++++++++++++++++++ src/cpu/allwinner/a10/chip.h | 11 +++++++++ src/cpu/allwinner/a10/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/ram_segs.h | 30 ++++++++++++++++++++++++ 5 files changed, 118 insertions(+) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 1b720bf..a86d719 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -8,6 +8,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c romstage-y += bootblock_media.c +romstage-y += cbmem.c romstage-y += clock.c romstage-y += pinmux.c romstage-y += timer.c @@ -16,7 +17,9 @@ romstage-y += uart.c romstage-y += uart_console.c ramstage-y += bootblock_media.c +ramstage-y += cbmem.c ramstage-y += clock.c +ramstage-y += cpu.c ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c diff --git a/src/cpu/allwinner/a10/cbmem.c b/src/cpu/allwinner/a10/cbmem.c new file mode 100644 index 0000000..4544b0d --- /dev/null +++ b/src/cpu/allwinner/a10/cbmem.c @@ -0,0 +1,26 @@ +/* + * Provides cbmem utilities for romstage and ramstage + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "ram_segs.h" +#include <cbmem.h> + +#if CONFIG_DYNAMIC_CBMEM + +void *cbmem_top(void) +{ + return a1x_get_cbmem_top(); +} + +#else + +void get_cbmem_table(u64 *base, u64 *size) +{ + *size = CONFIG_COREBOOT_TABLES_SIZE; + *base = (unsigned)a1x_get_cbmem_top() - CONFIG_COREBOOT_TABLES_SIZE; +} + +#endif diff --git a/src/cpu/allwinner/a10/chip.h b/src/cpu/allwinner/a10/chip.h new file mode 100644 index 0000000..16f60c0 --- /dev/null +++ b/src/cpu/allwinner/a10/chip.h @@ -0,0 +1,11 @@ +/* + * Allwinnwer A10 devicetree config struct + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> + +struct cpu_allwinner_a10_config { +}; diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c new file mode 100644 index 0000000..e0d4cdf --- /dev/null +++ b/src/cpu/allwinner/a10/cpu.c @@ -0,0 +1,48 @@ +/* + * Ramstage initialization for Allwinner CPUs + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cbmem.h> + + +static void cpu_enable_resources(device_t dev) +{ + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10, + CONFIG_DRAM_SIZE_MB << 10); + /* TODO: Declare CBFS cache as reserved? There's no guarantee we won't + * overwrite it. It seems to stay intact, being so high in RAM + */ +} + +static void cpu_init(device_t dev) +{ + /* TODO: Check if anything else needs to be explicitly initialized */ +} + +static void cpu_noop(device_t dev) +{ +} + +static struct device_operations cpu_ops = { + .read_resources = cpu_noop, + .set_resources = cpu_noop, + .enable_resources = cpu_enable_resources, + .init = cpu_init, + .scan_bus = NULL, +}; + +static void a1x_cpu_enable_dev(device_t dev) +{ + dev->ops = &cpu_ops; +} + +struct chip_operations cpu_allwinner_a10_ops = { + CHIP_NAME("CPU Allwinner A10") + .enable_dev = a1x_cpu_enable_dev, +}; diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h new file mode 100644 index 0000000..45141fe --- /dev/null +++ b/src/cpu/allwinner/a10/ram_segs.h @@ -0,0 +1,30 @@ +/* + * How we use DRAM on Allwinner CPUs + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <config.h> + +/* + * Put CBMEM at top of RAM + */ +static inline void *a1x_get_cbmem_top(void) +{ + return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20); +} + +/* + * By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region. + */ +static inline void *a1x_get_cbfs_cache_top(void) +{ + /* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */ + return a1x_get_cbmem_top() - (16 << 20); +} + +static inline void *a1x_get_cbfs_cache_base(void) +{ + return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE; +}

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New patch to review for coreboot: 367c267 adlink/lippert: Add Adlink names for devices with both names.
by Vladimir Serbinenko 19 Jan '14

19 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4744 -gerrit commit 367c2671851ad352e0963b4748b51eb1f1a94f6e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 19 05:34:14 2014 +0100 adlink/lippert: Add Adlink names for devices with both names. Change-Id: I6a3f089309a2610986545e4e45e35569ea2772ed Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/adlink/cexpress-gfr/board_info.txt | 8 ++++++++ src/mainboard/adlink/coremodule2-gf/board_info.txt | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/src/mainboard/adlink/cexpress-gfr/board_info.txt b/src/mainboard/adlink/cexpress-gfr/board_info.txt new file mode 100644 index 0000000..5b59df9 --- /dev/null +++ b/src/mainboard/adlink/cexpress-gfr/board_info.txt @@ -0,0 +1,8 @@ +Category: half +Board name: cExpress-GFR (+W83627DHG SIO) +Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lippert/toucan-af diff --git a/src/mainboard/adlink/coremodule2-gf/board_info.txt b/src/mainboard/adlink/coremodule2-gf/board_info.txt new file mode 100644 index 0000000..251192f --- /dev/null +++ b/src/mainboard/adlink/coremodule2-gf/board_info.txt @@ -0,0 +1,8 @@ +Board name: CoreModule2-GF +Category: half +Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1283 +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lippert/frontrunner-af

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coreboot-gerrit January 2014