Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4778
-gerrit
commit 34cfac9b926c472846f6ddc10e1d5334601e8d41
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Jan 22 17:12:35 2014 +0100
lenovo/x230: Add missing copyright line.
Change-Id: I5ecd25e23cebf83d4ae9300307aaac527e05c377
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/lenovo/x230/cmos.layout | 1 +
src/mainboard/lenovo/x230/dsdt.asl | 1 +
src/mainboard/lenovo/x230/fadt.c | 1 +
src/mainboard/lenovo/x230/gpio.h | 1 +
src/mainboard/lenovo/x230/hda_verb.h | 1 +
src/mainboard/lenovo/x230/mainboard.c | 1 +
src/mainboard/lenovo/x230/romstage.c | 1 +
src/mainboard/lenovo/x230/smihandler.c | 1 +
src/mainboard/lenovo/x230/thermal.h | 1 +
9 files changed, 9 insertions(+)
diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout
index 49a5fc1..6f8822f 100644
--- a/src/mainboard/lenovo/x230/cmos.layout
+++ b/src/mainboard/lenovo/x230/cmos.layout
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
index 0477226..20b0232 100644
--- a/src/mainboard/lenovo/x230/dsdt.asl
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -3,6 +3,7 @@
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/lenovo/x230/fadt.c b/src/mainboard/lenovo/x230/fadt.c
index 0ce3c72..27e6303 100644
--- a/src/mainboard/lenovo/x230/fadt.c
+++ b/src/mainboard/lenovo/x230/fadt.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/lenovo/x230/gpio.h b/src/mainboard/lenovo/x230/gpio.h
index 1ede56e..f0a32a8 100644
--- a/src/mainboard/lenovo/x230/gpio.h
+++ b/src/mainboard/lenovo/x230/gpio.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/lenovo/x230/hda_verb.h b/src/mainboard/lenovo/x230/hda_verb.h
index 2e5c7e5..a319c28 100644
--- a/src/mainboard/lenovo/x230/hda_verb.h
+++ b/src/mainboard/lenovo/x230/hda_verb.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c
index d32a75d..dbeff5a 100644
--- a/src/mainboard/lenovo/x230/mainboard.c
+++ b/src/mainboard/lenovo/x230/mainboard.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011-2012 Google Inc.
+ * Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index cfd0518..3ce4218 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c
index ca92091..bbe08e2 100644
--- a/src/mainboard/lenovo/x230/smihandler.c
+++ b/src/mainboard/lenovo/x230/smihandler.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h
index bae0e7f..ab24bb1 100644
--- a/src/mainboard/lenovo/x230/thermal.h
+++ b/src/mainboard/lenovo/x230/thermal.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4650
-gerrit
commit e3d4406c2dec03148e19f57f4be9f3e244299093
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Jun 7 02:11:41 2013 +0200
Make version look like something thinkpad_acpi would accept
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.
Not cleaned up as the idea of this patch seems to be met with resistance.
Can make it Thinkpad-specific if the idea is accepted.
Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/smbios.c | 7 +++++--
src/mainboard/lenovo/Kconfig | 4 ++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 65bf538..25bdb37 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -130,12 +130,15 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->vendor = smbios_add_string(t->eos, "coreboot");
#if !CONFIG_CHROMEOS
+#ifndef CONFIG_VENDOR_VERSION
+#define CONFIG_VENDOR_VERSION ""
+#endif
t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
if (strlen(CONFIG_LOCALVERSION))
- t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION CONFIG_LOCALVERSION);
else
- t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION COREBOOT_VERSION);
#else
#define SPACES \
" "
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index a29fdbf..21413fc 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -41,4 +41,8 @@ config MAINBOARD_VENDOR
string
default "Lenovo"
+config VENDOR_VERSION
+ string
+ default "CBET4000 "
+
endif # VENDOR_LENOVO
the following patch was just integrated into master:
commit 133ede83554f5eface210118c9f8db4c0d75f6f2
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 12 15:26:15 2014 +0100
Lenovo X230: new port
probably a problem in MRC:
- EHCI output failure after sysagent
- no S3
- no MRC cache
- MRC needs watchdog
- less MTRR could be used by some memory map optimisations
Not tested:
- dock (probably doesn't work)
- msata (probably works)
- wwan (probably works)
- mini displayport (probably works)
Blobs:
MRC
VGA Oprom
Change-Id: I5bdb9372971f48e048848d57b6c924b79782dbde
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
See http://review.coreboot.org/4679 for details.
-gerrit
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4777
-gerrit
commit 0fea3782c27dfa00dde0f776cd24d16cc96bea2e
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Jan 21 18:31:35 2014 -0600
intel/bd82x6x: Rename SATA speed "support" register to "limit"
"sata_interface_speed_support" implies that we must tell coreboot, via
devicetree.cb at what speed the SATA ports can operate. However, that
is not necessary, and the actual use of this register is to limit the
speed of all ports connected to the PCH.
As such, use "sata_interface_speed_limit" as a better name.
Change-Id: Icb07644d7bb044687b6b571bee6e2bde7f4cab85
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/google/butterfly/devicetree.cb | 2 +-
src/mainboard/google/stout/devicetree.cb | 2 +-
src/mainboard/kontron/ktqm77/devicetree.cb | 2 +-
src/southbridge/intel/bd82x6x/chip.h | 16 +++++++++++-----
src/southbridge/intel/bd82x6x/sata.c | 4 ++--
src/southbridge/intel/ibexpeak/sata.c | 4 ++--
6 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 9a7a1d5..36f3ba3 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -59,7 +59,7 @@ chip northbridge/intel/sandybridge
# Enable SATA ports 0 & 1
register "sata_port_map" = "0x3"
# Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_support" = "0x2"
+ register "sata_interface_speed_limit" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 653d3fe..e157035 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -59,7 +59,7 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x3"
# Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_support" = "0x2"
+ register "sata_interface_speed_limit" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index f6390ac..c850609 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge
# Enable all SATA ports 0-5
register "sata_port_map" = "0x3f"
# Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
- register "sata_interface_speed_support" = "0x3"
+ register "sata_interface_speed_limit" = "0x3"
# TODO: Enable generic LPC decodes...
register "gen1_dec" = "0x001c02e1"
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 0f2f0e9..c722da5 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -69,15 +69,21 @@ struct southbridge_intel_bd82x6x_config {
uint32_t sata_port1_gen3_tx;
/**
- * SATA Interface Speed Support Configuration
+ * SATA Interface Speed Support Configuration (ISS)
+ *
+ * This option limits the maximum SATA link speed on all SATA ports.
+ * For systems with a mix of 6G and 3G ports, each port will operate up
+ * to its capability, but not any higher than the limit set here. This
+ * option should only be used if the SATA port cannot operate at its
+ * full speed due to hardware bugs, such as board mis-routing.
*
* Only the lower two bits have a meaning:
* 00 - No effect (leave as chip default)
- * 01 - 1.5 Gb/s maximum speed
- * 10 - 3.0 Gb/s maximum speed
- * 11 - 6.0 Gb/s maximum speed
+ * 01 - 1.5 Gb/s maximum speed (Gen 1)
+ * 10 - 3.0 Gb/s maximum speed (Gen 2)
+ * 11 - 6.0 Gb/s maximum speed (Gen 3)
*/
- uint8_t sata_interface_speed_support;
+ uint8_t sata_interface_speed_limit;
uint32_t gen1_dec;
uint32_t gen2_dec;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 133ebee..8d12202 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -107,10 +107,10 @@ static void sata_init(struct device *dev)
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
/* Set ISS, if available */
- if (config->sata_interface_speed_support)
+ if (config->sata_interface_speed_limit)
{
reg32 &= ~0x00f00000;
- reg32 |= (config->sata_interface_speed_support & 0x03)
+ reg32 |= (config->sata_interface_speed_limit & 0x03)
<< 20;
}
write32(abar + 0x00, reg32);
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 078dc8e..2a6e454 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -110,9 +110,9 @@ static void sata_init(struct device *dev)
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
/* Set ISS, if available */
- if (config->sata_interface_speed_support) {
+ if (config->sata_interface_speed_limit) {
reg32 &= ~0x00f00000;
- reg32 |= (config->sata_interface_speed_support & 0x03)
+ reg32 |= (config->sata_interface_speed_limit & 0x03)
<< 20;
}
write32(abar + 0x00, reg32);