coreboot-gerrit December 2013

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Patch set updated for coreboot: 637a6ff cpu/allwinner/a10: Clarify the usage of SRAM during bootblock
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4563 -gerrit commit 637a6ff12ed827756825d858427469093cb7027a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 18:51:29 2013 -0500 cpu/allwinner/a10: Clarify the usage of SRAM during bootblock We have 32KiB of usable SRAM right when we boot. The first 24KiB can be loaded with our bootblock, while the other 8KiB can be used as stack during the bootblock stage. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Change-Id: I48d3a37869031c3c1dbc1fab71204d473d64deeb --- src/cpu/allwinner/a10/Kconfig | 10 +++++++--- src/cpu/allwinner/a10/Makefile.inc | 15 ++++++++------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 639108a..3df1ceb 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -42,18 +42,22 @@ config ROMSTAGE_BASE hex default SYS_SDRAM_BASE -# Keep the stack in SRAM +# Keep the stack in SRAM block A2. +# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the +# CPU. This gives us 32KiB of SRAM to boot with. The BROM bootloader will use up +# to 24KiB to load our bootblock, which leaves us the area from 24KiB to 32KiB +# to use however we see fit. config STACK_TOP hex default 0x00008000 config STACK_BOTTOM hex - default 0x00004000 + default 0x00006000 config STACK_SIZE hex - default 0x00004000 + default 0x00002000 ## TODO Change this to some better address not overlapping bootblock when ## cbfstool supports creating header in arbitrary location. diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 48f3110..9f7208a 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -21,15 +21,16 @@ get_bootblock_size= \ sed 's/[^0-9 ]//g')) \ $(shell echo $$(($(word 2, $(strip $(bb_s)))))) -# The boot ROM in the SoC will start loading code if a special boot0 header is +# The boot ROM in the SoC will start loading code if a special BOOT0 header is # found (at an offset of 8KiB in either NAND or SD), and the checksum is -# correct. this header is normally added by the 'mxsunxiboot' tool. The file -# passed to mksunxiboot should only include the bootblock due to size -# limitations. -# FIXME: Figure out how to safely integrate in coreboot.rom. For now, only copy -# the first 15 KiB of coreboot.rom (This will not collide with stack) +# correct. This header is normally added by the 'mxsunxiboot' tool. The boot ROM +# will load at most 24KiB of data to SRAM, so limit the file size accordingly. +# The BOOT0 header takes 32 bytes, so limit our file to 24KiB - 32 bytes. +# FIXME: Figure out how to safely integrate in coreboot.rom. +# FIXME: The file passed to mksunxiboot should only include the bootblock due +# to size limitations. $(obj)/BOOT0: $(obj)/coreboot.rom @printf " BOOT0 $(subst $(obj)/,,$(^))\n" touch $@ - dd if=$^ of=$^.tmp bs=1024 count=15 + dd if=$^ of=$^.tmp bs=24544 count=1 -mksunxiboot $^.tmp $@

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Patch set updated for coreboot: e87a900 cpu: Add initial support for Allwinner A10 SoC
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4549 -gerrit commit e87a9007451050307084bdfa1e83540282aa2b31 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 13 20:44:48 2013 -0600 cpu: Add initial support for Allwinner A10 SoC Add minimal support needed to get a bootblock capable of initialising a serial console. Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/Kconfig | 1 + src/cpu/Makefile.inc | 1 + src/cpu/allwinner/Kconfig | 1 + src/cpu/allwinner/Makefile.inc | 1 + src/cpu/allwinner/a10/Kconfig | 115 +++++++++++++++++++++++++++ src/cpu/allwinner/a10/Makefile.inc | 35 ++++++++ src/cpu/allwinner/a10/bootblock.c | 21 +++++ src/cpu/allwinner/a10/bootblock_media.c | 14 ++++ src/cpu/allwinner/a10/clock.h | 137 ++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/gpio.h | 51 ++++++++++++ src/cpu/allwinner/a10/memmap.h | 117 +++++++++++++++++++++++++++ src/cpu/allwinner/a10/monotonic_timer.c | 13 +++ src/cpu/allwinner/a10/pinmux.c | 30 +++++++ src/cpu/allwinner/a10/timer.c | 19 +++++ src/cpu/allwinner/a10/uart.c | 98 +++++++++++++++++++++++ src/cpu/allwinner/a10/uart.h | 77 ++++++++++++++++++ src/cpu/allwinner/a10/uart_console.c | 109 +++++++++++++++++++++++++ 17 files changed, 840 insertions(+) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index cd6c7a0..f3883d3 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -3,6 +3,7 @@ # (See also src/Kconfig) if ARCH_ARMV7 +source src/cpu/allwinner/Kconfig source src/cpu/armltd/Kconfig source src/cpu/samsung/Kconfig source src/cpu/ti/Kconfig diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 7cd9d5f..f206fdc 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,6 +1,7 @@ ################################################################################ ## Subdirectories ################################################################################ +subdirs-y += allwinner subdirs-y += amd subdirs-y += dmp subdirs-y += armltd diff --git a/src/cpu/allwinner/Kconfig b/src/cpu/allwinner/Kconfig new file mode 100644 index 0000000..d97cb64 --- /dev/null +++ b/src/cpu/allwinner/Kconfig @@ -0,0 +1 @@ +source src/cpu/allwinner/a10/Kconfig diff --git a/src/cpu/allwinner/Makefile.inc b/src/cpu/allwinner/Makefile.inc new file mode 100644 index 0000000..e52a12e --- /dev/null +++ b/src/cpu/allwinner/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_ALLWINNER_A10) += a10 diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig new file mode 100644 index 0000000..639108a --- /dev/null +++ b/src/cpu/allwinner/a10/Kconfig @@ -0,0 +1,115 @@ +config CPU_ALLWINNER_A10 + bool + default n + +if CPU_ALLWINNER_A10 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select HAVE_UART_MEMORY_MAPPED + select BOOTBLOCK_CONSOLE + select EARLY_CONSOLE + +config BOOTBLOCK_CPU_INIT + string + default "cpu/allwinner/a10/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + +# The "eGON.BT0" header takes 32 bytes +config BOOTBLOCK_BASE + hex + default 0x20 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x00 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x10 + +config CBFS_ROM_OFFSET + # Calculated by BL1 + max bootblock size. + default 0x4c00 + +# FIXME: untested +config ROMSTAGE_BASE + hex + default SYS_SDRAM_BASE + +# Keep the stack in SRAM +config STACK_TOP + hex + default 0x00008000 + +config STACK_BOTTOM + hex + default 0x00004000 + +config STACK_SIZE + hex + default 0x00004000 + +## TODO Change this to some better address not overlapping bootblock when +## cbfstool supports creating header in arbitrary location. +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x40 + +config SYS_SDRAM_BASE + hex + default 0x40000000 + +choice CONSOLE_SERIAL_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART0 + depends on CONSOLE_SERIAL_UART + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +config CONSOLE_SERIAL_UART4 + bool "UART4" + help + Serial console on UART4 + +config CONSOLE_SERIAL_UART5 + bool "UART5" + help + Serial console on UART5 + +config CONSOLE_SERIAL_UART6 + bool "UART6" + help + Serial console on UART6 + +config CONSOLE_SERIAL_UART7 + bool "UART7" + help + Serial console on UART7 + +endchoice + +endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc new file mode 100644 index 0000000..48f3110 --- /dev/null +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -0,0 +1,35 @@ +bootblock-y += pinmux.c +bootblock-y += bootblock_media.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c + +romstage-y += uart.c +romstage-y += uart_console.c +romstage-y += bootblock_media.c + +ramstage-y += uart.c +ramstage-y += uart_console.c +ramstage-y += timer.c +ramstage-y += monotonic_timer.c +ramstage-y += bootblock_media.c + + +real-target: $(obj)/BOOT0 + +get_bootblock_size= \ + $(eval bb_s=$(shell $(CBFSTOOL) $(1) print | grep bootblocksize | \ + sed 's/[^0-9 ]//g')) \ + $(shell echo $$(($(word 2, $(strip $(bb_s)))))) + +# The boot ROM in the SoC will start loading code if a special boot0 header is +# found (at an offset of 8KiB in either NAND or SD), and the checksum is +# correct. this header is normally added by the 'mxsunxiboot' tool. The file +# passed to mksunxiboot should only include the bootblock due to size +# limitations. +# FIXME: Figure out how to safely integrate in coreboot.rom. For now, only copy +# the first 15 KiB of coreboot.rom (This will not collide with stack) +$(obj)/BOOT0: $(obj)/coreboot.rom + @printf " BOOT0 $(subst $(obj)/,,$(^))\n" + touch $@ + dd if=$^ of=$^.tmp bs=1024 count=15 + -mksunxiboot $^.tmp $@ diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c new file mode 100644 index 0000000..38fe953 --- /dev/null +++ b/src/cpu/allwinner/a10/bootblock.c @@ -0,0 +1,21 @@ +/* + * Allwinner A10 bootblock initialization + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> +#include <arch/cache.h> + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ + uint32_t sctlr; + + /* enable dcache */ + sctlr = read_sctlr(); + sctlr |= SCTLR_C; + write_sctlr(sctlr); +} diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c new file mode 100644 index 0000000..a5863b6 --- /dev/null +++ b/src/cpu/allwinner/a10/bootblock_media.c @@ -0,0 +1,14 @@ +/* + * CBFS accessors for bootblock stage. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ +#include <cbfs.h> +#include <console/console.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + printk(BIOS_ERR, "Oh my! I don't know how to access CBFS yet."); + return 0; +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h new file mode 100644 index 0000000..e028d13 --- /dev/null +++ b/src/cpu/allwinner/a10/clock.h @@ -0,0 +1,137 @@ +/* + * Definitions for clock control and gating on Allwinner CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_CLOCK_H +#define CPU_ALLWINNER_A10_CLOCK_H + +#include "memmap.h" +#include <types.h> + +/* CPU_AHB_APB0 config values */ +#define CPU_CLK_SRC_MASK (3 << 16) +#define CPU_CLK_SRC_OSC24M (1 << 16) +#define CPU_CLK_SRC_PLL1 (2 << 16) +#define APB0_DIV_MASK (3 << 8) +#define APB0_DIV_1 (0 << 8) +#define APB0_DIV_2 (1 << 8) +#define APB0_DIV_4 (2 << 8) +#define APB0_DIV_8 (3 << 8) +#define AHB_DIV_MASK (3 << 4) +#define AHB_DIV_1 (0 << 4) +#define AHB_DIV_2 (1 << 4) +#define AHB_DIV_4 (2 << 4) +#define AHB_DIV_8 (3 << 4) +#define AXI_DIV_MASK (3 << 0) +#define AXI_DIV_1 (0 << 0) +#define AXI_DIV_2 (1 << 0) +#define AXI_DIV_3 (2 << 0) +#define AXI_DIV_4 (3 << 0) + +/* APB1_CLK_DIV values */ +#define APB1_CLK_SRC_MASK (3 << 24) +#define APB1_CLK_SRC_OSC24M (0 << 24) +#define APB1_CLK_SRC_PLL6 (1 << 24) +#define APB1_CLK_SRC_32K (2 << 24) +#define APB1_RAT_N_MASK (3 << 16) +#define APB1_RAT_N(m) (((m) & 0x3) << 16) +#define APB1_RAT_M_MASK 0x1f << 0) +#define APB1_RAT_M(n) (((n) & 0x1f) << 0) + +/* APB0_GATING values */ +#define APB0_GATE_KEYPAD (1 << 10) +#define APB0_GATE_IR(x) (((1 << (x)) & 0x3) << 6) +#define APB0_GATE_PIO (1 << 5) +#define APB0_GATE_IIS (1 << 3) +#define APB0_GATE_AC97 (1 << 2) +#define APB0_GATE_CODEC (1 << 0) + +/* APB1_GATING values */ +#define APB1_GATE_UART(x) (((1 << (x)) & 0xff) << 16) +#define APB1_GATE_PS2(x) (((1 << (x)) & 0x3) << 6) +#define APB1_GATE_CAN (1 << 4) +#define APB1_GATE_TWI(x) (((1 << (x)) & 0x7) << 0) + +struct a10_ccm { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_cfg; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ +} __attribute__ ((packed)); + +#endif /* CPU_ALLWINNER_A10_CLOCK_H */ diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h new file mode 100644 index 0000000..f285451 --- /dev/null +++ b/src/cpu/allwinner/a10/gpio.h @@ -0,0 +1,51 @@ +/* + * Definitions for GPIO and pin multiplexing on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef __CPU_ALLWINNER_A10_PINMUX_H +#define __CPU_ALLWINNER_A10_PINMUX_H + +#include <types.h> + +#define GPIO_BASE 0x01C20800 + +#define GPA 0 +#define GPB 1 +#define GPC 2 +#define GPD 3 +#define GPE 4 +#define GPF 5 +#define GPG 6 +#define GPH 7 +#define GPI 8 +#define GPS 9 + +struct a10_gpio_port { + u32 cfg[4]; + u32 dat; + u32 drv[2]; + u32 pul[2]; +} __attribute__ ((packed)); + +struct a10_gpio { + struct a10_gpio_port port[10]; + u8 reserved_0x168[0x98]; + + /* Offset 0x200 */ + u32 int_cfg[4]; + + u32 int_ctl; + u32 int_sta; + u8 reserved_0x21C[4]; + u32 int_deb; + + u32 sdr_pad_drv; + u32 sdr_pad_pul; +} __attribute__ ((packed)); + +void gpio_set_func(u8 port, u8 pin, u8 pad_func); + +#endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/memmap.h b/src/cpu/allwinner/a10/memmap.h new file mode 100644 index 0000000..78d81dc --- /dev/null +++ b/src/cpu/allwinner/a10/memmap.h @@ -0,0 +1,117 @@ +/* + * Memory map definitions for Allwinner A10 CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_MEMMAP_H +#define CPU_ALLWINNER_A10_MEMMAP_H + +#define A1X_SRAM_A1_BASE 0x00000000 +#define A1X_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define A1X_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define A1X_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define A1X_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define A1X_SRAM_D_BASE 0x01c00000 +#define A1X_SRAM_B_BASE 0x01c00000 /* 64 kiB (secure) */ + +#define A1X_SRAMC_BASE 0x01c00000 +#define A1X_DRAMC_BASE 0x01c01000 +#define A1X_DMA_BASE 0x01c02000 +#define A1X_NFC_BASE 0x01c03000 +#define A1X_TS_BASE 0x01c04000 +#define A1X_SPI0_BASE 0x01c05000 +#define A1X_SPI1_BASE 0x01c06000 +#define A1X_MS_BASE 0x01c07000 +#define A1X_TVD_BASE 0x01c08000 +#define A1X_CSI0_BASE 0x01c09000 +#define A1X_TVE0_BASE 0x01c0a000 +#define A1X_EMAC_BASE 0x01c0b000 +#define A1X_LCD0_BASE 0x01c0C000 +#define A1X_LCD1_BASE 0x01c0d000 +#define A1X_VE_BASE 0x01c0e000 +#define A1X_MMC0_BASE 0x01c0f000 +#define A1X_MMC1_BASE 0x01c10000 +#define A1X_MMC2_BASE 0x01c11000 +#define A1X_MMC3_BASE 0x01c12000 +#define A1X_USB0_BASE 0x01c13000 +#define A1X_USB1_BASE 0x01c14000 +#define A1X_SS_BASE 0x01c15000 +#define A1X_HDMI_BASE 0x01c16000 +#define A1X_SPI2_BASE 0x01c17000 +#define A1X_SATA_BASE 0x01c18000 +#define A1X_PATA_BASE 0x01c19000 +#define A1X_ACE_BASE 0x01c1a000 +#define A1X_TVE1_BASE 0x01c1b000 +#define A1X_USB2_BASE 0x01c1c000 +#define A1X_CSI1_BASE 0x01c1d000 +#define A1X_TZASC_BASE 0x01c1e000 +#define A1X_SPI3_BASE 0x01c1f000 + +#define A1X_CCM_BASE 0x01c20000 +#define A1X_INTC_BASE 0x01c20400 +#define A1X_PIO_BASE 0x01c20800 +#define A1X_TIMER_BASE 0x01c20c00 +#define A1X_SPDIF_BASE 0x01c21000 +#define A1X_AC97_BASE 0x01c21400 +#define A1X_IR0_BASE 0x01c21800 +#define A1X_IR1_BASE 0x01c21c00 + +#define A1X_IIS_BASE 0x01c22400 +#define A1X_LRADC_BASE 0x01c22800 +#define A1X_AD_DA_BASE 0x01c22c00 +#define A1X_KEYPAD_BASE 0x01c23000 +#define A1X_TZPC_BASE 0x01c23400 +#define A1X_SID_BASE 0x01c23800 +#define A1X_SJTAG_BASE 0x01c23c00 + +#define A1X_TP_BASE 0x01c25000 +#define A1X_PMU_BASE 0x01c25400 +#define A1X_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */ + +#define A1X_UART0_BASE 0x01c28000 +#define A1X_UART1_BASE 0x01c28400 +#define A1X_UART2_BASE 0x01c28800 +#define A1X_UART3_BASE 0x01c28c00 +#define A1X_UART4_BASE 0x01c29000 +#define A1X_UART5_BASE 0x01c29400 +#define A1X_UART6_BASE 0x01c29800 +#define A1X_UART7_BASE 0x01c29c00 +#define A1X_PS2_0_BASE 0x01c2a000 +#define A1X_PS2_1_BASE 0x01c2a400 + +#define A1X_TWI0_BASE 0x01c2ac00 +#define A1X_TWI1_BASE 0x01c2b000 +#define A1X_TWI2_BASE 0x01c2b400 + +#define A1X_CAN_BASE 0x01c2bc00 + +#define A1X_SCR_BASE 0x01c2c400 + +#define A1X_GPS_BASE 0x01c30000 +#define A1X_MALI400_BASE 0x01c40000 + +/* module sram */ +#define A1X_SRAM_C_BASE 0x01d00000 + +#define A1X_DE_FE0_BASE 0x01e00000 +#define A1X_DE_FE1_BASE 0x01e20000 +#define A1X_DE_BE0_BASE 0x01e60000 +#define A1X_DE_BE1_BASE 0x01e40000 +#define A1X_MP_BASE 0x01e80000 +#define A1X_AVG_BASE 0x01ea0000 + +/* CoreSight Debug Module */ +#define A1X_CSDM_BASE 0x3f500000 + +#define A1X_DRAM_BASE 0x40000000 /* 2 GiB */ + +#define A1X_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define A1X_CPU_CFG (A1X_TIMER_BASE + 0x13c) + +#endif /* CPU_ALLWINNER_A10_MEMMAP_H */ diff --git a/src/cpu/allwinner/a10/monotonic_timer.c b/src/cpu/allwinner/a10/monotonic_timer.c new file mode 100644 index 0000000..16d478a --- /dev/null +++ b/src/cpu/allwinner/a10/monotonic_timer.c @@ -0,0 +1,13 @@ +/* + * Placeholder for code to come (needed to complete build) + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + (void)mt; +} diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c new file mode 100644 index 0000000..2525de5 --- /dev/null +++ b/src/cpu/allwinner/a10/pinmux.c @@ -0,0 +1,30 @@ +/* + * Helpers to multiplex and configure pins on Allwinner SoCs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "gpio.h" + +#include <arch/io.h> + +static struct a10_gpio *const gpio = (void *)GPIO_BASE; + +void gpio_set_func(u8 port, u8 pin, u8 pad_func) +{ + u8 reg, bit; + u32 reg32; + + if ((port > GPS)) + return; + + pin &= 0x1f; + reg = pin / 8; + bit = (pin % 8) * 4; + + reg32 = read32(&gpio->port[port].cfg[reg]); + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + write32(reg32, &gpio->port[port].cfg[reg]); +} diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c new file mode 100644 index 0000000..e156398 --- /dev/null +++ b/src/cpu/allwinner/a10/timer.c @@ -0,0 +1,19 @@ +/* + * Placeholder for code to come(needed to complete build) + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <delay.h> +#include <timer.h> + +void init_timer(void) +{ + /* Stub */ +} + +void udelay(unsigned usec) +{ + /* Stub */ +} diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c new file mode 100644 index 0000000..dc98bff --- /dev/null +++ b/src/cpu/allwinner/a10/uart.c @@ -0,0 +1,98 @@ +/* + * Uart setup helpers for Allwinner SoCs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "uart.h" +#include <arch/io.h> + +/* Give me my 8250 UART definitions!!!! */ +/* TODO: Clean this up when uart8250mem works on ARM */ +#undef CONFIG_CONSOLE_SERIAL8250MEM +#define CONFIG_CONSOLE_SERIAL8250MEM 1 +#include <uart8250.h> + +/** + * \brief Configure line control settings for UART + */ +void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, + enum uart_parity parity, u8 stop_bits) +{ + u32 reg32; + u16 div; + struct a10_uart *uart = uart_base; + + /* Enable access to Divisor Latch register */ + write32(UART_LCR_DLAB, &uart->lcr); + /* Set baudrate */ + /* FIXME: We assume clock is 24MHz, which may not be the case */ + div = 24000000 / 16 / baud_rate; + write32((div >> 8) & 0xff, &uart->dlh); + write32(div & 0xff, &uart->dll); + /* Set line control */ + reg32 = (data_bits - 5) & UART_LCR_WLS_MSK; + switch (parity) { + case UART_PARITY_ODD: + reg32 |= UART_LCR_PEN; + break; + case UART_PARITY_EVEN: + reg32 |= UART_LCR_PEN; + reg32 |= UART_LCR_EPS; + break; + case UART_PARITY_NONE: /* Fall through */ + default: + break; + } + write32(reg32, &uart->lcr); +} + +void a10_uart_enable_fifos(void *uart_base) +{ + struct a10_uart *uart = uart_base; + + write32(UART_FCR_FIFO_EN, &uart->fcr); +} + +static int tx_fifo_full(struct a10_uart *uart) +{ + /* This may be a misnomer, or a typo in the datasheet. THRE indicates + * that the TX register is empty, not that the FIFO is not full, but + * this may be due to a datasheet typo. Keep the current name to signal + * intent. */ + return !(read32(&uart->lsr) & UART_LSR_THRE); +} + +static int rx_fifo_empty(struct a10_uart *uart) +{ + return !(read32(&uart->lsr) & UART_LSR_DR); +} + +/** + * \brief Read a single byte from the UART. + * + * Blocks until at least a byte is available. + */ +u8 a10_uart_rx_blocking(void *uart_base) +{ + struct a10_uart *uart = uart_base; + + while (rx_fifo_empty(uart)) ; + + return read32(&uart->rbr); +} + +/** + * \brief Write a single byte to the UART. + * + * Blocks until there is space in the FIFO. + */ +void a10_uart_tx_blocking(void *uart_base, u8 data) +{ + struct a10_uart *uart = uart_base; + + while (tx_fifo_full(uart)) ; + + return write32(data, &uart->thr); +} diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h new file mode 100644 index 0000000..86ab487 --- /dev/null +++ b/src/cpu/allwinner/a10/uart.h @@ -0,0 +1,77 @@ +/* + * Definitions for UART on Allwinner CPUs + * + * The UART on the A10 seems to be 8250-compatible, however, this has not been + * verified. Our 8250mem code is specific to x86, and does not yet work, so we + * have to re-implement it ARM-style for the time being. The register + * definitions are present in <uart7250.h>, and are not redefined here. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_UART_H +#define CPU_ALLWINNER_A10_UART_H + +#include "memmap.h" +#include <types.h> + +struct a10_uart { + union { + /* operational mode */ + u32 rbr; /* receiver buffer (read) */ + u32 thr; /* transmit holding (write) */ + /* config mode (DLAB set) */ + u32 dll; /* divisor latches low */ + }; + + union { + /* operational mode */ + u32 ier; /* interrupt enable */ + /* config mode (DLAB set) */ + u32 dlh; /* divisor latches high */ + }; + + union { + u32 iir; /* interrupt ID (read) */ + u32 fcr; /* FIFO control (write) */ + }; + + u32 lcr; /* line control */ + + /* 0x10 */ + u32 mcr; /* modem control */ + u32 lsr; /* line status, read-only */ + u32 msr; /* modem status */ + u32 sch; /* scratch register */ + + u8 reserved_0x20[0x50]; + + /* 0x70 */ + u8 reserved_0x70[0xc]; + u32 usr; /* UART status register */ + + /* 0x80 */ + u32 tfl; /* Transmit FIFO level */ + u32 rfl; /* Receive FIFO level */ + u8 reserved_0x88[0x18]; + + /* 0xa0 */ + u8 reserved_0xa0[4]; + u32 halt; /* Halt register */ + +} __attribute__ ((packed)); + +enum uart_parity { + UART_PARITY_NONE, + UART_PARITY_EVEN, + UART_PARITY_ODD, +}; + +void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, + enum uart_parity parity, u8 stop_bits); +void a10_uart_enable_fifos(void *uart_base); +u8 a10_uart_rx_blocking(void *uart_base); +void a10_uart_tx_blocking(void *uart_base, u8 data); + +#endif /* CPU_ALLWINNER_A10_UART_H */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c new file mode 100644 index 0000000..58930dd --- /dev/null +++ b/src/cpu/allwinner/a10/uart_console.c @@ -0,0 +1,109 @@ +/* + * Glue to UART code to enable serial console + * + * Copyright 2013 Google Inc. + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <config.h> +#include <types.h> +#include <uart.h> +#include <arch/io.h> + +#include <console/console.h> +#include <cpu/allwinner/a10/uart.h> + +static void *get_console_uart_base_addr(void) +{ + /* This big block gets compiled to a constant, not a function call */ + if (CONFIG_CONSOLE_SERIAL_UART0) + return (void *)A1X_UART0_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART1) + return (void *)A1X_UART1_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART2) + return (void *)A1X_UART2_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART3) + return (void *)A1X_UART3_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART4) + return (void *)A1X_UART4_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART5) + return (void *)A1X_UART5_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART6) + return (void *)A1X_UART6_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART7) + return (void *)A1X_UART7_BASE; + + /* If selection is invalid, default to UART0 */ + return (void *)A1X_UART0_BASE; +} + +static u32 get_console_uart_baud(void) +{ + if (CONFIG_CONSOLE_SERIAL_115200) + return 115200; + else if (CONFIG_CONSOLE_SERIAL_57600) + return 57600; + else if (CONFIG_CONSOLE_SERIAL_38400) + return 34800; + else if (CONFIG_CONSOLE_SERIAL_19200) + return 19200; + else if (CONFIG_CONSOLE_SERIAL_9600) + return 9600; + + /* Default to 115200 if selection is invalid */ + return 115200; +} + +static void a10_uart_init_dev(void) +{ + void *uart_base = get_console_uart_base_addr(); + /* Use default 8N1 encoding */ + a10_uart_configure(uart_base, get_console_uart_baud(), + 8, UART_PARITY_NONE, 1); + a10_uart_enable_fifos(uart_base); +} + +static unsigned char a10_uart_rx_byte(void) +{ + return a10_uart_rx_blocking(get_console_uart_base_addr()); +} + +static void a10_uart_tx_byte(unsigned char data) +{ + a10_uart_tx_blocking(get_console_uart_base_addr(), data); +} + +uint32_t uartmem_getbaseaddr(void) +{ + return (uint32_t) get_console_uart_base_addr(); +} + +#if !defined(__PRE_RAM__) +static const struct console_driver a10_uart_console __console = { + .init = a10_uart_init_dev, + .tx_byte = a10_uart_tx_byte, + .rx_byte = a10_uart_rx_byte, +}; +#else + +void uart_init(void) +{ + a10_uart_init_dev(); +} + +unsigned char uart_rx_byte(void) +{ + return a10_uart_rx_byte(); +} + +void uart_tx_byte(unsigned char data) +{ + a10_uart_tx_byte(data); +} + +void uart_tx_flush(void) +{ +} + +#endif

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Patch set updated for coreboot: c4601a8 cpu/allwinner/a10: Refactor and document pinmux API
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4565 -gerrit commit c4601a822ea12681688f45840b03da6b52289368 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 21:30:21 2013 -0500 cpu/allwinner/a10: Refactor and document pinmux API Include a function to multiplex more than one pin at a time. This is useful for peripherals that have the same function number for all their pins. Since we now have two functions for muxing pins, also document them. Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/gpio.h | 3 +- src/cpu/allwinner/a10/pinmux.c | 51 +++++++++++++++++++++++++- src/mainboard/cubietech/cubieboard/bootblock.c | 7 ++-- 3 files changed, 55 insertions(+), 6 deletions(-) diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index f285451..709f74b 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -46,6 +46,7 @@ struct a10_gpio { u32 sdr_pad_pul; } __attribute__ ((packed)); -void gpio_set_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func); #endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c index 2525de5..de87440 100644 --- a/src/cpu/allwinner/a10/pinmux.c +++ b/src/cpu/allwinner/a10/pinmux.c @@ -11,7 +11,14 @@ static struct a10_gpio *const gpio = (void *)GPIO_BASE; -void gpio_set_func(u8 port, u8 pin, u8 pad_func) +/** + * \brief Set the pad function of a single pin + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin the pin number in the given port (1 -> 31) + * @param[in] pad_func The peripheral function to which to connect this pin + */ +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func) { u8 reg, bit; u32 reg32; @@ -28,3 +35,45 @@ void gpio_set_func(u8 port, u8 pin, u8 pad_func) reg32 |= (pad_func & 0xf) << bit; write32(reg32, &gpio->port[port].cfg[reg]); } + +/** + * \brief Set the pad function of a group of pins + * + * Multiplex a group of pins to the same pad function. This is useful for + * peripherals that use the same function number for several pins. This function + * allows those pins to be set with a single call. + * + * Example: + * gpio_set_multipin_func(GPB, (1 << 23) | (1 << 22), 2); + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin_mask 32-bit mask indicating which pins to re-multiplex. For + * each set bit, the corresponding pin will be multiplexed. + * @param[in] pad_func The peripheral function to which to connect the pins + */ +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func) +{ + int j; + u8 reg, bit; + u32 reg32, mask_offset; + + if ((port > GPS)) + return; + + for (reg = 0; reg < 4; reg++) { + mask_offset = 8 * reg; + /* Don't run the inner loop if we're not touching any pins */ + if (!(pin_mask & (0xff << mask_offset))) + continue; + + reg32 = read32(&gpio->port[port].cfg[reg]); + for (j = 0; j < 8; j++) { + if (!(pin_mask & (1 << (j + mask_offset)))) + continue; + bit = j * 4; + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + } + write32(reg32, &gpio->port[port].cfg[reg]); + } +} diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 6e8b751..a91391c 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -18,8 +18,8 @@ | AHB_DIV_1 \ | AXI_DIV_1 -#define GPB22_UART0_TX_FUNC 2 -#define GPB23_UART0_RX_FUNC 2 +#define GPB_UART0_FUNC 2 +#define GPB_UART0_PINS ((1 << 22) | (1 << 23)) static void cubieboard_set_sys_clock(void) { @@ -57,8 +57,7 @@ static void cubieboard_setup_clocks(void) static void cubieboard_setup_gpios(void) { /* Mux UART pins */ - gpio_set_func(GPB, 22, GPB22_UART0_TX_FUNC); - gpio_set_func(GPB, 23, GPB23_UART0_RX_FUNC); + gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); } static void cubieboard_enable_uart(void)

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Patch set updated for coreboot: 90ada6b mainboard: Add preliminary support for A10-based Cubieboard
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4553 -gerrit commit 90ada6bb2f02e04cd84be8174796380145630923 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 13 20:25:04 2013 -0600 mainboard: Add preliminary support for A10-based Cubieboard Add a minimal infrastructure which initializes the system clocks and serial console. Change-Id: I768ede6ccf8674ffe9fecd8925cec89768209cab Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/cubietech/Kconfig | 18 ++++++ src/mainboard/cubietech/cubieboard/Kconfig | 29 +++++++++ src/mainboard/cubietech/cubieboard/Makefile.inc | 1 + src/mainboard/cubietech/cubieboard/bootblock.c | 80 ++++++++++++++++++++++++ src/mainboard/cubietech/cubieboard/devicetree.cb | 3 + src/mainboard/cubietech/cubieboard/romstage.c | 14 +++++ 7 files changed, 148 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index fdb0eac..6ba057a 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -48,6 +48,8 @@ config VENDOR_BROADCOM bool "Broadcom" config VENDOR_COMPAQ bool "Compaq" +config VENDOR_CUBIETECH + bool "Cubietech" config VENDOR_DIGITALLOGIC bool "DIGITAL-LOGIC" config VENDOR_DMP @@ -161,6 +163,7 @@ source "src/mainboard/bifferos/Kconfig" source "src/mainboard/biostar/Kconfig" source "src/mainboard/broadcom/Kconfig" source "src/mainboard/compaq/Kconfig" +source "src/mainboard/cubietech/Kconfig" source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/dmp/Kconfig" source "src/mainboard/eaglelion/Kconfig" diff --git a/src/mainboard/cubietech/Kconfig b/src/mainboard/cubietech/Kconfig new file mode 100644 index 0000000..840ee85 --- /dev/null +++ b/src/mainboard/cubietech/Kconfig @@ -0,0 +1,18 @@ +if VENDOR_CUBIETECH + +# Auto select common options +choice + prompt "Mainboard model" + +config BOARD_CUBIETECH_CUBIEBOARD + bool "Cubieboard" + +endchoice + +source "src/mainboard/cubietech/cubieboard/Kconfig" + +config MAINBOARD_VENDOR + string + default "Cubietech" + +endif # VENDOR_CUBIETECH diff --git a/src/mainboard/cubietech/cubieboard/Kconfig b/src/mainboard/cubietech/cubieboard/Kconfig new file mode 100644 index 0000000..72b797e --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/Kconfig @@ -0,0 +1,29 @@ +if BOARD_CUBIETECH_CUBIEBOARD + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_ALLWINNER_A10 + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default cubietech/cubieboard + +config MAINBOARD_PART_NUMBER + string + default "Cubieboard A10" + +config MAX_CPUS + int + default 1 + +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/cubietech/cubieboard/bootblock.c" + +config DRAM_SIZE_MB + int + default 1024 + +endif # BOARD_CUBIETECH_CUBIEBOARD diff --git a/src/mainboard/cubietech/cubieboard/Makefile.inc b/src/mainboard/cubietech/cubieboard/Makefile.inc new file mode 100644 index 0000000..29763fb --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/Makefile.inc @@ -0,0 +1 @@ +romstage-y += romstage.c diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c new file mode 100644 index 0000000..6e8b751 --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -0,0 +1,80 @@ +/* + * Minimal bootblock for Cubieboard + * It sets up CPU clock, and enables the bootblock console. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <arch/io.h> +#include <uart.h> +#include <console/console.h> +#include <cpu/allwinner/a10/gpio.h> +#include <cpu/allwinner/a10/clock.h> + +#define CPU_AHB_APB0_DEFAULT \ + CPU_CLK_SRC_OSC24M \ + | APB0_DIV_1 \ + | AHB_DIV_1 \ + | AXI_DIV_1 + +#define GPB22_UART0_TX_FUNC 2 +#define GPB23_UART0_RX_FUNC 2 + +static void cubieboard_set_sys_clock(void) +{ + u32 reg32; + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + + /* Switch CPU clock to main oscillator */ + write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg); + + /* Configure the PLL1. The value is the same one used by u-boot */ + write32(0xa1005000, &ccm->pll1_cfg); + + /* FIXME: Delay to wait for PLL to lock */ + u32 wait = 1000; + while (--wait); + + /* Switch CPU to PLL clock */ + reg32 = read32(&ccm->cpu_ahb_apb0_cfg); + reg32 &= ~CPU_CLK_SRC_MASK; + reg32 |= CPU_CLK_SRC_PLL1; + write32(reg32, &ccm->cpu_ahb_apb0_cfg); +} + +static void cubieboard_setup_clocks(void) +{ + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + + cubieboard_set_sys_clock(); + /* Configure the clock source for APB1. This drives our UART */ + write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0), + &ccm->apb1_clk_div_cfg); + +} + +static void cubieboard_setup_gpios(void) +{ + /* Mux UART pins */ + gpio_set_func(GPB, 22, GPB22_UART0_TX_FUNC); + gpio_set_func(GPB, 23, GPB23_UART0_RX_FUNC); +} + +static void cubieboard_enable_uart(void) +{ + u32 reg32; + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + /* Enable clock to UART0 */ + reg32 = read32(&ccm->apb1_gate); + reg32 |= APB1_GATE_UART(0); + write32(reg32, &ccm->apb1_gate); +} + +void bootblock_mainboard_init(void); +void bootblock_mainboard_init(void) +{ + cubieboard_setup_clocks(); + cubieboard_setup_gpios(); + cubieboard_enable_uart(); +} diff --git a/src/mainboard/cubietech/cubieboard/devicetree.cb b/src/mainboard/cubietech/cubieboard/devicetree.cb new file mode 100644 index 0000000..1358777 --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/devicetree.cb @@ -0,0 +1,3 @@ +chip cpu/allwinner/a10 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c new file mode 100644 index 0000000..19192cd --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -0,0 +1,14 @@ +/* + * Placeholder for Cubieboard romstage + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <console/console.h> + +void main(void) +{ + console_init(); + printk(BIOS_INFO, "You have managed to succesfully load romstage.\n"); +}

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Patch set updated for coreboot: 339a969 cpu/allwinner/a10: Refactor API for gating clocks to peripherals
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4571 -gerrit commit 339a9693ddb88f656de852d4cd88eaf249dc3645 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Dec 24 16:48:03 2013 -0500 cpu/allwinner/a10: Refactor API for gating clocks to peripherals Rather than having to track which bit in which register should be cleared or set to gate or ungate the clock to a certain peripheral, provide a simplified enum which encodes the register and bit. This change comes with a function which decodes the enum and gates/ungates the clock. This also removes the register-dependent bitmasks for APB0 and APB1 gating registers. Change-Id: Ib3ca16e54eb37eadc3ceb88f4ccc497829ac34bc Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 1 + src/cpu/allwinner/a10/clock.c | 42 +++++++++ src/cpu/allwinner/a10/clock.h | 116 ++++++++++++++++++++++--- src/mainboard/cubietech/cubieboard/bootblock.c | 7 +- 4 files changed, 148 insertions(+), 18 deletions(-) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 9f7208a..fecaf0e 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += bootblock_media.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c new file mode 100644 index 0000000..bc78743 --- /dev/null +++ b/src/cpu/allwinner/a10/clock.c @@ -0,0 +1,42 @@ +/* + * Helpers for clock control and gating on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "clock.h" + +#include <arch/io.h> + +/** + * \brief Enable the clock source for the peripheral + * + * @param[in] periph peripheral and clock type to enable @see a1x_clken + */ +void a1x_periph_clock_enable(enum a1x_clken periph) +{ + void *addr; + u32 reg32; + + addr = (void *)A1X_CCM_BASE + (periph >> 5); + reg32 = read32(addr); + reg32 |= 1 << (periph & 0x1f); + write32(reg32, addr); +} + +/** + * \brief Disable the clock source for the peripheral + * + * @param[in] periph peripheral and clock type to enable @see a1x_clken + */ +void a1x_periph_clock_disable(enum a1x_clken periph) +{ + void *addr; + u32 reg32; + + addr = (void *)A1X_CCM_BASE + (periph >> 5); + reg32 = read32(addr); + reg32 &= ~(1 << (periph & 0x1f)); + write32(reg32, addr); +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index e028d13..b9a0771 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -43,19 +43,108 @@ #define APB1_RAT_M_MASK 0x1f << 0) #define APB1_RAT_M(n) (((n) & 0x1f) << 0) -/* APB0_GATING values */ -#define APB0_GATE_KEYPAD (1 << 10) -#define APB0_GATE_IR(x) (((1 << (x)) & 0x3) << 6) -#define APB0_GATE_PIO (1 << 5) -#define APB0_GATE_IIS (1 << 3) -#define APB0_GATE_AC97 (1 << 2) -#define APB0_GATE_CODEC (1 << 0) +/** + * \brief Clock gating definitions + * + * The definitions are specified in the form: + * 31:5 register offset from A1X_CCM_BASE for the clock register + * 4:0 bit offset for the given peripheral + * + * The names have the form [periph_type][periph_number] + * + * These definitions are meant to be used with @ref a1x_periph_clock_enable and + * @ref a1x_periph_clock_disable + */ -/* APB1_GATING values */ -#define APB1_GATE_UART(x) (((1 << (x)) & 0xff) << 16) -#define APB1_GATE_PS2(x) (((1 << (x)) & 0x3) << 6) -#define APB1_GATE_CAN (1 << 4) -#define APB1_GATE_TWI(x) (((1 << (x)) & 0x7) << 0) +enum a1x_clken { + /* AXI module clock gating */ + A1X_CLKEN_DRAM_AXI = (0x5C << 5), + /* AHB0 module clock gating */ + A1X_CLKEN_USB0 = (0x60 << 5), + A1X_CLKEN_EHCI0, + RSVD_0x60_2, + A1X_CLKEN_EHCI1, + RSVD_0x60_4, + A1X_CLKEN_SS, + A1X_CLKEN_DMA, + A1X_CLKEN_BIST, + A1X_CLKEN_MMC0, + A1X_CLKEN_MMC1, + A1X_CLKEN_MMC2, + A1X_CLKEN_MMC3, + A1X_CLKEN_NC, + A1X_CLKEN_NAND, + A1X_CLKEN_SDRAM, + RSVD_0x60_15, + A1X_CLKEN_ACE, + A1X_CLKEN_EMAC, + A1X_CLKEN_TS, + RSVD_0x60_19, + A1X_CLKEN_SPI0, + A1X_CLKEN_SPI1, + A1X_CLKEN_SPI2, + A1X_CLKEN_SPI3, + A1X_CLKEN_PATA, + /* AHB1 module clock gating */ + A1X_CLKEN_DRAM_VE = (0x64 << 5), + A1X_CLKEN_TVD, + A1X_CLKEN_TVE0, + A1X_CLKEN_TVE1, + A1X_CLKEN_LCD0, + A1X_CLKEN_LCD1, + RSVD_0x64_6, + RSVD_0x64_7, + A1X_CLKEN_CSI0, + A1X_CLKEN_CSI1, + RSVD_0x64_10, + A1X_CLKEN_HDMI, + A1X_CLKEN_DE_BE0, + A1X_CLKEN_DE_BE1, + A1X_CLKEN_DE_FE0, + A1X_CLKEN_DE_FE1, + RSVD_0x64_16, + RSVD_0x64_17, + A1X_CLKEN_MP, + RSVD_0x64_19, + A1X_CLKEN_MALI400, + /* APB0 module clock gating */ + A1X_CLKEN_CODEC = (0x68 << 5), + A1X_CLKEN_NC_APB, + A1X_CLKEN_AC97, + A1X_CLKEN_IIS, + RSVD_0x68_4, + A1X_CLKEN_PIO, + A1X_CLKEN_IR0, + A1X_CLKEN_IR1, + RSVD_0x68_8, + RSVD_0x68_9, + A1X_CLKEN_KEYPAD, + /* APB1 module clock gating */ + A1X_CLKEN_TWI0 = (0x6C << 5), + A1X_CLKEN_TWI1, + A1X_CLKEN_TWI2, + RSVD_0x6C_3, + A1X_CLKEN_CAN, + A1X_CLKEN_SCR, + A1X_CLKEN_PS20, + A1X_CLKEN_PS21, + RSVD_0x6C_8, + RSVD_0x6C_9, + RSVD_0x6C_10, + RSVD_0x6C_11, + RSVD_0x6C_12, + RSVD_0x6C_13, + RSVD_0x6C_14, + RSVD_0x6C_15, + A1X_CLKEN_UART0, + A1X_CLKEN_UART1, + A1X_CLKEN_UART2, + A1X_CLKEN_UART3, + A1X_CLKEN_UART4, + A1X_CLKEN_UART5, + A1X_CLKEN_UART6, + A1X_CLKEN_UART7, +}; struct a10_ccm { u32 pll1_cfg; /* 0x00 pll1 control */ @@ -134,4 +223,7 @@ struct a10_ccm { u32 mbus_clk_cfg; /* 0x15c */ } __attribute__ ((packed)); +void a1x_periph_clock_enable(enum a1x_clken periph); +void a1x_periph_clock_disable(enum a1x_clken periph); + #endif /* CPU_ALLWINNER_A10_CLOCK_H */ diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index a91391c..a7a55b5 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -62,12 +62,7 @@ static void cubieboard_setup_gpios(void) static void cubieboard_enable_uart(void) { - u32 reg32; - struct a10_ccm *ccm = (void *)A1X_CCM_BASE; - /* Enable clock to UART0 */ - reg32 = read32(&ccm->apb1_gate); - reg32 |= APB1_GATE_UART(0); - write32(reg32, &ccm->apb1_gate); + a1x_periph_clock_enable(A1X_CLKEN_UART0); } void bootblock_mainboard_init(void);

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Patch set updated for coreboot: e606b4b cpu/allwinner/a10: Clear the usage of SRAM during the bootblock
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4563 -gerrit commit e606b4b0d25175dced10521ec8e1e52c54b3ce6e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 18:51:29 2013 -0500 cpu/allwinner/a10: Clear the usage of SRAM during the bootblock We have 32KiB of usable SRAM right when we boot. The first 24KiB can be loaded with our bootblock, while the other 8KiB can be used as stack during the bootblock stage. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Change-Id: I48d3a37869031c3c1dbc1fab71204d473d64deeb --- src/cpu/allwinner/a10/Kconfig | 10 +++++++--- src/cpu/allwinner/a10/Makefile.inc | 15 ++++++++------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 915578a..fcb1049 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -41,18 +41,22 @@ config ROMSTAGE_BASE hex default SYS_SDRAM_BASE -# Keep the stack in SRAM +# Keep the stack in SRAM block A2. +# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the +# CPU. This gives us 32KiB of SRAM to boot with. The BROM bootloader will use up +# to 24KiB to load our bootblock, which leaves us the area from 24KiB to 32 KiB +# to use however we see fit. config STACK_TOP hex default 0x00008000 config STACK_BOTTOM hex - default 0x00004000 + default 0x00006000 config STACK_SIZE hex - default 0x00004000 + default 0x00002000 ## TODO Change this to some better address not overlapping bootblock when ## cbfstool supports creating header in arbitrary location. diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 48f3110..9f7208a 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -21,15 +21,16 @@ get_bootblock_size= \ sed 's/[^0-9 ]//g')) \ $(shell echo $$(($(word 2, $(strip $(bb_s)))))) -# The boot ROM in the SoC will start loading code if a special boot0 header is +# The boot ROM in the SoC will start loading code if a special BOOT0 header is # found (at an offset of 8KiB in either NAND or SD), and the checksum is -# correct. this header is normally added by the 'mxsunxiboot' tool. The file -# passed to mksunxiboot should only include the bootblock due to size -# limitations. -# FIXME: Figure out how to safely integrate in coreboot.rom. For now, only copy -# the first 15 KiB of coreboot.rom (This will not collide with stack) +# correct. This header is normally added by the 'mxsunxiboot' tool. The boot ROM +# will load at most 24KiB of data to SRAM, so limit the file size accordingly. +# The BOOT0 header takes 32 bytes, so limit our file to 24KiB - 32 bytes. +# FIXME: Figure out how to safely integrate in coreboot.rom. +# FIXME: The file passed to mksunxiboot should only include the bootblock due +# to size limitations. $(obj)/BOOT0: $(obj)/coreboot.rom @printf " BOOT0 $(subst $(obj)/,,$(^))\n" touch $@ - dd if=$^ of=$^.tmp bs=1024 count=15 + dd if=$^ of=$^.tmp bs=24544 count=1 -mksunxiboot $^.tmp $@

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Patch set updated for coreboot: 37346d5 cpu: Add initial support for Allwinner A10 SoC
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4549 -gerrit commit 37346d545fc325a5233ed1ad66fc4589522b44a4 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 13 20:44:48 2013 -0600 cpu: Add initial support for Allwinner A10 SoC Add minimal support needed to get a bootblock capable of initialising a serial console. Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/Kconfig | 1 + src/cpu/Makefile.inc | 1 + src/cpu/allwinner/Kconfig | 1 + src/cpu/allwinner/Makefile.inc | 1 + src/cpu/allwinner/a10/Kconfig | 114 ++++++++++++++++++++++++++ src/cpu/allwinner/a10/Makefile.inc | 35 ++++++++ src/cpu/allwinner/a10/bootblock.c | 21 +++++ src/cpu/allwinner/a10/bootblock_media.c | 14 ++++ src/cpu/allwinner/a10/clock.h | 137 ++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/gpio.h | 51 ++++++++++++ src/cpu/allwinner/a10/memmap.h | 117 +++++++++++++++++++++++++++ src/cpu/allwinner/a10/monotonic_timer.c | 13 +++ src/cpu/allwinner/a10/pinmux.c | 30 +++++++ src/cpu/allwinner/a10/timer.c | 19 +++++ src/cpu/allwinner/a10/uart.c | 92 +++++++++++++++++++++ src/cpu/allwinner/a10/uart.h | 102 ++++++++++++++++++++++++ src/cpu/allwinner/a10/uart_console.c | 109 +++++++++++++++++++++++++ 17 files changed, 858 insertions(+) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index cd6c7a0..f3883d3 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -3,6 +3,7 @@ # (See also src/Kconfig) if ARCH_ARMV7 +source src/cpu/allwinner/Kconfig source src/cpu/armltd/Kconfig source src/cpu/samsung/Kconfig source src/cpu/ti/Kconfig diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 7cd9d5f..f206fdc 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,6 +1,7 @@ ################################################################################ ## Subdirectories ################################################################################ +subdirs-y += allwinner subdirs-y += amd subdirs-y += dmp subdirs-y += armltd diff --git a/src/cpu/allwinner/Kconfig b/src/cpu/allwinner/Kconfig new file mode 100644 index 0000000..d97cb64 --- /dev/null +++ b/src/cpu/allwinner/Kconfig @@ -0,0 +1 @@ +source src/cpu/allwinner/a10/Kconfig diff --git a/src/cpu/allwinner/Makefile.inc b/src/cpu/allwinner/Makefile.inc new file mode 100644 index 0000000..e52a12e --- /dev/null +++ b/src/cpu/allwinner/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_ALLWINNER_A10) += a10 diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig new file mode 100644 index 0000000..915578a --- /dev/null +++ b/src/cpu/allwinner/a10/Kconfig @@ -0,0 +1,114 @@ +config CPU_ALLWINNER_A10 + bool + default n + +if CPU_ALLWINNER_A10 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + select EARLY_CONSOLE + +config BOOTBLOCK_CPU_INIT + string + default "cpu/allwinner/a10/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + +# The "eGON.BT0" header takes 32 bytes +config BOOTBLOCK_BASE + hex + default 0x20 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x00 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x10 + +config CBFS_ROM_OFFSET + # Calculated by BL1 + max bootblock size. + default 0x4c00 + +# FIXME: untested +config ROMSTAGE_BASE + hex + default SYS_SDRAM_BASE + +# Keep the stack in SRAM +config STACK_TOP + hex + default 0x00008000 + +config STACK_BOTTOM + hex + default 0x00004000 + +config STACK_SIZE + hex + default 0x00004000 + +## TODO Change this to some better address not overlapping bootblock when +## cbfstool supports creating header in arbitrary location. +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x40 + +config SYS_SDRAM_BASE + hex + default 0x40000000 + +choice CONSOLE_SERIAL_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART0 + depends on CONSOLE_SERIAL_UART + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +config CONSOLE_SERIAL_UART4 + bool "UART4" + help + Serial console on UART4 + +config CONSOLE_SERIAL_UART5 + bool "UART5" + help + Serial console on UART5 + +config CONSOLE_SERIAL_UART6 + bool "UART6" + help + Serial console on UART6 + +config CONSOLE_SERIAL_UART7 + bool "UART7" + help + Serial console on UART7 + +endchoice + +endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc new file mode 100644 index 0000000..48f3110 --- /dev/null +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -0,0 +1,35 @@ +bootblock-y += pinmux.c +bootblock-y += bootblock_media.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c + +romstage-y += uart.c +romstage-y += uart_console.c +romstage-y += bootblock_media.c + +ramstage-y += uart.c +ramstage-y += uart_console.c +ramstage-y += timer.c +ramstage-y += monotonic_timer.c +ramstage-y += bootblock_media.c + + +real-target: $(obj)/BOOT0 + +get_bootblock_size= \ + $(eval bb_s=$(shell $(CBFSTOOL) $(1) print | grep bootblocksize | \ + sed 's/[^0-9 ]//g')) \ + $(shell echo $$(($(word 2, $(strip $(bb_s)))))) + +# The boot ROM in the SoC will start loading code if a special boot0 header is +# found (at an offset of 8KiB in either NAND or SD), and the checksum is +# correct. this header is normally added by the 'mxsunxiboot' tool. The file +# passed to mksunxiboot should only include the bootblock due to size +# limitations. +# FIXME: Figure out how to safely integrate in coreboot.rom. For now, only copy +# the first 15 KiB of coreboot.rom (This will not collide with stack) +$(obj)/BOOT0: $(obj)/coreboot.rom + @printf " BOOT0 $(subst $(obj)/,,$(^))\n" + touch $@ + dd if=$^ of=$^.tmp bs=1024 count=15 + -mksunxiboot $^.tmp $@ diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c new file mode 100644 index 0000000..38fe953 --- /dev/null +++ b/src/cpu/allwinner/a10/bootblock.c @@ -0,0 +1,21 @@ +/* + * Allwinner A10 bootblock initialization + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> +#include <arch/cache.h> + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ + uint32_t sctlr; + + /* enable dcache */ + sctlr = read_sctlr(); + sctlr |= SCTLR_C; + write_sctlr(sctlr); +} diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c new file mode 100644 index 0000000..a5863b6 --- /dev/null +++ b/src/cpu/allwinner/a10/bootblock_media.c @@ -0,0 +1,14 @@ +/* + * CBFS accessors for bootblock stage. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ +#include <cbfs.h> +#include <console/console.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + printk(BIOS_ERR, "Oh my! I don't know how to access CBFS yet."); + return 0; +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h new file mode 100644 index 0000000..e028d13 --- /dev/null +++ b/src/cpu/allwinner/a10/clock.h @@ -0,0 +1,137 @@ +/* + * Definitions for clock control and gating on Allwinner CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_CLOCK_H +#define CPU_ALLWINNER_A10_CLOCK_H + +#include "memmap.h" +#include <types.h> + +/* CPU_AHB_APB0 config values */ +#define CPU_CLK_SRC_MASK (3 << 16) +#define CPU_CLK_SRC_OSC24M (1 << 16) +#define CPU_CLK_SRC_PLL1 (2 << 16) +#define APB0_DIV_MASK (3 << 8) +#define APB0_DIV_1 (0 << 8) +#define APB0_DIV_2 (1 << 8) +#define APB0_DIV_4 (2 << 8) +#define APB0_DIV_8 (3 << 8) +#define AHB_DIV_MASK (3 << 4) +#define AHB_DIV_1 (0 << 4) +#define AHB_DIV_2 (1 << 4) +#define AHB_DIV_4 (2 << 4) +#define AHB_DIV_8 (3 << 4) +#define AXI_DIV_MASK (3 << 0) +#define AXI_DIV_1 (0 << 0) +#define AXI_DIV_2 (1 << 0) +#define AXI_DIV_3 (2 << 0) +#define AXI_DIV_4 (3 << 0) + +/* APB1_CLK_DIV values */ +#define APB1_CLK_SRC_MASK (3 << 24) +#define APB1_CLK_SRC_OSC24M (0 << 24) +#define APB1_CLK_SRC_PLL6 (1 << 24) +#define APB1_CLK_SRC_32K (2 << 24) +#define APB1_RAT_N_MASK (3 << 16) +#define APB1_RAT_N(m) (((m) & 0x3) << 16) +#define APB1_RAT_M_MASK 0x1f << 0) +#define APB1_RAT_M(n) (((n) & 0x1f) << 0) + +/* APB0_GATING values */ +#define APB0_GATE_KEYPAD (1 << 10) +#define APB0_GATE_IR(x) (((1 << (x)) & 0x3) << 6) +#define APB0_GATE_PIO (1 << 5) +#define APB0_GATE_IIS (1 << 3) +#define APB0_GATE_AC97 (1 << 2) +#define APB0_GATE_CODEC (1 << 0) + +/* APB1_GATING values */ +#define APB1_GATE_UART(x) (((1 << (x)) & 0xff) << 16) +#define APB1_GATE_PS2(x) (((1 << (x)) & 0x3) << 6) +#define APB1_GATE_CAN (1 << 4) +#define APB1_GATE_TWI(x) (((1 << (x)) & 0x7) << 0) + +struct a10_ccm { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_cfg; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ +} __attribute__ ((packed)); + +#endif /* CPU_ALLWINNER_A10_CLOCK_H */ diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h new file mode 100644 index 0000000..f285451 --- /dev/null +++ b/src/cpu/allwinner/a10/gpio.h @@ -0,0 +1,51 @@ +/* + * Definitions for GPIO and pin multiplexing on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef __CPU_ALLWINNER_A10_PINMUX_H +#define __CPU_ALLWINNER_A10_PINMUX_H + +#include <types.h> + +#define GPIO_BASE 0x01C20800 + +#define GPA 0 +#define GPB 1 +#define GPC 2 +#define GPD 3 +#define GPE 4 +#define GPF 5 +#define GPG 6 +#define GPH 7 +#define GPI 8 +#define GPS 9 + +struct a10_gpio_port { + u32 cfg[4]; + u32 dat; + u32 drv[2]; + u32 pul[2]; +} __attribute__ ((packed)); + +struct a10_gpio { + struct a10_gpio_port port[10]; + u8 reserved_0x168[0x98]; + + /* Offset 0x200 */ + u32 int_cfg[4]; + + u32 int_ctl; + u32 int_sta; + u8 reserved_0x21C[4]; + u32 int_deb; + + u32 sdr_pad_drv; + u32 sdr_pad_pul; +} __attribute__ ((packed)); + +void gpio_set_func(u8 port, u8 pin, u8 pad_func); + +#endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/memmap.h b/src/cpu/allwinner/a10/memmap.h new file mode 100644 index 0000000..78d81dc --- /dev/null +++ b/src/cpu/allwinner/a10/memmap.h @@ -0,0 +1,117 @@ +/* + * Memory map definitions for Allwinner A10 CPUs + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_MEMMAP_H +#define CPU_ALLWINNER_A10_MEMMAP_H + +#define A1X_SRAM_A1_BASE 0x00000000 +#define A1X_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define A1X_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define A1X_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define A1X_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define A1X_SRAM_D_BASE 0x01c00000 +#define A1X_SRAM_B_BASE 0x01c00000 /* 64 kiB (secure) */ + +#define A1X_SRAMC_BASE 0x01c00000 +#define A1X_DRAMC_BASE 0x01c01000 +#define A1X_DMA_BASE 0x01c02000 +#define A1X_NFC_BASE 0x01c03000 +#define A1X_TS_BASE 0x01c04000 +#define A1X_SPI0_BASE 0x01c05000 +#define A1X_SPI1_BASE 0x01c06000 +#define A1X_MS_BASE 0x01c07000 +#define A1X_TVD_BASE 0x01c08000 +#define A1X_CSI0_BASE 0x01c09000 +#define A1X_TVE0_BASE 0x01c0a000 +#define A1X_EMAC_BASE 0x01c0b000 +#define A1X_LCD0_BASE 0x01c0C000 +#define A1X_LCD1_BASE 0x01c0d000 +#define A1X_VE_BASE 0x01c0e000 +#define A1X_MMC0_BASE 0x01c0f000 +#define A1X_MMC1_BASE 0x01c10000 +#define A1X_MMC2_BASE 0x01c11000 +#define A1X_MMC3_BASE 0x01c12000 +#define A1X_USB0_BASE 0x01c13000 +#define A1X_USB1_BASE 0x01c14000 +#define A1X_SS_BASE 0x01c15000 +#define A1X_HDMI_BASE 0x01c16000 +#define A1X_SPI2_BASE 0x01c17000 +#define A1X_SATA_BASE 0x01c18000 +#define A1X_PATA_BASE 0x01c19000 +#define A1X_ACE_BASE 0x01c1a000 +#define A1X_TVE1_BASE 0x01c1b000 +#define A1X_USB2_BASE 0x01c1c000 +#define A1X_CSI1_BASE 0x01c1d000 +#define A1X_TZASC_BASE 0x01c1e000 +#define A1X_SPI3_BASE 0x01c1f000 + +#define A1X_CCM_BASE 0x01c20000 +#define A1X_INTC_BASE 0x01c20400 +#define A1X_PIO_BASE 0x01c20800 +#define A1X_TIMER_BASE 0x01c20c00 +#define A1X_SPDIF_BASE 0x01c21000 +#define A1X_AC97_BASE 0x01c21400 +#define A1X_IR0_BASE 0x01c21800 +#define A1X_IR1_BASE 0x01c21c00 + +#define A1X_IIS_BASE 0x01c22400 +#define A1X_LRADC_BASE 0x01c22800 +#define A1X_AD_DA_BASE 0x01c22c00 +#define A1X_KEYPAD_BASE 0x01c23000 +#define A1X_TZPC_BASE 0x01c23400 +#define A1X_SID_BASE 0x01c23800 +#define A1X_SJTAG_BASE 0x01c23c00 + +#define A1X_TP_BASE 0x01c25000 +#define A1X_PMU_BASE 0x01c25400 +#define A1X_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */ + +#define A1X_UART0_BASE 0x01c28000 +#define A1X_UART1_BASE 0x01c28400 +#define A1X_UART2_BASE 0x01c28800 +#define A1X_UART3_BASE 0x01c28c00 +#define A1X_UART4_BASE 0x01c29000 +#define A1X_UART5_BASE 0x01c29400 +#define A1X_UART6_BASE 0x01c29800 +#define A1X_UART7_BASE 0x01c29c00 +#define A1X_PS2_0_BASE 0x01c2a000 +#define A1X_PS2_1_BASE 0x01c2a400 + +#define A1X_TWI0_BASE 0x01c2ac00 +#define A1X_TWI1_BASE 0x01c2b000 +#define A1X_TWI2_BASE 0x01c2b400 + +#define A1X_CAN_BASE 0x01c2bc00 + +#define A1X_SCR_BASE 0x01c2c400 + +#define A1X_GPS_BASE 0x01c30000 +#define A1X_MALI400_BASE 0x01c40000 + +/* module sram */ +#define A1X_SRAM_C_BASE 0x01d00000 + +#define A1X_DE_FE0_BASE 0x01e00000 +#define A1X_DE_FE1_BASE 0x01e20000 +#define A1X_DE_BE0_BASE 0x01e60000 +#define A1X_DE_BE1_BASE 0x01e40000 +#define A1X_MP_BASE 0x01e80000 +#define A1X_AVG_BASE 0x01ea0000 + +/* CoreSight Debug Module */ +#define A1X_CSDM_BASE 0x3f500000 + +#define A1X_DRAM_BASE 0x40000000 /* 2 GiB */ + +#define A1X_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define A1X_CPU_CFG (A1X_TIMER_BASE + 0x13c) + +#endif /* CPU_ALLWINNER_A10_MEMMAP_H */ diff --git a/src/cpu/allwinner/a10/monotonic_timer.c b/src/cpu/allwinner/a10/monotonic_timer.c new file mode 100644 index 0000000..16d478a --- /dev/null +++ b/src/cpu/allwinner/a10/monotonic_timer.c @@ -0,0 +1,13 @@ +/* + * Placeholder for code to come (needed to complete build) + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + (void)mt; +} diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c new file mode 100644 index 0000000..2525de5 --- /dev/null +++ b/src/cpu/allwinner/a10/pinmux.c @@ -0,0 +1,30 @@ +/* + * Helpers to multiplex and configure pins on Allwinner SoCs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "gpio.h" + +#include <arch/io.h> + +static struct a10_gpio *const gpio = (void *)GPIO_BASE; + +void gpio_set_func(u8 port, u8 pin, u8 pad_func) +{ + u8 reg, bit; + u32 reg32; + + if ((port > GPS)) + return; + + pin &= 0x1f; + reg = pin / 8; + bit = (pin % 8) * 4; + + reg32 = read32(&gpio->port[port].cfg[reg]); + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + write32(reg32, &gpio->port[port].cfg[reg]); +} diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c new file mode 100644 index 0000000..e156398 --- /dev/null +++ b/src/cpu/allwinner/a10/timer.c @@ -0,0 +1,19 @@ +/* + * Placeholder for code to come(needed to complete build) + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <delay.h> +#include <timer.h> + +void init_timer(void) +{ + /* Stub */ +} + +void udelay(unsigned usec) +{ + /* Stub */ +} diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c new file mode 100644 index 0000000..923c7c1 --- /dev/null +++ b/src/cpu/allwinner/a10/uart.c @@ -0,0 +1,92 @@ +/* + * Uart setup helpers for Allwinner SoCs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "uart.h" +#include <arch/io.h> + +/** + * \brief Configure line control settings for UART + */ +void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, + enum uart_parity parity, u8 stop_bits) +{ + u32 reg32; + u16 div; + struct a10_uart *uart = uart_base; + + /* Enable access to Divisor Latch register */ + write32(UART_LCR_DLAB, &uart->lcr); + /* Set baudrate */ + /* FIXME: We assume clock is 24MHz, which may not be the case */ + div = 24000000 / 16 / baud_rate; + write32((div >> 8) & 0xff, &uart->dlh); + write32(div & 0xff, &uart->dll); + /* Set line control */ + reg32 = UART_LCR_DATALEN(data_bits); + switch (parity) { + case UART_PARITY_ODD: + reg32 |= UART_LCR_PEN; + break; + case UART_PARITY_EVEN: + reg32 |= UART_LCR_PEN; + reg32 |= UART_LCR_EPS; + break; + case UART_PARITY_NONE: /* Fall through */ + default: + break; + } + write32(reg32, &uart->lcr); +} + +void a10_uart_enable_fifos(void *uart_base) +{ + struct a10_uart *uart = uart_base; + + write32(UART_FCR_FIFOE, &uart->fcr); +} + +static int tx_fifo_full(struct a10_uart *uart) +{ + /* This may be a misnomer, or a typo in the datasheet. THRE indicates + * that the TX register is empty, not that the FIFO is not full, but + * this may be due to a datasheet typo. Keep the current name to signal + * intent. */ + return !(read32(&uart->lsr) & UART_LSR_THRE); +} + +static int rx_fifo_empty(struct a10_uart *uart) +{ + return !(read32(&uart->lsr) & UART_LSR_DR); +} + +/** + * \brief Read a single byte from the UART. + * + * Blocks until at least a byte is available. + */ +u8 a10_uart_rx_blocking(void *uart_base) +{ + struct a10_uart *uart = uart_base; + + while (rx_fifo_empty(uart)) ; + + return read32(&uart->rbr); +} + +/** + * \brief Write a single byte to the UART. + * + * Blocks until there is space in the FIFO. + */ +void a10_uart_tx_blocking(void *uart_base, u8 data) +{ + struct a10_uart *uart = uart_base; + + while (tx_fifo_full(uart)) ; + + return write32(data, &uart->thr); +} diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h new file mode 100644 index 0000000..c324dc1d --- /dev/null +++ b/src/cpu/allwinner/a10/uart.h @@ -0,0 +1,102 @@ +/* + * Definitions for UART on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_UART_H +#define CPU_ALLWINNER_A10_UART_H + +#include "memmap.h" +#include <types.h> + +/* UART_FCR definitions */ +#define UART_FCR_DMAM (1 << 3) +#define UART_FCR_XFIFOR (1 << 2) +#define UART_FCR_RFIFOR (1 << 1) +#define UART_FCR_FIFOE (1 << 0) + +/* UART_LCR definitions */ +#define UART_LCR_DLAB (1 << 7) +#define UART_LCR_BC (1 << 6) +#define UART_LCR_EPS (1 << 4) +#define UART_LCR_PEN (1 << 3) +#define UART_LCR_STOP_MASK (0x3 << 2) +#define UART_LCR_STOP_1BIT (0 << 2) +#define UART_LCR_STOP_2BIT (1 << 2) +#define UART_LCR_DLS_MASK (3 << 0) +#define UART_LCR_DATALEN(bits) ((bits - 5) & UART_LCR_DLS_MASK) + +/* UART_LSR definitions */ +#define UART_LSR_FIFOERR (1 << 7) +#define UART_LSR_TEMT (1 << 6) +#define UART_LSR_THRE (1 << 5) +#define UART_LSR_BI (1 << 4) +#define UART_LSR_FE (1 << 3) +#define UART_LSR_PE (1 << 2) +#define UART_LSR_OE (1 << 1) +#define UART_LSR_DR (1 << 0) + +#define BAUD_115200 (0xd) + +struct a10_uart { + union { + /* operational mode */ + u32 rbr; /* receiver buffer (read) */ + u32 thr; /* transmit holding (write) */ + /* config mode A and B */ + u32 dll; /* divisor latches low */ + }; + + union { + /* operational mode */ + u32 ier; /* interrupt enable */ + /* config mode A and B */ + u32 dlh; /* divisor latches high */ + }; + + union { + /* operational mode, config mode A */ + u32 iir; /* interrupt ID (read) */ + u32 fcr; /* FIFO control (write) */ + }; + + u32 lcr; /* line control */ + + /* 0x10 */ + u32 mcr; /* modem control */ + u32 lsr; /* line status, read-only */ + u32 msr; /* modem status */ + u32 sch; /* trigger level */ + + u8 reserved_0x20[0x50]; + + /* 0x70 */ + u8 reserved_0x70[0xc]; + u32 usr; /* frequency select */ + + /* 0x80 */ + u32 tfl; /* mode definition register 3 */ + u32 rfl; + u8 reserved_0x88[0x18]; + + /* 0xa0 */ + u8 reserved_0xa0[4]; + u32 halt; /* TX DMA threshold */ + +} __attribute__ ((packed)); + +enum uart_parity { + UART_PARITY_NONE, + UART_PARITY_EVEN, + UART_PARITY_ODD, +}; + +void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, + enum uart_parity parity, u8 stop_bits); +void a10_uart_enable_fifos(void *uart_base); +u8 a10_uart_rx_blocking(void *uart_base); +void a10_uart_tx_blocking(void *uart_base, u8 data); + +#endif /* CPU_ALLWINNER_A10_UART_H */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c new file mode 100644 index 0000000..58930dd --- /dev/null +++ b/src/cpu/allwinner/a10/uart_console.c @@ -0,0 +1,109 @@ +/* + * Glue to UART code to enable serial console + * + * Copyright 2013 Google Inc. + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <config.h> +#include <types.h> +#include <uart.h> +#include <arch/io.h> + +#include <console/console.h> +#include <cpu/allwinner/a10/uart.h> + +static void *get_console_uart_base_addr(void) +{ + /* This big block gets compiled to a constant, not a function call */ + if (CONFIG_CONSOLE_SERIAL_UART0) + return (void *)A1X_UART0_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART1) + return (void *)A1X_UART1_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART2) + return (void *)A1X_UART2_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART3) + return (void *)A1X_UART3_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART4) + return (void *)A1X_UART4_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART5) + return (void *)A1X_UART5_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART6) + return (void *)A1X_UART6_BASE; + else if (CONFIG_CONSOLE_SERIAL_UART7) + return (void *)A1X_UART7_BASE; + + /* If selection is invalid, default to UART0 */ + return (void *)A1X_UART0_BASE; +} + +static u32 get_console_uart_baud(void) +{ + if (CONFIG_CONSOLE_SERIAL_115200) + return 115200; + else if (CONFIG_CONSOLE_SERIAL_57600) + return 57600; + else if (CONFIG_CONSOLE_SERIAL_38400) + return 34800; + else if (CONFIG_CONSOLE_SERIAL_19200) + return 19200; + else if (CONFIG_CONSOLE_SERIAL_9600) + return 9600; + + /* Default to 115200 if selection is invalid */ + return 115200; +} + +static void a10_uart_init_dev(void) +{ + void *uart_base = get_console_uart_base_addr(); + /* Use default 8N1 encoding */ + a10_uart_configure(uart_base, get_console_uart_baud(), + 8, UART_PARITY_NONE, 1); + a10_uart_enable_fifos(uart_base); +} + +static unsigned char a10_uart_rx_byte(void) +{ + return a10_uart_rx_blocking(get_console_uart_base_addr()); +} + +static void a10_uart_tx_byte(unsigned char data) +{ + a10_uart_tx_blocking(get_console_uart_base_addr(), data); +} + +uint32_t uartmem_getbaseaddr(void) +{ + return (uint32_t) get_console_uart_base_addr(); +} + +#if !defined(__PRE_RAM__) +static const struct console_driver a10_uart_console __console = { + .init = a10_uart_init_dev, + .tx_byte = a10_uart_tx_byte, + .rx_byte = a10_uart_rx_byte, +}; +#else + +void uart_init(void) +{ + a10_uart_init_dev(); +} + +unsigned char uart_rx_byte(void) +{ + return a10_uart_rx_byte(); +} + +void uart_tx_byte(unsigned char data) +{ + a10_uart_tx_byte(data); +} + +void uart_tx_flush(void) +{ +} + +#endif

1 0

Patch set updated for coreboot: a08ad00 cpu/allwinner/a10: Refactor and document pinmux API
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4565 -gerrit commit a08ad00d7856e04ea36d333f4bd087583602b14f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 22 21:30:21 2013 -0500 cpu/allwinner/a10: Refactor and document pinmux API Include a function to multiplex more than one pin at a time. This is useful for peripherals that have the same function number for all their pins. Since we now have two functions for muxing pins, also document them. Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/gpio.h | 3 +- src/cpu/allwinner/a10/pinmux.c | 51 +++++++++++++++++++++++++- src/mainboard/cubietech/cubieboard/bootblock.c | 7 ++-- 3 files changed, 55 insertions(+), 6 deletions(-) diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h index f285451..709f74b 100644 --- a/src/cpu/allwinner/a10/gpio.h +++ b/src/cpu/allwinner/a10/gpio.h @@ -46,6 +46,7 @@ struct a10_gpio { u32 sdr_pad_pul; } __attribute__ ((packed)); -void gpio_set_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func); +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func); #endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c index 2525de5..de87440 100644 --- a/src/cpu/allwinner/a10/pinmux.c +++ b/src/cpu/allwinner/a10/pinmux.c @@ -11,7 +11,14 @@ static struct a10_gpio *const gpio = (void *)GPIO_BASE; -void gpio_set_func(u8 port, u8 pin, u8 pad_func) +/** + * \brief Set the pad function of a single pin + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin the pin number in the given port (1 -> 31) + * @param[in] pad_func The peripheral function to which to connect this pin + */ +void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func) { u8 reg, bit; u32 reg32; @@ -28,3 +35,45 @@ void gpio_set_func(u8 port, u8 pin, u8 pad_func) reg32 |= (pad_func & 0xf) << bit; write32(reg32, &gpio->port[port].cfg[reg]); } + +/** + * \brief Set the pad function of a group of pins + * + * Multiplex a group of pins to the same pad function. This is useful for + * peripherals that use the same function number for several pins. This function + * allows those pins to be set with a single call. + * + * Example: + * gpio_set_multipin_func(GPB, (1 << 23) | (1 << 22), 2); + * + * @param[in] port GPIO port of the pin (GPA -> GPS) + * @param[in] pin_mask 32-bit mask indicating which pins to re-multiplex. For + * each set bit, the corresponding pin will be multiplexed. + * @param[in] pad_func The peripheral function to which to connect the pins + */ +void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func) +{ + int j; + u8 reg, bit; + u32 reg32, mask_offset; + + if ((port > GPS)) + return; + + for (reg = 0; reg < 4; reg++) { + mask_offset = 8 * reg; + /* Don't run the inner loop if we're not touching any pins */ + if (!(pin_mask & (0xff << mask_offset))) + continue; + + reg32 = read32(&gpio->port[port].cfg[reg]); + for (j = 0; j < 8; j++) { + if (!(pin_mask & (1 << (j + mask_offset)))) + continue; + bit = j * 4; + reg32 &= ~(0xf << bit); + reg32 |= (pad_func & 0xf) << bit; + } + write32(reg32, &gpio->port[port].cfg[reg]); + } +} diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 6e8b751..a91391c 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -18,8 +18,8 @@ | AHB_DIV_1 \ | AXI_DIV_1 -#define GPB22_UART0_TX_FUNC 2 -#define GPB23_UART0_RX_FUNC 2 +#define GPB_UART0_FUNC 2 +#define GPB_UART0_PINS ((1 << 22) | (1 << 23)) static void cubieboard_set_sys_clock(void) { @@ -57,8 +57,7 @@ static void cubieboard_setup_clocks(void) static void cubieboard_setup_gpios(void) { /* Mux UART pins */ - gpio_set_func(GPB, 22, GPB22_UART0_TX_FUNC); - gpio_set_func(GPB, 23, GPB23_UART0_RX_FUNC); + gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); } static void cubieboard_enable_uart(void)

1 0

Patch set updated for coreboot: 7905dbb mainboard: Add preliminary support for A10-based Cubieboard
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4553 -gerrit commit 7905dbb2e6e15eb52a39f5ad122aebe33de2441a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Dec 13 20:25:04 2013 -0600 mainboard: Add preliminary support for A10-based Cubieboard Add a minimal infrastructure which initializes the system clocks and serial console. Change-Id: I768ede6ccf8674ffe9fecd8925cec89768209cab Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/cubietech/Kconfig | 18 ++++++ src/mainboard/cubietech/cubieboard/Kconfig | 29 +++++++++ src/mainboard/cubietech/cubieboard/Makefile.inc | 1 + src/mainboard/cubietech/cubieboard/bootblock.c | 80 ++++++++++++++++++++++++ src/mainboard/cubietech/cubieboard/devicetree.cb | 3 + src/mainboard/cubietech/cubieboard/romstage.c | 14 +++++ 7 files changed, 148 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index fdb0eac..6ba057a 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -48,6 +48,8 @@ config VENDOR_BROADCOM bool "Broadcom" config VENDOR_COMPAQ bool "Compaq" +config VENDOR_CUBIETECH + bool "Cubietech" config VENDOR_DIGITALLOGIC bool "DIGITAL-LOGIC" config VENDOR_DMP @@ -161,6 +163,7 @@ source "src/mainboard/bifferos/Kconfig" source "src/mainboard/biostar/Kconfig" source "src/mainboard/broadcom/Kconfig" source "src/mainboard/compaq/Kconfig" +source "src/mainboard/cubietech/Kconfig" source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/dmp/Kconfig" source "src/mainboard/eaglelion/Kconfig" diff --git a/src/mainboard/cubietech/Kconfig b/src/mainboard/cubietech/Kconfig new file mode 100644 index 0000000..840ee85 --- /dev/null +++ b/src/mainboard/cubietech/Kconfig @@ -0,0 +1,18 @@ +if VENDOR_CUBIETECH + +# Auto select common options +choice + prompt "Mainboard model" + +config BOARD_CUBIETECH_CUBIEBOARD + bool "Cubieboard" + +endchoice + +source "src/mainboard/cubietech/cubieboard/Kconfig" + +config MAINBOARD_VENDOR + string + default "Cubietech" + +endif # VENDOR_CUBIETECH diff --git a/src/mainboard/cubietech/cubieboard/Kconfig b/src/mainboard/cubietech/cubieboard/Kconfig new file mode 100644 index 0000000..72b797e --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/Kconfig @@ -0,0 +1,29 @@ +if BOARD_CUBIETECH_CUBIEBOARD + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_ALLWINNER_A10 + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default cubietech/cubieboard + +config MAINBOARD_PART_NUMBER + string + default "Cubieboard A10" + +config MAX_CPUS + int + default 1 + +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/cubietech/cubieboard/bootblock.c" + +config DRAM_SIZE_MB + int + default 1024 + +endif # BOARD_CUBIETECH_CUBIEBOARD diff --git a/src/mainboard/cubietech/cubieboard/Makefile.inc b/src/mainboard/cubietech/cubieboard/Makefile.inc new file mode 100644 index 0000000..29763fb --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/Makefile.inc @@ -0,0 +1 @@ +romstage-y += romstage.c diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c new file mode 100644 index 0000000..6e8b751 --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -0,0 +1,80 @@ +/* + * Minimal bootblock for Cubieboard + * It sets up CPU clock, and enables the bootblock console. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <arch/io.h> +#include <uart.h> +#include <console/console.h> +#include <cpu/allwinner/a10/gpio.h> +#include <cpu/allwinner/a10/clock.h> + +#define CPU_AHB_APB0_DEFAULT \ + CPU_CLK_SRC_OSC24M \ + | APB0_DIV_1 \ + | AHB_DIV_1 \ + | AXI_DIV_1 + +#define GPB22_UART0_TX_FUNC 2 +#define GPB23_UART0_RX_FUNC 2 + +static void cubieboard_set_sys_clock(void) +{ + u32 reg32; + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + + /* Switch CPU clock to main oscillator */ + write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg); + + /* Configure the PLL1. The value is the same one used by u-boot */ + write32(0xa1005000, &ccm->pll1_cfg); + + /* FIXME: Delay to wait for PLL to lock */ + u32 wait = 1000; + while (--wait); + + /* Switch CPU to PLL clock */ + reg32 = read32(&ccm->cpu_ahb_apb0_cfg); + reg32 &= ~CPU_CLK_SRC_MASK; + reg32 |= CPU_CLK_SRC_PLL1; + write32(reg32, &ccm->cpu_ahb_apb0_cfg); +} + +static void cubieboard_setup_clocks(void) +{ + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + + cubieboard_set_sys_clock(); + /* Configure the clock source for APB1. This drives our UART */ + write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0), + &ccm->apb1_clk_div_cfg); + +} + +static void cubieboard_setup_gpios(void) +{ + /* Mux UART pins */ + gpio_set_func(GPB, 22, GPB22_UART0_TX_FUNC); + gpio_set_func(GPB, 23, GPB23_UART0_RX_FUNC); +} + +static void cubieboard_enable_uart(void) +{ + u32 reg32; + struct a10_ccm *ccm = (void *)A1X_CCM_BASE; + /* Enable clock to UART0 */ + reg32 = read32(&ccm->apb1_gate); + reg32 |= APB1_GATE_UART(0); + write32(reg32, &ccm->apb1_gate); +} + +void bootblock_mainboard_init(void); +void bootblock_mainboard_init(void) +{ + cubieboard_setup_clocks(); + cubieboard_setup_gpios(); + cubieboard_enable_uart(); +} diff --git a/src/mainboard/cubietech/cubieboard/devicetree.cb b/src/mainboard/cubietech/cubieboard/devicetree.cb new file mode 100644 index 0000000..1358777 --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/devicetree.cb @@ -0,0 +1,3 @@ +chip cpu/allwinner/a10 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c new file mode 100644 index 0000000..19192cd --- /dev/null +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -0,0 +1,14 @@ +/* + * Placeholder for Cubieboard romstage + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <console/console.h> + +void main(void) +{ + console_init(); + printk(BIOS_INFO, "You have managed to succesfully load romstage.\n"); +}

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Patch set updated for coreboot: 6c350c4 cpu/allwinner/a10: Refactor API for gating clocks to peripherals
by Alexandru Gagniuc 29 Dec '13

29 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4571 -gerrit commit 6c350c46e4021b2c944b187dcae44cef00a5689e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Dec 24 16:48:03 2013 -0500 cpu/allwinner/a10: Refactor API for gating clocks to peripherals Rather than having to track which bit in which register should be cleared or set to gate or ungate the clock to a certain peripheral, provide a simplified enum which encodes the register and bit. This change comes with a function which decodes the enum and gates/ungates the clock. This also removes the register-dependent bitmasks for APB0 and APB1 gating registers. Change-Id: Ib3ca16e54eb37eadc3ceb88f4ccc497829ac34bc Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 1 + src/cpu/allwinner/a10/clock.c | 42 +++++++++ src/cpu/allwinner/a10/clock.h | 116 ++++++++++++++++++++++--- src/mainboard/cubietech/cubieboard/bootblock.c | 7 +- 4 files changed, 148 insertions(+), 18 deletions(-) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 9f7208a..fecaf0e 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += bootblock_media.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c new file mode 100644 index 0000000..bc78743 --- /dev/null +++ b/src/cpu/allwinner/a10/clock.c @@ -0,0 +1,42 @@ +/* + * Helpers for clock control and gating on Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "clock.h" + +#include <arch/io.h> + +/** + * \brief Enable the clock source for the peripheral + * + * @param[in] periph peripheral and clock type to enable @see a1x_clken + */ +void a1x_periph_clock_enable(enum a1x_clken periph) +{ + void *addr; + u32 reg32; + + addr = (void *)A1X_CCM_BASE + (periph >> 5); + reg32 = read32(addr); + reg32 |= 1 << (periph & 0x1f); + write32(reg32, addr); +} + +/** + * \brief Disable the clock source for the peripheral + * + * @param[in] periph peripheral and clock type to enable @see a1x_clken + */ +void a1x_periph_clock_disable(enum a1x_clken periph) +{ + void *addr; + u32 reg32; + + addr = (void *)A1X_CCM_BASE + (periph >> 5); + reg32 = read32(addr); + reg32 &= ~(1 << (periph & 0x1f)); + write32(reg32, addr); +} diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index e028d13..b9a0771 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -43,19 +43,108 @@ #define APB1_RAT_M_MASK 0x1f << 0) #define APB1_RAT_M(n) (((n) & 0x1f) << 0) -/* APB0_GATING values */ -#define APB0_GATE_KEYPAD (1 << 10) -#define APB0_GATE_IR(x) (((1 << (x)) & 0x3) << 6) -#define APB0_GATE_PIO (1 << 5) -#define APB0_GATE_IIS (1 << 3) -#define APB0_GATE_AC97 (1 << 2) -#define APB0_GATE_CODEC (1 << 0) +/** + * \brief Clock gating definitions + * + * The definitions are specified in the form: + * 31:5 register offset from A1X_CCM_BASE for the clock register + * 4:0 bit offset for the given peripheral + * + * The names have the form [periph_type][periph_number] + * + * These definitions are meant to be used with @ref a1x_periph_clock_enable and + * @ref a1x_periph_clock_disable + */ -/* APB1_GATING values */ -#define APB1_GATE_UART(x) (((1 << (x)) & 0xff) << 16) -#define APB1_GATE_PS2(x) (((1 << (x)) & 0x3) << 6) -#define APB1_GATE_CAN (1 << 4) -#define APB1_GATE_TWI(x) (((1 << (x)) & 0x7) << 0) +enum a1x_clken { + /* AXI module clock gating */ + A1X_CLKEN_DRAM_AXI = (0x5C << 5), + /* AHB0 module clock gating */ + A1X_CLKEN_USB0 = (0x60 << 5), + A1X_CLKEN_EHCI0, + RSVD_0x60_2, + A1X_CLKEN_EHCI1, + RSVD_0x60_4, + A1X_CLKEN_SS, + A1X_CLKEN_DMA, + A1X_CLKEN_BIST, + A1X_CLKEN_MMC0, + A1X_CLKEN_MMC1, + A1X_CLKEN_MMC2, + A1X_CLKEN_MMC3, + A1X_CLKEN_NC, + A1X_CLKEN_NAND, + A1X_CLKEN_SDRAM, + RSVD_0x60_15, + A1X_CLKEN_ACE, + A1X_CLKEN_EMAC, + A1X_CLKEN_TS, + RSVD_0x60_19, + A1X_CLKEN_SPI0, + A1X_CLKEN_SPI1, + A1X_CLKEN_SPI2, + A1X_CLKEN_SPI3, + A1X_CLKEN_PATA, + /* AHB1 module clock gating */ + A1X_CLKEN_DRAM_VE = (0x64 << 5), + A1X_CLKEN_TVD, + A1X_CLKEN_TVE0, + A1X_CLKEN_TVE1, + A1X_CLKEN_LCD0, + A1X_CLKEN_LCD1, + RSVD_0x64_6, + RSVD_0x64_7, + A1X_CLKEN_CSI0, + A1X_CLKEN_CSI1, + RSVD_0x64_10, + A1X_CLKEN_HDMI, + A1X_CLKEN_DE_BE0, + A1X_CLKEN_DE_BE1, + A1X_CLKEN_DE_FE0, + A1X_CLKEN_DE_FE1, + RSVD_0x64_16, + RSVD_0x64_17, + A1X_CLKEN_MP, + RSVD_0x64_19, + A1X_CLKEN_MALI400, + /* APB0 module clock gating */ + A1X_CLKEN_CODEC = (0x68 << 5), + A1X_CLKEN_NC_APB, + A1X_CLKEN_AC97, + A1X_CLKEN_IIS, + RSVD_0x68_4, + A1X_CLKEN_PIO, + A1X_CLKEN_IR0, + A1X_CLKEN_IR1, + RSVD_0x68_8, + RSVD_0x68_9, + A1X_CLKEN_KEYPAD, + /* APB1 module clock gating */ + A1X_CLKEN_TWI0 = (0x6C << 5), + A1X_CLKEN_TWI1, + A1X_CLKEN_TWI2, + RSVD_0x6C_3, + A1X_CLKEN_CAN, + A1X_CLKEN_SCR, + A1X_CLKEN_PS20, + A1X_CLKEN_PS21, + RSVD_0x6C_8, + RSVD_0x6C_9, + RSVD_0x6C_10, + RSVD_0x6C_11, + RSVD_0x6C_12, + RSVD_0x6C_13, + RSVD_0x6C_14, + RSVD_0x6C_15, + A1X_CLKEN_UART0, + A1X_CLKEN_UART1, + A1X_CLKEN_UART2, + A1X_CLKEN_UART3, + A1X_CLKEN_UART4, + A1X_CLKEN_UART5, + A1X_CLKEN_UART6, + A1X_CLKEN_UART7, +}; struct a10_ccm { u32 pll1_cfg; /* 0x00 pll1 control */ @@ -134,4 +223,7 @@ struct a10_ccm { u32 mbus_clk_cfg; /* 0x15c */ } __attribute__ ((packed)); +void a1x_periph_clock_enable(enum a1x_clken periph); +void a1x_periph_clock_disable(enum a1x_clken periph); + #endif /* CPU_ALLWINNER_A10_CLOCK_H */ diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index a91391c..a7a55b5 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -62,12 +62,7 @@ static void cubieboard_setup_gpios(void) static void cubieboard_enable_uart(void) { - u32 reg32; - struct a10_ccm *ccm = (void *)A1X_CCM_BASE; - /* Enable clock to UART0 */ - reg32 = read32(&ccm->apb1_gate); - reg32 |= APB1_GATE_UART(0); - write32(reg32, &ccm->apb1_gate); + a1x_periph_clock_enable(A1X_CLKEN_UART0); } void bootblock_mainboard_init(void);

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coreboot-gerrit December 2013