coreboot-gerrit December 2013

coreboot-gerrit@coreboot.org

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1377 discussions

Patch merged into coreboot/master: 007fa11 AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge
by gerrit＠coreboot.org 30 Dec '13

30 Dec '13

the following patch was just integrated into master: commit 007fa11d63a75ed46c175cf59ea2dd5ae02b50e6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 23:14:27 2013 +0200 AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4567 for details. -gerrit

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Patch merged into coreboot/master: b039953 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
by gerrit＠coreboot.org 30 Dec '13

30 Dec '13

the following patch was just integrated into master: commit b039953dcea6750ac4b454cd234591eff32c027c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 20:48:40 2013 +0200 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4558 for details. -gerrit

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Patch merged into coreboot/master: c5c95e9 AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORT
by gerrit＠coreboot.org 30 Dec '13

30 Dec '13

the following patch was just integrated into master: commit c5c95e9530564ee2edcb2c59a78fc49a8c499ec6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 23 09:56:36 2013 +0200 AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORT Change-Id: Ie109f58bd8ce54754b8d0b00118e75ace8717df0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4566 for details. -gerrit

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New patch to review for coreboot: 061cdd8 SuperIO: Add support for Nuvoton NCT6779D (Draft)
by Alec Ari 30 Dec '13

30 Dec '13

Alec Ari (neotheuser(a)ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4589 -gerrit commit 061cdd836b19d9ac3a315617673f738c2bff1b5d Author: Alec Ari <neotheuser(a)ymail.com> Date: Sun Dec 29 23:48:38 2013 -0600 SuperIO: Add support for Nuvoton NCT6779D (Draft) Adds support for the Nuvoton NCT6779D Super I/O (Not working) This is an entry draft and a lot of the datasheet I had difficulty understanding, therefor this commit should be thoroughly reviewed and verified by an experienced developer before pushing this into the official tree. This commit will not work as-is and has not been tested. It is unknown as to whether this will even compile. Change-Id: I03b3c39e4409bd57e8c0759d9c3fdd160f0376d4 Signed-off-by: Alec Ari <neotheuser(a)ymail.com> --- src/superio/nuvoton/Kconfig | 2 + src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct6779d/Makefile.inc | 23 ++++++++++ src/superio/nuvoton/nct6779d/early_init.c | 47 +++++++++++++++++++ src/superio/nuvoton/nct6779d/nct6779d.h | 76 +++++++++++++++++++++++++++++++ src/superio/nuvoton/nct6779d/superio.c | 68 +++++++++++++++++++++++++++ 6 files changed, 217 insertions(+) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 142738d..8bbfdb0 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -21,3 +21,5 @@ config SUPERIO_NUVOTON_WPCM450 bool config SUPERIO_NUVOTON_NCT5104D bool +config SUPERIO_NUVOTON_NCT6779D + bool diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 18025c9..d115bac 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -19,3 +19,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d diff --git a/src/superio/nuvoton/nct6779d/Makefile.inc b/src/superio/nuvoton/nct6779d/Makefile.inc new file mode 100644 index 0000000..1900470 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Alec Ari (neotheuser(a)ymail.com) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += early_init.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c + diff --git a/src/superio/nuvoton/nct6779d/early_init.c b/src/superio/nuvoton/nct6779d/early_init.c new file mode 100644 index 0000000..3e51724 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/early_init.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pnp_def.h> +#include "nct6779d.h" + +static void pnp_enter_extended_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87,port); + outb(0x87,port); +} + +static void pnp_exit_extended_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa,port); +} + +static void nct6779d_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_extended_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev,0); + pnp_set_iobase(dev,PNP_IDX_IO0, iobase); + pnp_set_enable(dev,1); + pnp_exit_extended_mode(dev); +} diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h new file mode 100644 index 0000000..5019380 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/nct6779d.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_NCT6779D_NCT6779D_H +#define SUPERIO_NUVOTON_NCT6779D_NCT6779D_H + +/* Logical Device Numbers (LDN). */ +#define NCT6779D_ACPI 0x0a /* ACPI */ + +/* Should NCT6779D_HWMN be a virtual LDN since it is for Hardware Monitor and Front Panel LED? */ +#define NCT6779D_HWMN 0x0b /* Hw-mon / Front Pan LED */ + +#define NCT6779D_WDT1 0x0d /* WDT1 */ +#define NCT6779D_CIRW 0x0e /* CIR Wake-up */ +#define NCT6779D_PPOD 0x0f /* GPIO Push-Pull / Open drain select */ +#define NCT6779D_PAR 0x01 /* Parallel Port */ +#define NCT6779D_SP1 0x02 /* Com1 */ + +/* Should NCT6779D_SP2 be a virtual LDN since it is for UART B & IR? */ +#define NCT6779D_SP2 0x03 /* Com2 (UART B & IR) */ + +#define NCT6779D_KBD 0x05 /* Keyboard Controller */ +#define NCT6779D_CIR 0x06 /* CIR */ + +/* Should NCT6779D_GPIO_WDT be a virtual LDN since it is for WDT1, GPIO 0,1? */ +#define NCT6779D_GPIO_WDT 0x08 /* GPIO WDT Interface */ + +#define NCT6779D_UART 0x14 /* Port 80 UART */ +#define NCT6779D_DSLP 0x16 /* Deep Sleep */ + +/* Virtual Logical Device Numbers (LDN) */ +/* What is going on here? */ +#define NCT6779D_GPIO_ALL_V 0x09 /* GPIO - 1,2,3,4,5,6,7,8 */ + +/* Why does this LDN share some of the same functions from 0x09? */ +#define NCT6779D_GPIO_V 0x07 /* GPIO - 6,7,8 */ + +/* Virtual devices sharing the enables are encoded as follows: + VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN +*/ + +/* No idea what I'm doing from this point on */ +#define NCT6779D_GPIO6 ((6 << 8) | NCT6779D_GPIO_V) +#define NCT6779D_GPIO7 ((7 << 8) | NCT6779D_GPIO_V) +#define NCT6779D_GPIO8 ((8 << 8) | NCT6779D_GPIO_V) + +/* NCT6779D_GPIO_ALL_V overlaps NCT6779D_GPIO_V (6,7,8 are overlapped) */ +#define NCT6779D_GPIO1_ALL ((1 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO2_ALL ((2 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO3_ALL ((3 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO4_ALL ((4 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO5_ALL ((5 << 8) | NCT6779D_GPIO_ALL_V) + +/* GPIO6,7,8_ALL need different values than GPIO6,7,8 to avoid being redefined */ +#define NCT6779D_GPIO6_ALL ((9 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO7_ALL ((10 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO8_ALL ((11 << 8) | NCT6779D_GPIO_ALL_V) + +#endif diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c new file mode 100644 index 0000000..9076e30 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> +#include "nct6779d.h" + +static void nct6779d_init(device_t dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6779d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Some 0x07f8, 0 values may be incorrect */ + /* Some might be missing PNP_IO1 and PNP_IRQ1 so please verify this */ + { &ops, NCT6779D_PAR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* 0x01 */ + { &ops, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* 0x02 */ + { &ops, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* 0x03 */ + { &ops, NCT6779D_KBD, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* 0x05 */ + { &ops, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* 0x06 */ + { &ops, NCT6779D_GPIO_WDT}, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* 0x08 */ + /* Simply just copied the rest of the non-virtual LDNs here */ + { &ops, NCT6779D_ACPI}, /* 0x0a */ + { &ops, NCT6779D_HWMN, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* 0x0b */ + { &ops, NCT6779D_WDT1}, /* 0x0d */ + { &ops, NCT6779D_CIRW, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* 0x0e */ + { &ops, NCT6779D_PPOD}, /* 0x0f */ + { &ops, NCT6779D_UART}, /* 0x14 */ + { &ops, NCT6779D_DSLP}, /* 0x16 */ + /* Insert GPIO stuff here */ +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6779d_ops = { + CHIP_NAME("NUVOTON NCT6779D Super I/O") + .enable_dev = enable_dev, +};

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New patch to review for coreboot: 16d0597 cpu/allwinner/a10: Add basic TWI (I²C) driver
by Alexandru Gagniuc 30 Dec '13

30 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4588 -gerrit commit 16d0597493e9ec71218ea04887213cab31d6931f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Dec 28 21:50:54 2013 -0500 cpu/allwinner/a10: Add basic TWI (I²C) driver Change-Id: I11b10301199e5ff1a45d9b7d2958cc7b6667a29c Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 1 + src/cpu/allwinner/a10/twi.c | 206 +++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/twi.h | 58 +++++++++++ 3 files changed, 265 insertions(+) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index fecaf0e..6865529 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -11,6 +11,7 @@ romstage-y += bootblock_media.c ramstage-y += uart.c ramstage-y += uart_console.c ramstage-y += timer.c +ramstage-y += twi.c ramstage-y += monotonic_timer.c ramstage-y += bootblock_media.c diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c new file mode 100644 index 0000000..f409422 --- /dev/null +++ b/src/cpu/allwinner/a10/twi.c @@ -0,0 +1,206 @@ +/* + * Setup helpers for Two Wire Interface (TWI) (I²C) Allwinner CPUs + * + * Only functionality for I²C master is provided. + * Largely based on the uboot-sunxi code. + * + * Copyright (C) 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "memmap.h" +#include "twi.h" + +#include <arch/io.h> +#include <delay.h> +#include <device/i2c.h> + +#define TWI_BASE(n) (A1X_TWI0_BASE + 0x400 * (n)) + +#define TWI_TIMEOUT (50 * 1000) + +static u8 is_busy(struct a1x_twi *twi) +{ + return (read32(&twi->stat) != TWI_STAT_IDLE) ; +} + +static enum cb_err wait_until_idle(struct a1x_twi *twi) +{ + u32 i = TWI_TIMEOUT; + while(i-- && is_busy((twi))) + udelay(1); + return i ? CB_SUCCESS : CB_ERR; +} + +/* FIXME: This function basic, and unintelligent */ +static void configure_clock(struct a1x_twi *twi, u32 speed_hz) +{ + /* FIXME: We assume clock is 24MHz, which may not be the case */ + u32 apb_clk = 24000000, m, n; + + /* Pre-divide the clock by 8 */ + n = 3; + m = (apb_clk >> n) / speed_hz; + write32(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk); +} + +void a1x_twi_init(u8 bus, u32 speed_hz) +{ + u32 i = TWI_TIMEOUT; + struct a1x_twi *twi = (void *)TWI_BASE(bus); + + configure_clock(twi, speed_hz); + + /* Enable the I²C bus */ + write32(TWI_CTL_BUS_EN, &twi->ctl); + /* Issue soft reset */ + write32(1, &twi->reset); + + while (i-- && read32(&twi->reset)) + udelay(1); +} + +static void clear_interrupt_flag(struct a1x_twi *twi) +{ + write32(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl); +} + +static void i2c_send_data(struct a1x_twi *twi, u8 data) +{ + write32(data, &twi->data); + clear_interrupt_flag(twi); +} + +static enum twi_status wait_for_status(struct a1x_twi *twi) +{ + u32 i = TWI_TIMEOUT; + /* Wait until interrupt is asserted again */ + while (i-- && !(read32(&twi->ctl) & TWI_CTL_INT_FLAG)) + udelay(1); + /* A timeout here most likely indicates a bus error */ + return i ? read32(&twi->stat) : TWI_STAT_BUS_ERROR; +} + +static void i2c_send_start(struct a1x_twi *twi) +{ + u32 reg32, i; + + /* Send START condition */ + reg32 = read32(&twi->ctl); + reg32 &= ~TWI_CTL_INT_FLAG; + reg32 |= TWI_CTL_M_START; + write32(reg32, &twi->ctl); + + /* M_START is automatically cleared after condition is transmitted */ + i = TWI_TIMEOUT; + while (i-- && (read32(&twi->ctl) & TWI_CTL_M_START)) + udelay(1); +} + +static void i2c_send_stop(struct a1x_twi *twi) +{ + u32 reg32; + + /* Send STOP condition */ + reg32 = read32(&twi->ctl); + reg32 &= ~TWI_CTL_INT_FLAG; + reg32 |= TWI_CTL_M_STOP; + write32(reg32, &twi->ctl); +} + +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + unsigned alen, uint8_t *buf, unsigned len) +{ + unsigned count = len; + enum twi_status expected_status; + struct a1x_twi *twi = (void *)TWI_BASE(bus); + + if (wait_until_idle(twi) != CB_SUCCESS) + return CB_ERR; + + i2c_send_start(twi); + if (wait_for_status(twi) != TWI_STAT_TX_START) + return CB_ERR; + + /* Send chip address */ + i2c_send_data(twi, chip << 1); + if (wait_for_status(twi) != TWI_STAT_TX_AW_ACK) + return CB_ERR; + + /* Send data address */ + i2c_send_data(twi, addr); + if (wait_for_status(twi) != TWI_STAT_TXD_ACK) + return CB_ERR; + + /* Send restart for read */ + i2c_send_start(twi); + if (wait_for_status(twi) != TWI_STAT_TX_RSTART) + return CB_ERR; + + /* Send chip address */ + i2c_send_data(twi, chip << 1 | 1); + if (wait_for_status(twi) != TWI_STAT_TX_AR_ACK) + return CB_ERR; + + /* Start ACK-ing received data */ + setbits_le32(&twi->ctl, TWI_CTL_A_ACK); + expected_status = TWI_STAT_RXD_ACK; + + /* Read data */ + while (count > 0) { + if (count == 1) { + /* Do not ACK the last byte */ + clrbits_le32(&twi->ctl, TWI_CTL_A_ACK); + expected_status = TWI_STAT_RXD_NAK; + } + + clear_interrupt_flag(twi); + + if (wait_for_status(twi) != expected_status) + return CB_ERR; + + *buf++ = read32(&twi->data); + count--; + } + + i2c_send_stop(twi); + + return len; +} + +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + unsigned alen, const uint8_t *buf, unsigned len) +{ + unsigned count = len; + struct a1x_twi *twi = (void *)TWI_BASE(bus); + + if (wait_until_idle(twi) != CB_SUCCESS) + return CB_ERR; + + i2c_send_start(twi); + if (wait_for_status(twi) != TWI_STAT_TX_START) + return CB_ERR; + + /* Send chip address */ + i2c_send_data(twi, chip << 1); + if (wait_for_status(twi) != TWI_STAT_TX_AW_ACK) + return CB_ERR; + + /* Send data address */ + i2c_send_data(twi, addr); + if (wait_for_status(twi) != TWI_STAT_TXD_ACK) + return CB_ERR; + + /* Send data */ + while (count > 0) { + i2c_send_data(twi, *buf++); + if (wait_for_status(twi) != TWI_STAT_TXD_ACK) + return CB_ERR; + count--; + } + + i2c_send_stop(twi); + + return len; +} diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h new file mode 100644 index 0000000..c5f2974 --- /dev/null +++ b/src/cpu/allwinner/a10/twi.h @@ -0,0 +1,58 @@ +/* + * Definitions Two Wire Interface (TWI) (I²C) Allwinner CPUs + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef CPU_ALLWINNER_A10_TWI_H +#define CPU_ALLWINNER_A10_TWI_H + +#include <types.h> + +/* TWI_CTL values */ +#define TWI_CTL_INT_EN (1 << 7) +#define TWI_CTL_BUS_EN (1 << 6) +#define TWI_CTL_M_START (1 << 5) +#define TWI_CTL_M_STOP (1 << 4) +#define TWI_CTL_INT_FLAG (1 << 3) +#define TWI_CTL_A_ACK (1 << 2) + +/* TWI_STAT values */ +enum twi_status { + TWI_STAT_BUS_ERROR = 0x00, /**< Bus error */ + TWI_STAT_TX_START = 0x08, /**< START sent */ + TWI_STAT_TX_RSTART = 0x10, /**< Repeated START sent */ + TWI_STAT_TX_AW_ACK = 0x18, /**< Sent address+read, ACK */ + TWI_STAT_TX_AW_NAK = 0x20, /**< Sent address+read, NAK */ + TWI_STAT_TXD_ACK = 0x28, /**< Sent data, got ACK */ + TWI_STAT_TXD_NAK = 0x30, /**< Sent data, no ACK */ + TWI_STAT_LOST_ARB = 0x38, /**< Lost arbitration */ + TWI_STAT_TX_AR_ACK = 0x40, /**< Sent address+write, ACK */ + TWI_STAT_TX_AR_NAK = 0x48, /**< Sent address+write, NAK */ + TWI_STAT_RXD_ACK = 0x50, /**< Got data, sent ACK */ + TWI_STAT_RXD_NAK = 0x58, /**< Got data, no ACK */ + TWI_STAT_IDLE = 0xf8, /**< Bus idle*/ +}; + +/* TWI_CLK values */ +#define TWI_CLK_M_MASK (0xf << 3) +#define TWI_CLK_M(m) (((m - 1) << 3) & TWI_CLK_M_MASK) +#define TWI_CLK_N_MASK (0x7 << 0) +#define TWI_CLK_N(n) (((n) << 3) & TWI_CLK_N_MASK) + +struct a1x_twi { + u32 addr; /**< 0x00: Slave address */ + u32 xaddr; /**< 0x04: Extended slave address */ + u32 data; /**< 0x08: Data byte */ + u32 ctl; /**< 0x0C: Control register */ + u32 stat; /**< 0x10: Status register */ + u32 clk; /**< 0x14: Clock control register */ + u32 reset; /**< 0x18: Software reset */ + u32 efr; /**< 0x1C: Enhanced Feature register */ + u32 lcr; /**< 0x20: Line control register */ +}; + +void a1x_twi_init(u8 bus, u32 speed_hz); + +#endif /* CPU_ALLWINNER_A10_TWI_H */

1 0

Patch set updated for coreboot: 7b752d0 RFC: console: Make 8250 memmaped console independent of Oxford PCIe952
by Alexandru Gagniuc 30 Dec '13

30 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4587 -gerrit commit 7b752d0e368bd79bb83d0496ed57fd04f41aafd3 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 19:33:06 2013 -0500 RFC: console: Make 8250 memmaped console independent of Oxford PCIe952 RFC: Request for comments. DO NOT MERGE (YET) Running the console on an 8250-compatible memory-mapped UART was only possible via an Oxford PCIe952 adapter, as the console code explicitly depended on variables and functions defined by the Oxford driver. Change-Id: Icde4cdb2d671865502293183aed5664e8690a9ac Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/armv7/early_console.c | 5 +-- src/arch/x86/lib/romstage_console.c | 5 +-- src/console/console.c | 6 +-- src/drivers/oxford/oxpcie/Makefile.inc | 1 + src/drivers/oxford/oxpcie/oxpcie_early.c | 13 ++++-- src/drivers/oxford/oxpcie/oxpcie_memconsole.c | 62 +++++++++++++++++++++++++++ src/include/uart8250.h | 9 ++-- src/lib/uart8250mem.c | 53 +---------------------- 8 files changed, 82 insertions(+), 72 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 84f97ba..3a24075 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -27,10 +27,7 @@ void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart8250_mem_tx_byte(uart8250_mem_get_baseaddr(), byte) #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 278ef1a..cddc16d 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -41,10 +41,7 @@ void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart8250_mem_tx_byte(uart8250_mem_get_baseaddr(), byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/console/console.c b/src/console/console.c index a31e293..93c5f88 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -106,11 +106,11 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_CONSOLE_SERIAL +#if CONFIG_CONSOLE_SERIAL && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif -#if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM - oxford_init(); +#if CONFIG_CONSOLE_SERIAL8250MEM + uart_mem_init(); #endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 6cc29c4..b967e02 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -2,4 +2,5 @@ ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c +ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_memconsole.c endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d04e9d4..ed6a7ff 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -38,7 +38,12 @@ #if defined(__PRE_RAM__) int oxford_oxpcie_present CAR_GLOBAL; -void oxford_init(void) +u32 uart8250_mem_get_baseaddr(void) +{ + return CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +} + +u32 uart_mem_init(void) { u16 reg16; oxford_oxpcie_present = 1; @@ -92,7 +97,7 @@ void oxford_init(void) */ id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; + return -1; device = OXPCIE_DEVICE_3; break; case 0xc1581415: /* e.g. Startech MPEX2S952 */ @@ -101,7 +106,7 @@ void oxford_init(void) default: /* No UART here. */ oxford_oxpcie_present = 0; - return; + return -1; } /* Setup base address on device */ @@ -117,6 +122,8 @@ void oxford_init(void) u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); + + return uart0_base; } #endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_memconsole.c b/src/drivers/oxford/oxpcie/oxpcie_memconsole.c new file mode 100644 index 0000000..d1d0ce4 --- /dev/null +++ b/src/drivers/oxford/oxpcie/oxpcie_memconsole.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Subject to the GNU GPL version 2. + */ + +#include <uart8250.h> +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#include "option_table.h" +#endif + +u32 uart_mem_init(void) +{ + unsigned uart_baud = CONFIG_TTYS0_BAUD; + u32 uart_bar = 0; + unsigned div; + + /* find out the correct baud rate */ +#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE + static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; + unsigned b_index = 0; +#if defined(__PRE_RAM__) && CONFIG_USE_OPTION_TABLE + b_index = read_option(baud_rate, 0); + b_index &= 7; + uart_baud = baud[b_index]; +#else + if (get_option(&b_index, "baud_rate") == CB_SUCCESS) + uart_baud = baud[b_index]; +#endif +#endif + + /* Now find the UART base address and calculate the divisor */ + +#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) + device_t dev = dev_find_device(0x1415, 0xc158, NULL); + if (!dev) + dev = dev_find_device(0x1415, 0xc11b, NULL); + + if (dev) { + struct resource *res = find_resource(dev, 0x10); + + if (res) { + uart_bar = res->base + 0x1000; // for 1st UART + // uart_bar = res->base + 0x2000; // for 2nd UART + } + } + + if (!uart_bar) +#endif + uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART + // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART + + div = 4000000 / uart_baud; + + if (uart_bar) + uart8250_mem_init(uart_bar, div); + + return uart_bar; +} diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 2a0dfcd..c63f398 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,6 +20,8 @@ #ifndef UART8250_H #define UART8250_H +#include <types.h> + /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -133,13 +135,8 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); void uart8250_mem_tx_flush(unsigned base_port); void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); +u32 uart8250_mem_get_baseaddr(void); -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; - -void oxford_init(void); -#endif #endif #endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..39dec37 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,8 +20,8 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> #if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> #include "option_table.h" #endif #include <device/device.h> @@ -102,54 +102,3 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) /* Set to 3 for 8N1 */ write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } - -u32 uart_mem_init(void) -{ - unsigned uart_baud = CONFIG_TTYS0_BAUD; - u32 uart_bar = 0; - unsigned div; - - /* find out the correct baud rate */ -#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE - static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; - unsigned b_index = 0; -#if defined(__PRE_RAM__) - b_index = read_option(baud_rate, 0); - b_index &= 7; - uart_baud = baud[b_index]; -#else - if (get_option(&b_index, "baud_rate") == CB_SUCCESS) - uart_baud = baud[b_index]; -#endif -#endif - - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE - -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); - - if (dev) { - struct resource *res = find_resource(dev, 0x10); - - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } - - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART - - div = 4000000 / uart_baud; -#endif - - if (uart_bar) - uart8250_mem_init(uart_bar, div); - - return uart_bar; -}

1 0

New patch to review for coreboot: 4dd21bf RFC: console: Make 8250 memmaped console independent of Oxford PCIe952
by Alexandru Gagniuc 30 Dec '13

30 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4587 -gerrit commit 4dd21bfa42c8a05e6dfa0882a973ba5f14471700 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 19:33:06 2013 -0500 RFC: console: Make 8250 memmaped console independent of Oxford PCIe952 RFC: Request for comments. DO NOT MERGE (YET) Running the console on an 8250-compatible memory-mapped UART was only possible via an Oxford PCIe952 adapter, as the console code explicitly depended on variables and functions defined by the Oxford driver. Change-Id: Icde4cdb2d671865502293183aed5664e8690a9ac Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/armv7/early_console.c | 5 +-- src/arch/x86/lib/romstage_console.c | 5 +-- src/console/console.c | 6 ++-- src/drivers/oxford/oxpcie/Makefile.inc | 1 + src/drivers/oxford/oxpcie/oxpcie_early.c | 13 ++++++-- src/include/uart8250.h | 9 ++---- src/lib/uart8250mem.c | 53 +------------------------------- 7 files changed, 20 insertions(+), 72 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 84f97ba..3a24075 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -27,10 +27,7 @@ void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart8250_mem_tx_byte(uart8250_mem_get_baseaddr(), byte) #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 278ef1a..cddc16d 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -41,10 +41,7 @@ void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart8250_mem_tx_byte(uart8250_mem_get_baseaddr(), byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/console/console.c b/src/console/console.c index a31e293..93c5f88 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -106,11 +106,11 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_CONSOLE_SERIAL +#if CONFIG_CONSOLE_SERIAL && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif -#if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM - oxford_init(); +#if CONFIG_CONSOLE_SERIAL8250MEM + uart_mem_init(); #endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 6cc29c4..b967e02 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -2,4 +2,5 @@ ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c +ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_memconsole.c endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d04e9d4..ed6a7ff 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -38,7 +38,12 @@ #if defined(__PRE_RAM__) int oxford_oxpcie_present CAR_GLOBAL; -void oxford_init(void) +u32 uart8250_mem_get_baseaddr(void) +{ + return CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +} + +u32 uart_mem_init(void) { u16 reg16; oxford_oxpcie_present = 1; @@ -92,7 +97,7 @@ void oxford_init(void) */ id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; + return -1; device = OXPCIE_DEVICE_3; break; case 0xc1581415: /* e.g. Startech MPEX2S952 */ @@ -101,7 +106,7 @@ void oxford_init(void) default: /* No UART here. */ oxford_oxpcie_present = 0; - return; + return -1; } /* Setup base address on device */ @@ -117,6 +122,8 @@ void oxford_init(void) u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); + + return uart0_base; } #endif diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 2a0dfcd..c63f398 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,6 +20,8 @@ #ifndef UART8250_H #define UART8250_H +#include <types.h> + /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -133,13 +135,8 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); void uart8250_mem_tx_flush(unsigned base_port); void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); +u32 uart8250_mem_get_baseaddr(void); -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; - -void oxford_init(void); -#endif #endif #endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..39dec37 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,8 +20,8 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> #if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> #include "option_table.h" #endif #include <device/device.h> @@ -102,54 +102,3 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) /* Set to 3 for 8N1 */ write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } - -u32 uart_mem_init(void) -{ - unsigned uart_baud = CONFIG_TTYS0_BAUD; - u32 uart_bar = 0; - unsigned div; - - /* find out the correct baud rate */ -#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE - static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; - unsigned b_index = 0; -#if defined(__PRE_RAM__) - b_index = read_option(baud_rate, 0); - b_index &= 7; - uart_baud = baud[b_index]; -#else - if (get_option(&b_index, "baud_rate") == CB_SUCCESS) - uart_baud = baud[b_index]; -#endif -#endif - - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE - -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); - - if (dev) { - struct resource *res = find_resource(dev, 0x10); - - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } - - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART - - div = 4000000 / uart_baud; -#endif - - if (uart_bar) - uart8250_mem_init(uart_bar, div); - - return uart_bar; -}

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New patch to review for coreboot: 4cd2666 uart8250_mem_console.c: Remove inclusion of mc146818rtc.h
by Alexandru Gagniuc 30 Dec '13

30 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4586 -gerrit commit 4cd2666265da9e7d94544ac726a3e173c0b50878 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 18:27:56 2013 -0500 uart8250_mem_console.c: Remove inclusion of mc146818rtc.h The RTC functionality ptovided by the include is specific to x86, but is not used for this type of console. Change-Id: I82d0dfdb6e8b67bc81291a7a5d63ced91e095772 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/console/uart8250mem_console.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..3833e47 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static u32 uart_bar = 0;

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New patch to review for coreboot: 9d60a04 uart8250.h: Do not guard entire include file by config options
by Alexandru Gagniuc 30 Dec '13

30 Dec '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4585 -gerrit commit 9d60a04ce5acc1f196f8fa39265fd4a901e932dd Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 18:13:58 2013 -0500 uart8250.h: Do not guard entire include file by config options Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or CONFIG_CONSOLE_SERIAL8250MEM. The config-specific options are already properly guarded, and there is no need to guard the register and bit definitions. Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/include/uart8250.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/include/uart8250.h b/src/include/uart8250.h index e6a318a..2a0dfcd 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,8 +20,6 @@ #ifndef UART8250_H #define UART8250_H -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -144,6 +142,4 @@ void oxford_init(void); #endif #endif -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - #endif /* UART8250_H */

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Patch set updated for coreboot: b393160 AMD (K8/fam10): Rewrite CAR migration in post_cache_as_ram
by Kyösti Mälkki 30 Dec '13

30 Dec '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4583 -gerrit commit b393160f907eccac64ea0f146f520db96fa679a0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 29 12:07:54 2013 +0200 AMD (K8/fam10): Rewrite CAR migration in post_cache_as_ram Old routine copied all of CAR region as-is right below CONFIG_RAMTOP. Most of this region was reserved to interleave AP CPU address spaces and unused on BSP CPU. The only part of CAR region requiring a copy in RAM is the sysinfo structure. Improved routine changes this as follows: A region of size 'backup_size' below CONFIG_RAMTOP is cleared. In case of S3 resume, OS context from this region is first copied to high memory (CBMEM_ID_RESUME). At stack switch, CAR stack is discarded. Top of the stack for BSP is located at 'CONFIG_RAMTOP - car_size' for the remaining part of the romstage. This region is part of 'backup_size' and was zeroed before the switch took place. Before CAR is torn down the region of CAR_GLOBALS (and CAR_CBMEM), including the relevant sysinfo data for AP nodes memory training, is copied at 'CONFIG_RAMTOP - car_size'. Change-Id: Ie45b576aec6a2e006bfcb26b52fdb77c24f72e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/cache_as_ram.inc | 5 +- src/cpu/amd/car/post_cache_as_ram.c | 171 ++++++++++++++++++++---------------- 2 files changed, 97 insertions(+), 79 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 8f0abce..6d704c5 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -424,10 +424,9 @@ CAR_FAM10_ap_out: cache_as_ram_switch_stack: /* Return address. */ popl %eax - /* Resume memory. */ + /* New stack. */ popl %eax - subl $(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp - pushl %eax + movl %eax, %esp call cache_as_ram_new_stack all_mtrr_msrs: diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 81175da..2e64416 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -8,10 +8,9 @@ #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" -static inline void print_debug_pcar(const char *strval, uint32_t val) -{ - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -} +#if CONFIG_RAMTOP <= 0x100000 + #error "You need to set CONFIG_RAMTOP greater than 1M" +#endif /* from linux kernel 2.6.32 asm/string_32.h */ @@ -29,37 +28,80 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi : "memory", "cc"); } -#if CONFIG_HAVE_ACPI_RESUME +#define PRINTK_IN_CAR 1 +#define ACTUAL_CAR_SIZE 1 -static inline void *backup_resume(void) { - void *resume_backup_memory; - int suspend = acpi_is_wakeup_early(); +#if PRINTK_IN_CAR +#define print_car_debug(x) print_debug(x) +#else +#define print_car_debug(x) +#endif + +extern char _car_data_start[]; +extern char _car_data_end[]; - if (!suspend) - return NULL; +#if ACTUAL_CAR_SIZE +static size_t car_data_size(void) +{ + size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + return ALIGN(car_size, 64); +} - if (!cbmem_reinit()) - return NULL; +static size_t backup_size(void) +{ + size_t car_size = &_car_data_end[0] - &_car_data_start[0]; + return ALIGN(car_size + 1024, 1024); +} +#else +#define car_data_size() 0x1000 +#define backup_size() 0x2000 +#endif - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); +static void memcpy_(void *d, const void *s, size_t len) +{ +#if PRINTK_IN_CAR + printk(BIOS_SPEW, " Copy [%08x-%08x] to [%08x - %08x] ... ", + (u32) s, (u32) (s + len - 1), (u32) d, (u32) (d + len - 1)); +#endif + memcpy(d, s, len); +} - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ +static void memset_(void *d, int val, size_t len) +{ +#if PRINTK_IN_CAR + printk(BIOS_SPEW, " Fill [%08x-%08x] ... ", (u32) d, (u32) (d + len - 1)); +#endif + memset(d, val, len); +} +static void prepare_romstage_ramstack(void *resume_backup_memory) +{ + size_t backup_top = backup_size(); + print_car_debug("Prepare CAR migration and stack regions..."); +#if CONFIG_HAVE_ACPI_RESUME if (resume_backup_memory) { - print_debug_pcar("Will copy coreboot region to: ", (uint32_t) resume_backup_memory); - /* copy only backup only memory used for CAR */ - memcopy(resume_backup_memory+HIGH_MEMORY_SAVE-CONFIG_DCACHE_RAM_SIZE, - (void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), - CONFIG_DCACHE_RAM_SIZE); //inline + memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, + (void *)(CONFIG_RAMTOP - backup_top), backup_top); } - - return resume_backup_memory; +#endif + memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); + print_car_debug("Done\n"); } + +static void prepare_ramstage_region(void *resume_backup_memory) +{ + size_t backup_top = backup_size(); + print_car_debug("Prepare ramstage memory region... "); +#if CONFIG_HAVE_ACPI_RESUME + if (resume_backup_memory) { + memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); + memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE - backup_top); + } #endif + if (!resume_backup_memory) + memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); + print_car_debug("Done\n"); +} /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */ @@ -75,56 +117,46 @@ static void vErrata343(void) #endif } -void cache_as_ram_switch_stack(void *resume_backup_memory); +void cache_as_ram_switch_stack(void * new_stack); +void cache_as_ram_new_stack (void); void post_cache_as_ram(void) { void *resume_backup_memory = NULL; -#if 1 - { - /* Check value of esp to verify if we have enough room for stack in Cache as RAM */ - unsigned v_esp; - __asm__ volatile ( - "movl %%esp, %0\n\t" - : "=a" (v_esp) - ); - print_debug_pcar("v_esp=", v_esp); - } -#endif - - /* copy data from cache as ram to - ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. - */ -#if CONFIG_RAMTOP <= 0x100000 - #error "You need to set CONFIG_RAMTOP greater than 1M" -#endif #if CONFIG_HAVE_ACPI_RESUME - resume_backup_memory = backup_resume(); + if (acpi_is_wakeup_early()) { + cbmem_reinit(); + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + } #endif - - print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); + prepare_romstage_ramstack(resume_backup_memory); /* from here don't store more data in CAR */ vErrata343(); - memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline - cache_as_ram_switch_stack(resume_backup_memory); -} + size_t car_size = car_data_size(); + void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); -void -cache_as_ram_new_stack (void *resume_backup_memory); + print_car_debug("Copying data from cache to RAM... "); + memcpy_(migrated_car, &_car_data_start[0], car_size); + print_car_debug("Done\n"); -void -cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) -{ - /* We can put data to stack again */ + /* New stack grows right below migrated_car. */ + print_car_debug("Switching to use RAM as stack... "); + cache_as_ram_switch_stack(migrated_car); - /* only global variable sysinfo in cache need to be offset */ - print_debug("Done\n"); + /* We do not come back. */ +} - print_debug("Disabling cache as ram now \n"); +void cache_as_ram_new_stack (void) +{ + void *resume_backup_memory = NULL; +#if PRINTK_IN_CAR + printk(BIOS_DEBUG, "Top about %08x ... Done\n", (u32) &resume_backup_memory); +#endif + print_car_debug("Disabling cache as ram now\n"); disable_cache_as_ram_bsp(); disable_cache(); @@ -132,24 +164,11 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) enable_cache(); #if CONFIG_HAVE_ACPI_RESUME - /* now copy the rest of the area, using the WB method because we already - run normal RAM */ - if (resume_backup_memory) { - memcopy(resume_backup_memory, - (void *)(CONFIG_RAMBASE), - (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); + if (acpi_is_wakeup_early()) { + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); } #endif - - print_debug("Clearing initial memory region: "); - -#if CONFIG_HAVE_ACPI_RESUME - /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); -#else - memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); -#endif - print_debug("Done\n"); + prepare_ramstage_region(resume_backup_memory); set_sysinfo_in_ram(1); // So other core0 could start to train mem @@ -157,5 +176,5 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) copy_and_run(); /* We will not return */ - print_debug("should not be here -\n"); + print_car_debug("should not be here -\n"); }

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coreboot-gerrit December 2013