coreboot-gerrit November 2013

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New patch to review for coreboot: d6dd32b libpayload: ARM: Don't leave alignment checking on after the exception test
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4255 -gerrit commit d6dd32b0227aad36672fd8ae31f1723f1924c6db Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 20:48:06 2013 -0700 libpayload: ARM: Don't leave alignment checking on after the exception test Currently, the exception handling code on ARM in libpayload turns on alignment checks as an easy way to generate an exception for testing purposes. It was leaving it on which disabled unaligned accesses for other, unlreated code running later. This change adjusts the code so the original value of the alignment bit is restored after the test exception. Built and booted into depthcharge on pit with an unaligned accesses added after the call to exception_init in the depthcharge's main. Before this change, the access caused an exception. After this change, the access completed successfully. Change-Id: If92cab3cc8eabca7c5b0560ce88a8796a27fe3b2 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59372 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/arch/armv7/exception.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/arch/armv7/exception.c b/payloads/libpayload/arch/armv7/exception.c index 5e4e23d..9efc312 100644 --- a/payloads/libpayload/arch/armv7/exception.c +++ b/payloads/libpayload/arch/armv7/exception.c @@ -143,9 +143,8 @@ void exception_init(void) sctlr &= ~sctlr_te; /* Set V=0 in SCTLR so VBAR points to the exception vector table. */ sctlr &= ~sctlr_v; - /* Enforce alignment. */ - sctlr |= sctlr_a; - set_sctlr(sctlr); + /* Enforce alignment temporarily. */ + set_sctlr(sctlr | sctlr_a); extern uint32_t exception_table[]; set_vbar((uintptr_t)exception_table); @@ -153,4 +152,7 @@ void exception_init(void) test_abort = 1; exception_test(); test_abort = 0; + + /* Restore alignment settings. */ + set_sctlr(sctlr); }

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New patch to review for coreboot: c2adedd libpayload: Make the region to scan for the cb tables configurable.
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4254 -gerrit commit c2adeddfb3bd9b9e0740f923bd2c725b70d92c5e Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 04:54:38 2013 -0700 libpayload: Make the region to scan for the cb tables configurable. The address range to scan for the coreboot tables varies from machine to machine based on the range memory occupies on the SOC being booted and on the amount of memory installed on the machine. To make libpayload work on different ARM systems with different needs, this change makes the region to scan configurable. In the future, we might want to come up with a more automatic mechanism like on x86, although there's less consistency on ARM as far as what ranges are even memory in the first place. Change-Id: Ib50efe25a6152171b0fbd0e324dbc5e89c527d6e Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59242 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/arch/armv7/Config.in | 8 ++++++++ payloads/libpayload/arch/armv7/coreboot.c | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/armv7/Config.in b/payloads/libpayload/arch/armv7/Config.in index 6c1bf44..79cd676 100644 --- a/payloads/libpayload/arch/armv7/Config.in +++ b/payloads/libpayload/arch/armv7/Config.in @@ -33,4 +33,12 @@ config ARCH_SPECIFIC_OPTIONS # dummy def_bool y select LITTLE_ENDIAN +config COREBOOT_INFO_RANGE_BASE + hex "Base of the range to search for the coreboot tables" + +config COREBOOT_INFO_RANGE_SIZE + hex "Size of the range to search for the coreboot tables" + default 0x4000000 + + endif diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index b6178f7..bc9b47e 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -284,7 +284,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0xbc000000), 0x4000000, info); + int ret = cb_parse_header(phys_to_virt(CONFIG_COREBOOT_INFO_RANGE_BASE), + CONFIG_COREBOOT_INFO_RANGE_SIZE, info); return (ret == 1) ? 0 : -1; }

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New patch to review for coreboot: d1d5dcf lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4253 -gerrit commit d1d5dcf41d02ddbe6bc3c2e0ad28a71161fb542a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jun 19 10:49:29 2013 -0700 lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects LynxPoint-LP has a lot of GPEs and the "default" set has been moved to register 4 starting at bit offset 96. This means that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP but still bit 13 in LPT-H. suspend on falco and wake from usb 4 | 2013-06-19 10:49:17 | ACPI Enter | S3 5 | 2013-06-19 10:49:22 | ACPI Wake | S3 6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0 Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59265 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/audio.asl | 15 ++++++++++----- src/southbridge/intel/lynxpoint/acpi/usb.asl | 22 ++++++++++++++++++++-- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index a455328..2bc1168 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -27,10 +27,15 @@ Device (HDEF) { Name (_ADR, 0x001b0000) - // Power Resources for Wake - Name (_PRW, Package(){ - 13, // Bit 13 of GPE - 4 // Can wake from S4 state. - }) + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } } diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 5c1f6a5..6583cb3 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -27,7 +27,16 @@ Device (EHCI) { Name(_ADR, 0x001d0000) - Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } // Leave USB ports on for to allow Wake from USB @@ -61,7 +70,16 @@ Device (XHCI) { Name(_ADR, 0x00140000) - Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake + Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + + Method (_PRW, 0) { // Power Resources for Wake + If (\ISLP ()) { + Return (PRWL) + } Else { + Return (PRWH) + } + } // Leave USB ports on for to allow Wake from USB

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New patch to review for coreboot: 988fe16 libpayload: Add missing break statement in coreboot table parsing
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4252 -gerrit commit 988fe165a68d45307b13a94a4f51440a5fee3e24 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 12:06:50 2013 -0700 libpayload: Add missing break statement in coreboot table parsing Otherwise the code would try to parse GPIOs when encountering a mainboard entry in the coreboot table. This never caused any problems because the mainboard entry is parsed before the GPIO entry. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I1443bda8585a990a39115743d48304ec4b54bccb Reviewed-on: https://gerrit.chromium.org/gerrit/59292 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/arch/armv7/coreboot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index 414b7fa..b6178f7 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -250,6 +250,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) #endif case CB_TAG_MAINBOARD: info->mainboard = (struct cb_mainboard *)ptr; + break; #ifdef CONFIG_CHROMEOS case CB_TAG_GPIO: cb_parse_gpios(ptr, info);

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New patch to review for coreboot: c851199 lynxpoint: move all pcie device handling to pcie.c
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4251 -gerrit commit c8511995cfbfae480bf41e05ff7b8320380b202d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:28:04 2013 -0500 lynxpoint: move all pcie device handling to pcie.c Some of the pcie logic was located in pch.c as well as pcie.c. Move all pcie logic to the same pcie.c file. This is a straight cut-and-paste (no logic changes) except for a rename from pch_pcie_enable() -> pch_pcie_enable_dev(). Change-Id: I338c53039b95f255ab9ced313c51193a9d34b404 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59277 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.c | 187 +-------------------------------- src/southbridge/intel/lynxpoint/pch.h | 1 + src/southbridge/intel/lynxpoint/pcie.c | 185 ++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+), 186 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index f13efb0..b4605f5 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -289,198 +289,13 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) pch_iobp_write(address, data); } -/* Check if any port in set X to X+3 is enabled */ -static int pch_pcie_check_set_enabled(device_t dev) -{ - device_t port; - int port_func; - int dev_func = PCI_FUNC(dev->path.pci.devfn); - - printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); - - /* Go through static device tree list of devices - * because enumeration is still in progress */ - for (port = all_devices; port; port = port->next) { - /* Only care about PCIe root ports */ - if (PCI_SLOT(port->path.pci.devfn) != - PCI_SLOT(dev->path.pci.devfn)) - continue; - - /* Check if port is in range and enabled */ - port_func = PCI_FUNC(port->path.pci.devfn); - if (port_func >= dev_func && - port_func < (dev_func + 4) && - port->enabled) - return 1; - } - - /* None of the ports in this set are enabled */ - return 0; -} - -/* RPFN is a write-once register so keep a copy until it is written */ -static u32 new_rpfn; - -/* Swap function numbers assigned to two PCIe Root Ports */ -static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) -{ - u32 old_rpfn = new_rpfn; - - printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", - old_fn, new_fn); - - new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); - - /* Old function set to new function and disabled */ - new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); - new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); -} - -/* Update devicetree with new Root Port function number assignment */ -static void pch_pcie_devicetree_update(void) -{ - device_t dev; - - /* Update the function numbers in the static devicetree */ - for (dev = all_devices; dev; dev = dev->next) { - u8 new_devfn; - - /* Only care about PCH PCIe root ports */ - if (PCI_SLOT(dev->path.pci.devfn) != - PCH_PCIE_DEV_SLOT) - continue; - - /* Determine the new devfn for this port */ - new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, - RPFN_FNGET(new_rpfn, - PCI_FUNC(dev->path.pci.devfn))); - - if (dev->path.pci.devfn != new_devfn) { - printk(BIOS_DEBUG, - "PCH: PCIe map %02x.%1x -> %02x.%1x\n", - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), - PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); - - dev->path.pci.devfn = new_devfn; - } - } -} - -/* Special handling for PCIe Root Port devices */ -static void pch_pcie_enable(device_t dev) -{ - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - u32 reg32; - - /* - * Save a copy of the Root Port Function Number map when - * starting to walk the list of PCIe Root Ports so it can - * be updated locally and written out when the last port - * has been processed. - */ - if (PCI_FUNC(dev->path.pci.devfn) == 0) { - new_rpfn = RCBA32(RPFN); - - /* - * Enable Root Port coalescing if the first port is disabled - * or the other devices will not be enumerated by the OS. - */ - if (!dev->enabled) - config->pcie_port_coalesce = 1; - - if (config->pcie_port_coalesce) - printk(BIOS_INFO, - "PCH: PCIe Root Port coalescing is enabled\n"); - } - - if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); - - /* - * PCIE Power Savings for PantherPoint and CougarPoint/B1+ - * - * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 - * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 - * - * This check is done here instead of pcie driver - * because the pcie driver enable() handler is not - * called unless the device is enabled. - */ - if ((PCI_FUNC(dev->path.pci.devfn) == 0 || - PCI_FUNC(dev->path.pci.devfn) == 4)) { - /* Handle workaround for PPT and CPT/B1+ */ - if (!pch_pcie_check_set_enabled(dev)) { - u8 reg8 = pci_read_config8(dev, 0xe2); - reg8 |= 1; - pci_write_config8(dev, 0xe2, reg8); - } - - /* - * Enable Clock Gating for shared PCIe resources - * before disabling this particular port. - */ - pci_write_config8(dev, 0xe1, 0x3c); - } - - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Do not claim downstream transactions for PCIe ports */ - new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); - - /* Disable this device if possible */ - pch_disable_devfn(dev); - } else { - int fn; - - /* - * Check if there is a lower disabled port to swap with this - * port in order to maintain linear order starting at zero. - */ - if (config->pcie_port_coalesce) { - for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { - if (!(new_rpfn & RPFN_HIDE(fn))) - continue; - - /* Swap places with this function */ - pch_pcie_function_swap( - PCI_FUNC(dev->path.pci.devfn), fn); - break; - } - } - - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } - - /* - * When processing the last PCIe root port we can now - * update the Root Port Function Number and Hide register. - */ - if (PCI_FUNC(dev->path.pci.devfn) == 7) { - printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - RCBA32(RPFN), new_rpfn); - RCBA32(RPFN) = new_rpfn; - - /* Update static devictree with new function numbers */ - if (config->pcie_port_coalesce) - pch_pcie_devicetree_update(); - } -} - void pch_enable(device_t dev) { u32 reg32; /* PCH PCIe Root Ports get special handling */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) - return pch_pcie_enable(dev); + return pch_pcie_enable_dev(dev); if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7c18705..9acdd1f 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -166,6 +166,7 @@ void pch_disable_devfn(device_t dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void pch_pcie_enable_dev(device_t dev); #if CONFIG_ELOG void pch_log_state(void); #endif diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index a3b84e3..28f4b6a 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -25,6 +25,191 @@ #include <device/pci_ids.h> #include "pch.h" +/* Check if any port in set X to X+3 is enabled */ +static int pch_pcie_check_set_enabled(device_t dev) +{ + device_t port; + int port_func; + int dev_func = PCI_FUNC(dev->path.pci.devfn); + + printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); + + /* Go through static device tree list of devices + * because enumeration is still in progress */ + for (port = all_devices; port; port = port->next) { + /* Only care about PCIe root ports */ + if (PCI_SLOT(port->path.pci.devfn) != + PCI_SLOT(dev->path.pci.devfn)) + continue; + + /* Check if port is in range and enabled */ + port_func = PCI_FUNC(port->path.pci.devfn); + if (port_func >= dev_func && + port_func < (dev_func + 4) && + port->enabled) + return 1; + } + + /* None of the ports in this set are enabled */ + return 0; +} + +/* RPFN is a write-once register so keep a copy until it is written */ +static u32 new_rpfn; + +/* Swap function numbers assigned to two PCIe Root Ports */ +static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) +{ + u32 old_rpfn = new_rpfn; + + printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", + old_fn, new_fn); + + new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); + + /* Old function set to new function and disabled */ + new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); + new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); +} + +/* Update devicetree with new Root Port function number assignment */ +static void pch_pcie_devicetree_update(void) +{ + device_t dev; + + /* Update the function numbers in the static devicetree */ + for (dev = all_devices; dev; dev = dev->next) { + u8 new_devfn; + + /* Only care about PCH PCIe root ports */ + if (PCI_SLOT(dev->path.pci.devfn) != + PCH_PCIE_DEV_SLOT) + continue; + + /* Determine the new devfn for this port */ + new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, + RPFN_FNGET(new_rpfn, + PCI_FUNC(dev->path.pci.devfn))); + + if (dev->path.pci.devfn != new_devfn) { + printk(BIOS_DEBUG, + "PCH: PCIe map %02x.%1x -> %02x.%1x\n", + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn), + PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); + + dev->path.pci.devfn = new_devfn; + } + } +} + +/* Special handling for PCIe Root Port devices */ +void pch_pcie_enable_dev(device_t dev) +{ + struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + u32 reg32; + + /* + * Save a copy of the Root Port Function Number map when + * starting to walk the list of PCIe Root Ports so it can + * be updated locally and written out when the last port + * has been processed. + */ + if (PCI_FUNC(dev->path.pci.devfn) == 0) { + new_rpfn = RCBA32(RPFN); + + /* + * Enable Root Port coalescing if the first port is disabled + * or the other devices will not be enumerated by the OS. + */ + if (!dev->enabled) + config->pcie_port_coalesce = 1; + + if (config->pcie_port_coalesce) + printk(BIOS_INFO, + "PCH: PCIe Root Port coalescing is enabled\n"); + } + + if (!dev->enabled) { + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + + /* + * PCIE Power Savings for PantherPoint and CougarPoint/B1+ + * + * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 + * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 + * + * This check is done here instead of pcie driver + * because the pcie driver enable() handler is not + * called unless the device is enabled. + */ + if ((PCI_FUNC(dev->path.pci.devfn) == 0 || + PCI_FUNC(dev->path.pci.devfn) == 4)) { + /* Handle workaround for PPT and CPT/B1+ */ + if (!pch_pcie_check_set_enabled(dev)) { + u8 reg8 = pci_read_config8(dev, 0xe2); + reg8 |= 1; + pci_write_config8(dev, 0xe2, reg8); + } + + /* + * Enable Clock Gating for shared PCIe resources + * before disabling this particular port. + */ + pci_write_config8(dev, 0xe1, 0x3c); + } + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Do not claim downstream transactions for PCIe ports */ + new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); + + /* Disable this device if possible */ + pch_disable_devfn(dev); + } else { + int fn; + + /* + * Check if there is a lower disabled port to swap with this + * port in order to maintain linear order starting at zero. + */ + if (config->pcie_port_coalesce) { + for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { + if (!(new_rpfn & RPFN_HIDE(fn))) + continue; + + /* Swap places with this function */ + pch_pcie_function_swap( + PCI_FUNC(dev->path.pci.devfn), fn); + break; + } + } + + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } + + /* + * When processing the last PCIe root port we can now + * update the Root Port Function Number and Hide register. + */ + if (PCI_FUNC(dev->path.pci.devfn) == 7) { + printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", + RCBA32(RPFN), new_rpfn); + RCBA32(RPFN) = new_rpfn; + + /* Update static devictree with new function numbers */ + if (config->pcie_port_coalesce) + pch_pcie_devicetree_update(); + } +} + static void pch_pcie_pm_early(struct device *dev) { /* RPC has been moved. It is in PCI config space now. */

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New patch to review for coreboot: 1c6d6b7 lynxpoint: expose pch_disable_devfn()
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4250 -gerrit commit 1c6d6b735241d302cbaca40cd8eeec9904706ea0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:20:37 2013 -0500 lynxpoint: expose pch_disable_devfn() The function to disable devices was formerly named pch_hide_devfn(). This routine was doing more than hiding devices. It was disabling them, i.e. turning them off. Therefore, rename it to pch_disable_devfn(). Also, allow external callers to this function. Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59276 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.c | 10 +++++----- src/southbridge/intel/lynxpoint/pch.h | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 05462c5..f13efb0 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -92,7 +92,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -static void pch_hide_devfn(device_t dev) +void pch_disable_devfn(device_t dev) { switch (dev->path.pci.devfn) { case PCI_DEVFN(19, 0): /* Audio DSP */ @@ -432,8 +432,8 @@ static void pch_pcie_enable(device_t dev) /* Do not claim downstream transactions for PCIe ports */ new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); - /* Hide this device if possible */ - pch_hide_devfn(dev); + /* Disable this device if possible */ + pch_disable_devfn(dev); } else { int fn; @@ -491,8 +491,8 @@ void pch_enable(device_t dev) PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32); - /* Hide this device if possible */ - pch_hide_devfn(dev); + /* Disable this device if possible */ + pch_disable_devfn(dev); } else { /* Enable SERR */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c46153c..7c18705 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -162,6 +162,7 @@ void disable_gpe(u32 mask); #include <arch/acpi.h> #include "chip.h" void pch_enable(device_t dev); +void pch_disable_devfn(device_t dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);

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New patch to review for coreboot: d599823 lynxpoint: expose iobp functions
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4249 -gerrit commit d599823b3b6999f74099c9a6d8c14f94f84965bf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 19 13:12:48 2013 -0500 lynxpoint: expose iobp functions The iobp functions are useful to may of the southbridge devices as certain values need to be updated to properly initialize the devices. Therefore expose read, write, and updated iobp functions. Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59275 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/pch.c | 25 +++++++++++++++++++------ src/southbridge/intel/lynxpoint/pch.h | 2 ++ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 58c68cd..05462c5 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -201,7 +201,7 @@ static inline int iobp_poll(void) return 0; } -static u32 pch_iobp_read(u32 address) +u32 pch_iobp_read(u32 address) { u16 status; @@ -239,10 +239,15 @@ static u32 pch_iobp_read(u32 address) return RCBA32(IOBPD); } -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +void pch_iobp_write(u32 address, u32 data) { u16 status; - u32 data = pch_iobp_read(address); + + if (!iobp_poll()) + return; + + /* Set the address */ + RCBA32(IOBPIRI) = address; /* WRITE OPCODE */ status = RCBA16(IOBPS); @@ -250,9 +255,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) status |= IOBPS_WRITE; RCBA16(IOBPS) = status; - /* Update the data */ - data &= andvalue; - data |= orvalue; RCBA32(IOBPD) = data; /* Undocumented magic */ @@ -276,6 +278,17 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); } +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data = pch_iobp_read(address); + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + pch_iobp_write(address, data); +} + /* Check if any port in set X to X+3 is enabled */ static int pch_pcie_check_set_enabled(device_t dev) { diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6ee81d1..c46153c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -162,6 +162,8 @@ void disable_gpe(u32 mask); #include <arch/acpi.h> #include "chip.h" void pch_enable(device_t dev); +u32 pch_iobp_read(u32 address); +void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG void pch_log_state(void);

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New patch to review for coreboot: 085b95e Add description to MAINBOARD_VENDOR string so it can be overridden
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4248 -gerrit commit 085b95e32607eddd7273e4df6e7081d85a3cecdf Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 18 13:19:26 2013 -0700 Add description to MAINBOARD_VENDOR string so it can be overridden A quirk of the Kconfig used in coreboot is that config options cannot be overriden by local config changes unless they have a description string. 1) Add CONFIG_MAINBOARD_VENDOR="Custom" to local config 2) Build and flash coreboot 3) cat /sys/class/dmi/id/sys_vendor and look for "Custom" Change-Id: I1b5f2124cd4a22c056c025143ae5bcaafa6b03f0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59088 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 4c36932..9ed615d 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -58,7 +58,7 @@ source "src/mainboard/google/snow/Kconfig" source "src/mainboard/google/stout/Kconfig" config MAINBOARD_VENDOR - string + string "Mainboard Vendor" default "Google" endif # VENDOR_GOOGLE

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New patch to review for coreboot: 119873d peppy: Add an inverted input GPIO type
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4247 -gerrit commit 119873d7a671c48169849f0e1bd2f7520906837b Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Tue Jun 11 20:30:09 2013 -0700 peppy: Add an inverted input GPIO type The wake device input pins are active low and the GPIOs need to be set as inverted when they are marked as an input so they are not spuriously logged. Also sync pin states from Falco initial commit. Reference change: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323 Change-Id: I66e136d389d53a367436d816fa84dacdc8e86bad Reviewed-on: https://gerrit.chromium.org/gerrit/58334 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Dave Parker <dparker(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)google.com> --- src/mainboard/google/peppy/gpio.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/peppy/gpio.h b/src/mainboard/google/peppy/gpio.h index 7c023b5..dab086a 100644 --- a/src/mainboard/google/peppy/gpio.h +++ b/src/mainboard/google/peppy/gpio.h @@ -35,7 +35,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_INPUT, /* 9: RAM_ID1 */ LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ LP_GPIO_UNUSED, /* 11: UNUSED */ - LP_GPIO_IRQ_EDGE, /* 12: TRACKPAD_INT_L */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ LP_GPIO_INPUT, /* 13: RAM_ID0 */ LP_GPIO_INPUT, /* 14: EC_IN_RW */ LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ @@ -48,7 +48,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 22: UNUSED */ LP_GPIO_UNUSED, /* 23: UNUSED */ LP_GPIO_UNUSED, /* 24: UNUSED */ - LP_GPIO_IRQ_EDGE, /* 25: TOUCH_INT_L */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ LP_GPIO_UNUSED, /* 26: UNUSED */ LP_GPIO_UNUSED, /* 27: UNUSED */ LP_GPIO_UNUSED, /* 28: UNUSED */ @@ -74,10 +74,10 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 48: UNUSED */ LP_GPIO_UNUSED, /* 49: UNUSED */ LP_GPIO_UNUSED, /* 50: UNUSED */ - LP_GPIO_IRQ_EDGE, /* 51: ALS_INT_L */ - LP_GPIO_IRQ_EDGE, /* 52: SIM_DET */ - LP_GPIO_ACPI_SCI, /* 53: TRACKPAD_INT_DX (WAKE) */ - LP_GPIO_ACPI_SCI, /* 54: TOUCH_INT_L_DX (WAKE) */ + LP_GPIO_INPUT, /* 51: ALS_INT_L */ + LP_GPIO_INPUT, /* 52: SIM_DET */ + LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */ + LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */ LP_GPIO_UNUSED, /* 55: UNUSED */ LP_GPIO_UNUSED, /* 56: UNUSED */ LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */

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New patch to review for coreboot: 461be9d falco/slippy: Fix DMIC nid verb.
by Stefan Reinauer 20 Nov '13

20 Nov '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4246 -gerrit commit 461be9d271e5d901c4bfab536eef88f2396a33cc Author: Dylan Reid <dgreid(a)chromium.org> Date: Fri Jun 14 11:50:35 2013 -0700 falco/slippy: Fix DMIC nid verb. Set nid 0x12 instead of nid 0x05. The DMIC is on NIC 0x12. Change-Id: Ifc883b65a50aeec6a6d3ad02fe8418f124e6241d Signed-off-by: Dylan Reid <dgreid(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58711 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Jay Kim <yongjaek(a)chromium.org> Tested-by: Jay Kim <yongjaek(a)chromium.org> --- src/mainboard/google/falco/hda_verb.h | 8 ++++---- src/mainboard/google/slippy/hda_verb.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/falco/hda_verb.h b/src/mainboard/google/falco/hda_verb.h index 3866a51..958b6c2 100644 --- a/src/mainboard/google/falco/hda_verb.h +++ b/src/mainboard/google/falco/hda_verb.h @@ -32,10 +32,10 @@ static const u32 mainboard_cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ - 0x00571c10, - 0x00571d10, - 0x00571ea6, - 0x00571fb7, + 0x01271c10, + 0x01271d10, + 0x01271ea6, + 0x01271fb7, /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ 0x01471c10, // group 1, front left/right diff --git a/src/mainboard/google/slippy/hda_verb.h b/src/mainboard/google/slippy/hda_verb.h index 3866a51..958b6c2 100644 --- a/src/mainboard/google/slippy/hda_verb.h +++ b/src/mainboard/google/slippy/hda_verb.h @@ -32,10 +32,10 @@ static const u32 mainboard_cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ - 0x00571c10, - 0x00571d10, - 0x00571ea6, - 0x00571fb7, + 0x01271c10, + 0x01271d10, + 0x01271ea6, + 0x01271fb7, /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ 0x01471c10, // group 1, front left/right

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coreboot-gerrit November 2013