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Change subject: flashchips: Add Support for XMC XM25QU80B
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Hi Kan, you uploaded new patchset and seems like all comments are resolved, but you haven't marked them as resolved.
If you done everything and ready for the review, you need to respond to comments and mark them resolved (or you can click Done button on each comment). And then you need to click Reply at the top, to send your replies.
This way I will know for sure that you are happy with your patch and I can review it again.
Thank you!
(and same for the other patch)
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Change subject: ch347_spi: Add spi clock frequency selection
......................................................................
Patch Set 5:
(2 comments)
File ch347_spi.c:
https://review.coreboot.org/c/flashrom/+/82776/comment/20c47497_5bef2c78?us… :
PS5, Line 290: int index = 0;
I just noticed this when testing your patch. If the spispeed isn't set, `divisor` defaults to 1 (30 MHz), but the message in line 370 says 60M because `index` defaults to 0:
```
flashrom 1.4.0-devel (git:v1.2-1460-g59c77b71) on Linux 6.9.4-arch1-1 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Invalid SPI speed, using 30MHz clock spi.
CH347 SPI clock set to 60M.
```
You could change index to default to 1, but then there would be two variables that need the proper default set. Perhaps rework it so that it only uses `index` (dropping `divisor`) and then determines the value to pass to `ch347_spi_init()` based on that?
https://review.coreboot.org/c/flashrom/+/82776/comment/9e1fd19d_74b923ea?us… :
PS5, Line 370: msg_pinfo("CH347 SPI clock set to %s.\n", spispeeds[index].name);
If the spispeed parameter is invalid, `index` is 8 here, so this prints out `CH347 SPI clock set to (null)`, though `divisor` will still be the default 1 so flashrom will internally proceed with 30 MHz.
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/83182?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add Support for XMC XM25QH16C/XM25QH16D
......................................................................
flashchips: Add Support for XMC XM25QH16C/XM25QH16D
Add initial support for the SPI flash chip XM25QH16C/XM25QH16D
Datasheet link: https://www.xmcwh.com/uploads/798/XM25QH16C_Ver1.8.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I215084ed33ca9261f6c7b91ef868ca8db85e61ad
Signed-off-by: Kan Sun <ssunkkan(a)gmail.com>
---
M flashchips.c
M include/flashchips.h
2 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/83182/2
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/83180?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add Support for XMC XM25QU80B
......................................................................
flashchips: Add Support for XMC XM25QU80B
Add initial support for the SPI flash chip XM25QU80B
Datasheet link: https://www.xmcwh.com/uploads/520/XM25QU80B_Ver1.4.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I8350f4ba94b4819e6496b9c5fddc8617bc0528b5
Signed-off-by: Kan Sun <ssunkkan(a)gmail.com>
---
M flashchips.c
M include/flashchips.h
2 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/83180/2
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Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/flashrom/+/83144?usp=email )
Change subject: ichspi: Add support for Panther Lake
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/83144/comment/2fb6b9d1_423034a0?us… :
PS2, Line 9: Panther Lake
> I see, of course I have no premium account :)
>
> Then I will ask you to send the patches if you find any bugs, or improvements. I understand that [Panther Lake] is something you are/will be actively working now. Thank you!
yes, PTL is something that we will work activity from now.
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Change subject: ichspi: Add support for Panther Lake
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/83144/comment/8e8ba198_eee34ea6?us… :
PS2, Line 9: Panther Lake
> > Newbie question, how do I find the doc? :) I tried go to intel. […]
I see, of course I have no premium account :)
Then I will ask you to send the patches if you find any bugs, or improvements. I understand that [Panther Lake] is something you are/will be actively working now. Thank you!
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Change subject: ch347_spi: Add spi clock frequency selection
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS4:
> Sorry for not reviewing this earlier; I was busy with other things and missed this patch.
Thank you for your patient review.
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