June 2024 - flashrom-gerrit - mail.coreboot.org

[XS] Change in flashrom[main]: VERSION: Update version to 1.4.0-rc1
by Anastasia Klimchuk (Code Review) 27 Jun '24

27 Jun '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83227?usp=email ) Change subject: VERSION: Update version to 1.4.0-rc1 ...................................................................... VERSION: Update version to 1.4.0-rc1 Change-Id: I013a35de898cbd5c09d254baccb3d644c1def2a0 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M VERSION 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/83227/1 diff --git a/VERSION b/VERSION index 90e4bc2..3280933 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.4.0-devel +1.4.0-rc1 -- To view, visit https://review.coreboot.org/c/flashrom/+/83227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I013a35de898cbd5c09d254baccb3d644c1def2a0 Gerrit-Change-Number: 83227 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QH16C/XM25QH16D
by Anastasia Klimchuk (Code Review) 27 Jun '24

27 Jun '24

Attention is currently required from: Nikolai Artemiev, Ssunk, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Ssunk. ( https://review.coreboot.org/c/flashrom/+/83182?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: flashchips: Add Support for XMC XM25QH16C/XM25QH16D ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Kan, could you please rebase this patch on the latest main branch? The reason is I merged your other patch CB:83180 and now this one has merge conflict, because both patch were adding new chip model id macro on line 850 in flashchips.h This one can go to line 851 now. You will need to sync your local repo, rebase this commit on top and push the patch again. Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/83182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I215084ed33ca9261f6c7b91ef868ca8db85e61ad Gerrit-Change-Number: 83182 Gerrit-PatchSet: 2 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ssunk <ssunkkan(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 27 Jun 2024 00:56:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QU80B
by Anastasia Klimchuk (Code Review) 27 Jun '24

27 Jun '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83180?usp=email ) Change subject: flashchips: Add Support for XMC XM25QU80B ...................................................................... flashchips: Add Support for XMC XM25QU80B Add initial support for the SPI flash chip XM25QU80B Datasheet link: https://www.xmcwh.com/uploads/520/XM25QU80B_Ver1.4.pdf Tested with ch341a programmer: probe, read, write, erase Change-Id: I8350f4ba94b4819e6496b9c5fddc8617bc0528b5 Signed-off-by: Kan Sun <ssunkkan(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83180 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c M include/flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 6977a26..aa16c50 100644 --- a/flashchips.c +++ b/flashchips.c @@ -21899,6 +21899,44 @@ { .vendor = "XMC", + .name = "XM25QU80B", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU80B, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256 } }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", .name = "XM25QH64C", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 691ffc5..d0c1aff 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -847,6 +847,7 @@ #define ST_M45PE16 0x4015 #define XMC_XM25QH64C 0x4017 #define XMC_XM25QU64C 0x4117 +#define XMC_XM25QU80B 0x5014 #define XMC_XM25QH128A 0x7018 #define XMC_XM25QH128C 0x4018 #define XMC_XM25QU128C 0x4118 -- To view, visit https://review.coreboot.org/c/flashrom/+/83180?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8350f4ba94b4819e6496b9c5fddc8617bc0528b5 Gerrit-Change-Number: 83180 Gerrit-PatchSet: 3 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in flashrom[main]: util/ich_descriptors_tool: Add Panther Lake SoC to supported chipsets
by Anastasia Klimchuk (Code Review) 27 Jun '24

27 Jun '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83149?usp=email ) Change subject: util/ich_descriptors_tool: Add Panther Lake SoC to supported chipsets ...................................................................... util/ich_descriptors_tool: Add Panther Lake SoC to supported chipsets This change extends the ich_descriptors_tool to recognize and process descriptors for Intel's upcoming Panther Lake SoC. BUG=b:347669091 TEST=ich_descriptors_tool is able to detect "panther" chipset and show below information: > ./util/ich_descriptors_tool/ich_descriptors_tool Need the file name of a descriptor image to read from. usage: './util/ich_descriptors_tool/ich_descriptors_tool -f <image file name> [-c <chipset name>] [-d]' ... ... To also print the data stored in the descriptor straps you have to indicate the chipset series with the '-c' parameter and one of the possible arguments: - "ich8", - "ich9", - "ich10", - "apollo" for Intel's Apollo Lake SoC. - "gemini" for Intel's Gemini Lake SoC. - "jasper" for Intel's Jasper Lake SoC. - "meteor" for Intel's Meteor Lake SoC. - "panther" for Intel's Panther Lake SoC. ... ... - "300" or "cannon" for Intel's 300 series chipsets. - "400" or "comet" for Intel's 400 series chipsets. - "500" or "tiger" for Intel's 500 series chipsets. - "600" or "alder" for Intel's 600 series chipsets. Change-Id: I17d616d346daca15b43eb294401ac0c672b64c4a Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83149 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Sam McNally <sammc(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/ich_descriptors_tool/ich_descriptors_tool.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, but someone else must approve Anastasia Klimchuk: Looks good to me, approved diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 844d8e9..09587f7 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -129,6 +129,7 @@ "\t- \"gemini\" for Intel's Gemini Lake SoC.\n" "\t- \"jasper\" for Intel's Jasper Lake SoC.\n" "\t- \"meteor\" for Intel's Meteor Lake SoC.\n" +"\t- \"panther\" for Intel's Panther Lake SoC.\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -248,6 +249,8 @@ cs = CHIPSET_ELKHART_LAKE; else if (strcmp(csn, "meteor") == 0) cs = CHIPSET_METEOR_LAKE; + else if (strcmp(csn, "panther") == 0) + cs = CHIPSET_PANTHER_LAKE; } ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc); -- To view, visit https://review.coreboot.org/c/flashrom/+/83149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I17d616d346daca15b43eb294401ac0c672b64c4a Gerrit-Change-Number: 83149 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: ichspi: Add support for Panther Lake
by Anastasia Klimchuk (Code Review) 27 Jun '24

27 Jun '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83144?usp=email ) Change subject: ichspi: Add support for Panther Lake ...................................................................... ichspi: Add support for Panther Lake This patch adds Panther Lake support into flashrom as per Intel Panther Lake SPI programming doc, number: 815466. BUG=b:347669091 TEST=Flashrom is able to detect PTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Panther Lake-U/H 12Xe". .... > flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Panther Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83144 Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Hsuan-ting Chen <roccochen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Sam McNally <sammc(a)google.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M include/programmer.h 4 files changed, 33 insertions(+), 4 deletions(-) Approvals: Sam McNally: Looks good to me, but someone else must approve Hsuan-ting Chen: Looks good to me, approved build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved Jamie Ryu: Looks good to me, but someone else must approve diff --git a/chipset_enable.c b/chipset_enable.c index 1c24b92..facf29e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -607,6 +607,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: @@ -715,6 +716,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: boot_straps = boot_straps_pch500; break; case CHIPSET_APOLLO_LAKE: @@ -750,6 +752,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -1019,6 +1022,11 @@ return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE); } +static int enable_flash_ptl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_PANTHER_LAKE); +} + static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); @@ -2186,6 +2194,8 @@ {0x8086, 0x7a8d, B_S, NT, "Intel", "WM690", enable_flash_pch600}, {0x8086, 0x7a8c, B_S, NT, "Intel", "HM670", enable_flash_pch600}, {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl}, + {0x8086, 0xe323, B_S, DEP, "Intel", "Panther Lake-U/H 12Xe", enable_flash_ptl}, + {0x8086, 0xe423, B_S, DEP, "Intel", "Panther Lake-H 4Xe", enable_flash_ptl}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index 6de4316..eaf44b0 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -50,6 +50,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_JASPER_LAKE: return 16; @@ -80,6 +81,7 @@ case CHIPSET_APOLLO_LAKE: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: @@ -122,7 +124,7 @@ "C620 series Lewisburg", "C740 series Emmitsburg", "300 series Cannon Point", "400 series Comet Point", "500 series Tiger Point", "600 series Alder Point", "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake", - "Meteor Lake", + "Meteor Lake", "Panther Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -220,6 +222,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -319,6 +322,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: return freq_str[3][value]; case CHIPSET_ELKHART_LAKE: return freq_str[4][value]; @@ -368,6 +372,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -508,7 +513,9 @@ cs == CHIPSET_500_SERIES_TIGER_POINT || cs == CHIPSET_600_SERIES_ALDER_POINT || cs == CHIPSET_C740_SERIES_EMMITSBURG || - cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE) { + cs == CHIPSET_JASPER_LAKE || + cs == CHIPSET_METEOR_LAKE || + cs == CHIPSET_PANTHER_LAKE) { const char *const master_names[] = { "BIOS", "ME", "GbE", "DevE", "EC", }; @@ -1083,6 +1090,8 @@ return CHIPSET_JASPER_LAKE; else if (content->CSSO == 0x70) return CHIPSET_METEOR_LAKE; + else if (content->CSSO == 0x60) + return CHIPSET_PANTHER_LAKE; } msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n"); return CHIPSET_500_SERIES_TIGER_POINT; @@ -1107,6 +1116,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1268,6 +1278,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -1314,6 +1325,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: diff --git a/ichspi.c b/ichspi.c index cc56e0c..f74fb05 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2111,6 +2111,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: *num_pr = 6; /* Includes GPR0 */ *reg_pr0 = PCH100_REG_FPR0; swseq->reg_ssfsc = PCH100_REG_SSFSC; @@ -2151,6 +2152,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: *num_freg = 16; break; default: @@ -2213,6 +2215,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08"PRIx32" (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); @@ -2294,6 +2297,7 @@ case CHIPSET_BAYTRAIL: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: break; default: ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR); @@ -2333,6 +2337,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: break; default: tmp = mmio_readl(spibar + ICH9_REG_FPB); @@ -2376,8 +2381,9 @@ ich_gen == CHIPSET_GEMINI_LAKE || ich_gen == CHIPSET_JASPER_LAKE || ich_gen == CHIPSET_ELKHART_LAKE || - ich_gen == CHIPSET_METEOR_LAKE)) { - msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake.\n"); + ich_gen == CHIPSET_METEOR_LAKE || + ich_gen == CHIPSET_PANTHER_LAKE)) { + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor/Panther Lake.\n"); ich_spi_mode = ich_hwseq; } diff --git a/include/programmer.h b/include/programmer.h index 8ef6ffd..a90624b 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -363,6 +363,7 @@ CHIPSET_ELKHART_LAKE, /* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */ CHIPSET_METEOR_LAKE, + CHIPSET_PANTHER_LAKE, }; /* ichspi.c */ -- To view, visit https://review.coreboot.org/c/flashrom/+/83144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0 Gerrit-Change-Number: 83144 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in flashrom[main]: hwaccess_x86_io: Fix Android compilation with bionic libc
by Anastasia Klimchuk (Code Review) 27 Jun '24

27 Jun '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83133?usp=email ) Change subject: hwaccess_x86_io: Fix Android compilation with bionic libc ...................................................................... hwaccess_x86_io: Fix Android compilation with bionic libc Recently Android Bionic LibC got sys/io.h. Use this header to access ioperm(). Use Assembly for I/O, as Bionic does not have inb(), outb(), etc. Tested on Android 14 by adding flashrom and pciutils as external repositories, adding Android.bp blueprints (Android specialized build system - Soong), building, running and accessing (read, erase, write) SPI flash on x86 device. Change-Id: Id80b83c2718679c925ed6ddfe33cbe837eea0429 Signed-off-by: Jakub Czapiga <czapiga(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83133 Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> Reviewed-by: Hsuan-ting Chen <roccochen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M hwaccess_x86_io.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: Peter Marheine: Looks good to me, approved Hsuan-ting Chen: Looks good to me, approved build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/hwaccess_x86_io.c b/hwaccess_x86_io.c index 93d29d8..70b7439 100644 --- a/hwaccess_x86_io.c +++ b/hwaccess_x86_io.c @@ -58,10 +58,11 @@ #define USE_IOPERM 9 #if defined(__ANDROID__) -#include <sys/glibc-syscalls.h> +#include <sys/io.h> +#include <unistd.h> -#define IO_PORT_PERMISSION USE_IOPL -#define IO_PORT_FUNCTION USE_LIBC_TARGET_LAST +#define IO_PORT_PERMISSION USE_IOPERM +#define IO_PORT_FUNCTION USE_ASM #endif #if defined(__linux__) && !defined(__ANDROID__) -- To view, visit https://review.coreboot.org/c/flashrom/+/83133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Id80b83c2718679c925ed6ddfe33cbe837eea0429 Gerrit-Change-Number: 83133 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QH16C/XM25QH16D
by Ssunk (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Ssunk has posted comments on this change by Ssunk. ( https://review.coreboot.org/c/flashrom/+/83182?usp=email ) Change subject: flashchips: Add Support for XMC XM25QH16C/XM25QH16D ...................................................................... Patch Set 2: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/83182/comment/649d8739_192c482c?us… : PS2, Line 21935: .voltage = {2700, 3600}, > Hi, […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I215084ed33ca9261f6c7b91ef868ca8db85e61ad Gerrit-Change-Number: 83182 Gerrit-PatchSet: 2 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 10:49:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ssunk <ssunkkan(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QH16C/XM25QH16D
by Ssunk (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Ssunk has posted comments on this change by Ssunk. ( https://review.coreboot.org/c/flashrom/+/83182?usp=email ) Change subject: flashchips: Add Support for XMC XM25QH16C/XM25QH16D ...................................................................... Patch Set 2: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/83182/comment/57229c32_d4916d63?us… : PS2, Line 21935: .voltage = {2700, 3600}, > I wanted to ask, why you set minimum voltage as 2. […] Hi, We will modify the operate voltage from 2.7~3.6v to 2.3v~3.6v for all the D family product and upload that to the official website soon. Thanks -- To view, visit https://review.coreboot.org/c/flashrom/+/83182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I215084ed33ca9261f6c7b91ef868ca8db85e61ad Gerrit-Change-Number: 83182 Gerrit-PatchSet: 2 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 26 Jun 2024 10:48:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[XS] Change in flashrom[main]: tests/selfcheck.c: Include the missing header lifecycle.h
by Hsuan-ting Chen (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Anastasia Klimchuk, Hsuan Ting Chen. Hsuan-ting Chen has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/83219?usp=email ) Change subject: tests/selfcheck.c: Include the missing header lifecycle.h ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I will get a build error in the CHROMIUM repository: ``` ../tests/selfcheck.c:155:9: error: return type defaults to ‘int’ [-Werror=implicit-int] 155 | SKIP_TEST(selfcheck_board_matches_table) | ^~~~~~~~~ ../tests/selfcheck.c:155:9: error: no previous prototype for ‘SKIP_TEST’ [-Werror=missing-prototypes] ../tests/selfcheck.c: In function ‘SKIP_TEST’: ../tests/selfcheck.c:155:9: error: type of ‘selfcheck_board_matches_table’ defaults to ‘int’ [-Werror=implicit-int] ../tests/selfcheck.c:157: error: expected ‘{’ at end of input ../tests/selfcheck.c:157: error: control reaches end of non-void function [-Werror=return-type] cc1: all warnings being treated as errors [109/148] Generating doc/documentation with a custom command ninja: build stopped: subcommand failed. ``` However, I cannot reproduce this error in the UPSTREAM version. Regardless, adding this change makes sense to me – as long as we need it, we should include it. -- To view, visit https://review.coreboot.org/c/flashrom/+/83219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ifc07ac66320712fdbf31504b9a980354c1883f40 Gerrit-Change-Number: 83219 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Jun 2024 10:14:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in flashrom[main]: tests/selfcheck.c: Include the missing header lifecycle.h
by Hsuan-ting Chen (Code Review) 26 Jun '24

26 Jun '24

Attention is currently required from: Hsuan Ting Chen. Hello Hsuan Ting Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/83219?usp=email to review the following change. Change subject: tests/selfcheck.c: Include the missing header lifecycle.h ...................................................................... tests/selfcheck.c: Include the missing header lifecycle.h selfcheck.c is using the macro SKIP_TEST, so we should include the header lifecycle.h. BUG=none TEST=meson test -C builddir/ Change-Id: Ifc07ac66320712fdbf31504b9a980354c1883f40 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> --- M tests/selfcheck.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/19/83219/1 diff --git a/tests/selfcheck.c b/tests/selfcheck.c index e235d8e..6e19f60 100644 --- a/tests/selfcheck.c +++ b/tests/selfcheck.c @@ -17,6 +17,7 @@ #include "string.h" #include "include/test.h" +#include "lifecycle.h" #include "programmer.h" #include "tests.h" #include <cmocka.h> -- To view, visit https://review.coreboot.org/c/flashrom/+/83219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ifc07ac66320712fdbf31504b9a980354c1883f40 Gerrit-Change-Number: 83219 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org>

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