October 2021 - flashrom-gerrit

Change in flashrom[master]: flashchips: Add ISSI IS25LQ016
by Angel Pons (Code Review) 02 Jun '23

02 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40431 ) Change subject: flashchips: Add ISSI IS25LQ016 ...................................................................... flashchips: Add ISSI IS25LQ016 Datasheet: http://www.issi.com/WW/pdf/25LQ016.pdf Tested all four PREW functions with a FT2232H. Change-Id: I02f19767b8a60fb2d37adab34894b6edb6ac4494 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M flashchips.c M flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/40431/1 diff --git a/flashchips.c b/flashchips.c index b4006df..a25f915 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7049,6 +7049,44 @@ { .vendor = "ISSI", + .name = "IS25LQ016", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25LQ016, + .total_size = 2048, + .page_size = 256, + /* OTP: 1024B total; read 0x4b; write 0xb1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2300, 3600}, + }, + + { + .vendor = "ISSI", .name = "IS25WP032", .bustype = BUS_SPI, .manufacture_id = ISSI_ID_SPI, diff --git a/flashchips.h b/flashchips.h index e5ef390..b5c0aeb 100644 --- a/flashchips.h +++ b/flashchips.h @@ -459,6 +459,7 @@ #define ISSI_IS25LP064 0x6017 #define ISSI_IS25LP128 0x6018 #define ISSI_IS25LP256 0x6019 +#define ISSI_IS25LQ016 0x1445 #define ISSI_IS25WP032 0x7016 #define ISSI_IS25WP064 0x7017 #define ISSI_IS25WP128 0x7018 -- To view, visit https://review.coreboot.org/c/flashrom/+/40431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I02f19767b8a60fb2d37adab34894b6edb6ac4494 Gerrit-Change-Number: 40431 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Added missing voltages
by Name of user not set (Code Review) 02 Jun '23

02 Jun '23

roman.stingler(a)gmail.com has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40432 ) Change subject: flashchips: Added missing voltages ...................................................................... flashchips: Added missing voltages Signed-off-by: Roman Stingler <roman.stingler(a)gmail.com> Change-Id: I0825ab11e53c0b018b49173907e2b274a4cf1fab --- M flashchips.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/40432/1 diff --git a/flashchips.c b/flashchips.c index b4006df..f2d9fc1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7650,6 +7650,7 @@ }, .write = write_82802ab, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -7677,6 +7678,7 @@ }, .write = write_82802ab, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -7704,6 +7706,7 @@ }, .write = write_82802ab, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -7727,6 +7730,7 @@ .unlock = unlock_28f004s5, .write = write_82802ab, .read = read_memmapped, + .voltage = {2700, 3600}, }, { @@ -7755,6 +7759,7 @@ }, .write = write_82802ab, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -7783,6 +7788,7 @@ }, .write = write_82802ab, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -9972,6 +9978,7 @@ .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -17550,6 +17557,7 @@ }, .write = write_jedec, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -17573,6 +17581,7 @@ }, .write = write_jedec, .read = read_memmapped, + .voltage = {4500, 5500}, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/40432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0825ab11e53c0b018b49173907e2b274a4cf1fab Gerrit-Change-Number: 40432 Gerrit-PatchSet: 1 Gerrit-Owner: roman.stingler(a)gmail.com Gerrit-MessageType: newchange

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Change in flashrom[master]: flaschips.c: Fix building with CONFIG_DUMMY=no
by Arthur Heymans (Code Review) 21 Apr '23

21 Apr '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47166 ) Change subject: flaschips.c: Fix building with CONFIG_DUMMY=no ...................................................................... flaschips.c: Fix building with CONFIG_DUMMY=no With CONFIG_DUMMY=yes dummuflasher.c is not linked in so there is definition of probe_variable_size. Change-Id: Ib9bae93fadc55cf133e837e63419da104a6298be Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M flashchips.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/47166/1 diff --git a/flashchips.c b/flashchips.c index 48efb85..1681f42 100644 --- a/flashchips.c +++ b/flashchips.c @@ -19081,3 +19081,7 @@ }; const unsigned int flashchips_size = ARRAY_SIZE(flashchips); + +#if !CONFIG_DUMMY +int probe_variable_size(struct flashctx *flash) { return 0; }; +#endif -- To view, visit https://review.coreboot.org/c/flashrom/+/47166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9bae93fadc55cf133e837e63419da104a6298be Gerrit-Change-Number: 47166 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in flashrom[master]: buspirate: Add option for setting the aux pin
by Sean Anderson (Code Review) 13 Apr '23

13 Apr '23

Sean Anderson has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43608 ) Change subject: buspirate: Add option for setting the aux pin ...................................................................... buspirate: Add option for setting the aux pin This adds a parameter to drive the aux pin low (or high if you explicitly want the previous behavior). Some boards need to have a reset pin driven low before the firmware can be safely flashed. With the Bus Pirate, this is most easily done with the auxiliary pin. Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775 Signed-off-by: Sean Anderson <seanga2(a)gmail.com> --- M buspirate_spi.c M flashrom.8.tmpl 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/43608/1 diff --git a/buspirate_spi.c b/buspirate_spi.c index fdfc0e4..1ccb107 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -228,6 +228,7 @@ int serialspeed_index = -1; int ret = 0; int pullup = 0; + int aux = 1; dev = extract_programmer_param("dev"); if (dev && !strlen(dev)) { @@ -277,6 +278,17 @@ } free(tmp); + tmp = extract_programmer_param("aux"); + if (tmp) { + if (strcasecmp("high", tmp) == 0) + ; /* Default */ + else if (strcasecmp("low", tmp) == 0) + aux = 0; + else + msg_perr("Invalid AUX state, driving high by default.\n"); + } + free(tmp); + /* Default buffer size is 19: 16 bytes data, 3 bytes control. */ #define DEFAULT_BUFSIZE (16 + 3) bp_commbuf = malloc(DEFAULT_BUFSIZE); @@ -520,11 +532,18 @@ } /* Initial setup (SPI peripherals config): Enable power, CS high, AUX */ - bp_commbuf[0] = 0x40 | 0x0b; + bp_commbuf[0] = 0x40 | 0x09; if (pullup == 1) { bp_commbuf[0] |= (1 << 2); msg_pdbg("Enabling pull-up resistors.\n"); } + if (aux) { + bp_commbuf[0] |= (1 << 1); + msg_pdbg("Driving AUX high.\n"); + } else { + msg_pdbg("Driving AUX low.\n"); + } + ret = buspirate_sendrecv(bp_commbuf, 1, 1); if (ret) return 1; diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db50d59..caf860c 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -902,6 +902,19 @@ .URLB "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…" \ "in a guide by dangerousprototypes" . Only the external supply voltage (Vpu) is supported as of this writing. +.sp +An optional aux parameter specifies the state of the Bus Pirate auxiliary pin. +This may be used to drive the auxiliary pin high or low before a transfer. +Syntax is +.sp +.B " flashrom -p buspirate_spi:aux=state" +.sp +where +.B state +can be +.BR high " or " low . +The default +.BR state " is " high . .SS .BR "pickit2_spi " programmer .IP -- To view, visit https://review.coreboot.org/c/flashrom/+/43608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775 Gerrit-Change-Number: 43608 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Anderson <seanga2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: cli_classic: Report the gathered layout entries at level dbg
by Nico Huber (Code Review) 04 Nov '22

04 Nov '22

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31012 Change subject: cli_classic: Report the gathered layout entries at level dbg ...................................................................... cli_classic: Report the gathered layout entries at level dbg Change-Id: I7678ba5138f0d722ee44747fe123f192abdd0ffd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M cli_classic.c M layout.c M layout.h 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/31012/1 diff --git a/cli_classic.c b/cli_classic.c index ced08c6..536ef24 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -645,6 +645,8 @@ goto out_shutdown; } + report_layout(layout); + flashrom_layout_set(fill_flash, layout); flashrom_flag_set(fill_flash, FLASHROM_FLAG_FORCE, !!force); #if CONFIG_INTERNAL == 1 diff --git a/layout.c b/layout.c index fa66238..c589d17 100644 --- a/layout.c +++ b/layout.c @@ -229,3 +229,17 @@ return ret; } + +void report_layout(const struct flashrom_layout *const l) +{ + unsigned int i; + + if (!l) + return; + + msg_gdbg("Gathered %zu layout entries:\n", l->num_entries); + for (i = 0; i < l->num_entries; ++i) { + msg_gdbg("%08"PRIx32":%08"PRIx32" %s\n", + l->entries[i].start, l->entries[i].end, l->entries[i].name); + } +} diff --git a/layout.h b/layout.h index eb54a4f..61311bc 100644 --- a/layout.h +++ b/layout.h @@ -59,4 +59,6 @@ int process_include_args(struct flashrom_layout *); +void report_layout(const struct flashrom_layout *); + #endif /* !__LAYOUT_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/31012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7678ba5138f0d722ee44747fe123f192abdd0ffd Gerrit-Change-Number: 31012 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Fix W25Q256.W
by Patrick Rudolph (Code Review) 26 May '22

26 May '22

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/44810 to review the following change. Change subject: flashchips: Fix W25Q256.W ...................................................................... flashchips: Fix W25Q256.W Used the datasheet from here: https://www.winbond.com/resource-files/w25q256jw%20spi%20revb%2012082017.pdf The chips supports all native 4BA instructions. Change-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M flashchips.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/44810/1 diff --git a/flashchips.c b/flashchips.c index 8b5b5cc..2c16f89 100644 --- a/flashchips.c +++ b/flashchips.c @@ -16854,8 +16854,8 @@ .page_size = 256, /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN - | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -16863,12 +16863,18 @@ { { .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 1024} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {32 * 1024 * 1024, 1} }, -- To view, visit https://review.coreboot.org/c/flashrom/+/44810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0 Gerrit-Change-Number: 44810 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: jlink_spi: Add option to enable target power
by zapb (Code Review) 30 Apr '22

30 Apr '22

zapb has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48380 ) Change subject: jlink_spi: Add option to enable target power ...................................................................... jlink_spi: Add option to enable target power Change-Id: I026c22ae1c22541d0024f164c827909ca4a34cf4 Signed-off-by: Marc Schink <dev(a)zapb.de> --- M flashrom.8.tmpl M jlink_spi.c 2 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/48380/1 diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db50d59..2299dad 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -1279,6 +1279,9 @@ .sp syntax where \fBfrequency\fP is the SPI clock frequency in kHz. The maximum speed depends on the device in use. +.sp +The \fBpower=on\fP option can be used to activate the 5 V power supply (PWR_5V) +of the J-Link during a flash operation. .SS .BR "stlinkv3_spi " programmer .IP diff --git a/jlink_spi.c b/jlink_spi.c index 3a73c01..8344af2 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -54,6 +54,7 @@ static struct jaylink_context *jaylink_ctx; static struct jaylink_device_handle *jaylink_devh; static bool reset_cs; +static bool enable_target_power; static bool assert_cs(void) { @@ -166,6 +167,15 @@ static int jlink_spi_shutdown(void *data) { + if (enable_target_power) { + int ret = jaylink_set_target_power(jaylink_devh, false); + + if (ret != JAYLINK_OK) { + msg_perr("jaylink_set_target_power() failed: %s.\n", + jaylink_strerror(ret)); + } + } + if (jaylink_devh) jaylink_close(jaylink_devh); @@ -258,6 +268,21 @@ else msg_pdbg("Using TRST as chip select signal.\n"); + enable_target_power = false; + arg = extract_programmer_param("power"); + + if (arg) { + if (!strcasecmp(arg, "on")) { + enable_target_power = true; + } else { + msg_perr("Invalid value for 'power' argument: '%s'.\n", arg); + free(arg); + return 1; + } + } + + free(arg); + ret = jaylink_init(&jaylink_ctx); if (ret != JAYLINK_OK) { @@ -368,6 +393,13 @@ } } + if (enable_target_power) { + if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SET_TARGET_POWER)) { + msg_perr("Device does not support target power.\n"); + return 1; + } + } + uint32_t ifaces; ret = jaylink_get_available_interfaces(jaylink_devh, &ifaces); @@ -389,6 +421,18 @@ return 1; } + if (enable_target_power) { + ret = jaylink_set_target_power(jaylink_devh, true); + + if (ret != JAYLINK_OK) { + msg_perr("jaylink_set_target_power() failed: %s.\n", jaylink_strerror(ret)); + return 1; + } + + /* Wait some time until the target is powered up. */ + internal_sleep(10000UL); + } + struct jaylink_hardware_status hwstat; ret = jaylink_get_hardware_status(jaylink_devh, &hwstat); -- To view, visit https://review.coreboot.org/c/flashrom/+/48380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I026c22ae1c22541d0024f164c827909ca4a34cf4 Gerrit-Change-Number: 48380 Gerrit-PatchSet: 1 Gerrit-Owner: zapb <dev(a)zapb.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Add Icelake U to known systems
by Mimoja (Code Review) 13 Apr '22

13 Apr '22

Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37987 ) Change subject: chipset_enable.c: Add Icelake U to known systems ...................................................................... chipset_enable.c: Add Icelake U to known systems Intel Icelake Systems use an (so far) underdescribed 495 Series Chipset that behaves compaitble to pch300 chips. Change-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15 Signed-off-by: Johanna Schander <git(a)mimoja.de> --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/37987/1 diff --git a/chipset_enable.c b/chipset_enable.c index e826d90..988720b 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2046,6 +2046,7 @@ {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0x3482, B_S, DEP, "Intel", "Icelake U Premium", enable_flash_pch300}, #endif {0}, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/37987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15 Gerrit-Change-Number: 37987 Gerrit-PatchSet: 1 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: hwaccess: Add endianness converting deserialization functions
by Nico Huber (Code Review) 13 Apr '22

13 Apr '22

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31016 Change subject: hwaccess: Add endianness converting deserialization functions ...................................................................... hwaccess: Add endianness converting deserialization functions Add functions like uint32_t read_le32(const void *); Change-Id: Idde177acf8bc5f94cd046b6539dc31532c98e452 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M hwaccess.h 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/31016/1 diff --git a/hwaccess.h b/hwaccess.h index af7054b..5df4fc3 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -20,6 +20,7 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#include <stdint.h> #include "platform.h" #if NEED_PCI == 1 @@ -109,6 +110,19 @@ #define le_to_cpu32 cpu_to_le32 #define le_to_cpu64 cpu_to_le64 +#define read_from(endianness, bits) \ +static inline uint##bits##_t read_##endianness##bits(const void *from) \ +{ \ + return le_to_cpu##bits(*(uint##bits##_t *)from); \ +} + +read_from(be, 8) +read_from(be, 16) +read_from(be, 32) +read_from(le, 8) +read_from(le, 16) +read_from(le, 32) + #if NEED_RAW_ACCESS == 1 #if IS_X86 -- To view, visit https://review.coreboot.org/c/flashrom/+/31016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idde177acf8bc5f94cd046b6539dc31532c98e452 Gerrit-Change-Number: 31016 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Enable Tiger Lake U support
by Edward O'Callaghan (Code Review) 10 Apr '22

10 Apr '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37777 ) Change subject: chipset_enable.c: Enable Tiger Lake U support ...................................................................... chipset_enable.c: Enable Tiger Lake U support Did a basic local test with --flash-name and -r bios and ran strings to see if the bios contained reasonable data. BUG=b:146089922 Change-Id: I2c13e0173c9b5e17d2ae197f4a4ab9aa2825c1b3 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/37777/1 diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..d5a2f03 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1996,6 +1996,7 @@ {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, + {0x8086, 0xa082, B_FS, NT, "Intel", "Tiger Lake U", enable_flash_pch300}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/37777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2c13e0173c9b5e17d2ae197f4a4ab9aa2825c1b3 Gerrit-Change-Number: 37777 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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