October 2018 - flashrom-gerrit

Change in flashrom[master]: chipset_enable.c: Mark Intel H81 as DEP
by Tristan Corrick (Code Review) 31 Oct '18

31 Oct '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29391 Change subject: chipset_enable.c: Mark Intel H81 as DEP ...................................................................... chipset_enable.c: Mark Intel H81 as DEP Tested on an ASRock H81M-HDS. The flash chip has been read, written, and erased many times without issue. Most boards with this chipset will have the ME region locked, hence the selection of DEP. Change-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/29391/1 diff --git a/chipset_enable.c b/chipset_enable.c index 22021a7..c1639a6 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1849,7 +1849,7 @@ {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8}, + {0x8086, 0x8c5c, DEP, "Intel", "H81", enable_flash_pch8}, {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8}, -- To view, visit https://review.coreboot.org/29391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4 Gerrit-Change-Number: 29391 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in flashrom[master]: flashchips: Add IS25LP256 and IS25WP256
by Nico Huber (Code Review) 30 Oct '18

30 Oct '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/29306 ) Change subject: flashchips: Add IS25LP256 and IS25WP256 ...................................................................... flashchips: Add IS25LP256 and IS25WP256 Tested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers. Tested IS25WP256 using Dediprog SF600. Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> Reviewed-on: https://review.coreboot.org/29306 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M flashchips.c M flashchips.h 2 files changed, 102 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index bbd5cad..d2a8d77 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7376,6 +7376,56 @@ { .vendor = "ISSI", + .name = "IS25LP256", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25LP256, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + /* could also use spi_block_erase_d7 */ + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2300, 3600}, + }, + + { + .vendor = "ISSI", .name = "IS25WP032", .bustype = BUS_SPI, .manufacture_id = ISSI_ID_SPI, @@ -7502,6 +7552,56 @@ { .vendor = "ISSI", + .name = "IS25WP256", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25WP256, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + /* could also use spi_block_erase_d7 */ + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "ISSI", .name = "IS29GL064B", .bustype = BUS_PARALLEL, .manufacture_id = ISSI_ID, diff --git a/flashchips.h b/flashchips.h index 429acef..434c355 100644 --- a/flashchips.h +++ b/flashchips.h @@ -456,9 +456,11 @@ #define ISSI_ID_SPI 0x9D /* ISSI ID used for SPI flash, see also PMC_ID_NOPREFIX */ #define ISSI_IS25LP064 0x6017 #define ISSI_IS25LP128 0x6018 +#define ISSI_IS25LP256 0x6019 #define ISSI_IS25WP032 0x7016 #define ISSI_IS25WP064 0x7017 #define ISSI_IS25WP128 0x7018 +#define ISSI_IS25WP256 0x7019 #define ISSI_PMC_IS29GL032B 0xF9 #define ISSI_PMC_IS29GL032T 0xF6 #define ISSI_PMC_IS29GL064B 0x7E1000 -- To view, visit https://review.coreboot.org/29306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Gerrit-Change-Number: 29306 Gerrit-PatchSet: 5 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[master]: flashchips: Add IS25LP256 and IS25WP256
by Nico Huber (Code Review) 30 Oct '18

30 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29306 ) Change subject: flashchips: Add IS25LP256 and IS25WP256 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/29306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Gerrit-Change-Number: 29306 Gerrit-PatchSet: 4 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 09:39:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: flashchips: Add IS25LP256 and IS25WP256
by David Hendricks (Code Review) 30 Oct '18

30 Oct '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/29306 ) Change subject: flashchips: Add IS25LP256 and IS25WP256 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29306/1/flashchips.c File flashchips.c: https://review.coreboot.org/#/c/29306/1/flashchips.c@7399 PS1, Line 7399: .block_erase = spi_block_erase_20, > Also aliased as d7. I wouldn't mind if you don't want to add it. […] I tried adding d7, but ran into the NUM_ERASEFUNCTIONS limit. So I went with a comment instead - No need to change NUM_ERASEFUNCTIONS to accommodate a redundant instruction. -- To view, visit https://review.coreboot.org/29306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Gerrit-Change-Number: 29306 Gerrit-PatchSet: 4 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 23:08:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: flashchips: Add IS25LP256 and IS25WP256
by David Hendricks (Code Review) 30 Oct '18

30 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29306 to look at the new patch set (#4). Change subject: flashchips: Add IS25LP256 and IS25WP256 ...................................................................... flashchips: Add IS25LP256 and IS25WP256 Tested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers. Tested IS25WP256 using Dediprog SF600. Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M flashchips.c M flashchips.h 2 files changed, 102 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/29306/4 -- To view, visit https://review.coreboot.org/29306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Gerrit-Change-Number: 29306 Gerrit-PatchSet: 4 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[master]: flashchips: Add IS25LP256 and IS25WP256
by David Hendricks (Code Review) 30 Oct '18

30 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29306 to look at the new patch set (#3). Change subject: flashchips: Add IS25LP256 and IS25WP256 ...................................................................... flashchips: Add IS25LP256 and IS25WP256 Tested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers. Tested IS25WP256 using Dediprog SF600. Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M flashchips.c M flashchips.h 2 files changed, 106 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/29306/3 -- To view, visit https://review.coreboot.org/29306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a Gerrit-Change-Number: 29306 Gerrit-PatchSet: 3 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[master]: flashchips: Add W25Q256JV support
by David Hendricks (Code Review) 30 Oct '18

30 Oct '18

David Hendricks has submitted this change and it was merged. ( https://review.coreboot.org/29305 ) Change subject: flashchips: Add W25Q256JV support ...................................................................... flashchips: Add W25Q256JV support Similar to W25Q256FV, but it supports the native 4BA page program instruction (12h). Note that the variant with QE enabled by default shares the device ID of the W25Q256FV. Tested using a Raspberry Pi. Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> Reviewed-on: https://review.coreboot.org/29305 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M flashchips.c M flashchips.h 2 files changed, 49 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 8065283..bbd5cad 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15550,6 +15550,53 @@ { .vendor = "Winbond", + .name = "W25Q256JV_M", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256JV_M, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25Q20.W", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index 218cb5b..429acef 100644 --- a/flashchips.h +++ b/flashchips.h @@ -916,7 +916,7 @@ #define WINBOND_NEX_W25Q32_V 0x4016 /* W25Q32BV; W25Q32FV in SPI mode (default) */ #define WINBOND_NEX_W25Q64_V 0x4017 /* W25Q64BV, W25Q64CV; W25Q64FV in SPI mode (default) */ #define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV; W25Q128FV in SPI mode (default) */ -#define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV */ +#define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV or W25Q256JV_Q (QE=1) */ #define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ #define WINBOND_NEX_W25Q40BW 0x5013 /* W25Q40BW */ #define WINBOND_NEX_W25Q80BW 0x5014 /* W25Q80BW */ @@ -927,6 +927,7 @@ #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ #define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ +#define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ #define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_W19B160BB 0x49 -- To view, visit https://review.coreboot.org/29305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4 Gerrit-Change-Number: 29305 Gerrit-PatchSet: 2 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[master]: flashchips: Add W25Q256JV support
by David Hendricks (Code Review) 30 Oct '18

30 Oct '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/29305 ) Change subject: flashchips: Add W25Q256JV support ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29305/1/flashchips.c File flashchips.c: https://review.coreboot.org/#/c/29305/1/flashchips.c@15561 PS1, Line 15561: /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ > doesn't add any information (I guess the copied comment above is only a leftover) Agreed, the comment is stale. We should probably clean up all those in a follow-up patch. -- To view, visit https://review.coreboot.org/29305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4 Gerrit-Change-Number: 29305 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 22:50:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: [WIP]dediprog: Implement 4-byte-address support
by David Hendricks (Code Review) 30 Oct '18

30 Oct '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/28804 ) Change subject: [WIP]dediprog: Implement 4-byte-address support ...................................................................... Patch Set 1: (2 comments) > Patch Set 1: > > (2 comments) > > > I was able to test this and it works with one small change (see > > comments). > > > > I used an SF600 with firmware 7.2.21, with W25Q256JVFM and > > MX25L25735FMI and wrote to 1MB ranges in the lower and upper halves > > of the chip. > > At least something works now... > > Did you test the native instructions only? e.g. you could remove > the native flags / erase functions (and in another step the enter > 4BA flags) for your chip to test different paths. I think so... I tried with only FEATURE_4BA_NATIVE enabled and I also tried with only FEATURE_4BA enabled, the former should have used native instructions only, right? > Maybe we should add a chip test mode to flashrom first. Yes, I think that would be a great idea. Built-in chip testing has been on my TODO list for a while. I hacked up something for testing write-protection capabilities a while back for CrOS flashrom: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/… > With all > the possible Dedicrap programmers, hardware and firmware revisions > we'll have a lot to test; or start to whitelist individual combi- > nations :-/ May as well start with what we know works. https://review.coreboot.org/#/c/28804/1/dediprog.c File dediprog.c: https://review.coreboot.org/#/c/28804/1/dediprog.c@390 PS1, Line 390: use_4ba = true; > So this path seems to have failed for Ron but succeeded for David... […] It's worth noting that Ron also hacked it to only do slow reads. I think there is an issue in that path, though, as I was unable to successfully test the fmap patch using a dediprog because the binary search algorithm would always use small reads. I'll need to investigate that some other time though. https://review.coreboot.org/#/c/28804/1/dediprog.c@399 PS1, Line 399: data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12 > Hard to tell... it's obviously redundant with data_packet[4]. I could […] Perhaps. But at least I have one known good configuration. Let's start with that. -- To view, visit https://review.coreboot.org/28804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I665d0806aec469a3509620a760815861fbe22841 Gerrit-Change-Number: 28804 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Oct 2018 22:48:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: [WIP]dediprog: Implement 4-byte-address support
by Nico Huber (Code Review) 30 Oct '18

30 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28804 ) Change subject: [WIP]dediprog: Implement 4-byte-address support ...................................................................... Patch Set 1: (2 comments) > I was able to test this and it works with one small change (see > comments). > > I used an SF600 with firmware 7.2.21, with W25Q256JVFM and > MX25L25735FMI and wrote to 1MB ranges in the lower and upper halves > of the chip. At least something works now... Did you test the native instructions only? e.g. you could remove the native flags / erase functions (and in another step the enter 4BA flags) for your chip to test different paths. Maybe we should add a chip test mode to flashrom first. With all the possible Dedicrap programmers, hardware and firmware revisions we'll have a lot to test; or start to whitelist individual combi- nations :-/ https://review.coreboot.org/#/c/28804/1/dediprog.c File dediprog.c: https://review.coreboot.org/#/c/28804/1/dediprog.c@390 PS1, Line 390: use_4ba = true; So this path seems to have failed for Ron but succeeded for David... I fear we have to get back to reverse engineering if we want reliable support for this crapware. https://review.coreboot.org/#/c/28804/1/dediprog.c@399 PS1, Line 399: data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12 > For some reason I cannot explain, this needs to be WRITE_MODE_4B_ADDR_256B_PAGE_PGM. […] Hard to tell... it's obviously redundant with data_packet[4]. I could imagine bad things. For instance they could have used hard-coded instructions first, and added data_packet[4] only later. Or maybe they try to cache and check the 4BA mode setting? who knows. I get the desperate feeling that we might need a more fine-grained version distinction. -- To view, visit https://review.coreboot.org/28804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I665d0806aec469a3509620a760815861fbe22841 Gerrit-Change-Number: 28804 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Oct 2018 21:37:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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flashrom-gerrit October 2018